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Differential Amplifier:: Out D

A differential amplifier amplifies the difference between two input voltages (V1 and V2) and rejects input voltages that are common to both inputs. The differential gain (Ad) should be very high while the common-mode gain (Ac) should be 0. This provides high common mode rejection ratio (CMRR). A source coupled-pair differential amplifier uses two matched transistors (M1 and M2) operated in saturation. The output current difference (ΔId) is proportional to the square root of the input voltage difference (ΔVi). The transconductance of the differential pair (gm(diff)) relates ΔId to ΔVi.
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0% found this document useful (0 votes)
65 views

Differential Amplifier:: Out D

A differential amplifier amplifies the difference between two input voltages (V1 and V2) and rejects input voltages that are common to both inputs. The differential gain (Ad) should be very high while the common-mode gain (Ac) should be 0. This provides high common mode rejection ratio (CMRR). A source coupled-pair differential amplifier uses two matched transistors (M1 and M2) operated in saturation. The output current difference (ΔId) is proportional to the square root of the input voltage difference (ΔVi). The transconductance of the differential pair (gm(diff)) relates ΔId to ΔVi.
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DIFFERENTIAL AMPLIFIER:

2
( V 1+V
)
2

Vout = Ad(V1-V2)+Ac

Ad=Differential gain and Ac=Common-mode gain


Ideally: Ad=very high and Ac=0
CMRR (Common Mode Rejection Ratio) =

Ad
Ac

ICMR (Input Common Mode Range): It specifies the range of input voltage over which device
will work as differential amplifier.
Offset voltage: It is the applied input differential voltage to differential amplifier for which
output is zero.
How to find the differential voltage for which output is zero?
Ans: Firstly, short both the inputs of differential amplifier and divide the obtained output by
amplifier gain which is the required offset voltage.

SOURCE COUPLED-PAIR DIFFERENTIAL AMPLIFIER:


Assumption:
1) Neglect substrate bias voltage
2) M1 and M2 geometrically matched
M1 and M2 are operate in saturation mode
Iss= Id1+Id2
Id1

Iss = 2Id1

increases but Iss is fixed. Id2

I d1 =

n Cox
W
L (Vgs1-vt)2
2

I d2 =

n Cox
W

2
L (Vgs2-vt)2

V gs 2 -v t =

Id

Id1 =

Iss
2

Case-1 (V1>V2)
Consider transistor M1 , Vgs1 increases, Id1 increases so Vs
will reduce .

Id1 = Iss- Id2 I d =I d 1 -Id2 Id 1=

V gs 1 -v t =

Id2

2 Id 1 L
n Cox W

2 Id 2 L
n Cox W

1
2

1
2

=
=

Iss+ Id
2

& Id2 =

( Id + Iss) L
n Cox W
( IdIss) L
n Cox W

V i =v gs 1 -v gs 2 =v1-v2
V i ={(vgs1-vt)-(vgs2-vt)}

Squaring both the sides we have

( Id + Iss) L
( Id Iss) L

n Cox W
n Cox W

IssId
2

V i

( Id + Iss) L ( Id Iss) L
L
2
2
+
2
n Cox W
n Cox W
n Cox W (Iss -Id )

By solving the above equation we have


Id

n Cox W
2 Iss L
Vi
2L
0.5 n Cox W

1
2

=gm(diff)

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