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Cmos Digital Ic Design Mid Paper

1. The document contains a 10 question multiple choice quiz on concepts in digital logic design including CMOS logic gates. Topics covered include pseudo NMOS logic, transmission gates, sequential vs combinational logic. 2. It also contains 3 short answer questions asking students to derive threshold voltages, equivalent circuits and voltage levels for different logic gates including pseudo NMOS inverters, NAND gates and CMOS transmission gates. 3. Students are asked to explain complex logic circuits, draw the circuit diagram and layout for a CMOS NAND2 gate, and represent and analyze the transient response, rise time and fall time of CMOS transmission gates. The questions test a range of topics from logic gate fundamentals to circuit

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Rasool Reddy
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Download as DOCX, PDF, TXT or read online on Scribd
531 views

Cmos Digital Ic Design Mid Paper

1. The document contains a 10 question multiple choice quiz on concepts in digital logic design including CMOS logic gates. Topics covered include pseudo NMOS logic, transmission gates, sequential vs combinational logic. 2. It also contains 3 short answer questions asking students to derive threshold voltages, equivalent circuits and voltage levels for different logic gates including pseudo NMOS inverters, NAND gates and CMOS transmission gates. 3. Students are asked to explain complex logic circuits, draw the circuit diagram and layout for a CMOS NAND2 gate, and represent and analyze the transient response, rise time and fall time of CMOS transmission gates. The questions test a range of topics from logic gate fundamentals to circuit

Uploaded by

Rasool Reddy
Copyright
© © All Rights Reserved
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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SECTION-I

Each question carries one mark

1. The is a__________ constant on the order of 5v/m.

1X10=10
[

a) process-independent b) process-dependent c) input variable d) gain


2. ICs are functional irrespective of accurate knowledge of ____ delays
[
]
a) Logic b) fan-out c) gate
d) rise time
3. During the 70% rise time the pseudo nmos inverter transistor Q2 is in the _____region [
]
a) Saturation b) active c) cut-off d) linear
4. Nmos logic has practically disappeared due to its_________
[ ]
a) Less logic b) more area c) speed d) power dissipation
5. The Output High Voltage(VOH) for two input NOR gate with depletion nmos loads is
_____
[ ]
a) VDD b) Ground
c) Vth d) Vtp
6. The threshold voltage of NOR2 gate in CMOS logic is______ [ ]
a) 1.5V b) 2V c) 2.5V d) 3V
7. The AOI gate enables the_______ realization of a Boolean function in one logic stage
[ ]
a) Products
b) sums c) SOP d) POS
8. The eight-transistor implementation of the logic XOR function uses___CMOS TGs and
___CMOS inverters
[ ]
a)one, three b) one, one c) two, two d) two, one
9. In CMOS Transmission gates, the output voltage is Vout>(VDD-VT,n), the nmos transistor
will be ___________
[ ]
a)Saturation b) linear c) cut-off d) turned-off
10. Feedback loop exists in which type of circuits
[ ]
a) Sequential b) combinational c) analog d) digital

SECTION-II
Answer any Three of the following

5X3=15

1. a) Explain about Pseudo-Nmos logic and derive inverter threshold Voltage.


b) Find Vth of Pseudo nmos inverter for n/ p=4.2V, Vtn=0.8V, Vtp=-0.9V
(W/L)2/(W/L)1=2 ,VDD=3.3V
2. Derive the gain at the gate threshold voltage of pseudo nmos inverter with smallsignal equivalent circuits
3. Derive the VOL & drain current (ID) for two-input NAND gate with depletion nmos
loads.
4. a) Explain about complex logic circuits in detail with different classes for logic-low
Voltage level.
b) Draw the circuit diagram and LAYOUT for Two input CMOS NAND2 gate
5. a) Draw the Four different representations of CMOS transmission gate(TG)
b) Explain about (i) Transient response
(ii) Rise time
(iii) Fall time

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