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Sahyadri: College of Engineering & Management

This document is a test paper for the course DSP Algorithm and Architecture from Sahyadri College of Engineering & Management. The test contains 3 questions with multiple parts each. Question 1 deals with scaling factors to prevent overflow and Q-notation used in DSP algorithms. Question 2 involves writing a TMS320C54XX program for an interpolating FIR filter and deriving an expression for a butterfly structure signal flow graph. Question 3 covers timing diagrams for memory interfaces, generating bit reversed addresses, and representing numbers in Q15 and Q7 format.

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45 views1 page

Sahyadri: College of Engineering & Management

This document is a test paper for the course DSP Algorithm and Architecture from Sahyadri College of Engineering & Management. The test contains 3 questions with multiple parts each. Question 1 deals with scaling factors to prevent overflow and Q-notation used in DSP algorithms. Question 2 involves writing a TMS320C54XX program for an interpolating FIR filter and deriving an expression for a butterfly structure signal flow graph. Question 3 covers timing diagrams for memory interfaces, generating bit reversed addresses, and representing numbers in Q15 and Q7 format.

Uploaded by

saralabitm
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOC, PDF, TXT or read online on Scribd
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SAHYADRI

COLLEGE OF ENGINEERING & MANAGEMENT


DEPARTMENT OF ELECTRONICS & COMMUNICATION

DSP Algorithm and Architecture (06EC74)


Test: I

Date: 11-10-2012

Max.Marks: 25

Sem: 7

TH

Duration: 1.15 Hour


Faculty: Mr. Praveen

NOTE: Answer any TWO full questions

Determine the optimum scaling factor to prevent overflow.

4 Marks

What do you mean by Q-notation used in DSP algorithm

6 Marks

implementation? Write program to multiply two Q15 numbers.


Describe the operation of the following instructions of

2.5 Marks

TMS320C54XX processors. i) MPY *AR2- , AR4+0,B


2

ii)MAS *AR3- , AR4+ , B , A iii)SSBX SXM


Write
TMS320C54XX
program
that

illustrates

the

implementation of an interpolating FIR filter of length 15 and

6.5 Marks

interpolating factor 5.
b

Sketch a signal flow graph for general Butterfly structure. Derive

6 Marks

expression for the same.


3

Draw the timing diagram for memory interface for read-read-

5 Marks

write sequence of operation. Explain the purpose of each signal


involved
b

Write the subroutine for bit reverse address generation. Explain

5 Marks

the same.
c

Represent each of the following in Q15 and Q7 format. i)4400


ii)0.3125

2.5 marks

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