The TEST instruction in x86 assembly performs a bitwise AND operation on two operands and modifies the flags SF, ZF, PF without storing the result. It can compare values of different sizes, like 8-bit, 16-bit, 32-bit or 64-bit registers, immediate values, or register indirect values. The OF and CF flags are set to 0, while the AF flag is undefined. There are 9 opcodes depending on the operand types and sizes.
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The TEST instruction in x86 assembly performs a bitwise AND operation on two operands and modifies the flags SF, ZF, PF without storing the result. It can compare values of different sizes, like 8-bit, 16-bit, 32-bit or 64-bit registers, immediate values, or register indirect values. The OF and CF flags are set to 0, while the AF flag is undefined. There are 9 opcodes depending on the operand types and sizes.
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TEST (x86 instruction)
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In the x86 assembly language, the TEST instruction performs a bitwise AND on two operands. The flags SF, ZF, PF are modified while the result of the AND is discarded. The OF and CF flags are set to 0, while AF flag is undefined. There are 9 different opcodes for the TEST instruction depending on the type and size of the operands. It can compare 8-bit, 16-bit, 32-bit or 64-bit values. It can also compare registers, immediate values and register indirect values.[1]
TEST opcode variations[edit]
The TEST operation sets the flags CF and OF to zero. The SF is set to the MSB of the result of the AND. If the result of the AND is 0, the ZF is set to 1, otherwise set to 0. The parity flag is set to the bitwise XNOR of the result of the AND. The value of AF is undefined.