VLSI Architecture Project Report

on

8-bit Microprocessor

SUBMITTED BY:
S. Raviteja Raju (2014H123158P)
Suhas.B (2014H123167P)
R.Sureshkumar (2014H123165P)

SUBMITTED TO:
Dr. S GURUNARAYANAN
Mr. KAVINDRA KANDPAL

Page | 1

Table of Contents
Design of General Purpose Microprocessor ................................................................................................................ 3
Introduction:............................................................................................................................................................... 3
Instruction Set: ........................................................................................................................................................... 3
Design of Control Unit: ............................................................................................................................................... 4
Design of Datapath Unit: ............................................................................................................................................ 6
Verilog Code: .............................................................................................................................................................. 7
Test Bench ................................................................................................................................................................ 21
Instruction Set used for testing the Processor .............................................................................................................. 22
Simulation Results ........................................................................................................................................................ 23
Test Bench results ......................................................................................................................................................... 27
RTL Synthesis Using RC COMPILER: ........................................................................................................................... 29
Area Report: ................................................................................................................................................................. 32
Power Report: ............................................................................................................................................................... 32
Timing Report: .............................................................................................................................................................. 32
Floorplanning and Physical Synthesis: ...................................................................................................................... 33
Floorplanning: .............................................................................................................................................................. 33
Layout ........................................................................................................................................................................... 34
Area Report: ................................................................................................................................................................ 35
Power Report: ............................................................................................................................................................... 35
Timing Report ............................................................................................................................................................... 35

Page | 2

Design of General Purpose Microprocessor

Introduction:
General purpose processors (GPP) are designed for general purpose
computers such as PCs or workstations. The computation speed of a GPP is the main
concern and the cost of the GPP is usually much higher than that of DSPs and
microcontrollers.
In this project, an 8-bit general purpose microprocessor has been
implemented. It offers commonly required eight 8-bit instructions which are load,
store, add, subtract, input, jump if zero, jump if positive and halt respectively.
The processor is divided into two blocks:
1) Control Unit and
2) Data path Unit
Instruction Set:
The instruction set for the general purpose microprocessor has eight
instructions as shown in figure below.

Page | 3

Design of Control Unit:

Start
0000

Fetch
0001

decode
0010

load
0011

Store
0100

Add
0101

Sub
0110

Input
0111

JZ
1000

JPOS
1001

Halt
1010

Fig: State Diagram Showing different states of Control unit

Page | 4

Current
State
Q3Q2Q1Q0
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010

000
0001
0010
0011
0000
0000
0000
0000
0000
0000
0000
1010

Control
State
Word Q3Q2Q1Q0
0000
0
Start
0001
1
Fetch
0010
2
Decode
0011
3
Load
0100
4
Store
0101
5
Add
0110
6
Sub
0111
7
IN

001
0001
0010
0100
0000
0000
0000
0000
0000
0000
0000
1010

D3D2D1D0
IR7 IR6 IR5
011
100
0001
0001
0010
0010
0110
0111
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
1010
1010

010
0001
0010
0101
0000
0000
0000
0000
0000
0000
0000
1010

101
0001
0010
1000
0000
0000
0000
0000
0000
0000
0000
1010

110
0001
0010
1001
0000
0000
0000
0000
0000
0000
0000
1010

111
0001
0010
1010
0000
0000
0000
0000
0000
0000
0000
1010

IR
Load

PC
Load

MemInst

Asel

MemWr

Aload

Sub

JmpMux

Halt

00

00

00

10

00

00

00

01

00

00

00

1000
JZ

1001
JPOS

10

1010
Halt

If
Aeq0=1
then 1,
Else 0
If
Apos=1
then 1,
Else 0
0

Page | 5

Design of Datapath Unit:

Page | 6

Verilog Code:
`timescale 1ps / 1ps
// Top Module
module processor(clock,Reset,Input,Halt,Output);
input clock,Reset;
input [7:0]Input;
output Halt;
output [7:0]Output;

wire IRload, JMPmux, PCload, Meminst, Memwr, Aload, Sub,Aeq0, Apos;

wire [7:0] IR;
wire [1:0] Asel;
wire [4:0] PC;
wire [3:0] q;

datapath data1(clock,Reset,PC,Input,IRload, JMPmux, PCload, Meminst, Memwr, Aload,

Sub,IR,Aeq0, Apos,Asel,Output);

control_unit control1(clock,Reset,Halt,q,IR,IRload, JMPmux, PCload, Meminst, Memwr, Aload,

Sub,IR,Aeq0, Apos,Asel);

endmodule

Page | 7

// Datapath
module datapath(clock,Reset,PC,Input,IRload, JMPmux, PCload, Meminst, Memwr, Aload,
Sub,IR,Aeq0, Apos,Asel,Output);
input IRload, JMPmux, PCload, Meminst, Memwr, Aload, Sub;
input Reset, clock;
output Aeq0,Apos;
input [1:0]Asel;
input [7:0] Input;
input [4:0] PC;
output [7:0] IR;
output [7:0] Output;

wire Aeq0, Apos;

wire [4:0] ADDR;
wire [7:0] in_m, out_m, sum;
wire cout;
wire [7:0] A_in, Aout;
wire [4:0] to_PC,PC_mux;
wire [7:0] IR_in;

ram mem1(clock, ADDR, Memwr, in_m, out_m);

register IR1(clock, Reset, IRload, IR_in, IR);

// memory
// instruction register

mux_2x1 mux1(JMPmux, IR[4:0],to_PC , PC_mux);

sequence

// Mux to select jump / normal

Page | 8

PC_register PC1(clock, Reset, PCload, PC_mux, PC);

Incrementer PC_incr(PC, to_PC);

// program counter

// Incrementing program counter

mux_2x1 mux2(Meminst, IR[4:0], PC, ADDR);

// to select mem instruc or normal instruc

mux_4x1 mux3(Asel, sum, Input, out_m, 8'b00000000, A_in); // to select from where operand
comes to accumulator
register Acc(clock, Reset, Aload, A_in, Aout);
n_bit_addsub arith(Sub, Aout, out_m, sum, cout);

// Accumulator register
// Add_sub unit

assign Aeq0 = ~(|Aout);

assign Apos = ~(Aout[7]);
assign IR_in= out_m;
assign Output= Aout;
assign in_m= Aout;
endmodule

//DATAPATH Ends

// Control Unit
module control_unit(clock,Reset,Halt,q,IR,IRload, JMPmux, PCload, Meminst, Memwr, Aload,
Sub,IR,Aeq0, Apos,Asel);

input clock,Reset;
input [7:0] IR;
output IRload, JMPmux, PCload, Meminst, Memwr, Aload, Sub,Aeq0, Apos;
output [1:0]Asel;
output Halt;
Page | 9

input [3:0]q;
wire [3:0]q_b;
wire [7:5]IR_b;
wire [4:0]PC_mux;
wire [3:0]D;
and a1(d_1,q_b[3],q_b[2],q[1],q_b[0]);
and a2(d_2,q[3],q_b[2],q[1],q_b[0]);
and a3(d_3,q_b[3],q_b[2],q_b[1],q[0]);
and a4(d_4,q_b[3],q_b[2],q_b[1],q_b[0]);

//D3
or o1(d3_1,IR[5],IR[6]);
and a5(d3_2,d_1,d3_1,IR[7]);
or o2(D[3],d3_2,d_2);
//D2
not n3(IR_b[7],IR[7]);
and a6(d2_1,d3_1,IR_b[7]);
not n4(IR_b[6],IR[6]);
not n5(IR_b[5],IR[5]);
and a7(d2_2,IR[7],IR_b[6],IR_b[5]);
or o3(d2_3,d2_1,d2_2);
and a8(D[2],d_1,d2_3);

Page | 10

//D1
xnor x1(d1_1,IR[5],IR[6]);
and a9(d1_2,d1_1,d_1);
or o4(D[1],d1_2,d_3,d_2);
//D0
and a10(d0_1,IR_b[6],IR_b[5]);
and a11(d0_2,IR[6],IR_b[5]);
or o5(d0_3,d0_1,d0_2);
and a12(d0_4,d0_3,d_1);
or o6(D[0],d0_4,d_4);
//D0
D_FF D_FF3(D[3],clock,Reset,q[3],q_b[3]);
D_FF D_FF2(D[2],clock,Reset,q[2],q_b[2]);
D_FF D_FF1(D[1],clock,Reset,q[1],q_b[1]);
D_FF D_FF0(D[0],clock,Reset,q[0],q_b[0]);

assign IRload = d_3;

//PCload
and a13(d_5,q[3],q_b[2],q_b[1],q_b[0]);
and a14(d_6,q[3],q_b[2],q_b[1],q[0]);
and a15(p_1,d_5,Aeq0);
and a16(p_2,d_6,Apos);
or o7(PCload,d_3,p_1,p_2);

Page | 11

//Meminst
and a17(d_7,q_b[3],q_b[2],q[1],q[0]);
and a18(d_8,q_b[3],q[2],q_b[1],q_b[0]);
and a19(d_9,q_b[3],q[2],q_b[1],q[0]);
and a20(d_10,q_b[3],q[2],q[1],q_b[0]);
or o8(Meminst,q[3],q[2],q[1]);
assign Memwr = d_8;

//Aload
and a21(d_11,q_b[3],q[2],q[1],q[0]);
or o9(Aload,d_7,d_9,d_10,d_11);
assign Sub = d_10;
or o10(JMPmux,d_5,d_6);

assign Halt = d_2;

assign Asel[1]=d_7;
assign Asel[0]=d_11;
endmodule

module mux_2x1(sel, in1, in0, out);

input sel;
input [4:0] in0, in1;
output [4:0] out;

Page | 12

reg [4:0]out;
always @(*)
begin
case(sel)
1'b0:out=in0;
1'b1:out=in1;
endcase
end
endmodule

module mux_4x1(sel, in0, in1, in2, in3, out);

input [1:0] sel;
input [7:0] in0, in1, in2, in3;
output [7:0] out;
reg [7:0] out;
always @(*)
begin
case(sel)
2'b00:out=in0;
2'b01:out=in1;
2'b10:out=in2;
2'b11:out=in3;
endcase

Page | 13

end
endmodule

module register(clk, rst, en, in, out);

input clk, rst, en;
input [7:0] in;
output [7:0] out;
wire [7:0] out;
genvar i;
generate for(i=0; i<8; i=i+1)
begin : register
DFF D( clk, rst, en, in[i], out[i]);
end
endgenerate
endmodule

module DFF(clk, rst, en, d, q);

input rst, clk, en, d;
output q;
reg q;
always @(posedge clk, rst)
begin
if (rst == 1)

Page | 14

q= 1'b0;
else if (en == 1)
q= d;
end
endmodule
// PC Register
module PC_register(clk, rst, en, in, out);
input clk, rst, en;
input [4:0] in;
output [4:0] out;
wire [4:0] out;
genvar i;
generate for(i=0; i<5; i=i+1)
begin : register
DFF D( clk, rst, en, in[i], out[i]);
end
endgenerate
endmodule
// PC Incrementer
module Incrementer(in , out);
input [4:0] in;
output [4:0] out;

Page | 15

assign out = in + 5'b00001;

endmodule

// Ram module
module ram(clk, addr, we, din, dout);
input clk,we;
input [4:0] addr;
input [7:0] din;
output reg[7:0] dout;
reg [7:0] mem[31:0];

initial
begin
mem[0] = 8'b00010000;
mem[1] = 8'b01010001;
mem[2] = 8'b01110001;
mem[3] = 8'b10011111;
mem[4] = 8'b10110010;
mem[5] = 8'b00010000;
mem[16] = 8'b10101010;
mem[17] = 8'b01010101;
mem[18] = 8'b00010000;
mem[19] = 8'b11000000;

Page | 16

mem[20] = 8'b00010001;
mem[21] = 8'b11000000;
end

always @(posedge clk)

begin
if (we)
mem[addr] = din;
else
dout = mem[addr];
end
endmodule

// Adder_sub module
module n_bit_addsub(add_sub, a, b, s, cout
);
parameter n =8;

input [n-1:0] a;
input [n-1:0] b;
input add_sub;
output [n-1:0] s;
output cout;

Page | 17

wire [n-1:0] a;
wire [n-1:0] b;
wire add_sub;
wire [n-1:0] s;
wire cout;
wire [n:0]c;
wire [n-1:0]d;

// xor of 'b' and control signal

//if add_sub=0, then add

//if add_sub=1, then 2's com sub
assign c[0] = add_sub;

// assign conditional value to c[0]

generate
genvar i;
// Generalized n bit ripple carry adder
for(i=0;i<n;i=i+1)
begin : nbit
xor (d[i],b[i],add_sub);
FA FAn(a[i],d[i],c[i],s[i],c[i+1]);
end
endgenerate
assign cout=c[n];
endmodule

Page | 18

module FA(a,b,c,s,co
);
input a;
input b;
input c;
output s;
output co;
wire a,b,c;
reg s,co;

always @(a or b or c)
begin
s = a ^ b ^ c;
co = (a & b) | (b & c) | (c & a);
end
endmodule

module D_FF(d,clk,clear,q,q_b);
input d,clk,clear;
output q,q_b;
wire d,clk,clear;
reg q,q_b;

Page | 19

always @(posedge clk,clear)

begin
if (clear)
begin
q = 1'b0;
q_b = 1'b1;
end
else if(clk)
begin
q = d;
q_b = ~d;
end
end
endmodule

Page | 20

Test Bench
module test_bench();
reg clock,Reset;
reg [7:0] Input;
wire Halt;
wire [7:0] Output;
processor2 proc_test(clock,Reset,Input,Halt,Output);
initial
begin
clock =1;
Reset =1;
Input =8'b01010101;
#2 Reset =0;
#120 $finish;
end
always
#1 clock = ~clock;
always
#2 $display($time, " clock = %b, reset = %b, Input = %b, Halt = %b, Output =
%b",clock,Reset,Input,Halt,Output);
endmodule

Page | 21

Instruction Set used for testing the Processor

mem[0] = 8'b00010000; //Load A with contents of memory 10000
mem[1] = 8'b00110001; //Store memory 10001 with contents of A
mem[2] = 8'b01010010; //Add A with contents of memory 10010
mem[3] = 8'b01110001; // Subtract A with contents of memory 10001
mem[4] = 8'b10011111; //Input A, here we are giving 01010101
mem[5] = 8'b10100000; //Jump on Zero to address 00000
mem[6] = 8'b01110000; // Subtract A with contents of memory 10000
mem[7] = 8'b10101010; //Jump on Zero to address 01010
mem[8] = 8'b00010000; //Load A with contents of memory 10000
mem[9] = 8'b11110000; //halt
mem[10] = 8'b00010010; //Load A with contents of memory 10010
mem[11] = 8'b11000000; //Jump on positive to memory 00000
mem[12] = 8'b00010000; //Load A with contents of memory 10000
mem[13] = 8'b11001000; // Jump on positive to memory 01000

mem[16] = 8'b01010101; //data stored

mem[18] = 8'b10101010; // data stored

Page | 22

Simulation Results

Page | 23

Page | 24

Page | 25

Page | 26

Test Bench results

2 clock = 0, reset = 0, Input = 01010101, Halt = 0, Output = 00000000
4 clock = 0, reset = 0, Input = 01010101, Halt = 0, Output = 00000000
6 clock = 0, reset = 0, Input = 01010101, Halt = 0, Output = 00000000
8 clock = 0, reset = 0, Input = 01010101, Halt = 0, Output = 00000000
10 clock = 0, reset = 0, Input = 01010101, Halt = 0, Output = 01010101
12 clock = 0, reset = 0, Input = 01010101, Halt = 0, Output = 01010101
14 clock = 0, reset = 0, Input = 01010101, Halt = 0, Output = 01010101
16 clock = 0, reset = 0, Input = 01010101, Halt = 0, Output = 01010101
18 clock = 0, reset = 0, Input = 01010101, Halt = 0, Output = 01010101
20 clock = 0, reset = 0, Input = 01010101, Halt = 0, Output = 01010101
22 clock = 0, reset = 0, Input = 01010101, Halt = 0, Output = 01010101
24 clock = 0, reset = 0, Input = 01010101, Halt = 0, Output = 01010101
26 clock = 0, reset = 0, Input = 01010101, Halt = 0, Output = 11111111
28 clock = 0, reset = 0, Input = 01010101, Halt = 0, Output = 11111111
30 clock = 0, reset = 0, Input = 01010101, Halt = 0, Output = 11111111
32 clock = 0, reset = 0, Input = 01010101, Halt = 0, Output = 11111111
34 clock = 0, reset = 0, Input = 01010101, Halt = 0, Output = 10101010
36 clock = 0, reset = 0, Input = 01010101, Halt = 0, Output = 10101010
38 clock = 0, reset = 0, Input = 01010101, Halt = 0, Output = 10101010
40 clock = 0, reset = 0, Input = 01010101, Halt = 0, Output = 10101010
42 clock = 0, reset = 0, Input = 01010101, Halt = 0, Output = 01010101
44 clock = 0, reset = 0, Input = 01010101, Halt = 0, Output = 01010101
46 clock = 0, reset = 0, Input = 01010101, Halt = 0, Output = 01010101
48 clock = 0, reset = 0, Input = 01010101, Halt = 0, Output = 01010101
50 clock = 0, reset = 0, Input = 01010101, Halt = 0, Output = 01010101
52 clock = 0, reset = 0, Input = 01010101, Halt = 0, Output = 01010101
54 clock = 0, reset = 0, Input = 01010101, Halt = 0, Output = 01010101
56 clock = 0, reset = 0, Input = 01010101, Halt = 0, Output = 01010101
58 clock = 0, reset = 0, Input = 01010101, Halt = 0, Output = 00000000
60 clock = 0, reset = 0, Input = 01010101, Halt = 0, Output = 00000000
62 clock = 0, reset = 0, Input = 01010101, Halt = 0, Output = 00000000
64 clock = 0, reset = 0, Input = 01010101, Halt = 0, Output = 00000000
66 clock = 0, reset = 0, Input = 01010101, Halt = 0, Output = 00000000
68 clock = 0, reset = 0, Input = 01010101, Halt = 0, Output = 00000000
70 clock = 0, reset = 0, Input = 01010101, Halt = 0, Output = 00000000
72 clock = 0, reset = 0, Input = 01010101, Halt = 0, Output = 00000000
74 clock = 0, reset = 0, Input = 01010101, Halt = 0, Output = 10101010
76 clock = 0, reset = 0, Input = 01010101, Halt = 0, Output = 10101010
78 clock = 0, reset = 0, Input = 01010101, Halt = 0, Output = 10101010
80 clock = 0, reset = 0, Input = 01010101, Halt = 0, Output = 10101010
82 clock = 0, reset = 0, Input = 01010101, Halt = 0, Output = 10101010
84 clock = 0, reset = 0, Input = 01010101, Halt = 0, Output = 10101010
86 clock = 0, reset = 0, Input = 01010101, Halt = 0, Output = 10101010
88 clock = 0, reset = 0, Input = 01010101, Halt = 0, Output = 10101010
Page | 27

90 clock = 0, reset = 0, Input = 01010101, Halt = 0, Output = 01010101

92 clock = 0, reset = 0, Input = 01010101, Halt = 0, Output = 01010101
94 clock = 0, reset = 0, Input = 01010101, Halt = 0, Output = 01010101
96 clock = 0, reset = 0, Input = 01010101, Halt = 0, Output = 01010101
98 clock = 0, reset = 0, Input = 01010101, Halt = 0, Output = 01010101
100 clock = 0, reset = 0, Input = 01010101, Halt = 0, Output = 01010101
102 clock = 0, reset = 0, Input = 01010101, Halt = 0, Output = 01010101
104 clock = 0, reset = 0, Input = 01010101, Halt = 0, Output = 01010101
106 clock = 0, reset = 0, Input = 01010101, Halt = 0, Output = 01010101
108 clock = 0, reset = 0, Input = 01010101, Halt = 0, Output = 01010101
110 clock = 0, reset = 0, Input = 01010101, Halt = 0, Output = 01010101
112 clock = 0, reset = 0, Input = 01010101, Halt = 1, Output = 01010101
114 clock = 0, reset = 0, Input = 01010101, Halt = 1, Output = 01010101
116 clock = 0, reset = 0, Input = 01010101, Halt = 1, Output = 01010101
118 clock = 0, reset = 0, Input = 01010101, Halt = 1, Output = 01010101
120 clock = 0, reset = 0, Input = 01010101, Halt = 1, Output = 01010101

Page | 28

RTL Synthesis Using RC COMPILER:

Fig: RTL View of Main Processor Block

Fig: RTL view of Control Unit

Page | 29

Fig: RTL View of Datapath Unit

Fig. PC Register

Page | 30

Fig. Accumulator Register

Page | 31

Area Report:

Instance

Cells

Processor

698

Cell Area
9259

Net Area

Wire load

enG5K (S)

Power Report:

Instance

Cells

Leakage
Power(nW)

Dynamic
Power(nW)

Total
Power(nW)

Processor

698

25.895

759190.761

759216.656

Timing Report:

Clock Period(ps)
4000

Arrival
Time (ps)
3555

Slack (ps)
445

Page | 32

Floorplanning and Physical Synthesis:

Using SOC Encounter floorplanning and physical synthesis of the processor designed is done. Here
the .sdc and the NL.v files required for synthesis are taken from RC Compiler.

Floorplanning:

Fig. Modules on Core

The above figure shows the placement of the modules Datapath and Control Unit on the core. As
we can see from figure almost 90% of chip core is occupied.

Page | 33

Layout

Fig. Layout of Processor

The above figure shows the layout of the 8-bit processor designed. While making the layout using
SOC Encounter the h/w ratio is kept as 1 and the core utilization factor is kept 0.95 so that maximum part
of the core is utilized and the final density is very high.

Page | 34

Area Report:
Instance

Area of Standard
cells
7259.056 um2

Processor

Area of Core

Area of Chip

7890.554 um2

11015.013 um2

Power Report:
Instance
Processor

Internal Power
(mW)
0.6754

Total Switching
Power(mW)
0.09035

Total Leakage
Power(mW)
2.563e-05

Total Power
(mW)
0.7658

Timing Report
Here the clock used is 4000ps.

Instance
Processor
Pre CTS
Post Route

Arrival Time(ps)
3.015
3.158

Slack Time(ps)
0.750
0.606

Page | 35