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FPGA Implementation of Universal Asynchronous Receiver and Transmitter (UART)

The document describes the implementation of a Universal Asynchronous Receiver and Transmitter (UART) on an FPGA. It provides details on serial data transfer, UART parameters, the design process including block diagrams, state machines and HDL code for the receiver subsystem. It also discusses testing the UART circuit using HyperTerminal.

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100 views13 pages

FPGA Implementation of Universal Asynchronous Receiver and Transmitter (UART)

The document describes the implementation of a Universal Asynchronous Receiver and Transmitter (UART) on an FPGA. It provides details on serial data transfer, UART parameters, the design process including block diagrams, state machines and HDL code for the receiver subsystem. It also discusses testing the UART circuit using HyperTerminal.

Uploaded by

VaseaPupchin
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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ECE 428 Programmable ASIC Design

FPGA Implementation of Universal Asynchronous


Receiver and Transmitter (UART)

Haibo Wang
ECE Department
Southern Illinois University
Carbondale, IL 62901
1-1

Serial Data Transfer


Asynchronous v.s. Synchronous
Asynchronous transfer does not require clock signal. However, it transfers extra bits
(start bits and stop bits) during data communication
Synchronous transfer does not transfer extra bits. However, it requires clock signal
Frame
Asynchronous
Data transfer

Synchronous
Data transfer

data
Start
bit B0 B1 B2 B3 B4

Stop bits
B5 B6
Parity

clk

data
B0

B1

B2

B3

B4

B5
11-2
1-2

Overview of UART and RS-232


Signal swing +10V, -10V
UART
RS232
Trans.shift
Shift Reg.

TxD

D[7:0]
Rec. Shift Reg.

RxD
Ground

Interface

Baud
rate ckt.

Standard logic level

DB9 connector (front view)

Most materials presented here are from FPGA Prototyping by Verilog Examples by Pong Chu.
You can download the UART chapter of the book at: http://academic.csuohio.edu/chu_p/rtl/fpga_vlog.html
1-3

UART Parameters

Signal is 1 (high voltage) when the system is idle


Start bit is placed before the data and, optionally, stop bits are placed at the end of data
Start bit is 0 and stop bits are 1
LSB is first transmitted or received
Baud rate: number of bits per second; frequently used baud rate: 9600, 19,200
Number of Data bits
Stop bits
Whether parity check is enabled?
Multiplication factor for clock, e.g. x8 clk (means baud rate x 8 = system clock freq.)

1-4

How to Assign UART Parameters


Fix the parameters at the design stage (this example)
Make it programmable with using configuration (mode) register
Example: 8251 chip
7

Number of
Stop bits
00:
01:
10:
11:

invalid
1 bit
1.5 bits
2 bits

Mode register

Baud Rate

Parity enable
0: disable
1: enable
Character length

Parity
0: odd
1: even

00:
01:
10:
11:

00: Syn. Mode


01: x1 clock
10: x16 clock
11: x64 clock

5 bits
6 bits
7 bits
8 bits
1-5

Block Diagram of UART Receiving Subsystem

Assume N data bits, M stop bits and fCLK=16*baud rate

1-6

ASMD of UART Receiving Subsystem


FSM (Finite State Machine)
ASM Chart (Algorithmic State Machine)
FSMD (Finite State Machine with Data Path)
ASMD (ASM with data path)

1-7

HDL Coding for UART Receiving Subsystem


The ASMD chart contains four states: idle, start, data, stop

1-8

HDL Coding for UART Receiving Subsystem


Coding for operations within one state

1-9

Clocking Issue of Receiver Design

Should we use s_tick as clock signal or clock enable signal?

Functionally OK

Better
1-10

Interface Circuit of UART Receiving Subsystem

1-11

Complete UART Circuit

1-12

Configure HyperTerminal to test UART Circuit

1-13

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