Basic Computer Organization & Design

Session-7
Memory Reference Instructions

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Recap of Session-6

In Basic Computer, a machine instruction is execute

d in the following cycle:
1. Fetch an instruction from memory
2. Decode the instruction
3. Read the effective address from memory if the ins
truction has an indirect address

4. Execute the instruction

After an instruction is executed, the cycle starts agai
n at step 1, for the next instruction

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Recap of session-6

INSTRUCTION SET COMPLETENESS

A computer should have a set of instructions so that the user can
construct machine language programs to evaluate any function
that is known to be computable.
Instruction Types
Functional Instructions
- Arithmetic, logic, and shift instructions
- ADD, CMA, INC, CIR, CIL, AND, CLA
Transfer Instructions
- Data transfers between the main memory
and the processor registers
- LDA, STA
Control Instructions
- Program sequencing and control
- BUN, BSA, ISZ
Input/Output Instructions
- Input and output
- INP, OUT

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Recap of session-6

DETERMINE THE TYPE OF INSTRUCTION

Start
SC
AR PC

T0

IR M[AR], PC PC + 1

T1
T2

Decode Opcode in IR(12-14),

AR IR(0-11), I IR(15)
(Register or I/O) = 1
(I/O) = 1

I
T3

Execute
input-output
instruction
SC 0

D'7IT3:
D'7I'T3:
D7I'T3:
D7IT3:

D7

= 0 (Memory-reference)

= 0 (register)

(indirect) = 1
T3

Execute
register-reference
instruction
SC 0

T3
AR M[AR]

= 0 (direct)
T3
Nothing

Execute
memory-reference
instruction
SC 0

T4

AR M[AR]
Nothing
Execute a register-reference instr.
Execute an input-output instr.

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Recap of session-6

REGISTER REFERENCE INSTRUCTIONS

Register Reference Instructions are identified when
- D7 = 1, I = 0
- Register Ref. Instr. is specified in b0 ~ b11 of IR
- Execution starts with timing signal T3
r = D7 IT3 => Register Reference Instruction
Bi = IR(i) , i=0,1,2,...,11
r:
SC 0
CLA
rB11:
AC 0
CLE
rB10:
E0
CMA
rB9:
AC AC
CME
rB8:
E E
CIR rB7:
AC shr AC, AC(15) E, E AC(0)
CIL rB6:
AC shl AC, AC(0) E, E AC(15)
INC rB5:
AC AC + 1
SPArB4:
if (AC(15) = 0) then (PC PC+1)
SNA
rB3:
if (AC(15) = 1) then (PC PC+1)
SZArB2:
if (AC = 0) then (PC PC+1)
SZErB1:
if (E = 0) then (PC PC+1)

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Session-7:
MEMORY REFERENCE INSTRUCTIONS

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MR Instructions

MEMORY REFERENCE INSTRUCTIONS

Symbol

Operation
Decoder

Symbolic Description

AND
D0 AC AC M[AR]
ADD
D1 AC AC + M[AR], E Cout
LDA
D2 AC M[AR]
STA D3 M[AR] AC
BUN
D4 PC AR
BSA
D5 M[AR] PC, PC AR + 1
ISZ D6 M[AR] M[AR] + 1, if M[AR] + 1 = 0 then PC PC+1
- The effective address of the instruction is in AR and was placed there during
timing signal T2 when I = 0, or during timing signal T3 when I = 1
- Memory cycle is assumed to be short enough to complete in a CPU cycle
- The execution of MR instruction starts with T4
AND to AC
D0T4:
DR M[AR]
Read operand
D0T5:
AC AC DR, SC 0
AND with AC
ADD to AC
D1T4:
DR M[AR]
Read operand
D1T5:
AC AC + DR, E Cout, SC 0 Add to AC and store carry in E
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MEMORY REFERENCE INSTRUCTIONS

LDA: Load to AC
D2T4:
DR M[AR]
D2T5:
AC DR, SC 0
STA: Store AC
D3T4:
M[AR] AC, SC 0
BUN: Branch Unconditionally
D4T4:
PC AR, SC 0
BSA: Branch and Save Return Address
M[AR] PC, PC AR + 1
Memory, PC, AR at time T4

20
PC = 21

BSA

135

Next instruction

AR = 135
136

Subroutine

BUN
Memory

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135

Memory, PC after execution

20

BSA

135

21

Next instruction

135

21
Subroutine

PC = 136

BUN

135

Memory

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MR Instructions

MEMORY REFERENCE INSTRUCTIONS

BSA:
D5T4:
D5T5:

M[AR] PC, AR AR + 1
PC AR, SC 0

ISZ: Increment and Skip-if-Zero

D6T4:
DR M[AR]
D6T5:
DR DR + 1
D6T4:
M[AR] DR, if (DR = 0) then (PC PC + 1), SC 0

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MR Instructions

FLOWCHART FOR MEMORY REFERENCE INSTRUCTIONS

Memory-reference instruction
AND
D0 T 4
DR M[AR]

ADD

LDA

D1 T 4
DR M[AR]

D0 T 5
D1 T 5
AC AC DR
AC AC + DR
SC 0
E Cout
SC 0
BUN

BSA

STA
D2 T 4

DR M[AR]

D 3T 4

M[AR] AC
SC 0

D2 T 5
AC DR
SC 0

ISZ

D4 T 4
D5 T 4
D6 T 4
PC AR
M[AR] PC
DR M[AR]
SC 0
AR AR + 1
D5 T 5
PC AR
SC 0

D6 T 5
DR DR + 1
D6 T 6
M[AR] DR
If (DR = 0)
then (PC PC + 1)
SC 0

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Answer the following

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Session-8

Input/output instructions and Int

errupt

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MR Instructions

Recap of Session-7:
MEMORY REFERENCE INSTRUCTIONS
Symbol

Operation
Decoder

AND
ADD
LDA
STA D3
BUN
BSA
ISZ D6

Symbolic Description

D0 AC AC M[AR]
D1 AC AC + M[AR], E Cout
D2 AC M[AR]
M[AR] AC
D4 PC AR
D5 M[AR] PC, PC AR + 1
M[AR] M[AR] + 1, if M[AR] + 1 = 0 then PC PC+1

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Session-8
Input/output instructions and Interrupt

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I/O and Interrupt

INPUT-OUTPUT AND INTERRUPT

A Terminal with a keyboard and a Printer
Input-Output Configuration
Input-output
terminal
Printer

Serial
communication
interface

Computer
registers and
flip-flops

Receiver
interface

OUTR

FGO

AC

INPR
OUTR
FGI
FGO
IEN

Input register - 8 bits

Output register - 8 bits
Input flag - 1 bit
Output flag - 1 bit
Interrupt enable - 1 bit

Keyboard

Transmitter
interface

INPR

FGI

Serial Communications Path

Parallel Communications Path

- The terminal sends and receives serial information

- The serial info. from the keyboard is shifted into INPR
- The serial info. for the printer is stored in the OUTR
- INPR and OUTR communicate with the terminal
serially and with the AC in parallel.
- The flags are needed to synchronize the timing
difference between I/O device and the computer
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I/O and Interrupt

PROGRAM CONTROLLED DATA TRANSFER

-- CPU --

-- I/O Device --

/* Input */
/* Initially FGI = 0 */
loop: If FGI = 0 goto loop
AC INPR, FGI 0
/* Output */
/* Initially FGO = 1 */
loop: If FGO = 0 goto loop
OUTR AC, FGO 0
FGI=0

loop: If FGI = 1 goto loop

INPR new data, FGI 1
loop: If FGO = 1 goto loop
consume OUTR, FGO 1
FGO=1

Start Input

Start Output

FGI 0
yes

FGI=0

AC Data
yes

no

no

AC INPR
yes

More
Character
no
END

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FGO=0
OUTR AC
FGO 0

yes

More
Character
no
END
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INPUT-OUTPUT INSTRUCTIONS

D7IT3 = p
IR(i) = Bi, i = 6, , 11
p: SC 0
Clear SC
INP pB11:
AC(0-7) INPR, FGI 0
Input char. to AC
OUT
pB10:
OUTR AC(0-7), FGO 0
Output char. from AC
SKI pB9:if(FGI = 1) then (PC PC + 1)
Skip on input flag
SKO
pB8:if(FGO = 1) then (PC PC + 1) Skip on output flag
ION pB7:IEN 1
Interrupt enable on
IOF pB6:IEN 0
Interrupt enable off

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I/O and Interrupt

PROGRAM-CONTROLLED INPUT/OUTPUT
Program-controlled I/O
- Continuous CPU involvement
I/O takes valuable CPU time
- CPU slowed down to I/O speed
- Simple
- Least hardware

Input
LOOP,

SKI DEV
BUN LOOP
INP DEV

Output
LOOP,
LOP,

LDA
SKO
BUN
OUT

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DATA
DEV
LOP
DEV
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INTERRUPT INITIATED INPUT/OUTPUT

- Open communication only when some data has to be passed --> interrupt.
- The I/O interface, instead of the CPU, monitors the I/O device.
- When the interface founds that the I/O device is ready for data transfer,
it generates an interrupt request to the CPU
- Upon detecting an interrupt, the CPU stops momentarily the task
it is doing, branches to the service routine to process the data
transfer, and then returns to the task it was performing.

* IEN (Interrupt-enable flip-flop)

- can be set and cleared by instructions
- when cleared, the computer cannot be interrupted

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I/O and Interrupt

FLOWCHART FOR INTERRUPT CYCLE

R = Interrupt f/f
Instruction cycle

=0

IEN
=1
=1

=1

FGI
=0
FGO
=0

=1

Interrupt cycle
Store return address
in location 0
M[0] PC

Fetch and decode

instructions
Execute
instructions

=0
Branch to location 1
PC 1

IEN 0
R0

R1

- The interrupt cycle is a HW implementation of a branch

and save return address operation.
- At the beginning of the next instruction cycle, the
instruction that is read from memory is in address 1.
- At memory address 1, the programmer must store a branch instruction
that sends the control to an interrupt service routine
- The instruction that returns the control to the original
program is "indirect BUN 0"
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I/O and Interrupt

REGISTER TRANSFER OPERATIONS IN INTERRUPT CYCLE

Memory
Before interrupt
0
1

BUN

1120

Main
Program

255
PC = 256
1120

After interrupt cycle

0
PC = 1 0

Main
Program

255
256
1120

I/O
Program
1

BUN

256
BUN
1120

I/O
Program
0

BUN

Register Transfer Statements for Interrupt Cycle

- R F/F 1 if IEN (FGI + FGO)T0T1T2
T0T1T2 (IEN)(FGI + FGO): R 1
- The fetch and decode phases of the instruction cycle
must be modified Replace T0, T1, T2 with R'T0, R'T1, R'T2
- The interrupt cycle :
RT0:AR 0, TR PC
RT1:M[AR] TR, PC 0
RT2:PC PC + 1, IEN 0, R 0, SC 0

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Answer the following

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Session-9
Design of Basic Computer
Design of accumulator Logic

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Recap of Session-8

Input /Output Instructions

D7IT3 = p
IR(i) = Bi, i = 6, , 11
p: SC 0
Clear SC
INP pB11:
AC(0-7) INPR, FGI 0
Input char. to AC
OUT
pB10:
OUTR AC(0-7), FGO 0
Output char. from AC
SKI pB9:if(FGI = 1) then (PC PC + 1)
Skip on input flag
SKO
pB8:if(FGO = 1) then (PC PC + 1) Skip on output flag
ION pB7:IEN 1
Interrupt enable on
IOF pB6:IEN 0
Interrupt enable off

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COMPLETE COMPUTER DESCRIPTION

Flowchart of Operations
start

SC 0, IEN 0, R 0

=0(Instruction
R
Cycle)
RT0
AR PC
RT1
IR M[AR], PC PC + 1
RT2
AR IR(0~11), I IR(15)
D0...D7 Decode IR(12 ~ 14)
=1(Register or I/O)

=1 (I/O)

=0 (Register)

D7IT3
Execute
I/O
Instruction

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D7IT3
Execute
RR
Instruction

D7

=1(Interrupt
Cycle)

RT0
AR 0, TR PC

RT1
M[AR] TR, PC 0
RT2
PC PC + 1, IEN 0
R 0, SC 0
=0(Memory Ref)

=1(Indir)

D7IT3
AR <- M[AR]

=0(Dir)

D7IT3
Idle

Execute MR
Instruction

D7T4

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COMPLETE COMPUTER DESCRIPTION

ooperations
Fetch
Decode

RT0:
RT1:
RT2:

Indirect
D7IT3:
Interrupt
T0T1T2(IEN)(FGI + FGO):
RT0:
RT1:
Memory-ReferenceRT2:
AND
D0T4:
ADD
D0T5:
D1T4:
LDA
D1T5:
D2T4:
STA
D2T5:
BUN
D3T4:
BSA
D4T4:
ISZ
D5T4:
D5T5:
D6T4:
D6T5:
D6T6:
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Description

Micr

AR PC
IR M[AR], PC PC + 1
D0, ..., D7 Decode IR(12 ~ 14),
AR IR(0 ~ 11), I IR(15)
AR M[AR]
R1
AR 0, TR PC
M[AR] TR, PC 0
PC PC + 1, IEN 0, R 0, SC 0
DR M[AR]
AC AC DR, SC 0
DR M[AR]
AC AC + DR, E Cout, SC 0
DR M[AR]
AC DR, SC 0
M[AR] AC, SC 0
PC AR, SC 0
M[AR] PC, AR AR + 1
PC AR, SC 0
DR M[AR]
DR DR + 1
M[AR] DR, if(DR=0) then (PC PC + 1),
SC 0
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COMPLETE COMPUTER DESCRIPTION

ooperations

Register-Reference
D7IT3 = r
IR(i) = Bi
r:
CLA
rB11:
CLE
rB10:
CMA
rB9:
CME
rB8:
CIR
rB7:
CIL
rB6:
INC
SPA
rB5:
SNA
rB4:
SZA
rB3:
SZE
rB2:
HLT
rB1:
rB0:
Input-Output
D7IT3 = p
INP
IR(i) = Bi
OUT
p:
SKI
pB11:
SKO
pB10:
ION
pB9:
IOF
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Description

Micr

(Common to all register-reference instr)

(i = 0,1,2, ..., 11)
SC 0
AC 0
E0
AC AC
E E
AC shr AC, AC(15) E, E AC(0)
AC shl AC, AC(0) E, E AC(15)
AC AC + 1
If(AC(15) =0) then (PC PC + 1)
If(AC(15) =1) then (PC PC + 1)
If(AC = 0) then (PC PC + 1)
If(E=0) then (PC PC + 1)
S0
(Common to all input-output instructions)
(i = 6,7,8,9,10,11)
SC 0
AC(0-7) INPR, FGI 0
OUTR AC(0-7), FGO 0
If(FGI=1) then (PC PC + 1)
If(FGO=1) then (PC PC + 1)
IEN 1
IEN 0
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Design of Basic Computer

DESIGN OF BASIC COMPUTER(BC)

Hardware Components of BC
A memory unit: 4096 x 16.
Registers:
AR, PC, DR, AC, IR, TR, OUTR, INPR, and SC
Flip-Flops(Status):
I, S, E, R, IEN, FGI, and FGO
Decoders:
a 3x8 Opcode decoder
a 4x16 timing decoder
Common bus: 16 bits
Control logic gates:
Adder and Logic circuit: Connected to AC
Control Logic Gates
- Input Controls of the nine registers
- Read and Write Controls of memory
- Set, Clear, or Complement Controls of the flip-flops
- S2, S1, S0 Controls to select a register for the bus
- AC, and Adder and Logic circuit
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Design of Basic Computer

CONTROL OF REGISTERS AND MEMORY

Address Register; AR
Scan all of the register transfer statements that change the content of AR:
RT0:
AR PC
LD(AR)
RT2:
AR IR(0-11) LD(AR)
D7IT3: AR M[AR]
LD(AR)
RT0:
AR 0
CLR(AR)
D5T4: AR AR + 1
INR(AR)
LD(AR) = R'T0 + R'T2 + D'7IT3
CLR(AR) = RT0
INR(AR) = D5T4

T2

D'7
I
T3

From bus

12

12

AR

To bus
Clock

LD
INR
CLR

R
T0
D
T4

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Design of Basic Computer

CONTROL OF FLAGS
IEN: Interrupt Enable Flag
pB7: IEN 1 (I/O Instruction)
pB6: IEN 0 (I/O Instruction)
RT2: IEN 0 (Interrupt)
p = D7IT3 (Input/Output Instruction)

D
I

T3

p
B7
B6

IEN

R
T2

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Design of Basic Computer

CONTROL OF COMMON BUS

x1
x2
x3
x4
x5
x6
x7

S2
Encoder

S1
S0

x1 x2 x3 x4 x5 x6 x7
0
1
0
0
0
0
0
0

For AR

0
0
1
0
0
0
0
0

0
0
0
1
0
0
0
0

0
0
0
0
1
0
0
0

0
0
0
0
0
1
0
0

0
0
0
0
0
0
1
0

0
0
0
0
0
0
0
1

S2 S1 S0
0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

Multiplexer
bus select
inputs

selected
register
none
AR
PC
DR
AC
IR
TR
Memory

D4T4: PC AR
D5T5: PC AR

x1 = D4T4 + D5T5
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Design of AC Logic

DESIGN OF ACCUMULATOR LOGIC

Circuits associated with AC
From DR
From INPR

16
16
8

Adder and
logic
circuit

16

16

AC

To bus
LD

INR

CLR

Clock

Control
gates

All the statements that change the content of AC

D0T5:
AC AC DR
AND with DR
D1T5:
AC AC + DR
Add with DR
D2T5:
AC DR
Transfer from DR
pB11:
AC(0-7) INPR
Transfer from INPR
rB9: AC AC
Complement
rB7 : AC shr AC, AC(15) E Shift right
rB6 : AC shl AC, AC(0) E
Shift left
rB11 :
AC 0
Clear
rB5 : AC AC + 1
Increment
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Design of AC Logic

CONTROL OF AC REGISTER
Gate structures for controlling
the LD, INR, and CLR of AC
From Adder
and Logic
D0
T5
D1

AND

D2
T5
p
B 11
r
B9

DR

B7
B6
B5

ADD

16

16

AC

To bus
Clock

LD
INR

CLR

INPR
COM
SHR
SHL
INC
CLR

B 11
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Design of AC Logic

ALU (ADDER AND LOGIC CIRCUIT)

One stage of Adder and Logic circuit

DR(i)

AC(i)
AND
Ci

Ii

FA
C i+1
From
INPR
bit(i)

LD

ADD

DR
INPR

AC(i)

COM
SHR

AC(i+1)
SHL
AC(i-1)

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Answer the following

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