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This document discusses system-on-chip (SOC) testing. It introduces SOC and built-in self-test (BIST), which uses linear feedback shift registers (LFSRs) to generate test patterns. It then describes a technique for low power test pattern generation using LP-LFSRs. The document simulations the standard LFSR and LP-LFSR techniques on benchmark circuits and compares their power consumption, finding that LP-LFSR reduces power. It concludes and discusses potential future work.

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Teja Patti
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35 views4 pages

Index For Sample

This document discusses system-on-chip (SOC) testing. It introduces SOC and built-in self-test (BIST), which uses linear feedback shift registers (LFSRs) to generate test patterns. It then describes a technique for low power test pattern generation using LP-LFSRs. The document simulations the standard LFSR and LP-LFSR techniques on benchmark circuits and compares their power consumption, finding that LP-LFSR reduces power. It concludes and discusses potential future work.

Uploaded by

Teja Patti
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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CHAPTER I

INTRODUCTION

1.1

INTRODUCTION TO SYSTEM-ON-CHIP (SOC)

1.2

LINEAR FEEDBACK SHIFT REGISTERS (LFSR )

1.3

INTRODUCTION TO BIST

1.4

INTRODUCTION TO VLSI

1.4.1 OVERVIEW

1.4.2 What is VLSI?

1.4.3Applications

1.4.4 ASIC

CHAPTER II SOC BACKGROUND


2.1

SOC

2.2

SOC Attributes

10

2.3
2.4
2.5
2.6

SOC Design Tools and Methodology


SOC Power Consumption
SOC Manufacturing Processes
SOC Test and Assembly

11

CHAPTER III
3.1

12
14
16

SOC TEST

SOC TEST

3.2 SOC Test Tools and Methodology


3.3 Test Approaches (External and Conventional DFT)
3.4

Built-In-Self-Test (BIST)

3.5

BIST Pattern Generation Using LFSR

240
2
2
2
3
2
4

CHAPTER IV

LOW POWER PATTERNGENERATION

2
5
2

4.1

Idea Behind Low Power Test Pattern Generation

32

4.2

A Technique to Produce Low Power


Pattern for BIST
Benchmark Design Circuits
Braun Array multiplier

33

4.3
4.4
4.5

37
42

Working of a project

43

CHAPTER V IMPLEMENTATION AND RESULTS


5.1

Simulation Using Standard LFSR Pattern

5.2

Simulation Using LP-LFSR

5.3

Power Consumption Using standard LFSR

5.4

Power Consumption Using LP-LFSR

5.5

Power Consumption Comparison

(Standard LFSR versus LP-LFSR)


5.6

Summary

53
CHAPTER VI CONCLUSION AND FUTURE WORK
6.1

Conclusion

56
6.2

Future

work

57
BIBLIOGRAPHY
58

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