Mohd Anvar

Al- Ameen Engg. College

Programmable Logic Devices

Mohammed Anvar P.K
AP/ECE
Al-Ameen Engineering College

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Mohd Anvar

PLDs

Programmable Logic Devices (PLD)

General purpose chip for implementing circuits
Can be customized using programmable switches

Main types of PLDs

PLA
PAL
ROM
CPLD
FPGA

Custom chips: standard cells, sea of gates

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ROM, PAL and PLA Configurations

Mohd Anvar

Al- Ameen Engg. College

Fixed
AND array
(decoder)

Inputs

Programmable
Connections

Programmable
OR array

Outputs

(a) Programmable read-only memory (PROM)

Inputs

Programmable
Connections

Programmable
AND array

Fixed
OR array

Outputs

(b) Programmable array logic (PAL) device

Inputs

Programmable
Connections

Programmable
AND array

Programmable
Connections

Programmable
OR array

(c) Programmable logic array (PLA) device

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Outputs

Mohd Anvar

Al- Ameen Engg. College

Programmable Logic Array (PLA)

Use to implement
circuits in SOP form
The connections in
the AND plane are
programmable
The connections in
the OR plane are
programmable

x1 x2

xn

Input buffers
and
inverters
x1 x1

xn xn
P1

AND plane

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OR plane
Pk

f1

fm

Mohd Anvar

Al- Ameen Engg. College

Gate Level Version of PLA

x1

x2

x3

Programmable
connections

f1 = x1x2+x1x3'+x1'x2'x3

OR plane

P1

f2 = x1x2+x1'x2'x3+x1x3
P2

P3

P4

AND plane

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f1

f2

Mohd Anvar

Al- Ameen Engg. College

Customary Schematic of a PLA

x1

x2

x3

OR plane

f1 = x1x2+x1x3'+x1'x2'x3

P1

f2 = x1x2+x1'x2'x3+x1x3
P2

P3

P4

x marks the connections left in place

after programming

AND plane

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f1

f2

PLA Logic Implementation

Mohd Anvar

Al- Ameen Engg. College

Key to Success: Shared Product Terms

Equations
Example:

F0 = A + B C
F1 = A C + A B
F2 = B C + A B
F3 = B C + A

Personality Matrix
Product Inputs
term
A B C
AB
1 1 BC
- 0 1
AC
1 - 0
BC
- 0 0
A
1 - -

Outputs
F0 F 1 F 2 F 3
0 1 1 0
0 0 0 1
0 1 0 0
1 0 1 0
1 0 0 1

Reuse
of
terms

Input Side:
1 = asserted in term
0 = negated in term
- = does not participate
Output Side:
1 = term connected to output
0 = no connection to output

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Mohd Anvar

PLA Logic Implementation

Al- Ameen Engg. College

Example Continued - Unprogrammed device

A

All possible connections are available

before programming

F0

F1

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F2

F3

Mohd Anvar

PLA Logic Implementation

Example Continued Programmed part

Al- Ameen Engg. College

Unwanted connections are "blown"

AB
BC
AC
BC
A

Note: some array structures

work by making connections
rather than breaking them
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F0

F1

F2

F3

Mohd Anvar

PLA Logic Implementation

Al- Ameen Engg. College

Unprogrammed device

Alternative representation for

high fan-in structures
Short-hand notation
so we don't have to
draw all the wires!
X at junction indicates
a connection

A B C D
AB
AB
CD

Notation for implementing

CD

F0 = A B + A B
F1 = C D + C D

Programmed device

AB+AB

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CD+CD

Mohd Anvar

PLA Logic Implementation

Al- Ameen Engg. College

A B C

Design Example

ABC

Multiple functions of A, B, C

A
B

F1 = A B C

C
A

F2 = A + B + C

F3 = A B C

C
ABC

F4 = A + B + C

ABC

F5 = A B C

ABC
ABC

F6 = A B C

ABC
ABC
ABC

F1 F2 F3 F4 F5

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F6

Mohd Anvar

Al- Ameen Engg. College

Programmable Array Logic (PAL)

Also used to implement

circuits in SOP form

x1 x2

xn

Input buffers
and
inverters

The connections in
the AND plane are
programmable

x1 x1

The connections in
the OR plane are
NOT programmable

fixed connections

xn xn
P1

AND plane

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OR plane
Pk

f1

fm

Mohd Anvar

Al- Ameen Engg. College

Example Schematic of a PAL

x1

x2

x3

f1 = x1x2x3'+x1'x2x3
f2 = x1'x2'+x1x2x3

P1
f1
P2

P3
f2
P4

AND plane
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PAL Logic Implementation

Mohd Anvar

Al- Ameen Engg. College

K-maps

Design Example: BCD to Gray Code Converter

Truth Table
A
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

B
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

C
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

D
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

W
0
0
0
0
0
1
1
1
1
1
X
X
X
X
X
X

X
0
0
0
0
1
1
0
0
0
0
X
X
X
X
X
X

Y
0
0
1
1
1
1
1
1
0
0
X
X
X
X
X
X

Z
0
1
1
0
0
0
0
1
1
0
X
X
X
X
X
X

AB
00
CD

01

11

10

00

01

AB
00
CD

01

11

10

00

01

11

10

D
11

C
10

B
K-map for W

B
K-map for X

AB
00
CD

01

11

10

00

01

Minimized Functions:

AB
00
CD

01

11

10

00

01

11

10

D
11

W=A+BD+BC
X=BC
Y=B+C
Z=ABCD+BCD+AD+BCD

X
C

C
10

B
K-map for Y

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B
K-map for Z

Mohd Anvar

PAL Logic Implementation

Al- Ameen Engg. College

Programmed PAL:

A B

C D
A
BD
BC

Minimized Functions:

W=A+BD+BC
X=BC
Y=B+C
Z=ABCD+BCD+AD+BCD

BC
0
0
0
B
C
0
0
AB C D
BCD
AD
BCD

4 product terms per each OR gate

W

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PAL Logic Implementation

Mohd Anvar

Al- Ameen Engg. College

Code Converter Discrete Gate Implementation

A

B
D

B
C

A
B
C
D

W
B
C
D

2
D

A
2

3
4

B
C

B
C
D

1: 7404 hex inverters

2,5: 7400 quad 2-input NAND
3: 7410 tri 3-input NAND
4: 7420 dual 4-input NAND

4 SSI Packages vs. 1 PLA/PAL Package!

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Mohd Anvar

PLA Logic Implementation

Another Example: Magnitude Comparator

A

AB
00
CD

AB
00
CD

01

11

10

00

00

01

11

Al- Ameen Engg. College

ABCD

01

11

10

01

11

10

ABCD
ABCD
D

ABCD

C
10

AC
AC

K-map for EQ

K-map for NE

BD
BD

AB
00
CD

A
01

11

10

AB
00
CD

A
01

11

10

ABD

00

00

BCD

01

01

ABC

11

11

10

10

D
C

BCD

B
K-map for LT

B
K-map for GT

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EQ NE LT

GT

 Comparing PALs and PLAs

Mohd Anvar

Al- Ameen Engg. College

PALs have the same limitations as PLAs (small number of

allowed AND terms) plus they have a fixed OR plane
less flexibility than PLAs
PALs are simpler to manufacture, cheaper, and faster
(better performance)
PALs also often have extra circuitry connected to the
output of each OR gate
The OR gate plus this circuitry is called a macrocell

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Mohd Anvar

Al- Ameen Engg. College

Select
Enable
OR gate from PAL

Macrocell

Flip-flop
Clock

back to AND plane

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Mohd Anvar

Al- Ameen Engg. College

Combinational and Sequential PLDS

16L4 PAL Combinational Logic
Up to 16 inputs
32 bit & bit-bar lines
Up to 4 outputs
Up to 7 product terms per output
1 product term/output for tri-state
control
Input, Output, Bi-driectional bus (on
per output basis)
Note fuse numbers (early technology)

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Mohd Anvar

Al- Ameen Engg. College

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Mohd Anvar

Al- Ameen Engg. College

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Mohd Anvar

Al- Ameen Engg. College

16R4 PAL Sequential Logic

16 inputs (counting feedback into array from DFFs)
Again 32 bit & bit-bar lines
4 outputs (Q outputs from 8 DFFs)
Up to 64 product terms
The flip-flops are all controlled by a common clock
which is tied directly to pin 1 on the device.
pin 11, which is used as a dedicated input for the
output enable of the flip-flops.

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Mohd Anvar

Al- Ameen Engg. College

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Mohd Anvar

Simple PLDS

Al- Ameen Engg. College

PLD 22V10 Combinational/Sequential Logic

PAL devices are most commonly used SPLD
Eg: PAL 22v10
II input pins that feed the AND plane and an additional
input that can serve as Clock input
The OR gates are of variable size, ranges from 8 to 16
inputs
From 8 to 16 product terms per output
Each out put pin has tristate buffer,which allows the pin to
optionally be used as input pin
Introduction of Macro cell-the circuitry between OR gate
and an out put in PAL
Combinational and/or sequential logic in 1 PLD
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Mohd Anvar

Complex Programmable Logic

Devices (CPLD)

Al- Ameen Engg. College

SPLDs (PLA, PAL) are limited in size due to the small

number of input and output pins and the limited number
of product terms
Combined number of inputs + outputs < 32 or so

CPLDs contain multiple circuit blocks on a single chip

Each block is like a PAL: PAL-like block
Connections are provided between PAL-like blocks via an
interconnection network that is programmable
Each block is connected to an I/O block as well

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Mohd Anvar

Al- Ameen Engg. College

PAL-like
block

PAL-like
block

I/O block

I/O block

Structure of a CPLD

PAL-like
block

PAL-like
block

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I/O block

I/O block

Interconnection wires

Mohd Anvar

Al- Ameen Engg. College

Internal Structure of a PAL-like Block

Includes macrocells
Usually about 16 each
PAL-like block

Fixed OR planes
OR gates have fan-in
between 5-20

XOR gates provide

negation ability

PAL-like block
DQ

DQ

XOR has a control

input

DQ

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Mohd Anvar

Al- Ameen Engg. College

More on PAL-like Blocks

CPLD pins are provided to control XOR, MUX, and tri-state
gates
When tri-state gate is disabled, the corresponding output
pin can be used as an input pin
The associated PAL-like block is then useless

The AND plane and interconnection network are

programmable
Commercial CPLDs have between 2-100 PAL-like blocks
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 Example CPLD
Mohd Anvar

Al- Ameen Engg. College

Use a CPLD to implement the function

f = x1x3x6' + x1x4x5x6' + x2x3x7 + x2x4x5x7
(from interconnection wires)
x1 x2 x3 x4 x5 x6 x7

unused

PAL-likeblock
0 1

f
D Q

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Mohd Anvar

The Xilinx 9500-series CPLD

The internal PLDs are called Configurable Functional Blocks

(FBs or CFBs)
Each FB has 36 inputs and 18 Macrocells (effectively a 36V18)
Each CLPD is packaged in a plastic-leaded chip carrier (PLCC)
The number of I/O pins are much less than the total number of
Macrocells in family of devices

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Mohd Anvar

Al- Ameen Engg. College

Xinlinx CPLDs

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Mohd Anvar

Architecture of Xilinx 9500-family CPLD

Al- Ameen Engg. College

36 Signal pins

18 outputs

Global Clock
Global set/reset
Global 3 state control
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18 Output
enable signals

Mohd Anvar

Al- Ameen Engg. College

XC9500 I/O Block

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Mohd Anvar

Al- Ameen Engg. College

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Mohd Anvar

Al- Ameen Engg. College

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Mohd Anvar

FPGA

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SPLDs and CPLDs are relatively small and useful for simple
logic devices
Up to about 20000 gates

Field Programmable Gate Arrays (FPGA) can handle larger

circuits
No AND/OR planes
Provide logic blocks, I/O blocks, and interconnection wires and
switches
Logic blocks provide functionality
Interconnection switches allow logic blocks to be connected to
each other and to the I/O pins
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Mohd Anvar

IOB

IOB

IOB

CLB

CLB

CLB

CLB

CLB

IOB

CLB

IOB
IOB

IOB

IOB

IOB

FPGA Structure

Input/Output
Block

IOB

SM
CLB

SM
CLB

IOB

SM
CLB

SM
CLB

SM
CLB

SM
IOB

Configurable
Logic
Block

Al- Ameen Engg. College

SM
CLB

SM

SM

CLB

CLB

CLB

CLB

IOB

IOB

IOB

IOB

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Switch
Matrix

Mohd Anvar

FPGA CLB Structure

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Mohd Anvar

Al- Ameen Engg. College

LUTs

Logic blocks are implemented using a lookup table (LUT)

Small number of inputs, one output
Contains storage cells that can be loaded with the desired values
A 2 input LUT uses 3 MUXes
x
to implement any desired function 1
of 2 variables
Shannon's expansion at work!

0/1
0/1
0/1
0/1

x2

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Mohd Anvar

Al- Ameen Engg. College

Example 2 Input LUT

x1
0
0
1
1

x2
0
1
0
1

f
1
0
0
1

f = x1'x2' + x1x2, or using Shannon's expansion:

f = x1'(x2') + x1(x2)
= x1'(x2'(1) + x2(0)) + x1(x2'(0) + x2(1))

x1
1
0
0
1
x2
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Mohd Anvar

Al- Ameen Engg. College

3 Input LUT
x1
x2

7 2x1 MUXes and

8 storage cells are
required

0/1
0/1
0/1

Commercial LUTs have

4-5 inputs, and 16-32
storage cells

0/1
0/1
0/1
0/1
0/1
x3

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Mohd Anvar

Programming an FPGA

Al- Ameen Engg. College

LUTs contain volatile storage cells

None of the other PLD technologies are volatile
FPGA storage cells are loaded via a PROM when power is first
applied

The UP2 Education Board by Altera contains a JTAG port, a

MAX 7000 CPLD, and a FLEX 10K FPGA
The MAX 7000 CPLD chip is EPM7128SLC84-7
EPM7 MAX 7000 family; 128 macrocells; LC84 84 pin PLCC
package; 7 speed grade

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 Example FPGA
Mohd Anvar

Al- Ameen Engg. College

Use an FPGA with 2 input LUTS to implement the function f

x
f
= x1x2 + x2'x3
3

f1 = x1x2
f2 = x2'x3
f = f1 + f2

x1

x2

x1 0
0 f
1
x2 0
1

x2 0
1 f
2
x3 0
0

f1 0
1
1
f2
1

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Mohd Anvar

Al- Ameen Engg. College

Another Example FPGA

Use an FPGA with 2 input LUTS to implement the function f =
x1x3x6' + x1x4x5x6' + x2x3x7 + x2x4x5x7
Fan-in of expression is too large for FPGA (this was simple to do in a
CPLD)
Factor f to get sub-expressions with max fan-in = 2
f = x1x6'(x3 + x4x5) + x2x7(x3 + x4x5)
= (x1x6' + x2x7)(x3 + x4x5)

Could use Shannon's expansion instead

Goal is to build expressions out of 2-input LUTs

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 FPGA Implementation
Mohd Anvar

Al- Ameen Engg. College

f = (x1x6' + x2x7)(x3 + x4x5)

x4

x5

x3

x1

x6

x1 0
0 A
x6 1
0

x4 0
0 C
x5 0
1

x3 0
1 E
1
C 1

x2 0
0 B
x7 0
1

A 0
1 D
1
B 1

D 0
0 f
0
E 1

x2

x7

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Mohd Anvar

ALTERA FLEX 10K

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Mohd Anvar

Al- Ameen Engg. College

FLEX 10K Logic array block

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Mohd Anvar

Al- Ameen Engg. College

FLEX 10K Embedded Array block

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Mohd Anvar

Al- Ameen Engg. College

Xilinx XC400-CLB

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Mohd Anvar

XC400 -IOB

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Mohd Anvar

Al- Ameen Engg. College

Wish you all the best..

Thank you
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