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Computer System Organisation by Morris Mano Solution

this document contains detailed solution of Computer systems and architecture by Morris mano for chapter 4 to chapter 8.

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Divyanshu
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2K views

Computer System Organisation by Morris Mano Solution

this document contains detailed solution of Computer systems and architecture by Morris mano for chapter 4 to chapter 8.

Uploaded by

Divyanshu
Copyright
© © All Rights Reserved
Available Formats
Download as PDF or read online on Scribd
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CHAPTER 4 44 . { } —Piged Ynd Clock +] 4.2 Ro a Pal TatitoTs |S: So Rs load ” 0000 |X x0 1000 |001 ws 0100/0114 0010/1041 ooo1|+14 s So=T; +Ts load = To Ty+ ToT 4.3 P:R1— R2 P'Q: R1—R3 44 Connect the 4-line common bus to the four inputs of each register. Provide a "load" control input in each register. Provide a clock input for each register. To transfer from register C to register A: Apply S:So = 10 (to select C for the bus.) Enable the load input of A Apply a clock pulse. -20- 45 Register | 0 axa t 46 (a) (b) () 47 (a) (b) () 48 Decoder 2 3 1 wf fo [eer [IC Register’ Register | By D cl 3 Registers C, D 4 line Same as A,B. (Common bus 4 selection lines to select one of 16 registers. 16 « 1 multiplexers. 32 multiplexers, one for each bit of the registers. Read memory word specified by the address in AR into register R2. Write content of register R3 into the memory word specified by the address in AR Read memory word specified by the address in R5 and transfer content to R5 (destroys previous value) BR ~— mbit adder SUM i Dea ak Clock 2s 3 1, " — Count ,| mbit cy q ]_D ele Bin comur?— Coe 4.10 Clock v 0 Qua 2x1 wx [a | | y ve eit g.27 ig. 27) adder 4.4) (Fig. +6) 44 | os RI 44) gon) | - ig 40) [ns toad Cea rit. 4.A2 M AB Sum Gu 0 01110110 1101 0 7+6=13 0 1000+1001 0001 1 84+9=16+1 1 1100-1000 0100 1 12-8 1 0101-1010 1011 0 5— 10 = —5{in 2's comp.) 4 0000-0001 1111 0 0-1 =-1 (in 2’s comp.) 413 A-1=A+2's complement of 1=A +1111 ti oti oft tl CA AA 7a ajo q T T 1 2. bit aithmetic Fig. 49 Cout abit arithmetic cir Fig 49 Cout Is socom p Is ono > >> >b< soak 47 4.18 (a) A= 11011001, A= 11011001 B= 10110100 B=11111101 °F) Aj AOB01101101 11111104 AcAVB 4.19 (a) AR= 11110010 BR = 11111111(4) AR = 11110001 BR = 11111111 CR= 10111001 DR= 1110 1010 (b) CR = 10111001 BR = 1111 1111 DR = 11101010") +4 CR = 10101000 BI 0000 0000 AR = 1111 0001 DR = 11101010 (©) AR= 11110001.) CR = 10101000 AR = 01001001; BR = 00000000; CR= 10101000; DR= 11101010 4.20 R= 10011100 Arithmetic shift right: 11001110 Arithmetic shift left:00111000 overflow because a negative number changed to positive, 421 R= 11011101 Logical shiftleft: 101110104~ Circular shift right: 07011101 Logical shift right! “90101110 Circular shift left: 01011160 224 4.22 S=1 4.23 (a) (b) (c) Shift left Ao As AzAs hk H= 0010 shift left Cannot complement and increment the same register at the same time. Cannot transfer two different values (Rz and Rs) to the same register (Ri) at the same time. Cannot transfer a new value into a register (PC) and increment the original value by one at the same time. 225. CHAPTER 5 5A 256 K = 2° x 2 = 2'° 64 = 2° (a) Address: 18 bits Register code 6 bits Indirect bit! 1. bit 25 32-25 = 7 bits for opcode. () 1 7 6 18 = 32bits 1 [opeode [Register [Address (c) Data; 32 bits; address: 18 bits. 5.2 A direct address instruction needs two references to memory: (1) Read instruction; (2) Read operand, An indirect address instruction needs three references to memory: (1) Read instruction; (2) Read effective address; (3) Read operand. 5.3 (2) Memory read to bus and load to IR: IR — MIAR] (b) TR to bus and load to PC: PC — TR (©) AC to bus, write to memory, and load to DR: DR<—AC, — M[AR}— AC (¢) Add DR (or INPR) to AC: AC — AC + DR 54 (1) (2) (3) (4) S,S;S: Load(LD) Memory Adder (a) AR—PC 010 (PC) AR = = (b) IR —MIAR] 411 (M) IR Read =- (c) MIAR]— TR 110 (TR) - Write - (@) DR—aAC 100(AC) DRand = Transfer AC —DR AC DR to AC. (a) IR—MIPC] PC cannot provide address to memory. Address must be transferred to AR first ARe PC IR — MAR] (b) AC-AC+TR Add operation must be done with DR. Transfer TR to DR first. DR<—TR AC-AC+DR =26- (©) DReDR+AC Result of addition is transferred to AC (not DR). To save value of AC its content must be stored temporary in DR (or TR), AC «DR, DR AC (See answer to Problem 5.4(d)) AC+~AC+DR AC DR, DR + AC 56 (a) 0001 0000 0010 0010 = (1024)16 ADD (024)i5 ADD content of M[024]to AC ADD 024 (b) 1.041 0001 _0010_0100 = (B124):5 ISTA (124)e Store AC in M[M[124]] STAI 124 (©) 0441 0000 0010 0000 = (7020)5 Register Increment AC INC 57 CLE ClearE CME Complement E ISC goes 0 0 causing 7) = 1 221- 5.9 E AC PC AR R Initial 1 A937 021 — = CLA 1 0000 022 800 7800 CLE oO A937 022 400 7400 CMA. 1 56C8 022 200 7200 CME oO A937 022 100 7100 CIR 1 D49B 022 080 7080 CIL 1 526F 022 040 7040 INC 1 A938 022 020 7020 SPA 4 A937 022 010 7010 SNA 1 A937 023 008 7008 SZA 1 ‘A937 022 004 7004 SZE 1 ‘A937 022 002; 7002 HLT 1 A937 022 001 7001 5.10 PC AR DR AC IR. Initial 021 = = ‘AQ37 = ‘AND 022 083 Bar2 ‘A832 0083 ‘ADD 022 083 BaF2 6229 1083 LDA. 022 083 B8F2 BaF2 2083 STA 022 083 = A937 3083 BUN 083 083 = A937 4083 BSA 084 084 — A937 5083 ISZ 022 083 B8F3 A937 6083 5.11 PC AR DR IR Sc Initial 7FF = = = oO To 7FF 7FF = — 1 Ty 800 TFF = EASF 2 Te 800 AQF = EASF 3 Ts 800 C35 = EASE 4 Te 800 C35 FEFF EASE 5 Ts 800 C35 0000 EASE 6 Ts 801 C35 0000 EASF 0 5.12 Memory (a) 9=(1001) noo) SAF] 932E l=1 ADD ADD | 32E 32E ogAc. sac | eBoF 228+ AC = 7EC3 (b) AC = 7EC3 DR = 8BSF oas2 (app) PC = 3AF + 1= 380 AR = 7AC DR = 8B9F ‘AC = 0A62 5.13 XOR Dols DR < MIAR] DoTs. AC — AC @ DR,SC ~0 ADM DiTs DR + MAR] DiTs DR — AC, AC — AC+DR DiTe MIAR] — AC, AC — DR, SC 0 SUB DT. DR <— MAR] DzTs DR «AC, AC DR DoTs AC — AC Doty AC —AC+1 D2Te AC — AC +DR, SC <0 XCH DsTe DR — MIAR] DsTs MAR] — AC, AC — DR, SC —0 SEQ DT DR < MAR] D.Ts TR —AC,AC —AC @ DR DaTs If(AC = 0) then (PC — PC +1), AC — TR, SC —0 BPA DsTe. If(AC =0 ~ AC (15) = 0) then (PC_— AR), SC —0 5.14 Converts the ISZ instruction from a memory-reference instruction to a register- reference instruction. The nev instruction ICSZ can be executed at time T; instead of time Ts, a saving of 3 clock cycles. 229. 5.15 Modify fig. 5.9. i ‘Same as Fig. 5.9 (Direct) Ty AR PC, PC —PC+ I AR(2— 7; “AR = MIAR} Execute memory-reference instruction 5.16 @) 6 ° PC 5 Memory GIR at iB 7 z 3 TR ac 7 oF 3 TR DR (b) Moaaoey opcode V2 address V2 address operand | — sits —o} -30- (©) To IR —M(PC),PC —PC+1 Ty AR(O-7)— MIPC], PC — PC +1 Te AR(8-15) — MIPC], PC — PC #1 Ts DR FGo 5.24 X, places PC onto the bus. From Table 5.6: RTs: AR — PC RTo: TR — PC DsTs: MIAR] — PC Xe = RTo + RTo + Ds Ta = (R' + R) To + DsTs = To + DsTa -32- 5.25 From Table 5.6: CLR (SC) = RT2 + DrTs (I'+l) + (Do + Di + De + Ds ) Ts + (Ds + Ds) Ts + DeTs CHAPTER 6 64 010 011 012 013 014 015 016 017 62 100 101 102 103 104 105 106 63 CLA STA LDA ADD ADD STA LDA MA INC ADD STA LDA ADD STA IR 7800 1016 4014 7001 0017 4013 0001 0014 0001 1010 0101 ‘AND 1100 _0110 1000 0100 = —(8184)is Ac FFFEA « Answer 0000 0001 A more efficient compiler will optimize the machine code as follows: LDA ADD STA LDA CMA INC ADD STA AC PC CLA 0000 011 ADD 016 C1A5 012 BUN 014 C1A5 014 HLT 8184 014 AND 017 8184 015 BUN 013 8184 013, C1A5 936 (C1A5)6 = = 1100 (93C6)is = = = 1001 1000 5103 BSA 103 7200 cMA 7001 HLT 0000 5101 <— Answer 7800 CLA 7020 INC C103 BUN 103 | | sumo sum] suM| | SUM=SUM +A +B ul sum} 1 DIF-DIF-C DIF pir} suM SUM ADD STA A B SUM c DIF DIF SUM SUM -34- 64 Aline of code such as: LDA | is interpreted by the assembler (Fig. 6.2) as a two symbol field with | as the symbolic address. A line of code such as: LDA Il is interpreted as a three symbol field. The first lis an address symbol and the second | as the Indirect bit. ‘Answer: Yes, it can be used for this assembler. 65 The assembler will not detect an ORG or END if the line has a label; according to the flow chart of Fig. 6.1. Such a label has no meaning and constitutes an error. To detect the error, modify the flow chart of Fig. 6.1 + t ¥ sean tine of code [[ sate] a, P< “Ore goto 2nd 0 pass A D> error SORG> message store symbol 1 Tnerement LC LJ 66 (a) Memory Characters Hex Binary word 1 DE 44.45 0100 0100 0100 0101 2 CSpace 4320 0100 0011 0010 0000 3 -3 2D 33 0010 1101 0011 0011 4 5CR 35 0D 0011 0101 0000 1101 (b) — (35)s0 = (0000 0000 0010 0011), =35) > 11111114 1101 1101 = (FFDD):5 67 (a) Lop 105 (100):0 = (0000 0000 0110 0100). ADS 10B PTR 40¢ (100}n= (11114 1111 1001 1100) = (FF9C)s NBR 40D 75) = (0000 0000 0100 1011), = (0048 ner 40E (75)10 = ( de = (0048):6 SUM 10F (23):0 = (0000 0000 0001 0111), = (0017):7 -35- (b) Loc 100 101 102 103 104 105 106 107 108 109 410A Modify flow chart of Fig. 6.1 a Hex ORG 2108 LDA 310C STA 210D LDA 310E STA 7800 CLA 910C LOP, ADD 610c Isz 610E Isz 4105 BUN 310F STA 7001 HLT 4100 ‘ADS PTR NBR CTR PTRI PTR CTR Lop SUM Loc 10B 10C 10D 10E 10F 150 1B3 1c store symbol symbol table Hex 0150 ADS, HEX 150 0000 PTR, HEXO FF9C NBR, DEC-100 0000 CTR, HEXO 0000 SJH, HEXO ORG 150 004B DEC 150 0017 DEC 23 END A\BSS 10 Atl A+2 Ats line ‘get opcode search symbol table for address symbol Is symbol in table? wate+1 | Pa message Lc [same as Fig. 6-2 A+4 A+ At A+7 A+B W A+9 M LCsetto example 6.10 (a) (b) 6.11 6.12 (a) MRI Table Memory Symbol word AND ADD non - Mi word CLA CLE | LDA CMA INC aaron AN D Space value AD D space value etc. IRI Table ey Sabot cL A Space value cL E space value etc. ADD A SPA BUN SZA BUN BUN N10 N30 N20 414D 4420 00 00 4144 4420 10.00 43.4C 4120 78.00 43.4C 4520 7400 IForm A-B Iskip if AC positive 1(A-B) < 0, go to N 10 Iskip if AC = 0 1(A-B) > 0, go to N30 1(A-B) = 0, go to N20 The program counts the number of 1's in the number stored in location WRD. Since WRD = (62C1);3 = (0110 0010 1100 0001), number of 1's is 6; 80 CTR will have (0006)15, -37- (b) 100 7400 CLE 101 7800 CLA 102 3110 STA 103 2111 LDA 104 7004 SZA 105 4107 BUN 106 10F BUN 107 7040 ROT, CIL 108 7002 SZE 109 4108 BUN 10A 4107 BUN 10B 7400 AGN, CLE 10C 6110 1SZ 10D 7004 SZA 10E 4107 BUN 10F 7001 STP, HLT 110 0000 CTR, HEX are 62C1 WRD, HEX END 6.13, (100)15 = (256)10 500 to SFF ORG 100 LDA ADS STA PTR _/Initialize pointer LDA NBR STA CTR _Initialize counter to -256 CLA LOP,STA PTRI store zero IsZ_ PTR Isz_ CTR BUN _LOP HLT ADS,HEX — 500 PTR,HEX 0. NBR, DEC -256 CTR,HEX 0 END ORG -38- 100 cTR WRD ROT STP AGN ROT cTR ROT 62C1 + (256):9 locations Initialize counter to zero 1 Word is zero; stop with CTR =0 [Bring bit to E Ibit = 1, go to count it bit = 0, repeat Increment counter Icheck if remaining bits = 0 No; rotate again yes; stop 6.14 LDA = A__/Load multiplier SZA Is it zero? BUN NZR HLT JA=0, product = 0 in AC NZR, CMA INC STA CTR /Store -A in counter CLA /Start with AC = 0 LOP,ADD _B__/Add multiplicand IsZ_ CTR BUN LOP /Repeat Loop A times HLT A,DEC - ‘multiplier B,DEC - — /multiplicand CTR,HEX © /counter END 6.15 The first time the program is executed, location CTR will go to 0. If the program, is ‘executed again starting from location (100);6, location CTR will be incremented and will not reach 0 until it is incremented 2° = 65,536 times, at which time it will reach 0 again. We need to initialize CTR and P as follows: LDA NBR STA CTR CLA STA P Program NBR, DEC-8 CTR, HEX 0 P, HEX 0 6.16 Multiplicand is initially in location XL. Will be shifted left into XH (which has zero initially), The partial product will contain two locations PL and PH (initially zero). Multiplier is in location Y. CTR = -16 -29- LOP, CLE LDA CIR STA SZE BUN BUN LDA ADD STA CLA cIL ADD ADD STA CLE LDA ciL STA LDA ciL STA ISZz BUN HLT ONE, ZRO. 6.17 If multiplier is negative, take the 2's complement of multiplier and multiplicand and then proceed as in Table 6.14 (with CTR Flow-Chart cTR=7 Poo plus Y-Y+1 x Peed ai ‘Same as beginning of program in Table 6.14 ONE xe a PL Double-precision add POX+P Same as program XH In Table 6.15 PH PH xt Double-precision left-shift XL XH+XL XH XH CTR Repeat 16 times. LOP -7). check sign of multiplier 2s complement multiplier 2s complement multiplicand ——— “Table Geld =40- 6.18 CAA-B CLE To form a double-precision LDA BL 2's complement of subtrahend CMA BH +BL, INC 1's complement is formed and 1 added once. ADD AL STAAL Save CLA Carry cil Thus, BL is complemented and incremented STA TMP while BH is only complemented. LOA BH CMA Location TMP saves the cary ADD AH from E while BH ‘Add cany-+ ADD TMP is complemented. STA CH HLT TMP, HEX 0 6.19 Z=xX@ y= xy txy=[(xy)'. (xy)T LDA Y cMA AND TMP AND x CMA CMA STA Z STA TMP HLT LDA x xX, MA Y, AND YZ CMA TMP, 6.20 LDA Xx CLE IL /zero to low order bit; sign bit in E SZE BUN ONE SPA BUN OVF BUN EXT ONE, SNA BUN OVF EXT, HLT 241 6.21 Calling program BSA SUB SUB, HEX 1234 /subtrahend HEX 4321. /minuend HEX 0 difference 6.22 Calling Program BSA CMP HEX 100 /starling address DEC 32 /number of words LOP, Subroutine CMP, HEX 0 LDA CMPI STA PTR Isz_ CMP LDA CMPI PTR, CTR, 6.23 CR4, HEX 0 CIR CIR CIR CIR BUN CR4I AC E AC HEX 14 ‘00090111 1001 1100 + ‘079 ae 1001 60000111 1001-9079 subroutine HEX LDA CMA IN Isz ADD Isz STA IsZ BUN CMA INC STA LDA CMA STA ISZ ISZ BUN Isz BUN 282- ° SUB | SUB SUBI SUB SUB SUB SUB | cTR PTR | PIRI PTR CTR LOP CMP CMP | 6.24 LDA ADS STA PTR LDA NBR ADS, STA CTR PTR, LOP, BSA IN2 _/subroutine Table 6.20 STA PTRI NBR, ISZ_ PTR cTR, ISZ_ CTR 6.25 LDA WRD STA AND MS1 HLT STA CH1 WRD, HEX LDA WRD CH1, HEX AND MS2 CH2, HEX CLE MS1, HEX BSA SR8 /subroutine to Ms2, HEX shift right times eight times 6.26 + 4 Initialize memory| Load double buffer character again + f : Load next double ‘AND AC with character from buffer HEX FFOO into AC T t ‘Compare AC with AND AC with HEX ODO0 HEX 0OFF eS ‘Compare AC with HEX 00D Pack HEX OD to INE END) 248. BUN HTA HEX HEX DEC HEX. 6.28 SRV, STA CIR STA LDA CMA. SZA BUN SKI BUN INP OUT STA Isz BUN SAC SE MoD NXT NXT PT11 PT1 EXT 3213 SRV, STA SAC 7080 CIR 3214 STA SE F200 SKI 4209 BUN NXT F800 INP F400 OUT 8215, STA PTI 1 1SZ_PT4 6215 NXT, SKO F100 420E BUN EXT A216 LDA PT2 1 F400 OUT 6216 1SZ_PT2 2214 EXT, LDA SE 7040 cI 2213 LDA SAC F080 1ON 000 BUN ZRO | 0000 0000 0000 0000 NXT, LDA MOD SZA Icheck MOD BUN EXT service SKO out put BUN EXT MOD #all1's device LDA PT2 1 ouT service Isz_ PT2 input device EXT, continue as in Table 6.23 IMOD #0 44 CHAPTER 7 77 ‘A microprocessor is a small size CPU (computer on a chip). Microprogram is a program for a sequence of microoperations. The control unit of a microprocessor can be hardwired or microprogrammed, depending on the specific design. A microprogrammed computer does not have to be a microprocessor. 72 Hardwired control, by definition, does not contain a control memory. 73 Micro operation - an elementary digital computer operation. Micro instruction - an instruction stored in control memory. Micro program - a sequence of microinstructions. Micro code - same as microprogram. 1 40 fn 0 40 ‘sequencer ROM] [7 Micro JP [register || operations Clock y J Clock 2 sons 50 50 50ns Clock 1 Clock 2 Fe ae 1 ___ 1000 10° =10MHz 100x107 100 If the data register is removed, we can use a single phase frequency of each clock clock with a frequency of 1.IMHz, 75 Control memory = 2"°x 32 (a)_6 10 16 Select [Address | Micro operations 32 bits (b) 4 bits (c) 2 bits 245- 7.6 Control memory = 2" x 24 (a) 12 bits (b) 12 bits (c) 12 multiplexers, each of size 4-to-1 line. (c) 0111100 = 60 78 ‘opcode = 6 bits control memory 00| address = 11 bits kexxxxx| 79 inputs no outputs ‘The ROM can be programmed to provide any desired address for a given i the instruction, 7.10 Either multiplexers, three-state gates, or gate logic (equivalent to a mux) are needed to transfer information from many sources to a common destination. 7 FL F2 F3 (a) 011 110 000 INCACINCDR NOP {b) 000 100 101 NOP READ INCPC (©) 100 101 000 DRTAC ACTDR —NOP 7A2 Binary (a) READ DR < MIAR] F2=100 001 100 101 DRTAC = AC+-DR F3=101 (b) ACTOR DR ~ ses P When P = 0, T= G because G © O=G When P = 1, T=G', because G @ |=G' Where Gis the value of the selected bit in MU * 2. =50- CHAPTER 8 8.4 32 multiplexers, each of size 16 x 1 4 inputs each, to select one of 16 registers. 4-to-16 - line decoder 32 + 32 + 1 = 65 data input lines 32+1=33 data output lines. 4 4 4 6 = 1B bits SELA [SELB [SELD [OPR 8.2 30 + 80 + 10 = 120 n sec. (The decoder signals propagate at the same as the muxs.) 83 SEses S8SEs ese 8.6 PUSH PoP SELA SELB SELD OPR Control word RIC R2+R3 R2 RB RI ADD 010 011 001 00010 R4< RA R4 — R4 COMA 100 xxx 100 01110 R5.— R5—1 R5 — RS DECA 101 xxx 101 00110 R6— SH1R1 R1 — R6 SHLA 001 xxx 110 11000 R7 < Input Input — R7 SFA 000 xxx 111 00000 Control word SELA SELB SELD OPR Microoperation 001 010 011 00101 Rt R2 R3 SUB R3<—R1-R2 000 000 000 00000 Input Input None TSFA Output — Input 010 010 010 01100 R2 R2 R2 XOR R2—-R2@ R2 000 001 000 00010 Input Rt None ADD Output — Input +R 411 100 011 10000 R7R4.-R3_ SHRA R3 < shrR7 Stack full with 64 items. stack empty 3098 MISP] — DR 3998 SP—SP-1 SP SP+1 DR — M{SP] sp—| 4000 AB*CD*EF* +4 AB * ABD * CE * + * + FG+E*CD*+BtA+ ABCDE + * + * FGH + */ 88 (a) A_y,E F Bec 89 (b) A+B D*E (d) ((F+G)*E+D)*C+B) tA (3+ 4) [10 (2 +6) +8) =616 RPN: 34+26+10*8+* 7 7 616 8.10 WRITE (if not full) M [WC] — DR we —Wc+1 ASC —ASC +1 READ : (if not empty) DR + MIRC] RC«RC+1 ASC ASC ~1 FIFO Memory may wrap-around from 7t0 0 Read o|)y]or| ~}oo] RC -| Write we |-—-+| Empiy —os 8.11 8 12 12 opcode] Address 7 ‘Address 2 2° = 256 combinations. 256 — 250 = 6 combinations can be used for one address 232. 32bit Two address instructions opcode | Address One address instructor 6x2" Maximum number of one address instruction: = 6x2" = 24,576 8.12 (4) RPN: x AB-C + DE x Fx GHK x +/= 8.13 256 K = 2° x 2" = 2" op code Mode Register ‘Address 5 3 6 18 = 32 Address = 18 bits Mode = 3” Register =__6 27 bits op code 5 32__ bits 8.14 Z= Effective address PC W[ppcode Mode @) Direct: wel ¥ () Indirect: [RX )W+2Next instruction (©) Relative: | (a) Indexed z)epennd | 8.15 (a) Relative address = 500 - 751 = - 251 (b) 251 = 000011111011; ~ 251 = 111100000101 (©) PC = 751= 001011101111; 500 = 000111110100 PC= 751= 001011101111 RA = — 251 = +114100000101 EA= 500= 000111110100 8.16 ‘Assuming one word per instruction or operand Computational type Branch type Fetch instruction Fetch instruction Fetch effective address _Fetch effective address and transfer to PC Fetch operand —_ 3 memory references ‘2 memory references. 8.17 ‘The address part of the indexed mode instruction must be set to zero. 8.18 Effective address (a) Direct: 400 ee (3 mmediate: 201 PC-r300 opcode Mode (c)__ Relative: 302 + 400 = 702 sor] 400 (4) Reg. Indirect: 200 0 (e) Indexed: 200 + 400 = 600 aa 8.19 1=C 0=C 1=C 0=Reset initial carry 6E C3 56 7A 13° 55 6B BE 82 18 C2 09 Add with carry 8.20 10011100 10011100 10011100 40101010 AND 10101010 OR 10101010 XOR 10001000 11111110 00110110 8.21 (a) AND with: 0000000011111111 (b) OR with: 0000000011111111 (©) XOR with: 0000111111110000 8.22 Initial: 01111011 Cc SHR: 00111101 SHL: 11110110 SHRA: 00111101 SHLA: 11110110 (over flow) ROR: 10111101 ROL: 11110110 RORC: 10111101 ROLC: 11110111 8.23 +83=01010011 —83= 10101101 +68=01000100 —68 = 10111100 (a) 83 10101101 +68 +01000100 =45 "11110001 {in 2's complement) (b) 10 carries -68 10111100 =83 +10101101 451 “01101001 A 128. (over flow) (c) 68 = 10111100 — 34 = 11011110 @=1 (d) —83 = 10101101 166 # 01011010 Over flow. 8.24 Z= Fo P's Fo F's F's F's FoF Fo + Fy + Fo + Fy + Fe + Fs + Fo + Fr) 8.25 11 (a)72 01110010 cé 11000110 138 00111000 C=1 S=0Z=0V=0 (b) 01 72 01110010 4E 90011110 90 10010000 C=0 S=1 Z2=0V=1 (©) 8A= 10011010 2 comp 01100110. 72 01110010 Ds. 11011000 C=0S=1Z=0V=1 (Borrow = 1) (d)72= 01110010 8D 10001100 00 00000000 S=0Z=1V=0 =0 S=0 Z=1V=0 if A B if A=B, therefore Z=1ifA + B For A> B we must have A 2 B provided A + B OrC =OandZ=0(CZ)=1 For A < Bwe must have A Bimplies that A—B > 0 (positive or zero) ‘Sign S = 0 if no over flow (positive) or S = 1 if over flow (sign reversal) Boolean expression: S'V' + SV = 1 or (S @ V)=0 A B (A- B negative) then S ifV=0 orS=0ifV=1 (S@V)=1 A> B implies A > B but not A= B (S ® V)=OandZ=0 A< Blmplies A< Bor A=B S@V=1o0rZ=1 (SOV +A-1 yey 8.29 Unsigned Signed A= 01000001 65 +65 B = 10000100 132 = 124 A+B= 11000101 197-59 (c)C=0 Z=0 S=1 V=0 (d)BNC BNZ BM BNV 8.30 (a) A= 01000001 = + 65 10000100 = 132 A-B= 10111101 =~ 67 (2's comp. of 01000011) (b) C (borrow) =1;Z=0 65 < 132 A 127 (overflow) 65 >-124 A>B () BGT, BGE, BNE 8.32 PC SP Top of Stack Initial 1120 3560 5320 After CALL 6720 3559 1122 After RETURN 1122 3560 5320 8.33 Branch instruction — Branch without being able to return Subroutine call — Branch to subroutine and then return to calling program. Program interrupt — Hardware initiated branch with possibility to return 8.34 See Sec. 8-7 under “Types of Interrupts”. 8.35 (a) SP — SP-1 (a) PC < M[SP] MISP] — PSW SP << SP+1 SP < SP-1 PSW < M[SP] M[SP] <- PC SP < SP+1 TR < IAD (TRis a temporary register) PSW < MITR] TReTR+1 PC < MITR] Go to fetch phase 8.37 Window Size= L+2C+G Computer 1: 10 + 12 + 10 = 32 Computer 2: 8 + 16 +8 = 32 Computer 3: 16 + 32 + 16 = 64 Register file = (L+C) W+G Computer 1: (10 + 6) 8 + 10 = 16 x 8 + 10 = 138, Computer 2: (8 + 8)4+8=16%4+8=72 Computer 3: (16 + 16) 16 + 16 = 32 * 16 + 16 = 528 -57- 8-38 (a) SUB R22, #1, R22 R22 < R22—1 (Subtract 1) (b) XOR R22, #-1, R22 R22 < R22 © all 1’s (x ® 1=x’) (c) SUB RO, R22, R22 R22 <— 0-R22 (d) ADD RO, RO, R22 R22 < 0+0 (e) SRA R22, #2, R22 Arithmetic shift right twice (f) ORR1,R1,R1 R1

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