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Test Bench

This document describes a test bench module for testing a memory. It initializes a clock and reset signal. It writes 4096 random values to memory addresses and logs the writes. It then reads from random addresses and logs the reads. The memory unit under test is instantiated and connected to the test signals.

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raghavendraks1989
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22 views

Test Bench

This document describes a test bench module for testing a memory. It initializes a clock and reset signal. It writes 4096 random values to memory addresses and logs the writes. It then reads from random addresses and logs the reads. The memory unit under test is instantiated and connected to the test signals.

Uploaded by

raghavendraks1989
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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// Test Bench

module memory_tb ();


reg clk, rst;
reg
read_rq;
reg
write_rq;
reg[11:0] row_adr;
reg[7:0] writedata;
wire[7:0] readdata;
reg [5:0] q_cnt;
integer seed;
integer out, rout;
initial
begin
clk = 0;
forever #10 clk = ~clk;
end
initial begin
rst = 0;
# 50 rst = 1;
end
always @(posedge clk or negedge rst)
begin
if (!rst)
begin
q_cnt <= 0;
write_data <= 'b0;
out = $fopen("mem_ram.vec","w");
rout = $fopen("mem_ram_read.vec","w");
end
else
begin
if (q_cnt < 4096)
begin
q_cnt <= q_cnt+1;
writedata <= $random(seed) & 'hFF;

read_rq <= 0;
write_rq <= 1;
row_adr <= q_cnt;
$fdisplay(out, "Address::%d:: %b :: -- contents in hex
%h", row_adr, writedata, writedata);
end
else
begin
q_cnt <= q_cnt;
writedata <= writedata;
row_adr <= $random(seed) & 'h3F;
read_rq <= 1;
write_rq <= 0;
$fdisplay(rout,"Address::%d:: %b :: -- read contents in
hex %h", row_adr, readdata, readdata);
end
end
end
mem_u_dut_ram (
.clk(clk),
.rst(rst),
.read_rq(read_rq),
.write_rq(write_rq),
.row_adr (row_adr),
.writedata(writedata),
.readdata(readdata)
);

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