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Assignment: (LUT Based Technology Mapping and Temporal Partitioning)

This document outlines an assignment involving LUT-based technology mapping and temporal partitioning for FPGAs. It is divided into 7 batches with different focus areas and references. The assignment is worth 10 marks total, with 5 marks for the assignment itself and 5 marks for a presentation. The assignment is due on November 19, 2012. Students should upload one word document per batch. References for each task are provided on the course website.

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Nirneya Gupta
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29 views

Assignment: (LUT Based Technology Mapping and Temporal Partitioning)

This document outlines an assignment involving LUT-based technology mapping and temporal partitioning for FPGAs. It is divided into 7 batches with different focus areas and references. The assignment is worth 10 marks total, with 5 marks for the assignment itself and 5 marks for a presentation. The assignment is due on November 19, 2012. Students should upload one word document per batch. References for each task are provided on the course website.

Uploaded by

Nirneya Gupta
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Assignment

(LUT Based Technology Mapping and Temporal Partitioning)


07-08-2012
Assignment and Presentation carries 05+05 marks. Last date for the assignment is 19-112012. Presentation schedule will be announced later. Upload only one word document per
batch. The references for the task are available in the course website.
Batch-1 (LUT based technology mapping- Area optimization)
MIS-fpga
Reference
R. Murgai, Y. Nishizaki, N. Shenoy, R. K. Brayton, and A. Sangiovanni-Vincentelli, Logic
synthesis for programmable gate arrays, in DAC 90: Proceedings of the 27th ACM/IEEE
conference on Design automation. New York, NY, USA: ACM Press, 1990, pp. 620625.
Batch 2 (LUT based technology mapping- Delay optimization)
MIS-pga-delay
Reference
R. Murgai, N. V. Shenoy, R. K. Brayton, and A. L. Sangiovanni-Vincentelli, Performance
directed synthesis for table look up programmable gate arrays. in ICCAD, 1991, pp. 572575.
Batch 3 (LUT based technology mapping- Maximizing the routability)
Bhat and Hill
Reference
N. B. Bhat and D. D. Hill, Routable technologie mapping for lut fpgas, in ICCD 92:
Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in
Computer & Processors. Washington, DC, USA: IEEE Computer Society, 1992, pp. 9598.
Batch 4 (LUT based technology mapping- Delay optimization)
DAG-map
Reference
K.-C. Chen, J. Cong, Y. Ding, A. B. Kahng, and P. Trajmar, Dag-map: Graph-based fpga
technology mapping for delay optimization, IEEE Design and Test of Computers, vol. 09, no. 3,
pp. 720, 1992.

Batch 5 (LUT based technology mapping- Area optimization)


Xmap
Reference
K. Karplus, Xmap: A technology mapper for table-lookup field-programmable gate arrays, in
DAC 91: Proceedings of the 28th conference on ACM/IEEE design automation. New York,
NY, USA: ACM Press, 1991, pp. 240243.
Batch 6 (Temporal Partitioning, NLP)
Reference
M. Kaul and R. Vemuri, Optimal temporal partitioning and synthesis for reconfigurable
architectures, 1998.
Batch 7 (Temporal Partitioning: Network Flow, it uses Flow map Algo)
Reference
H. Liu and D. F. Wong, Network flow-based circuit partitioning for time-multiplexed FPGAs,
in IEEE/ACM International Conference on Computer-Aided Design, 1998, pp. 497504

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