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Arbiter Testbench

This testbench code is testing an input arbiter module. It initializes the input requests and clock signals. It then applies different combinations of requests to the arbiter over time and checks the grant outputs to test that the arbiter is prioritizing requests correctly.

Uploaded by

chaitucvs
Copyright
© © All Rights Reserved
Available Formats
Download as ODT, PDF, TXT or read online on Scribd
124 views

Arbiter Testbench

This testbench code is testing an input arbiter module. It initializes the input requests and clock signals. It then applies different combinations of requests to the arbiter over time and checks the grant outputs to test that the arbiter is prioritizing requests correctly.

Uploaded by

chaitucvs
Copyright
© © All Rights Reserved
Available Formats
Download as ODT, PDF, TXT or read online on Scribd
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TESTBENCH CODE FOR INPUT ARBITER

module testarb;
// Inputs
reg [0:7]req0;
reg [0:7]req1;
reg [0:7]req2;
reg [0:7]req3;
reg rst;
reg clk;
// Outputs
wire gnt0;
wire gnt1;
wire gnt2;
wire gnt3;
// Instantiate the Unit Under Test (UUT)
arbitter uut (
.req0(req0),
.req1(req1),
.req2(req2),
.req3(req3),
.gnt0(gnt0),
.gnt1(gnt1),
.gnt2(gnt2),
.gnt3(gnt3),
.rst(rst),
.clk(clk)
);
initial begin
req0 = 0;
req1 = 0;
req2 = 0;
req3 = 0;
rst = 0;
clk=0;
end
always #5 clk=~clk;
initial begin
// Initialize Inputs
#10;
req0=8'b11111111;
req1=0;
req2=0;
req3=0;
#20;
req0=0;
req1=0;
req2=8'b10101010;
req3=0;
#20

req0=0;
req1=0;
req2=8'b10111010;
req3=0;
#20;
#20
req0=0;
req1=0;
req2=0;
req3=8'b11111111;
#20;
req0=8'b10111110;
req1=8'b00011000;
req2=8'b10110000;
req3=8'b10000000;
#20;
req0=0;
#20;
req1=0;
#20;
req2=0;
#20;
$finish;
end

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