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Mid Vlsi Fall2015 Sol 4

This document contains the solution to a midterm exam for a course on Very Large Scale Integrated Systems (VLSI Design). It includes 3 questions testing knowledge of VHDL modeling and design of integrated circuits. The questions involve designing a basic rate generator (BRG), a transmitter/receiver module (TX_RX), and using these modules in a top-level design.

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Mohamad El-Masry
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© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
29 views

Mid Vlsi Fall2015 Sol 4

This document contains the solution to a midterm exam for a course on Very Large Scale Integrated Systems (VLSI Design). It includes 3 questions testing knowledge of VHDL modeling and design of integrated circuits. The questions involve designing a basic rate generator (BRG), a transmitter/receiver module (TX_RX), and using these modules in a top-level design.

Uploaded by

Mohamad El-Masry
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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Faculty of Engineering

Solution of the Mid Exam


Fall 2015
Faculty

Engineering

Department

Electrical Communication & Electronic Systems

Module Code

ECE 511,445

Module Title

VLSI Design

Semester

58 - Fall 2015 (Solution)

Time Allowed

90 minutes

Total Mark

20

No. of Pages

5 including cover page

Material provided

None

Equipment permitted

Calculators

Additional Instructions None


No books, paper or electronic devices are permitted to be brought into the examination
room other than those specified above. Answers in Arabic will be disregarded and will
not be graded.

Faculty of Engineering
Mid Exam
Fall 2015
Module Title
: Very Large Scale Integrated Systems
Module Code
: ECE 511,445
Semester
: 58
--------------------------------------------------------------------------------------------------------------Question 1

(7 marks)

library ieee;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity BRG is
port ( A : IN STD_LOGIC_VECTOR( 15 DOWNTO 0);
clk , rst , S: in std_logic;
clkO : out std_logic);
end BRG;
architecture BRG of BRG is
signal T : std_logic ;
begin
process (clk , rst)
variable i : STD_LOGIC_VECTOR(16 DOWNTO 0) := (OTHERS => '0' );
begin
if rst = '0' then
T <= '0';
i := 0 ;
else
I := I+1 ;
if ( I = (A & '0' ) ) then
T <= not T ;
I := 0;
end if;
end if;
end process ;
WITH S SELECT
CLKO <= T WHEN '0' ,
CLK WHEN '1' ,
'Z' WHEN OTHERS ,
end BRG;
2

Question 2

(7 marks)

Library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
Entity TX_RX is
PORT ( TR : INOUT STD_LOGIC_VECTOR (11 DOWNTO 0);
TX , RX , RST , CLK : IN STD_LOGIC ;
TXF , RXF , D : INOUT STD_LOGIC )
);
End TX_RX ;
Architecture G of TX_RX is
Begin
process (clk )
variable i : integer := 0 ;
IF RISING_EDGE(CLK) THEN
if rst = '1' then
D <= '0'; RXF <= '0'; TXF <= '0';
i := 0 ;
else
IF ( TX = '1' AND RX = '0' ) THEN
IF TXF = '0' THEN
D <= TR ( I) ;
I := I+1 ;
if I = 12 then
TXF <= '1' ;
I := 0;
end if;
ELSIF TXF = '1' THEN
TXF <= '0' ;
END IF ;
END IF;
3

IF ( TX = '0' AND RX = '1' ) THEN


IF RXF = '0' THEN
TR ( I) <= D ;
I := I+1 ;
if I = 12 then
RXF <= '1' ;
I := 0;
end if;
ELSIF RXF = '1' THEN
RXF <= '0' ;
END IF ;
end if;
end if;
END IF ;
end process ;
END G ;
Question 3

(6 marks)

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
Entity TOP is
PORT ( UDB : INOUT STD_LOGIC_VECTOR ( 11 DOWNTO 0 );
UBRR : IN STD_LOGIC_VECTOR ( 15 DOWNTO 0 );
TEN , REN , SEL , GRS , OSC : IN STD_LOGIC ;
D_PAD , TF , RF : INOUT STD_LOGIC);
End TOP ;
Architecture TOP of TOP is
COMPONENT BRG
port ( A : IN STD_LOGIC_VECTOR( 15 DOWNTO 0);
clk , rst , S: in std_logic;
clkO : out std_logic);
END COMPONENT ;

Component TX_RX
PORT ( TR : INOUT STD_LOGIC_VECTOR (11 DOWNTO 0);
TX , RX , RST , CLK : IN STD_LOGIC ;
TXF , RXF , D : INOUT STD_LOGIC )
);
End Component;
SIGNAL CLK_T : STD_LOGIC;
BEGIN
Begin
X1 : BRG PORT MAP (UBRR , OSC , GRS , SEL , CLK_T) ;
X2 : TX_RX PORT MAP (UDB , TEN , REN , GRS , CLK_T , TF , RF , D_PAD) ;
END TOP ;

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