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Pseudo-nMOS, Dynamic CMOS and Domino CMOS Logic

The document discusses different logic styles for low-power electronic circuit design including pseudo-nMOS, dynamic CMOS, and domino CMOS logic. It provides details on their operation and tradeoffs between speed, power consumption and reliability compared to static CMOS logic.

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Dhirendra Kumar Singh
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102 views23 pages

Pseudo-nMOS, Dynamic CMOS and Domino CMOS Logic

The document discusses different logic styles for low-power electronic circuit design including pseudo-nMOS, dynamic CMOS, and domino CMOS logic. It provides details on their operation and tradeoffs between speed, power consumption and reliability compared to static CMOS logic.

Uploaded by

Dhirendra Kumar Singh
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPT, PDF, TXT or read online on Scribd
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ELEC 5270/6270 Spring 2011

Low-Power Design of Electronic Circuits

Pseudo-nMOS, Dynamic CMOS


and Domino CMOS Logic
Vishwani D. Agrawal

James J. Danaher Professor


Dept. of Electrical and Computer Engineering
Auburn University, Auburn, AL 36849
[email protected]
http://www.eng.auburn.edu/~
vagrawal/COURSE/E6270_Spr11/course.html
Copyright Agrawal, 2007

ELEC6270 Spring 11, Lecture 9

Static CMOS: Pros and Cons


Advantages:

Static (robust) operation, low


power, scalable with technology.
Disadvantages:
Large

size: An N input gate requires 2N transistors.


Large capacitance: Each fanout must drive two
devices.
Alternatives:

Pass-transistor logic (PTL),


pseudo-nMOS, dynamic CMOS, domino CMOS.

Copyright Agrawal, 2007

ELEC6270 Spring 11, Lecture 9

A Pseudo-nMOS Gate
VDD

VDD

PUN
Output

PDN

Inputs

Inputs

Output

CMOS Gate
Copyright Agrawal, 2007

PDN

Pseudo-nMOS Gate
ELEC6270 Spring 11, Lecture 9

Pseudo-nMOS NOR
VDD

Output
Input 1

Copyright Agrawal, 2007

Input 2

Input 3

ELEC6270 Spring 11, Lecture 9

Pseudo-nMOS NAND
VDD

Output

Input 1

Input 2

Copyright Agrawal, 2007

ELEC6270 Spring 11, Lecture 9

Pseudo-nMOS Inverter
VDD

Output
Input

Copyright Agrawal, 2007

ELEC6270 Spring 11, Lecture 9

Inverter Characteristics
3.0

Nominal device:

Output voltage, V

2.5

W
0.5
= = 2
Ln
0.25

W/Lp = 4

2.0
1.5

W/Lp
= 0.5

1.0

W/Lp
=1
W/Lp = 2

0.5
W/Lp = 0.25

0.0
0.0

0.5

1.0

1.5

2.0

2.5

Input voltage, V
Copyright Agrawal, 2007

ELEC6270 Spring 11, Lecture 9

Performance of Inverter
Size, W/Lp

Logic 0 voltage

Logic 0 static
power

Delay
01

0.693 V

564 W

14 ps

0.273 V

298 W

56 ps

0.133 V

160 W

123 ps

0.5

0.064 V

80 W

268 ps

0.25

0.031 V

41 W

569 ps

J. M. Rabaey, A. Chandrakasan and B. Nokoli, Digital Integrated


Circuits, Upper Saddle River, New Jersey: Pearson Education, 2003,
page 262.
Copyright Agrawal, 2007

ELEC6270 Spring 11, Lecture 9

Negative Aspects of Pseudo-nMOS


Output

0 state is ratioed logic.


Faster gates mean higher static power.
Low static power means slow gates.

Copyright Agrawal, 2007

ELEC6270 Spring 11, Lecture 9

A Dynamic CMOS Gate


VDD
Precharge
transistor

Inputs

Output

CK

Copyright Agrawal, 2007

PDN

CL

Evaluate
transistor

ELEC6270 Spring 11, Lecture 9

10

Two-Phase Operation in a Vector


Period
Phase

CK

Inputs

Output

Precharge

low

dont care

high

Evaluation

high

Copyright Agrawal, 2007

Valid inputs Valid outputs

ELEC6270 Spring 11, Lecture 9

11

4-Input NAND Dynamic CMOS Gate


VDD
CK

Output
= CK + (ABCD) CK

A
B

CL
tLH 0

C
D
CK

Copyright Agrawal, 2007

ELEC6270 Spring 11, Lecture 9

12

Characteristics of Dynamic CMOS

Nonratioed logic sizing of pMOS transistor is not important


for output levels.
Smaller number of transistors, N+2 vs. 2N.
Larger precharge transistor reduces output fall time, but
increases precharge power. Faster switching due to smaller
capacitance.
Static power negligible.
Short-circuit power none.
Dynamic power

no glitches following precharge, signals can either make transitions


only in one direction, 10, or no transition, 11.
only logic transitions all nodes at logic 0 are charged to VDD during
precharge phase.

Copyright Agrawal, 2007

ELEC6270 Spring 11, Lecture 9

13

Switching Speed and Power


Fewer

transistors mean smaller node


capacitance.
No short-circuit current to slow down
discharging of capacitance.
Only dynamic power consumed, but can
be higher than CMOS.

Copyright Agrawal, 2007

ELEC6270 Spring 11, Lecture 9

14

Logic Activity
Probability

of 0 1 transition:

Static

CMOS, p0 p1 = p0(1 p0)


Dynamic CMOS, p0 p0 p1
Example:

2-input NOR gate

Static

CMOS, Pdyn = 0.1875 CLVDD2fCK


Dynamic CMOS, Pdyn = 0.75 CLVDD2fCK
p1 = 0.5

p1 = 0.25
p0 = 0.75

p1 = 0.5
Copyright Agrawal, 2007

ELEC6270 Spring 11, Lecture 9

15

VDD
CK

Output
A

A=0
CK

CL

Evaluate

CK

Precharge

Charge Leakage

A
Ideal
Actual
Time

J. M. Rabaey, A. Chandrakasan and B. Nokoli, Digital Integrated


Circuits, Upper Saddle River, New Jersey: Pearson Education, 2003.
Copyright Agrawal, 2007

ELEC6270 Spring 11, Lecture 9

16

Bleeder Transistor
VDD

VDD

CK

CK
Output

A
B

CL

CK

CK

Copyright Agrawal, 2007

Output

ELEC6270 Spring 11, Lecture 9

CL

17

A Problems With Dynamic CMOS


VDD

VDD

CK
A=01
CK

CK

prech. evaluate

CK
B

C
CK

A
B
C

J. M. Rabaey, A. Chandrakasan and B. Nokoli, Digital Integrated


Circuits, Upper Saddle River, New Jersey: Pearson Education, 2003.
Copyright Agrawal, 2007

ELEC6270 Spring 11, Lecture 9

18

Remedy
Set

all inputs to gates to 0 during


precharge.
Since precharge raises all outputs to 1,
inserting inverters between gates will do
the trick.

Copyright Agrawal, 2007

ELEC6270 Spring 11, Lecture 9

19

Domino CMOS
VDD
CK
A=01
CK

VDD
CK

CK prech.

evaluate

CK

B
C

R. H. Krambeck, C. M. Lee and H.-F. S. Law, High-Speed Compact


Circuits with CMOS, IEEE J. Solid-State Circuits, vol. SC-17, no. 3,
pp. 614-619, June 1982.
Copyright Agrawal, 2007

ELEC6270 Spring 11, Lecture 9

20

Bleeder in Domino CMOS


VDD
CK

Output

A
B

CL

C
D
CK
Copyright Agrawal, 2007

ELEC6270 Spring 11, Lecture 9

21

Logic Mapping for Noninverting Gates


AND
A

ABC

C
D
Y

E
F
G
G+H

OR

ABC

AND/OR

D
E

F
G+H
Copyright Agrawal, 2007

ELEC6270 Spring 11, Lecture 9

22

Selecting a Logic Style


Static

CMOS: most reliable and predictable,


reasonable in power and speed, voltage scaling
and device sizing are well understood.
Pass-transistor logic: beneficial for multiplexer
and XOR dominated circuits like adders, etc.
For large fanin gates, static CMOS is inefficient;
a choice can be made between pseudo-nMOS,
dynamic CMOS and domino CMOS.

Copyright Agrawal, 2007

ELEC6270 Spring 11, Lecture 9

23

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