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Constant and High Speed Adder Design Using QSD Number System

This document describes a constant and high speed adder design using a Quaternary Signed Digit (QSD) number system. QSD allows for carry-free addition and borrow-free subtraction by representing each digit as a number from -3 to 3. This allows large numbers with 64 or more digits to be added with constant delay and less complexity compared to binary. The QSD adder design is simulated using ModelSim and synthesized using Microwind and Leonardo Spectrum. Verilog HDL is used and Modelsim and Xilinx ISE tools are required.

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Vishal Pathak
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41 views1 page

Constant and High Speed Adder Design Using QSD Number System

This document describes a constant and high speed adder design using a Quaternary Signed Digit (QSD) number system. QSD allows for carry-free addition and borrow-free subtraction by representing each digit as a number from -3 to 3. This allows large numbers with 64 or more digits to be added with constant delay and less complexity compared to binary. The QSD adder design is simulated using ModelSim and synthesized using Microwind and Leonardo Spectrum. Verilog HDL is used and Modelsim and Xilinx ISE tools are required.

Uploaded by

Vishal Pathak
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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Constant and high speed adder design using QSD

number system
ABSTRACT
With the binary number system, the computation speed is limited by
formation and propagation of carry especially as the number of bits increases.
Using a quaternary Signed Digit number system one may perform carry free
addition, borrow free subtraction and multiplication. However the QSD number
system requires a different set of prime modulo based logic elements for each
arithmetic operation. A carry free arithmetic operation can be achieved using a
higher radix number system such as Quaternary Signed Digit (QSD). In QSD, each
digit can be represented by a number from -3 to 3. Carry free addition and other
operations on a large number of digits such as 64, 128, or more can be
implemented with constant delay and less complexity. Design is simulated &
synthesized using Modelsim6.0, Microwind and Leonardo Spectrum.

LANGUAGE USED:
Verilog HDL
TOOLS REQUIRED:
MODELSIM Simulation
XILINX-ISE Synthesis

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