| t COs/ MOS Integrated Circuits CS 3 ees ne aeA New Approach To Data Service... 1975 RCA Solid State DATABOOKS Seven textbook-size volumes covering all current commercial RCA solid-state devices (through January 1, 1975) Linear Integrated Circuits and DMOS Devices (Data only) 2.0... eee ee eee eee SSD-201C Linear Integrated Circuits and DMOS Devices {Application Notes only) ...........--.-..-04 SSD-202C COS/MOS Digital Integrated Circuits . -SSD-203C Power Transistors -SSD-204C RF /Microwave Devices .. . .SSD-208C Thyristors, Rectifiers, and Diacs . . High-Reliability Devices Announcement Newsletter: ‘What's New in Solid State’ Availabe FREE to all DATABOOK users. "Bingo-type Response-Card Service” included with News- letter Available FREE to all DATABOOK users. Update Mailing Service available by subscription. \ndexed Binder available for Update Filing. NOTE: See pages 3 and 4 for additional information on this total data service. To qualify for Newsletter mailing, use the form on page 4 (unless you received your DATABOOK directly from RCA). You must qualify annually since a new mailing list is started for each edition of the DATABOOKS.RGA COS, MOS Integrated Circuits This DATABOOK contains complete data and related application notes on COS/MOS digital integrated circuits presently available from RCA Solid State Division as standard products. For ease of type selection, functional diagrams are shown on pages 8-18. Data sheets are then included in type-number sequence, followed by output-drive- current test-circuit connections, terminal- assignment diagrams, and dimensional outlines for all types, by application notes in numerical order, and finally by a comprehensive subject index. To simplify data reference, data sheets are arranged as nearly as possible in numerical sequence of device type numbers. Because some data sheets include more than one type number, however, some types may be out of sequence. If you don’t find the type you're looking for where you expect it to be, please consult the Index to Devices on page 7.Trade Mark(s} Registered © Marca(s) Registrada(s) Copyright 1974 by RCA Corporation {Alt rights reserved under Pan-American Copyright Convention) Printed in USA/11-74 Information furnished by RCA is believed to be accurate and reliable. However, no responsibility is assumed. by RCA for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of RCA. RCA Solid State | Box 3200 | Somerville, N.J., U.S.A. 08876 RCA Limited | Sunbury-on-Thames | Middlesex TWi6 7HW, England RCA s.2. | 4400 Herstal | Liege, Belgium 2RCA Solid State Total Data Service System The RCA Solid State DATABOOKS are supplemented throughout the year by a comprehensive data service system that keeps you aware of all new device announcements and lets you obtain as much or as little product information as you need — when you need it. New solid-state devices and related publications announced during the year are described in a newsletter entitled ‘What’s New in Solid State’. If you obtained your DATABOOK\s) directly from RCA, your name is already on the mailing list for this newsletter. If you obtained your book(s) from a source other than RCA and wish to receive the newsletter, please fill out the form on page 4, detach it, and mail it to RCA. Each newsletter issue contains a “bingo’-type fast-response form for your use in requesting information on new devices of interest to you. {f you wish to receive all new product information published throughout the year, without having to use the newsletter response form, you may subscribe to a mailing service which will bring you all new data sheets and application notes in a package every other month. You can also obtain a binder for easy filing of all your supplementary material. Provisions for obtaining information on the update mailing service and the binder are included in the order form ‘on page 4. Because we are interested in your reaction to this approach to data service, we invite you to add your comments to the form when you return it, or to send your remarks to one of the addresses listed at the top of the form. We solicit your constructive criticism to help us improve our service to you.Order Form for “What's New in Solid State” and for further information on Update Mailings and Binders Please fill out just ane copy of this form, and mail it to: {a) from U.S.A. and Canada: . RCA Solid State Division Box 3200 Somerville, N. J., U.S.A. 08876 (b) from Latin America and Far East: RCA Solid State international Sales ‘Somerville, N. J., U.S.A. 08876 {c) from United Kingdom, Europe, Middle East, and Africa: RCA Limited RCA s.a. ‘Sunbury-on-Thames or 4400 Herstal Middlesex TW16 7HW, England —_Liege, Belgium CiPtease add my name to the mailing list for “What's New in Solid State” OPlease send me details on obtaining update mailings for my DATABOOKS. and a binder for filing of supplementary material. - Name (Last) (initials) Company Address (Number! (Street, RFD, P.O, Box) Home Business (city) (State or Prov.) (Country) (Zip or Pstl. Zone) Funetion: (Check One) Activity: (Cheek One) Product Interest: indicate order of intorost if An Executive/ Administration ‘more than one is marked! 3.9 PrchannglProcoremant AL Jtinear 1¢'s C5 Researeh/Development 1s, COS! Bo Design engineer [pista c's, cosimos ED Appiieation/Components cLoigita1c's, Bipolar Engineer § Frhycstors Rectifiers FO Production/Menutscturing rvsale Ga euros He e(luauia Cra HO Reliability 40 F[L semiconductor Diodes 10 Education Training i 5 Comumer, Electronic ower Semiconductors 45 Progamproject Management G Consumer, Apolionce LIRF Powe: Semicond ic 0 Marketing No Space wLJmosrers Nb Ordnence fr Teanistors $0 Arones Epon F 3 Electronic Warfare J EJpemer Hybrid CieviteTable of Contents Page Index “o Application Notes ........ ence ence ee enes ree) 6 Index to Devices... .......0-0..0 0 eee e etn e neta rece eee eens 7 Functional Diagrams: Gates ...... Multivibrators . Flip-Flops . Latches . Shift Registers . . Counters ..... ene e eee Display Counters/Decoders/Drivers; Multiplexers Arithmetic Circuits . . Phase-Locked Loop . Schmitt Trigger . . Memories ... . Rate Multipliers . New Products Program .......... bebe eee eee eee bec eee pence e eee 19 Design and Operating Considerations ..............00085 beets beeen ZT COS/MOS Family Characteristics ...............-- beeeeene beeen nee eee 25 Ordering Information . . IC Packages and Lead Forms . Technical Data ........ tone Appendix: Output-Drive-Current Test-Circuit Connections - Terminal-Assignment Diagrams . . Dimensional Outlines Application Notes .... Subject Index ....Index to Application Notes Number Title 1CE-402 . “Operating Cansiderations for RCA Solid State Devices” . ICAN-6000 “Handling Considerations for MOS Integrated Circuits” . . ICAN-6080 - Digital-to-Analog Conversion Using the RCA-CD4007A COS/MOS IC” ICAN-6086......... “Timekeeping Advances Through COS/MOS Technology” ICAN-6101........, “The RCA COS/MOS Phase-Locked Loop — A Versatile Building Block for Micro-Power Digital and Analog Applications” . an ICAN-6166......... “COS/MOS MSI Counter and Register Design and Applications” 479 “Noise Immunity of COS/MOS Integrated-Circuit Logic Gates” “A Typical Data-Gathering and Processing System Using CD4000A Series COS/MOS Parts” . . ICAN-6176 ICAN-6210 ICAN-6218 ““Gate-Oxide Protection Circuit in RCA COS/MOS. ital Integrated Circuits” 514 ICAN-6224 “Radiation Resistance of the COS/MOS CD4000A Series” = seese cece. 516 ICAN-6230 “Using the CD4047A in COS/MOS Timing Applications" .. 518 ICAN-6267.......-. ““Astable and Monostable Oscillators Using RCA COS/MOS igital Integrated Circuits” . . ICAN-6289......-. “A COS/MOS PCM Telemetry and Remote Data Acquisition Design” “Power Supplies for COS/MOS Systems” . “Design of Fixed and Programmable Counters Using the ICAN-6304 ICAN-6498 RCA-CD4018A COS/MOS Presettable Divide-by-”N" Counter” ...-..+++++ 556 ICAN-6576 “Power-Supply Considerations tor COS/MOS Devices” 562 ICAN-6600 ‘Arithmetic Arrays Using Standard COS/MOS Building Blocks ICAN-6601 igital Signals 574 ICAN-6602 “Interfacing COS/MOS With Other Logic Families’ ICAN-6716 ital Frequency Synthesizers ing COS/MOS IC's” 598 ICAN-G733 2.0... “Battery Powered Digital-Display Clock/Timer and Metering Applications Utilizing the RCA-CD4026A and CD4033A Decade Counters — 7-Segment Output Types”... +... ss0eeeeeee 613 ICAN-6739......... “COS/MOS Rate Multipliers — Versatile Circuits for Synthesizing Digital Functions”Index to COS/MOS Integrated Circuits (Circuits marked with an asterisk (*) are also available in chip form, {A data shoot on COS/MOS IC chips, File No. 617, is available on request.) Type No. + epao00a, + epaoo1a, + coa002a, + coao04a, + cos0068, + 040078, + coao08a, co4o08a cp4o10a canna ep4o120 cpaoisa cpaoi4n coao18a cpaor6a eao170 cepaor8a caorea ‘co40208, coao21A, + cpao220 cosas, + opaozaa + coa0260 e40260 ep40z7A cp40z80 cD40290 * epaosoa + coaas1a, * cD40320 * co4033a * cpana4a + cDa0g5A + cpang6a + epang7A + cpaosea + cD4039a » cpao4oa + cpaoata + cp4042a + cDa043a + cpaoaaa + cDa045A + cpaoa6a + cpana7A + cpaodea * cpaoasa + cOa0s0a e405, cD 40828 cp40s3a, Description ‘Dual 3.input NOR gate plus inverter ‘Quad 2 input NOR oa Duel 4-input NOR, Replaced by CD4024A Series teestage static shit rogistor ual complementary pair plus inverter “4bit full addar with par ual 4-input NAND gore vol "D" fip-tlop with set/aser ‘estage static shift register Duel 4-stage static shift register ‘Quad bilateral switch Decade counteriaivicer Presettable divideby”N” counter Quad AND-OR select sate 14stage bineryiripple counter Batage static shift rapister Dividery-8 counter/aivider Triple S-nput NAND oat “Tetage binary counter ‘Triple 3input NOR gate Decade counter/divider Dual J-K mastarsieve fipstop ECD-to-decimal decoder Presettable upidown counter (Quad exclusive-OF gate GAstage static shit registor “Triple serial adder (positive logic) Decade counteriaivicer MSI B-stage static shift rogistor “4stage peraie! in/out shift register 4word x B-bit RAM [binary addressing) “Triple AND-OR bi-phave pairs “Triple serial adder (negative tog) word x B-bit RAM (wording addressing) ‘2at0ge binery/rippla counter (Quad true/complement but ‘Quad clocked "0" latch ‘Quad State NOR A/S latch ‘Quad d-state NAND AIS tatch ‘21-stage counter IMicropower phase-locked loop Monostable/astable multivibrator Expandable Binpust gote Hex butfer/eonvertr (inverting) Hex butfer/eonvertar (non-inverting) ‘Single Bchannel multiplexer ferential 4-channel multiplexer “Triple 2-channe! multiplexer Page No. Sfelzssgggsesiaegs 104 108 m4 119 124 32 130 139 145 150 197 162 168 130 173 18 108 195 163 183 208 212 a6 216 222 27 234 245, 282 252 259 259 259 Type No, + coso54a, + COs055A, * epaosea * eD40s7A ‘cpdos9a + ep406oa + cpaogia + ep4062a * cp40638. * cpsogsa cD40678, * cpsosaa, + cpacese 040708, + cpao71e + epao728 + co40738 * cpa0758 040768, 040778, + cpao7aa. + epaosie + cpsoa28 + cp408s8 + epaoesa cao898 * cp40038 cp40048, cpa0958 ep4ce68 40078 ‘epa0088 040098, cpaso28, co4si18 + coastaa, * coasts, * cossie8 coas208 045278 048328 * cpassea * cossses Deseription ‘ine Hiquic-erystalclspley driver 8CD-7-s9qment decodsr/driver [BCD-7- BINARY CONTROL INPUTS Nec*! 2) |4 ee vss"? Yee ‘FuNeTION CONTROL eRe yg 2STNE 3 He Re Re Ky {to De : [> wn *, [> | L, outeur ==" oe Lose AND OR PAIR Vn oy eae ois | 1 Moo je "—— epoo tLe AB os vastt off soon i enaatevene vss Lee v2cs-23070R| J*INM +ENABLE + AB+COFEF+ OH seeeazaae eriaess cotoaca ceososea coer7a Expandabn Wide, 24nput uttuntiona! Expandable Tine AND-OR tr? has Pie ‘AND. OF tnvrt (AO!) Geto input Gave (3 Cut State No. 876 File No. 812 File Ne, 636GATES Buffers & Inverters Dok. fet et Det: ot Dot. et Dotde Bho v55°7 cnaao7a cp40898 Dual Complementary Hex Pale Plus inverter Invortor No, 478 File No, 804 coxa0%e fees. eSabao4 te eDao09A, cD4049A epaoi0a, cD4050A File No.479 File No, 599 File No. 478 File No, 699 Hox Butfor/Convartar Hox Buffer/Convertor Non-tnverting Type Inverting Type Nest? Yoo" tes zosent epaoata ‘Quad Trus/Complerrent ‘Butter File No, 572 10 MULTIVIBRATORS € e-rmine ans Reon ~~ eccnaron aut | \ ssmout [sane Samet] Bi. ' Fen | ‘meevraror ‘ scuecr ws@tara| 8 2 Pa . | eye /i * : smoees@— 15 |g lure ue ° in » 2O}REH gH & ft = srooee@t— 7) 2 |i .——_l] =| srroaes coast18 20-107 Segment Latch REO Decoder Driver cossa28 tees-eo080 Praliminery ‘B-Input Priority Encoder COO56A {Line Ligud-crytl Disp Orivar File No. 624 ot ie @ ge em Se oS rou Hite. ° I roll é 1 POH on. hea wee OTT ET) pg Te "Olathe +e 2Or =e obeeaey 2 @H 5 [o. cline BEOLY sree © 5 aur aiseay-@! & FREQ IN, H+-@ Ho e0a056A, Liquid Crystal 8CO to 7-Sgment Decoder/Oriver ‘with Strobed-Latch Funetion Filo No. 634 15MULTIPLEXERS 1 wou] | ed a 2 ot cps0878 Re-2627 16-Chenne stceceaon0 Montiplexer/Demuttiplexer cpso16a 0568 Prliminary ‘epa0e78: ‘Quod Bilateral Switch Differential Channel File No.479 File No, 768 °, ‘ 1 our nao ie 00 a 4% iz ot ‘ a 2 a oom ae te “im } 20 a 2 op e La 040514 & ® Sh Single 8-Chennat 3 5 ws ral a Yes af javton cpass68 epassee | Dusl 1-04 Decoder/Demultiplexors ook foot Outpt Hh rene ey OubutLow “EI contre. Sac TRUTH TABLE ‘co4052A INPUTS: ‘OUTPUTS ‘oureurs Difteconta 4 Channel ENABLE [SELECT | __c04s658 eDa8568 Preliminary tr 8} A |a3| a2) | oo] 33 | O2| ai | O60 — o [ole folojo|+]i|i|fifo our OR oy CUTAN twrour fon by Ourrin o [ols fojo{sfofs{ifo|s wwovr {3 fe ex aurrn o [sto folsfolfo|+jo|:|1 cea SPrbe reer pb a] + [xlxfelolefof+|+|+ fa cos0ssa X= DONT CARE ‘Triple 2Channe! Preliminary 16 zy 1 oF @ nEccDER =z oe oceooen —, T T oot oot 1 {J i x] ~ Louth ' See tor st wry NI ° f sot 4]not eo KO! * fox 0% TemwinaL mo 82955 coaooen Foursit Full Adder with Pratl Carry Out File No, 479 ep40638 ARITHMETIC CIRCUITS: 4.21 Magnitude Comparator vss EMER cpsoaea Phase-Locked Loop File No, 637 a vo0 went =m current ai fe vent “sum af sts) [eenwne® se | | seecoes Ste] | Soares 8 Tee | feet west som q canny nese a coao28a scenes 8cD.to Decimal Decoder oes —_co40s8a File No, 503 “eile Serial Adders + = one Losie Losle care File No. 503 colthon mama sate sues LEFT SEmAL OHTA UNE siP YORE SHE REL ou sem neo bara une 2 renee taf pat Ee cacsiour SELECT 1 runeronas & apres s [Se taeBro0x MaDe contra. mcs St ABO mortal es tassour Hitter 1 Lock ‘ovenriow Yoo" !6 sos ‘CONDITIONAL ue vest mona} cock ss sgtomom ssl Swe stennz050 overrvow fo WeUTTOUTPOT oc oeaam nceisren coa0s7A 151 4.8 Arithmete Loole Unit File No. 635 SCHMITT TRIGGER, 22cs-23060 ep40038 (Quad 2cinput NAND Type File No. 856 7MEMORIES Word Organized warre_J 5 TNPUT GATING, P| 1 oH u Er bora x a 2 14] TTTTTT rong ranghigh BH ae ewory wen ions (eeaao cos0ssa co10304 se0e (nary Aderosing! «Word x88 (ret Wont Adri) aN ev3 iene. 613 Bit- Organized vss @—0 DAG) eG) EC sees %e0 @—0 { @ we. va > ara our ®@ «.., Es DecOoE y iow ;——4 : cwrtheace |< —6 Ay HH YY 2 e0a0614, 256-WWord by 1-8it Static Random Access Fle No, 763, RATE MULTIPLIERS. ss case tty [2 four mycrimuer 4 o2] | cucan—5T coasz78 BOD Rate Muttintior Prolieinaty 8NEW PRODUCTS PROGRAM ‘The CD Preliminary COS/MOS types listed below are some of the devices scheduled for introduction during 1975. Logie diagrams and terminal assignment diagrams are shown following the listing. Additional types will also be announced throughout the year. For information concerning announcement dates and product aveilability”, contact your RCA representative or supplier, or watch for announcement in the RCA Solid State Announcement Newsletter "What's New In Solid State” referred to on the inside front cover of this DATABOOK. Similar borne Cireuit Description Industry Type cp4s088, Dust 4-Bit Latch c14608 cp45108, 4-Bit BCD Up/Down Counter Mc14610 0045168 4.Bit Binary Up/Down Count MC14516 cp401008 32-Bit Left/Right i - cp4o1018 9-Bit Parity Generator & Checker - 00401028 Presettable 8-Bit BCD Down Counter - cp401038 Presettable 8-8it Binary Down Counter - cp401048 Three State 4-Bit Left/Right Shift Register - cp401058 4Word X 4-Bit FIFO Buffer - cp401068 Hex Schmitt Trigger Inverter - cpao1078 Dual 2-Input NAND Buffer/Driver - cp401088 4X 4 Multiport Register - cpao1818 4Bit Arithmetic Logic Unit - cpaota28 Look-Ahead Carry Block - cp401928 ‘Synchronous 4-Bit BCD Up/Down Counter (Dual Clock) - ep401938 ‘Synchronous 4-Bit Binary Up/Down Counter (Dual Clock) - cpa01048 4-Bit Left/Right Shift Register - “Because of tha wide intoest in COS/MOS parts, RCA reserves the right to limit sample quantities. vo —4 I 90 Lehr suet oof Boe naar scemeucae EES REGISTERS a fo arr ure os 3 eta 12 Ret yy boas e—bara Reavy Loon | Lean our cues aa 2m nese 7 our LEFT S| [2 tT 118.710.1615: cp401088 Yov"'S + Yes"® —— szcs-2eers ord x 4 Bit FIFO Butter co4o1008 22.8it Lofe Right Shitt Resist reser word & REET oe oureur nor cof 1S op same —, | or 4 fea oo He a0 wareo—) | 2 7 rn wre) — noe Ie es ar re ee 2s os 0 2 reap ia ee exoex 1 a 2 os READ 08- 81 wor, ‘SET Suck 7 ter, 2— oa ourru wea snes Su aw reno 8 —2| Las [2 EF mw isit_] tao 6—"4 mone | Mo. mope (Mo 91 9 seer], 10 oot oe Mi 19] Woortt cwoc desta « —— “* 5 ocean eer scence cos01088 epao1088 co4o1s4a 2State 4.Bit LateRigbt 4x 4 Multiport Register “Bit Left/Right Shit Register ‘Shit Regitar 19COUNTERS eset pecs-ensa cpasi08 coa5168 cD Binary 4.BIt Up/Down Counters LATCHES s-stare PRESET ERLE 0 20 o1 ot " eal oes 02 reser a 0. nese oureurs 08 INPUTS ec] srR08e. Po. 0) reser couNr uP camRy Ou oe IT G0 count oown SORROW OUT ri po reser Yoor's oe ae Sieve es Pe ‘STROBE cpaor9z8 cp4otsa8 vop-24 ‘8c Binary eser Ysso12 ‘Synchronous 4-Bit Up/Down Counters cpssoee Dust ait Latch BUFFERS AND INVERTERS yk Fo Pr pe Pa paps ps or oo = ewcaer Les Jo br bo | be ly oon SHEE sl tole a syn, ENABLE 91 3 38% Lie canes ourr | 4 ~ ol So le N vss cxocx: 00 4 Poe A RESET s2cs-2ens p wTe s|_ > liz comms coworone we vo Siow ss | Yon vent rromcate 88 Down Cots mre e cosorore seca Dual atop NaWD Bsa9:he Tae oe ARITHMETIC PARITY GENERATOR ‘CIRCUITS: FUNCTION SELECT a mae Bs 2 a 0 ourpur iNET Ye cry ‘compare oe woe ot 2 “ex poet aye or eee _ ‘our ‘oo poe cxenr w SE— x) 80% Wo g moor M __8} yO FY Canny be oi, ot se en couoro1e cososaaa cose oi ary Grr Lenker Bok ‘0% att Lie Un srdcester 20COS/MOS Design and Operating Considerations The information on the following pages serves as a brief introduction to COS/MOS specifications, ratings, and perform- ance characteristics, This information is included to help the user avoid problems in connection with over-all systems design. COS/MOS operation, design, and layout fundamentals ‘ase discussed in detail in the RCA COS/MOS Integrated Circuits Manual, CMS-211, ‘Maximum Ratings ‘The maximum ratings for all the COS/MOS devices included in this book are as follows: Characteristic Symbol “A” Series “B" Series Unit Supply Voltage Vpp- #151008 #181005 Vde Vss Input Voltage, All Inputs y, Vos “Vi Ypp Ve Device Power Dissipation per package Pp 200 mW Operating-Teniperature Range: T Ceramic Packages -55 to+125 °c Plastic Package AO t0 +85 °c Storage-Temperature Range: Typ 65 10 +150 °c Lead Temperature (Curing soldering) ata distance of 1/16 1/32 inch (1.5940.79 mm) from case for 10sec Tread +265 °C Operating Supply-Voltage Range COS/MOS integrated circuits are specified in one of two supply-voltage ranges: “A” -series devices operate from 3 10 15 volts, and “B"-series devices from 3 to 18 volts. Logic systems occasionally experience transient conditions on the power- supply line which, when added to the nominal power-bus voltage, could exceed the safe limits of circuits connected 10 the power bus. Recommended supply-voltage ranges. which realistically assess these conditions are 4 to 12 volts for “A series devices, and 4 to 15 volts for “B” sexies devices. The recommended maximum power-supply limit is substan- tially below the minimum primary breakdown limit for the devices to allow for limited powersupply transient and regulation limits. The minimum recommended supply voltage of 4 volts also takes into account transient and regulation limits. In addition, cireuits that operate in a linear mode over a portion of the voltage cange, such as RC or erystal oscillators, often require a supply voltage of at least 4 volts. Power Dissipation Power dissipation in a COS/MOS device is composed of two terms, quiescent (éc) dissipation and dynamic (ac) dissipation, Pg and P,, respectively. Quiescent dissipation, generally varying {rom a few nanowatts for small devices to tens of microwatts for large devices, 1s due to a combination of leakage effects comprising parasitic junction diodes (normally reverse-biased) and surface effects. Dynamic dissipation is comprised of two elements: (1) “through”-current that exists during the transition from one logic level to the other, when both N-MOS and P.MOS devices are momentarily conducting simultaneously, and (2) power-supply current required to charge the node and output capacitance during switching. The first component {internal switching) of dynamic dissipation is usually negligible compared to the component associated with charging capacitance, particularly for systems with fast rise and fall times. As transition times increase, however, through-current increases appreciably and the total current is a complex function of the transition times and capacitance. In most circuits, the ae dissipation (Pap) in watts is equal to Co Vppp2 f. where Co is the effective output capacitance Greluding load capacitance) in farads, Vpp i tke supply voltage in volts, and f is the frequency in Hz, Because the output capacitance must be charged from Vg t0 Vp once each period, dynamic dissipation increases. linearly with frequency und load capacitance, and as the square of the supply voltage Viyp. Each COS/MOS data sheet includes a curve showing dynamic power dissipation as @ function of frequency. Fig. 1 shows switching current and voltage waveforms for different values of load capacitance and input rise and fall times. System Noise Considerations In general, COS/MOS devices are much less sensitive to noise on power and ground lines than bipolar logic Families (uch as TTL of TL). However, this sensitivity varies as a function of the powecsupply voltage, and more importantly as @ function of synchronisin between noise spikes and input transitions. Good power distribution in digital systems requires that Ute power bus have a low dynamic impedance; for this purpose, discrete decoupling capacitors should be distributed across the power bus. Power-Source Rules ‘The sale operating procedures listed below can easily be understood by reference to the basic COS/MOS inverter and its gate-oxide protection network plus inherent diodes, as shown in Fig 2 1. When separate power supplies are used for the COS/MOS aCOS/MOS Design and Operating Considerations ¥ss| Tyg 08 F OE ot k Te) nur as 00) Your Mss 2s) yp 125 Iss 125) We) PUT te 800 a pete Too 25) ‘a | K 3 F ss 20) U Fig, 1-Switching-eurrant weveforme. ey device and for the device inputs, the device power supply should always be tumed on before the independent input signal sources, and the input signals should be tumed off before the power supply is tumed off (Vsg SV} < Vpp 2s 2 maximum limit). This rule will prevent over-disipation and possible damage of the D2 input-protection diode when the device power supply is grounded. When the device power supply is an open circuit, violation of this rule can result in undesired circuit operation although device damage should not resuit; ac inputs can be rectified by diode D2 to act asa power supply. 2. The power-supply operating voltage should be kept safely below the absolute maximum supply rating, as indicated previously. 22 3, The power-supply polarity for COS/MOS circuits should rnot be reversed. The data sheets state that the positive (Viyp) terainal should never be more than 0.5 volt negative respect to the negative (Vgs) terminal (Vp - Vg >-0.5 V). oureur +O Fig. 2~COS/MOS inverter ‘This absolute maximum rating means that reversal of polarity will forward-bias and short the structural and protection diodes between Vpp and Vgg. 4. Vpp should "be equal to or greater than Veg for COS/MOS buffers which have two power supplies (in particular, for CD4009A and CD4010A COS/MOS-toTTL “down”-conversion devices). 5. Power-source current capability should be limited to as Tow a value as reasonable to assure good logic operation. 6. Large values of resistors in series with Vpp or Veg should be avoided; transient turn-on of input. protection diodes can result from drops across such resistors during switching. Gate-Oxide Protection Networks A problem occasionally encountered in handling and testing low-power semiconductor devices, including MOS and small geometry bipolar devices, has been damage to gate oxide and/or p-n junctions. Fig. 3 shows the gate-oxide protection circuits sed to protect COS/MOS circuits from static electricity damage. ICAN-6218 gives further information on protection ciccuits, Although these circuits are included in all COS/MOS devices, the handling precautions discussed in ICAN-6218 and In ICAN-6000 should be observed. Input Signals and Ratings 1. Input signals should be maintained within the power- supply voltage range, Vsg < Vj < Vp, In applications such as astable and monostable multivibrators, input current can flow snd should be limited to the microampere level by use of a resistor in series with the input terminal affected. 2. Ail COS/MOS inputs should be terminated. When COS/MOS inputs are wired to edge card connectors with COS/MOS drive coming from another PC board, shunt resistor should be connected to Viyp oF Vgg in case the inputs become unterminated with the power supply on.COS/MOS Design and Operating Considerations ' ae : 2 ) : ®) Fig. 3-Protection circuits used in Input protection; {b) CD: 2 Rivest SFlurs @ ay Betsey ‘THESE plone ane ThaeReN fey pan OF THE MaNUPACTURING Process COS/MOS devices: (a) norma! gate 4059 and CDAO5IA gato input protection: (c) transmissiongate input-output protection: (a) setive finverter) ouput protection. 3. When COS/MOS circuits are driven by TTL logic, a “pull-up” resistor should be connected from the COS/MOS {input to 5 volts (further information is given in ICAN6602). 4, Input signals should be maintained within the recom mended inputsignal-swing range. Output Rules i The power dissipation in a COS/MOS package should not ‘exceed 200 milliwatts. The actual dissipation should be calculated when (a) shorting outputs directiy to Vp or Vgg, ©) driving low-impedance loads, or (c) directly driving the base of a pnp or n-pon bipolar transistor. 2. Output short cizcuits often result from testing errors or improper board assembly. Shorts on buffer outputs or across power supplies greater than 5 volts can damage COS/MOS devices 3. COS/MOS, like active pullup TTL, cannot be connected in the “‘wire-OR” configuration because an “on” P-MOS and sn “on™ N-MOS transistor could be directly shorted across the power-supply rails. 4. Paraleling inputs and outputs of gates is recommended ‘only when the gates are within the same IC package. 5. Output loads should retum ‘to a voltage within the supply-voltage range (Vipp) 10 Vgs)- 6. Large capacitive loads (greater than 5000 pF) on COS/MOS buffers or high-current drivers act like short circuits and may over-dissipate output transistors. 7. Output transistors may be over-cissipated by operating butfers as linear amplifiers or using these types as one-shot or astable muluvibrators Noise Immunity ‘The complementary structure of the inverter, common to all COS/MOS logic devices, results in a near-ideal input-output tansfer characteristic, with switching point midway (45% to 55%) between the O and 1 output logic levels. ‘The result is high dc noise immunity. Fig, 4 illustrates minimum and maximum transfer character- {sties useful for defining noise immunity for an inverter and a noninverter. The noise-immunity voltage (Viyy » Viyy) is that noise voltage at any one input which will not propagate through the system. Minimum noise immunity is 30% of the supply voltage (20% for some buifer types). Some noise- immunity definitions are given below: Vip max = the maximum input voltage at low-level input for which the output logic level does not change state. Viqj min = the minimum input voltage at high-level input for which the output logic level does not change state, Yi = Vie Yinn = Yp-Vit Voy min = minimum hightevel output voltage (logic 1 level) for rated Vyyy, (for an inverting logic function) or Viggy (fora noninverting logic function). Voz, mex = maximum low-level output voltage for rated Viv (for an inverting logic function) or Vwi (for non-inverting logic function). Noise immunity increases as the input noise pulse width becomes less than the propagation delay of the circuit. This condition is often described as ac noise immunity. (Further information on noise immunity is given in ICAN-6176,) 3 E 60 | | soy 4 Lo y 3 z i A Ey 3 3 =f wee fat 0 a Te IneUT VOLTAGE (Vz — VOLTS, o INPUT VOLTAGE (vz) — VOLTS o ig. 4-Minimur and maximum transter characteristics for (a) inverting ‘gic function, and () non-inverting logic function. 23COS/MOS Design and Operating Considerations ‘Clock Rise- and Fall-Time Reduirements ‘All COS/MOS clocked devices have maximum clock rise- and fall-time ratings (normally 5 to 15 microseconds). With fonger rise or fall times, a device may net function properly because of data ripple-through, false triggering problems, etc. Long rise and fall times on COS/MOS bufer-type inputs cause increased power dissipation which may exceed device capa- bility for power supplies above 5 volts. Paraltet Cl Process variations leading to differences in input threshold voltage among random device samples can cause loss of data between certain synchronously clocked sequential circuits, as shown in Fig. 5. This problem can be avoided if the clock rise ime (1,CL) is made less than the total of the fixed propagation delay plus the output transition time of the first stage, as determined from the device data for the specific loading condition in effect. Schmitt Trigger circuits such as the €D4093B ate am ideal solution to applications requiring wave shaping Three-State Logic ‘Three-state logic can be easily implemented by use of a transmission gate in the outpat circuit; this technique provides a solution to the wire-OR problem in many cases CASCADING WITH SLOW clock ‘CAN CAUSE ERROR (aa SWITCHING PONT #0.3 Voy ~~ ~-rroren ° [SWITCHING POINT® 0.7 Yoo ERROR Fig. 5-Error effect that results from a slow clock in cascaded circuits. 24COS/MOS Family Characteristics Overview CD4000A Series - RCA COS/MOS types designed for 3-to-15-volt operation: all package styles ED40008 Series — RCA COS/MOS types designed for 4-to-1 8-volt operation; all package styles ‘CD45008 Series — RCA COS/MOS types similar to industry 4500-series types designed for 3-to-18-volt operation; all package styles Packages Dual-indine Plastic — suffix AE or BE (-40°C to +85°C operation) Dual-in-line Ceramic — suffix AF or BF (-55°C to +125°C operation) Dual-in-fine Welded-Seal Ceramic — suffix AD or BD (-55°C to +125°C operation) FlatPack Ceramic ~ suffix AK or BK (55°C to +125°C operation) ‘Chip Form — suffix AH or BH (-55°C to +125°C operation) Feotures Ultra-Low Quiescent Power: 0.005 to 0.05 AW typical for SSI at Vpp = 5 V 0.1 to 0.5 nW typical for MSI at Vpp=5V ‘Wide Output-Voltage Swing when Driving COS/MOS: Highevel output — typically Vp Low-level output — typically Veg High Noise Immunity: 45% of Vipp typical 30% of Vpp guaranteed on most devices High Fan-Qué Driving COS/MOS: greater than 50 Input Current: +10 pA typical Standard Input-Protection Circuit: double diode clamps plus series resistor Low Input Capacitance: 5 pF typical Static Electrical Characteristics Quiescent Device Current (fy). The quiescent current is the device current drawn by an IC in the steady-state condition with no load on the output, The IC inputs are tied either to the positive (Vpp) terminal or the negative (Vg) terminal when quiescent current is measured. ‘Most devices exhibiting typical or “Iow” leakage currents at room ‘temperature (25°C) are dominated by p-n junction leakage. For these devices, 1y, doubles approximately every 11°C. Devices exhibiting ledkage currents close to the ‘maximum rating are dominated by surface leakage and will not generally follow an exponential characteristic, ie., surface leakage current will usually increase at @ considerably slower rate than junction leakage as the temperature is increased. Typical and minimum values for Iy, are given on individual COS/MOS data sheets. For “B"-series devices, these values are standardized for SSI types and for MSI types. Quiescent- device-current tes! circuits are also shown on the individual data sheets. Output Voltage Levels (Voz and Voy). Voy, i the logic-“0” or low-level output voltage. Vigqy is the logic-"1" or high-level output voltage. Voz, and Voyy are specified under no load with inputs set at Vi or Veg (ée., aoise-free input conditions). Values for both “A” series and “B" series devices are as follows: Low-Level Output (Voy): Typical value at #25°C Maximum value at 40°C/-55°C Maximum value at +85°C/+125°C High-Level Output (Voy): Typical value at 25°C Minimum value at 40°C/-55°C .... Minimum value at +85°C/+ 125°C - Voltage and Current Transfer Characteristics. Curves of voltage and current input/output characteristics are given in the individual data sheets for inverter, gate, and butler devices. DC Nowe Immunity (Vy and Viyy)- Noiseimmunity definitions were covered previously. Values for both “A”-series and “B”-series devices are given below: sv eeeeees Ground (Vgc) "00 “oosy y, NL | Ypp} You (min.) Inverting lnverting SSI Devices MSI Devices 5 36 4.2 10 72 9.0 15° 108 Bs Yew Yop Vor (max.) Tiverting __Taverling SSI Devices MSI Devices “A Series “B” Series s| 095 14 08 10 29 28 10 is* 42015 Specified for “B” series only. Noiseimmunity test circuits are shown on individual device data sheets. Output Drive Current (IpN and IpP). IpNis the output sink current (existing in the NMOS device) when the P-MOS device is “off” and the NMOS device is “on”, i.., logic “0” state. IpP is the output source current (existing in the P-MOS device) when the NMOS device is “off” and the PMOS device is “on”, ic., logic “1” state. Output-drive-current values are given in the individual data sheets. For CD4000B- series devices, these values are standardized as follows: 25