Minia University Faculty of Engineering Electrical Engineering Department
Minia University Faculty of Engineering Electrical Engineering Department
Faculty of Engineering
Electrical Engineering Department
Course: Digital design (VHDL Course)
Sheet No.: 1
Date:
Objectives:
Review the basics of digital circuit design (Difference between
Combinational Circuit and sequential circuit).
How to think about any program for any design.
The basic concept of VHDL language.
Lab tools:
Xilinx design tools (ISE design suite )
FPGA kit.
Remember:
Combinational Circuit and sequential circuit :
The main difference between sequential circuits and combinational circuits is that sequential
circuits compute their output based on input and state, and that the state is updated based
on a clock. Combinational logic circuits implement Boolean functions, so they are functions
only of their inputs, and are not based on clocks.
HDL construction:
Entity: define the model
Connectivity
Concurrency
Timing
Exercise 2:
Write VHDL program describe the even parity detector
3bit.
Exercise 3:
Using the structural description of the pervious example as
the following and write suitable VHDL code for it: