V2O7L.U ME Vv SECOND EDITION Modular Series on Solid State Devices Gerold W. Neudeck * Robert F. Pierret, Series EditorsPHYSICAL CONSTANTS Symbol Name Value q Magnitude of electronic charge 1,602 x 10°C me Electron rest mass 9.309 107kg m, Proton rest mass 1.673107 ke © Speed of light in vacuum 2,998 x 10% mis, & Permittivity of vacuum 8.854 10" Fin k Boltzmann's constant 1.381 x 108K 8.617 x 10 h Planck's constant 6.625 x10 ES 4.13510" SeV-s Ay Avogadro number 6.022 10 molecules!kg-mole KT ‘Thermal energy 0.02586 eV (T. 0.02526 eV (T E Bandgap of silicon at 300K Lizev K, Relative permittivity of silicon na K, Relative permittivity of silicon dioxide 39 n, Intrinsic carrier density in silicon at 300K 20"jem? CONVERSION FACTORS 1A =10-*om Limi? 5.2 um? =10°m 45 10%em* qum = 10"fem reV = 1.60210"! =10%m a 1.248 um (Ein eV) i milss... MODULAR SERIES ON SOLID STATE DEVICES Gerold W. Neudeck and Robert F, Pierret, Editors Volume V Introduction to Microelectronic Fabrication Second Edition Richard C. Jaeger Auburn University Prentice SEAN Prentice Hall Upper Saddle River New Jersev 07458Library of Congress Cataloging-in-Publication Data Jaeger, Richard C Introduction to microelectronic fabrication / Richard C. Jaeger—2nd Edition pom. (Modular series on solid state devices; . 5) Includes bibliographical references and index ISBN 0-201-44494-7, 1. Integrated circuits —Very large scale integration—Design and construction —Congresses. I.Tile. II, Series. CIP Data available Vice President and Editorial Director, ECS: Marcia . Horton Publisher: Tom Robbins Associate Editor: Alice Dworkin Feitorial Assistant: Jody McDonnell Vice President and Director of Production and Manufacturing, ESM: David W. Riccardi Executive Managing Editor: Vince O'Brien Managing Editor: David A. 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Ltd. oe ne ee RT RD eeu ne ce ene ieee ee pw enedTo My Family—Joan, Peter, and StephanieContents PREFACE xiii Chapter 1 An Overview of Microelectronic Fabrication 1 al 1.2 13 14 15 A Historical Perspective 1 An Overview of Monolithic Fabrication Processes and Structures 5 Metal-Oxide-Semiconductor (MOS) Processes 7 1.3.1 Basic NMOS Process 7 1.3.2 Basic Complementary MOS (CMOS) Process 9 Basic Bipolar Processing 10 Safety References 14 Problems 14 Chapter 2 Lithography 7 24 23 24 25 26 27 ‘The Photolithographic Process 17 2.4.1 Wafers and Wafer Cleaning 19 2.12 Barrier Layer Formation 21 2.13 Photoresist Application 21 2.14 Soft Baking /Prebaking 22 2.15 Mask Alignment 23 2.1.6 Photoresist Exposure and Development 23 2.17 Hard Baking 25 Etching Techniques 25 221 Wet Chemical Etching 25 22.2 Dry Etching Plasma Systems 26 22.3 Photoresist Removal 26 22.4 Metrology and Critical Dimension Control 28 Photomask Fabrication 28 Exposure Systems 28 Exposure Sources 34 Optical and Electron Microscopy 37 2.6.1 Optical Microscopy 37 2.6.2 Scanning Electron Microscopy 37 2.6.3 Transmission Electron Microscopy 38 Summary 38 References 40 Further Reading 40 Problems 40vi Contents Chapter 3 Chapter 4 Thermal Oxidation of icon 43 3.1 The Oxidation Process 43 3.2 Modeling Oxidation 44 3.3. Factors Influencing Oxidation Rate 46 3.4 Dopant Redistribution During Oxidation 51 3.5 Masking Properties of Silicon Dioxide $1 3.6 Technology of Oxidation 52 37 Oxide Quality 53 3.8 Selective Oxidation and Shallow Trench Formation 55 38.1 Trench Isolation 56 3.82 Chemical Mechanical Polishing (CMP) 57 3.9 Oxide Thickness Characterization 61 3.10 Process Simulation 61 Summary 61 References 63 Problems 64 Diffusion 67 41 The Diffusion Process 67 4.2 Mathematical Model for Diffusion 68 4.2.1 Constant-Source Diffusion 69 4.2.2 Limited-Source Diffusion 70 4.2.3 Two-Step Diffusion 71 43. The Diffusion Coefficient 72 4.4 Successive Diffusions 74 45 Solid-Solubility Limits 74 4.6 Junction Formation and Characterization 76 4.6.1 _ Vertical Diffusion and Junction Formation 76 4.62 Lateral Diffusion 78 463 Concentration-Dependent Diffusion 79 4.7 Sheet Resistance 81 471 — Sheet-Resistance Definition 82 4.7.2 Irvin's Curves 85 4.7.3 The Four-Point Probe 88 4.7.4 Vander Pauw's Method 88 4.8 Generation-Depth and Impurity Profile Measurement 90 4.81 Grove-and-Stain and Angle-Lap Methods 90 48.2 —Impurity-Profile Measurement 91 49 Diffusion Simulation 93 410 Diffusion Systems 95 4.10.1 Boron Diffusion 97 4.10.2 Phosphorus Diffusion 98 4.10.3 Arsenic Diffusion 99 4.10.4 Antimony Diffusion 100Chapter 5 Chapter 6 411 Contents vii Gettering 100 Summary 101 References 102 Problems 103 Jon Implantation 109 5 52 53 54 Be} 56 Implantation Technology 109 Mathematical Model for fon Implantation 111 Selective Implantation 114 Junction Depth and Sheet Resistance 117 Channeling, Lattice Damage, and Annealing 118 55.1 Channeling 118 5.52 Lattice Damage and Annealing 120 5.5.3 Deviations from the Gaussian Theory 121 Shallow Implantations 121 5.6.1 Low-Energy Implantation 122 5.62 Rapid Thermal Annealing 12: 563 Transient Enhanced Diffusion Summary 124 References 125 Source Listing 126 Problems 126 123 Film Deposition 129 61 6.2 63 64 Evaporation 129 641 Kinetic Gas Theory 130 6.12 Filament Evaporation 132 6.13 Electron-Beam Evaporation 132 6.14 Flash Evaporation 134 6.1.5 Shadowing and Step Coverage 134 Sputtering 135 Chemical Vapor Deposition 136 63.1 CVD Reactors 137 63.2 Polysilicon Deposition 138 63.3. Silicon Dioxide Deposition 139 634 Silicon Nitride Deposition 140 635 CVD Metal Deposition 141 Epitaxy 141 64.1 Vapor-Phase Epitaxy 142 64.2 Doping of Epitaxial Layers 145 643 BuriedLayers 145 644 Liquid-Phase and Molecular-Beam Epitaxy 148 Summary 148 References 149 Further Reading 149 Problems 149Contents Chapter 7 Chapter 8 Interconnections and Contacts 7A 72 73 74 15 16 Wd 18 Packaging and Yield 81 82 83 84 85 Interconnections in Integrated Circuits 151 Metal Interconnections and Contact Technology 153 7.21 Ohmic Contact Formation 153 7.22 Aluminum-Silicon Eutectic Behavior 154 7.2.3 Aluminum Spiking and Junction Penetration 155 7.2.4 Contact Resistance 156 7.25 Electromigration 157 Diffused Interconnections 158 Polysilicon Interconnections and Buried Contacts 159 7.4.1 Buried Contacts 160 7.42 Butted Contacts 162 Silicides and Multilayer-Contact Technology 162 75.1 Silicides, Polycides, and Salicides 162 7.5.2 Barrier Metals and Multilayer Contacts 164 The Liftoff Process 164 Multilevel Metallization 166 7.7.1. Basic Multilevel Metallization 166 7.7.2 Planarized Metallization 167 7.73 Low Dielectric Constant Interlevel Dielectrics 167 Copper Interconnects and Damascene Processes 168 7.8.1 Electroplated Copper Interconnect 168 7.82 Damascene Plating 168 7.8.3 Dual Damascene structures 169 Summary 172 References 172 Further Reading 173 Problems 174 ‘Testing 177 Wafer Thinning and Die Separation 178 Die Attachment 178 83.1 Epoxy Die Attachment 179 83.2 Eutectic Die Attachment 179 Wire Bonding 179 84.1 Thermocompression Bonding 182 84.2 Ultrasonic Bonding 183 843 Thermosonic Bonding 184 Packages 184 85.1 CircularTO-Style Packages 184 85.2 Dual-in-Line Packages (DIPs) 184Chapter 9 86 Contents ix 85.3 Pin-Grid Arrays (PGAs) 185 85.4 Leadless Chip Carriers (LCCs) 186 8.5.5 Packages for Surface Mounting 186 Flip-Chip and Tape-Automated-Bonding Processes 187 86.1 Flip-Chip Technology 188 86.2 Ball Grid Array (BGA) 190 8.6.3. The Tape-Automated-Bonding (TAB) Process 191 8.6.4 Chip Scale Packages 193 Yield 194 87.1 Uniform Defect Densities 194 8.7.2 Nonuniform Defect Densities 195 Summary 198 References 198 Further Reading 199 Problems 199 MOS Process Integration 201 91 93 94 Basic MOS Device Considerations 201 9.1.1 Gate-Oxide Thickness 202 9.1.2 Substrate Doping and Threshold Voltage 203 9.13 Junction Breakdown 204 9.14 Punch-through 204 9.1.5 Junction Capacitance 205 9.1.6 Threshold Adjustment 206 9.1.7 Field-Region Considerations 208 9.1.8 MOS Transistor Isolation 208 9.1.9 Lightly Doped Drain structures 210 9.1.10 MOS Transistor Scaling 210 MOS Transistor Layout and Design Rules 212 92.1 Metal-Gate Transistor Layout 213, 9.2.2 Polysilicon-Gate Transistor Layout 217 9.2.3. More-Aggressive Design Rules 218 9.2.4 Channel Length and Width Biases 219 Complementary MOS (CMOS) Technology 221 n-Well Process 221 p-Well and Twin Well Processes 221 Gate Doping 222 CMOS Isolation 224 CMOS Latchup 225 Shallow Trench Isolation 225 Silicon on Insulator 226 Summary 227 References 228 Problems 229x Contents Chapter 10 Bipolar Process Integration 233 Chapter 11 10.1 The Junction-Isolated Structure 233 10.2 Current Gain 235 10.3. Transit Time 236 10.4 Basewidth 237 10.5 Breakdown Voltages 239 10.5.1 Emitter-Base Breakdown Voltage 239 10.5.2 Circular Emitters 239 1053 Collector-Base Breakdown Voltage 240 10.6 Other Elements In SBC Technology 242 10.6.1 Emitter Resistor 243 10.6.2 Base Resistor 244 10.63 Epitaxial Layer Resistor 245 10.6.4 Pinch Resistor 246 10.6.5 Substrate pnp Transistor 246 10.6.6 Lateral pnp Transistors 248 10.6.7 Schottky Diodes 249 10.7 Layout Considerations 249 107.1 Buried-Layer and Isolation Diffusions 249 10.7.2 Base Diffusion to Isolation Diffusion Spacing 251 10.7.3 Emitter-Diffusion Design Rules 252 10.7.4 A Layout Example 252 10.8 Advanced Bipolar Structures 253 10.8.1 Locos Isolated Self-Aligned Contact Structure 254 10.82 Dual Polysilicon Self-Aligned Process 254 10.83 The Silicon Germanium Epitaxial Base Transistor 257 10.9 Other Bipolar Isolation Techniques 259 109.1 Collector-Diffusion Isolation (CDI) 259 10.9.2 Dielectric Isolation 259 10.10 BICMOS 262 Summary 263 References 264 Problems 265 Processes for MicroElectroMechanical Systems: MEMS 269 11.1 Mechanical Properties of Silicon 270 11.2 Bulk Micromachining 271 11.2.1 Isotropic and Anisotropic Etching 271 11.22 Diaphragm Formation 273 31.23 Cantilever Beams and Released Structures 275 licon Etchants 277 113.1 Isotropic Etching 277 11.32 Anisotropic Etching 278 113Contents xi 11.4 Surface Micromachining 279 11.4.1 Cantilever Beams, Bridges and Sealed Cavities 279 11.4.2 Movable In-Plane Structures 279 11.4.3 Out-of Plane Motion 282 11.4.4 Release Problems 286 115. High-Aspect-Ratio Micromachining: ‘The LIGA Molding Process 288 11.6 Silicon Wafer Bonding 289 11.6.1 Adhesive Bonding 289 11.6.2 Silicon Fusion Bonding 289 11.6.3 Anodic Bonding 291 11.7 IC Process Compatibility 292 11.7.1 Preprocessing 292 11.7.2 Postprocessing 292 11.7.3 Merged Processes 294 Summary 295 References 296 Problems 298 ANSWERS TO SELECTED PROBLEMS 301 INDEX 303Preface ‘The spectacular advances in the development and application of integrated circuit (IC) technology have led to the emergence of microelectronics process engineering as an independent discipline. Additionally, the pervasive use of integrated circuits requires a broad range of engineers in the electronics and allied industries to have a basic under- standing of the behavior and limitations of ICs. One of the goals of this book is to address the educational needs of individuals with a wide range of backgrounds. This text presents an introduction to the basic processes common to most IC technologies and provides a base for understanding more advanced processing and design courses. In order to contain the scope of the material, we deal only with mater- ial related to silicon processing and packaging, The details of many problems specifi- cally related to VLSV/ULSI fabrication are left to texts on advanced processing, although problem areas are mentioned at various points in this text, and goals of the International Technology Roadmap for Semiconductors are discussed as appropriate. Chapter 1 provides an overview of IC processes, and Chapters 2-6 then focus on the basic steps used in fabrication, including lithography, oxidation, diffusion, ion implantation and thin film deposition, and etching, Interconnection technology, packag- ing, and yield are covered in Chapters 7 and 8. Itis important to understand interactions between process design, device design, and device layout. For this reason, Chapter 9 and 10 on MOS and bipolar process integration have been included. Chapter 11 provides a brief introduction to the exciting area of Microelectromechanical Systems (MEMS). Major changes in the second edition of this text include new or expanded cover- age of lithography and exposure systems, trench isolation, chemical mechanical polish- ing, shallow junctions, transient-enhanced diffusion, copper Damescene processes, and process simulation. The chapters on MOS and bipolar process integration have been substantially modified, and the chapter on MEMS is entirely new. The problem sets have been expanded, and additional information on measurement techniques has been included. The text evolved from notes originally developed for a course introducing seniors and beginning graduate students to the fabrication of solid-state devices and integrated circuits. A basic knowledge of the material properties of silicon is needed. and we use Volume I of this Series as a companion text. An introductory knowledge of electronic components such as resistors, diodes, and MOS and bipolar transistors is also useful The material in the book is designed to be covered in one semester. In our case, the microelectronics fabrication course is accompanied by a corequisite laboratory. ‘The students design a simple device or circuit based upon their individual capability, and the designs are combined on a multiproject polysilicon gate NMOS chip. Design, fabrication, and testing are completed within the semester. Students from a variety of disciplines, including electrical, mechanical, chemical, and materials engineering; com- puter science; and physics, are routinely enrolled in the fabrication classes.xiv Preface Before closing, I must recognize a number of other books that have influenced the preparation of this text. These include The Theory and Practice of Microelectronics and VLSI Fabrication Principles by 8. K. Ghandi, Basic Integrated Circuit Engineering by D. J. Hamilton and W. G. Howard, Integrated Circuit Engineering by A. H. Glaser and G., E. Subak-Sharpe, Microelectronic Processing and Device Design by R. A. Colclaser, Semiconductor Devices—Physics and Technology by S. M. Sze, Semiconductor Integrated Circuit Processing Technology by W. R. Runyon and K. E. Bean, and The Science and Engineering of Microelectronic Fabrication by Stephen A. Campbell Thanks also go to the many colleagues who have provided suggestions and encouragement for the new edition and especially to our laboratory manager Charles Ellis who has been instrumental in molding the laboratory sections of our course. RICHARD C. JAEGER Auburn, Alabama1 Gaede Ata Pca cere acca An Overview of Microelectronic Fabrication A HISTORICAL PERSPECTIVE In this volume, we will develop an understanding of the basic processes used in mono- lithic integrated-circuit (IC) fabrication. Silicon is the dominant material used through- out the IC industry today, and in order to conserve space, only silicon processing will be discussed in this book. However, all of the basic processes discussed here are applic- able to the fabrication of compound semiconductor integrated circuits (ICs) such aS gallium arsenide or indium phosphide, as weil as thick- and thin-film hybrid ICs. Germanium was one of the first materials to receive wide attention for use in semiconductor device fabrication, but it was rapidly replaced by silicon during the early 1960s. Silicon emerged as the dominant material, because it was found to have two major processing advantages. Silicon can easily be oxidized to form a high-quality electrical insulator, and this oxide layer also provides an excellent barrier layer for the selective diffusion steps needed in integrated-circuit fabrication. Silicon was also shown to have a number of ancillary advantages. It is a very abundant element in nature, providing the possibility of a low-cost starting material. It has a wider bandgap than germanium and can therefore operate at higher tempera- tures than germanium. In retrospect, it appears that the processing advantages were the dominant reasons for the emergence of silicon over other semiconductor materials. The first successful fabrication techniques produced single transistors on a rec tangular silicon die 1-2 mm on a side. The first integrated circuits, fabricated at Texas Instruments and Fairchild Semiconductor in the early 1960s, included several transis- tors and resistors to make simple logic gates and amplifier circuits. From this modest beginning, the level of integration has been doubling every one to two years, and we have now reached integration levels of billions of components on a 20-mm x 20-mm die [1-3]. For example, one-gigabit dynamic random-access memory (DRAM) chips have more than 10° transistors and more than 10° capacitors in the memory array. a8 12 Chapter 1 An Overview of Microelectronic Fabrication well as millions of additional transistors in the access and decoding circuitry. One-giga- bit RAMs are currently being produced with photographic features measuring between 0,13 and 0.18 micron (ym). MOS transistors with dimensions below 0.05 pm have been fabricated successfully in research laboratories, and these devices continue to behave as predicted by macroscopic models, So we still have significant increases in integrated-circuit density yet to come, provided that manufacturable fabrication processes can be developed for deep submicron dimensions. ‘The larger the diameter of the wafer, the more integrated-circuit dice can be pro- duced at one time. Many wafers are processed at the same time, and the same silicon chip is replicated as many times as possible on a wafer of a given size. The size of sili- con wafers has steadily increased from 1-,2-,3-, 4-, 5-, and 6-in. diameters to the point where 8-in, (200-mm) wafers are now in production. (See Fig. 1.1(a).) Wafers with 300- mm diameters will be in full production in the near future, and 450 mm wafers are pro- jected to be in used by the end of the decade. Wafer thicknesses range from approximately 350 to 1250 microns. Large-diameter wafers must be thicker in order to maintain structural integrity and planarity during the wide range of processing steps encountered during IC fabrication. Figure 1.1(c) shows the approximate number of 10-mm x 10-mm dice that fit on a wafer of given diameter. For a given wafer processing cost, the more dice per wafer, the lower the individual die cost becomes. Thus, there are strong economic forces driving the IC industry to continually move to larger and larger wafer sizes. ‘The dramatic progress of IC miniaturization is depicted graphically in Fig. 1.2 [1-3] on pages 4 and 5. The complexities of memory chips and microprocessors have both grown exponentially with time. In the three decades since 1965, memory density has grown by a factor of more than 10 million from the 64-bit chip to the 1-Gb memory chip, as indicated in Fig. 1.2(a). Similarly, the number of transistors on a microproces- sor chip has increased by a factor of more than five thousand since 1970 (Fig 1.2 (b).) Since the commercial introduction of the integrated circuit, these increases in density have been achieved through a continued reduction in the minimum line width, or minimum feature size, that can be defined on the surface of the integrated circuit, as shown in Fig. 1.3 on page 6, Today, most corporate semiconductor laboratories around the world are actively working on deep submicron processes with feature sizes less than 0.1 um, less than one one-thousandth the diameter of a human hair! These trends and future projections are summarized in Table 1.1 on page 6, which is abstracted from the International Technology Road map for Semiconductors (ITRS) generated by the Semiconductor Industry Association [4]. The ITRS is updated every three years; the projections are mind-boggling, even for those of us who have worked in the industry for many years. By the year 2011, MOS transistor gate lengths are pro- jected to reach 30 nm (0.030 um), multigigabit DRAM chips will be commonplace, and microprocessors will have a billion transistors on die exceeding 25 mm (one inch) on an edge. It remains to be seen whether the industry meets these projections. However, progress will be impressive, even if only a fraction of the projections are achieved.” Historically there has been a problem with the units of measure used to describe integrated circuits. Horizontal dimensions were originally specified in mils (1 mil = 0,001 in.), whereas specification of the shallower vertical dimensions commonly made ‘"in the past several years, the IC industry has actually managed to exceed the ITRS goals.1.1. AHistorical Perspective 3 {B+ Invegrated circuit die 100 mm (4") iil 150 mm (6 ih 200 mm (8") F— Silicon wafer 450 mm (16") 300 mm (12" oe (b) 10000 1000 140 E £ 2 to 100 200 300) 200 500 Water diameter (mm) 0 4 8 2 16 20 Water diameter (in) © FIGURE 1.1 (a) Relative size of wafers with diameters ranging from 100 to 450 mm; (b) The same integrated circuit die is rep cated hundreds of times on a typical silicon wafes:(c) the graph gives the approximate number of 10 x 10 mm dice that can be fabricated on wafers of different diameters.FIGURE 1.2 (6) Dynamic memory den- sity versus year since 1960. FIGURE 1.2 (b) Number of transistors in a microprocessor versus year. 4 umber of transistors 10! 1a 1 = ISSCC Daa © TRS Goals 200 Boi P20 ~ wo w w 108 wt 480 3868 Pentium Dx sot 18sec Daa © ITRS Goals iene 1980 Yer 200 2 2020 eh eran1.2 1.2. An Overview of Monolithic Fabrication Processes and Structures 5. use of the metric system. Today, most of the dimensions are specified using the metric system, although Imperial units are occasionally still used. Throughout the rest of this, book, we will attempt to make consistent use of metric units, AN OVERVIEW OF MONOLITHIC FABRICATION PROCESSES AND STRUCTURES Monolithic IC fabrication can be illustrated by studying the basic cross sections of MOS and bipolar transistors in Figs. 1.4 (on page 7) and 1.5 (on page 8). The n-channel MOS transistor is formed in a p-type substrate. Source/drain regions are formed by selectively converting shallow regions at the surface to n-type material. Thin and thick silicon-dioxide regions on the surface form the gate insulator of the transistor and serve to isolate one device from another. A thin film of polysilicon is used to form the gate of the transistor, and a metal such as aluminum is used to make contact to the source and drain, Interconnections between devices can be made using the diffusions and the layers of polysilicon and metal. ‘The bipolar transistor in Fig. 1.5 has alternating n- and p-type regions selectively fab- ricated on a p-type substrate. Silicon dioxide is again used as an insulator, and aluminum is used to make electrical contact to the emitter, base, and collector of the transistor. Both the MOS and bipolar structures are fabricated through the repeated appli- cation of a number of basic processing steps: * Oxidation + Photolithography + Etching * Diffusion * Evaporation or sputtering * Chemical vapor deposition (CVD) * Ton implantation + Epitaxy + Annealing Silicon dioxide can be formed by heating a silicon wafer to a high temperature (1000 to 1200 °C) in the presence of oxygen. This process is called oxidation. Metal films can be deposited through evaporation by heating the metal to its melting point in a vacuum. Thin films of silicon nitride, silicon dioxide, polysilicon, and metals can all be formed through a process known as chemical vapor deposition (CVD), in which the material is deposited out of a gaseous mixture onto the surface of the wafer. Metals and insulators may also be deposited by a process called sputtering. Shallow n- and p-type layers are formed by high-temperature (1000 to 1200 °C) diffusion of donor ot acceptor impurities into silicon or by ion implantation, in which the wafer is bombarded with high-energy donor or acceptor ions generated in a high- voltage particle accelerator. In order to build devices and circuits, the n- and p-type regions must be formed selectively in the surface of the wafer. Silicon dioxide, silicon nitride, polysilicon, photo resist, and other materials can all be used to mask areas of the wafer surface to prevent6 Chapter 1 An Overview of Microelectronic Fabrication 10! 1° feature size (0) 1 ISSCC Data 19 TRS Goals 107 1960 i570 1980 1980 2000) 2010 2020 Year FIGURE 1.3, Feature size used in fabrication of dynamic memory as a function of time. ‘TABLE 1.1 International Technology Road Map for Semiconductors (ITRS) [4] - Selected Projections ‘Year of First Product Shipment 2001 2003-2005 200820112014 DRAM Metal Line Halt-Pitch (nm) 150 feos 10024 ce 70) 335 Microprocessor Gate Widths (nm) 100 Opes 45 3020 DRAM (G-bitsichip) 22 (ee eer cy 190 Microprocessor (M-transistorsichip) 48 95 190 © 54015004300 DRAM Chip Area: Year of Introduction (mm?) 400 430526 = 6006790 DRAM Chip Area: Production (mm?) 130 Figo =e 701322 eames e 290-220) MPU Chip Size at Introduction (mmm) 340 37 © 400 470 S40 620 MPU Chip Area: Second “shrink” (mm?) 180 m0 © 730-270 M0350 Water Size (mm) 300 300300, 450450450 Prec One eR NORRATH CPN ROIE