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Analog VLSI Notes MU

This is the Mumbai University's required data to approach the 8th semester-CVLSI examination in Electronics Engineering.

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Rishi Shah
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410 views

Analog VLSI Notes MU

This is the Mumbai University's required data to approach the 8th semester-CVLSI examination in Electronics Engineering.

Uploaded by

Rishi Shah
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF or read online on Scribd
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Ge TS 4 Vyyna uss eVest “mn TOMR Min = Vasi aNpsars 7 a +Vps5 + V5 ovin ren — von [5e \\-r0 | \ Vie = lp ap Con ‘L s— “ ipfadsest your epee " Men= “yaam mse(X)- = Gsm = fr mos (Ca NEA) a moe 342M Torn : Il. ae eos . l ee as eranciau. ade ‘ rode | fk ee Pp! RI . als pole jus gms meus 1K * total oun vime* conto] yun Plot v@Q) send C send os Vin = gory oe “O = Nout = 0: 2Vp-p Po Boe \Pinerivn QV ES eee Sine eset et - x oe even Ne \oo ra Mere cn +) , corn | | wy) (> ’ oe JMie). —> cp eu Tere ane a ee O in Vin bi Se Olp wematug Hee we eras eke ER =e , Slee Recke. Vin, Pulse (— 2" OAS OU fe Uae ES DES ar Min max Bee tine affine. Dey oo vie Vikq . 7se time osms +2 —2sv é€ : lens time, y pon time off em totel Erme avAv ow Ave ee ee Oo = 27.U3 LE 0:29 ws = yoo! l6yu 25 SR> loving p- Lo aa oth — \ 2/s Te 5 / / / Sardar Patel Institute of Technology Andheri (West) Mumbai-400058 Design of Two Stage Opamp Vdd Design Equations for the OpAmp: 1(Mn4) 2 I(Mn1) = I(Mp1) _ (Series connection) I(Mp1) = (Mp2) (Mirror) (Mp3) _ W/L (Mp3) I(Mp1) W/L (Mp1) 1(Mn1) = I(Mn2) = av Ca, = 1(Mn4) A= gm(Mn2) x gm(Mp3) x (rp(Mn2) Il ro(Mp2)) x (rp(Mn3) Il rp(Mp3)) GBW=G,,/C &m(mn2) = /2K’ W/L (Mn2)I(Mn2) Dr. Surendra Singh Rathod, S.P.1.T., Mumbai-400058 Sardar Patel Institute of Technology Andheri (West) Mumbai-400058 Steps to design the opamp: 1. We select a compensation capacitor value to obtain adequate stability. Typical values are a few pF. 2. We select a ratio of the bias currents of stage 2 and stage 1. Stage 2 would typically be operated at 5 times the tail current of the differential amplifier. We should ensure that the slew rate limit tion comes from the first stage charging the Miller capacitor and not by the second stage charging the load capacitor. 3. The slew rate required from the opamp determines {(IMin4), the tail current. Currents through Mn1, Mn2, Mp1 and Mp2 are half this value. Current through Mp3 is the assumed ratio (say 5) times the current through Mn4. At this stage, we know the current through all the transistors. 4. The required gain bandwidth product determines gm of the first stage. GBW=G6q/C Gn is equal to the gm of Mn1 or Mn2. Since the current as well as gm of Mn1 as well as Mn2 are now fixed, their geometries can be determined from: Im (mn2) = 2K W/E (Mn2)In2) ‘The W/L value for Mn1 is the same as that for Mn2. 5. Since currents through Mn2, Mp2, Mp3 and Mn3 are known, their output conductance’s can be calculated (go=l4/V, where V, is the early voltage=L/n’). The overall DC gain is given by fe _gm(Mn2)gm(Mp3) Go(Mn2) 1 go(Mp2))(g0(Mp3) I go(Mn3)) AS 8m for Mn2 and all go values are known, this determines the g,, for MP3. Once we know the g,, as welll as the current for Mp3, we can calculate its, geometry. 6. Once the geometry of Mp3 is known, geometries of Mp1 and Mp2 are determined by 1@Mp3) _ W/L (Mp3) 1(Mp1) W/L (Mp1) 7. The geometries of Mn4 and Mn3 are determined from current mirror ratios in relation to a given reference transistor for bias generation. Dr. Surendra Singh Rathod, S.P.1.T., Mumbai-400058 Sardar Patel Institute of Technology Andheri (West) Mumbai-400058 Example Design: Assume a technology where K’ for NMOS transistors is 120 wA/V and for PMOS transistors is 60 wA/V’. The threshold voltages for n and p channel transistors are 0.4 V and -0.4 V respectively. We shall use channel lengths which are about 4 times the minimum channel length. For this choice of l, assume that the Early Voltage V.=20V for both p and n channel transistors. We want to design an opamp with DC gain 80 dB {voltage gain of 10000). The gain bandwidth product is required to be 50 MHz and we would like a slew rate of 20 V/us. 1. We choose a compensation capacitor value of 2 pF. 2. We shall bias the second stage at 5 times the tail current of the differential stage wv 3. From the slew rate, = I(Mn4) « 1(MnA) = 2% 107"? x 22 = 40 uA ae 4. Therefore i(Mni)=I(Mn2)=I(Mp1)=I(Mp2}=20 yA and \(Mp3)=I(Mn3)=200 pA 5. From the GBW specification, 2n x 50 x 106 = Szuumzd This gives g,(Mn2)=628 uMho 6. To get a gm of 628 wMho with a current of 201A, 628 x 10-6 = (2x 120 x 10- x (W/L) x 20x 10> This gives the W/L of Mn2as = 82 W/L of Mn1 should be the same as Mn and Mn2 are matched. 7. goof Mni and Mp1 is = 20A/20V=1uMho Therefore the parallel output conductance of Mn1 and Mp1 is 2uMho 0 of Mn3 and Mp3 is = 200uA/20V=10uMho So the parallel output conductance of MP3 and Mn3 is 20Mho. ‘Therefore, to get an overall DC gain of 10000 nn = leap This gives the gm of Mp3 as = 32yMho 8. To get a gm of 32uMho with a drain current of. 200pA, we should have 32 x 106 = (2 x 60 x 10-* x (W/L) x 200 x 10-6 which gives the W/L of Mp3 as =17 9. Since the geometry of Mp1 and Mp2 has to be in the current ratio with Mp3, W/L of Mp1 and Mp2 should be =1.7 10. Finally, we assume that an n type reference bias transistor of ‘W/L=4 is available with a current of 10 HA. This will give the W/L of Mn4 and Mn3 as 16 and 80 respectively. This finishes the design for the simple opamp. Dr. Surendra Singh Rathod, $.P.|.T., Mumbai-400058 Rough, Vopr Vsaa or Vis © Vas - Ning Une Voo-Vses Nig. Nos = Netw. Vp -Nsaa> Ue > Nar UM ups g 3 aaa rorads se. a eneoeror ec "eaten “Bak oe De nC Se ee

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