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Emtech Core Verification

This project involved verifying a system on chip (SoC) designed to be the main controller for a critical system using an object oriented programming based testbench in System Verilog. Emtech led the verification process, developing the testbench using UVM and reusing in-house verification IPs. The testbench incorporated a loosely timed reference model to emulate high-level transactions for ambitious functional coverage requirements.

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59 views

Emtech Core Verification

This project involved verifying a system on chip (SoC) designed to be the main controller for a critical system using an object oriented programming based testbench in System Verilog. Emtech led the verification process, developing the testbench using UVM and reusing in-house verification IPs. The testbench incorporated a loosely timed reference model to emulate high-level transactions for ambitious functional coverage requirements.

Uploaded by

Sam
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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SOC ADVANCED

VERIFICATION E NVIRONMENT
DEVELOPMENT
Technical characteristics

Object Oriented Programming based Testbench.


Scalable
Maintainable
Reusable.
Advanced Test Design & Coverage Analysis.

Technologies & Tools

System Verilog & UVM.


VHDL & Verilog.
Constrained Random Verification (CRV).
System Verilog Assertions (SVA)
Code & Functional Coverage.
Formal Verification.
C/C++ & Matlab.
Direct Programming Interface (DPI)
FPGA based Emulation
Debugging Tools.
Scripting languages (Tcl, Python).

Project Description
This project consisted in the Verification of the System On Chip (SoC) designed to be the main controller of a Critical
System and implemented into a multimillion gate FPGA. The SoC incorporates a general purpose processor, several
application specific cores and controllers; all connected with a multi-master AXI bus and fault detection & recovery
resources. It also handles several dedicated interfaces with stringent timing constraints, as well as standard IO for
DRAM, SRAM, Ethernet, USB and I2C interfaces.
Emtech lead the overall verification process, from test plan definition, to testbench implementation, DUV simulation
and bug tracking. The verification environment was developed in System Verilog as a new instance of our continuously
improved framework. The UVM base library was employed for the testbench architecture and in-house developed
verification IPs (Agents) where integrated and reused. SV classes were extensively used to manage a complex Loosely
Timed reference model that involves an instruction level simulator for the CPU and allows emulating all the high level
transactions derived from ambitious functional coverage requirements.

Experience & Skills

Industry and Applications

State of the art functional verification methodologies.


OOP Verification Environment development & Verification IP integration.
Functional Coverage Space modeling and an0alysis
Formal Verification.
Event Driven Simulation & Debugging.
Digital Electronics.
Standard SoC components & IO: ARM Cortex, AMBA AHB-AXI, Ethernet, USB
and I2C.
ASIC & FPGA design & verification flows: Logic Synthesis, Static Timing
Analysis, Clock Domain Crossing, Power Management, and Place & Route.
System Bring Up & Silicon Validation Lab measurements.
Verification planning and management.

Technology Developers.
Consumer Electronics.
Verification IP.
Microelectronics.
Computer Hardware.
Critical Systems.

Viamonte 685 - 8000. Baha Blanca. Buenos Aires. Argentina. +542914532918.


Gallardo 855 8400. Bariloche - Ro Negro. Argentina. +542944458554.
www.emtech.com.ar [email protected]

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