CChapier 12. Fosdback end Stability © A common technique of frequency compensation utilizes the Miller multiplication ‘effet by incorporating a feedback capacitor across, wally, the seond stage of the basic amplifier. CHECKPOINT ‘After studying this chapter, the reader should have the ability to: W Describe some of the adventeges and disadvantages of negative feedback. (Section 123) Discuss the general characteristics of the four basic feedback configurations in terms of input and cutput signals and input and outpat resistances, (eetion 12.3) W Analyze feodback circuits. (Sections 124-127) © Design a feedback cacvit given the input signal and desired output signal. Sections 124-127) W Determine the loop gain of a feedback citeuit. (Section 12.8) ‘W Determine whether or not a three-stage feedback amplifier is stable, (Section 12.9) © Stabilize a three-stage amplifier using frequency compensation techniques. (Section 1210) REVIEW QUESTIONS: 1. What are the wo general types of Feedback and what are the advantages ard disadvancages of each type? ‘Write the ideal form of the general feedback wramsfer function, Define the Toop gain factor. ‘What is the difference between open-loop gain and closed-loop gain? Describe what is meant by the terms (a) gain sensitivity and (b) bandwidth extension. Sketch an iéeal series imput comnection, What is the input signal? Sketch an ideal shunt input connection. Wat isthe input signal? Sketch an iGeal series output connection. What is the output signal? Sketch an ideal shunt output connection. What is the output signal? Is the input resistance ofa series input conneetion sealer or larger than that of the ‘asic amplifier? Explain why from the input conection. 11. Is theinput resistance ofa shunt input conneetion smaller or lrger thar. chat ofthe basic amplifier? Explain why from the input connection, 12. Is the output resistance of a series output conrection smaller or larger than that of the basic amplifier? Explain why from the ou:put conrection, 13, {s the output resistance of a shunt output connection smaller or larger than that of the basic amplifier. Explain why from the ouiput connection 14, Describe the characteristics of a voltage amplifier. 15, Describe the characteristics of «current amplifier. 16, Deseribe the characteristics of a transconductance emplifer. 17. Describe the characteristics of a transresisiance amplifier. 18, Consider a noninverting op-amp circuit. Describe the type of input and output Feedback connections. 19. Consider ar inverting op-amp circuit, Describe the type of iaput and ourput feed- ‘back connections, 20. What is the Nyquist stability criterion for a feedback amplifier? ce eS ae Bata ‘im2 UL Analog Electronics 21. Using Bode plots, describe the conditions of stability and instability in a feedback amplifier. 22. What is phase margin? 23. What is amsant by frequency compensation? 24, ‘What is a dominant pole? 25. What is a common technique of frequency compensation in 2 feedback amplifier! PROBLEMS Section122 Bask Feedback Concepts 42.1 A negative feedback ampliier has a closed-loop gain of Ay = 80 and an open Joop gain of A = 10°, (a) What is she feedback transfer function #? (b) If the open-loop gain decreases by 20 pereent, deiermine the peroent change in the closed-loop gain. ‘What is the new value of 4/7 (c) Repeat parts (a) and (b) for 4 = 10°. 322 (a) A feedback amplifier is connected as shown in Figure P12.2, Each basic amplifier stage has an open-top guin of A = 10, The closed-loop gain is 4y = 100. Delermine the required feedback transfer function f. (b) If the gain of each stage increases by 10 percent, determine the percent change in the closed-loop voliag: gain, 123. Three voltage amplifiers are in cascade as shown in Figure P12.3 with various amplification factors. The 180 degret phase shift for negative feedback. actually occurs in the basic amplifier itself. (a) Determine the value of # such that the closed-loop voltage gain is Ay = V,/F, = —120. (b) Using the results of part (a), determine the percent change in dy ifeach individual amplifier gain decreases by 10 percent. 124 In vollage-follower application, the feedback transfer function is 6 = 1 and the idval closed-loop voltage gain is 4y = I. Determine the magnitude of the open-loop wolage gait sich thatthe closcdloop gain in an actual feedback circuit is within 0.02 percent of the ideal value (see Equation 12.5).Figure P12.2at a Figure P12.3 on‘Chapter 12 Feedback and Stability 425 An op-amp bas an open-loop low-frequency gain of A = 10° and an open-loop 34B frequency fy = 4H. Hf an inverting amplifier with « closed-loop low-frequency gain of [4y1 = 50 uses this op-amno, determine the closed-loop bancwidth. {6 (a) Determine the closed-loop bandwidth of a noninverting amplifier with a gain cof 50, The op-amp has the characterisics described in Problem 12.5. (b) Ifthe noninvert- ing ampliier gain i reduced to 10, determine the bandwidth, 12.7. Aninverting amplifier uses an op-amp with an open-loop 3B frequency of SHz, and bas a gain of [Ayyi = 50 and a bandwidth of 20kHz. Determine the required open- Joop low-frequency Op-amp gain. 12.8 Consider two opentoop amplifiers in cascade, with 4 noise signal generated ‘between the two amplifiers as in Figure 12 (a). Assume the amplification of the frst stage is Az = 100 and that ofthe second stage i = 1. I Fig = 10mV and ¥, = 1 mV, determine the signal-to-noise ratlo at the output 12.8 Two feedback configurations are shown in Figures P2.9a) and (b). At low input voltages, the two gains are 4, = az = 90 and at higher input voltages, the gains change tp Ay = A = 60. Determine the change in closed-loop tain, Ay feedback circuits. (See Figure 12.4.) Which feedback configuration will result in less distortion in the output signal? Figure P12.9 P1210 Determine the type of feedback configuration that should be used in a design to achieve the following objectives: (a) low input resistanee and low output resitance, {b) high input resistance and high output resistance, (¢) Low input resistance and high ‘output resistanes, and (4) high input resistance and low ontput resistance, 12.11 Consider a series of amplifiers and feodback circuits connected in the ideal feedback vonfigurations. In exch case the input resisiamce to the basic amplifier is R, = W0K2, the output resistance of the basic amplifier is R, = 149, and the loop gain is T= 10°. (a) Determine the maximum possible input resistance and minimum possible input resitance to the feedback circuit. (6) Determine the maximum possible ‘output resistance and minimum possible qutput resistance to the fendback circuit.() (b) ooS Part 1 Analog Electronics 12.12 A compound transconductance amplifier is 10 be designed by connecting two basic feedback ampliters in cascade. What two amplifiers should be connected in cas- cade to form the compound eixcuit? Is thee more than one possible design? Section12.3 Ideal Feedback Topologies 12.13 Consider the noninverting op-amp circuit in| ‘P12.13. The input resistance of the op-amp is X; = oo and the output resistance is R, = 0, but the op-amp has a finite ‘gain 4, (a) Weite the closed-toop transfer function in the form a4 A TF {b) What isthe expression for f? (€) If A = 10° and 4, = 20, what isthe required and Ri/Ri? (OIC A decreases by 19 percent, what is the percent change in 4? Figure P1213 1244 For the noninverting op-amp circuit in Figure PI2.13, the parameters are: A=l05, dy =20, R= 100k, and R, = 1002. Determine the closed-doop input and output Fesistaners, Ry andl Ry, respectively 42.18 Consider the op-amp circuit in Figure PI2.15. The op-amp has a finite gain, so that f= di,, anda zeto owtput impedance. (0) Write the closed-loop transfer function inthe form ee OF 8a (b) What is the expression for 8,” (6) MA = 10° and Ay = 25, what is the required 8; and Rp/Ry? (6) If A, decreases by 15 percent, what is the percent change in 4y? 4248 Anop-amp circuit is shown in Figure PL2.15. Its parameters are as described in Problem 12.15, except that &; = 2k and KR, = 20K2. Determine the closed-loop input and output resistances, Ry and Ry, respectively Ay Figure Pr2.16Chapter 12 Ferdback and Stability Figure P12.17 12:17 Consider the circuit in Figure P1217, The input resistance ofthe op-ampis R= 00 and the output resistance is R, =0. The op-amp has.a finite gain, so that 2 = 4, The current gain of the transistor is her. (@) Write the closed-loop sransfer function in the form ee FAA) “where 4y is the open-loop gain of the system. (b) What is the expression for 2 (6) If Ag = $ x 10" mS and Agr = 10m, what is the required , and Re? (4) Ii 4, increases by 10 percent, what is the corresponding percent change ia Ay? 12.48 The cireuit shown in Figure P12.17 has the seme parameters as described in Problem 12.17, except that R, = 20k8 and R, = 50k. Determine the closed-loop input and output resistances, Ry and Ry, respectively. 1248 Consider the current-to-voltege converter circuit shown in Figure P1219. The input resistance Ry is assumed to be small, the output resistance i R, = 0, and che op- amp gain A, is large. (a) Write the closed-loop transfes Function in the form Ag = {b) What isthe expression for A? (0) ILA, = $x 10° Rand Ay = 5 x 102, what isthe required A, and R? (A) If 4, decreases by 10 percent, what is the percent change in Ay? 12.20 For the current-to-voltage converte circuit in Figure PI2.19, the parameters are as deserted in Problem 12.19. FR; = 109, determine the closed-loop input resistance Ry. FigerePia.19,Part Analog Electronics Section 12.4 Voltage (Series-Shunt) Amplifiers "12.21 Consicer the voltage anaplifer in Figure P1221. The opamp parameters art Ay= 5x10, R= LOKR, and R, = [KID and the tcansistor parameters are hre — 100 and Ve = 80V. Determine Auy, Ry. and Ry. veny Figure b 12.21 igure P12.22 i 42.22 The circuit in Figure P1222 i an example of a series-shunt feedback circuit y ‘Assume the transistor parameters ate. Ire =100, Vashon) =0.7¥, and Vy = 00. | (2) Determine the quiescent collector currents aod the de voltage at the ouput, Oe (b) Determine the small-signal voltage gain. Ay = ¥5/, 1223 Consider the series-shunt feodback circuit in Figure P1223, vith transistor parameters: hye = 120, Vpcton) = 0.7, and ¥, =o0. (a) Determine the small-signal parameters for Q1. Qs, and Qs. Using nodat analysis, determine: (b) tbe small-signal ‘voltage gain 4, = vo/n. (6) the input sistance Ry, and ¢d) the output resistance Rey(Chapier 12 Feedback and Stability 12.24 Consider the BICMOS circuit in Figure P1224. The transistor parameters are: K,=0.2mA/V?, Vay = 1V, X= 0 for My and keg = 100, Veg(on) = 0.7, Fy = 00 for Q2. (a) Determine the small-signal parameters fot Mf) aod Qs.(b) Find the small- signal voltage gain Ay = v,/%, @) Determine the culpa: reistance Rar. Figure P1226 12.28 Figure P1225 shows a basic source follower circuit, Assume the transistor is biased such that Jpg =0.5mA. Assume the transistor parameters are Vy = 1V ard 2 = 0, and let Ry = 2KO. (a) Ir the transistor conduction parameter is K, =0.5ma/, determine Ayy = vofr, ad Rey. (b) Determine the percent change in Ay and Roy if the ‘conduction parameter increases 10 Ky = 0.8 mA/V" 1226 The transistor parameters for the circuit in Figure 12.26 are: hex = Si, Vyg(on) = 0.7, and Vy=0e. Using nodal analysis, determine the closeddoop small-signal voltage gain Ay = ro/ty at the midband frequency. ay FigueeP 12.25 Figure 12.28i. Pant IL Analog Ehctronis *DI2.27 Design a discrete transistor feedback voltage amplifier to provide a voltage gain of 50, Assume the availabic transistors have parameters: he = ‘The signal voltage source has a source resistance of Rs = 2KS2 and the load is R, 3KS. Verfy the design with a computer simulation. Determine Ry and Ry. *RDI228 Redesign the feedbeck circuit in Figure P12.22 using MOSFETs to provide a voltage gain of dy = 10. Assume transistor parameters of Vy = 2V, ke = EO WA/V?, and A = 0. Section12.§ Current (Shunt Series} Ampiitiers 012.29 An op-amp current gain amplifier (shunt-series configuration) is shown in Figure P1229. Design the circuit such that the load current is f, = 20mA when the input eurreat is f, = 200 uA viestoy Figure P12.29 Figure P12.20 4230 ‘The circuit in Figure P1230 has transistor parameters: hye = 100, Va(on) = 0.7, and Fg =o. (a) From the quisseeat values, determine the sialhsignal pa rameters for Q, and Qy. (+) Using aodal analysis, determine the smal-sgnal closed- loop current gain Ay = i/t, (@) Using nodal analysis, ind the input resistance Ry. 42.31 (@) Using the small-signal equivalent circuit in Figure 12.25 for the citewit in Figure 12.24(a) derive the expression for the small-signal current gain y= l/l, {b) Using the circuit parameters given in Figure 1224) and assuming transistor pa fammeters fg = 100 and F', = co, calrulate the value of dy. Compare this answer with the results of Example 12.9 912.82. The citcuit in Figure P12.32 is un example ofa shunt-series feedback circuit. A signal proportional to the output current is fed back to the shunt connection atthe bast of Q;. However, the circuit may be used as a voltage emplifer. Assume transistor parameters of ing = 120, Vye(on) = 0.7V, and V = co. (8) Determine the small-signal ‘Parameters for Q, aod Q.(b) Using nodal analysis, determine the small-signal voltage gain Ay = %/%—‘Chapter 12 Feedback and Sttiity Figure P12.92 12.93 Consider the circuit in Figure Pt2.32 with transistor parameters, hes = 120, Vgg(on) = 0.7, and V4 = 00. Using nodal analysis, determine the input resistance Ry. 412.84 For the transistors im te circuit in Figure P12.34, the parameters are: Arg = 30, Vgg(on) = 0.7 V, and V4 = 00. Using aodal analysis, determine the closed-loop current Bain Ay = iofig Reka Com R= 5000. Figure P12.34 "012.98 Design a discrete transistor feedback current amplifier to provide a current gain of 30, Assume the available transistors have parameters kre = 120 and Vg = 09, ‘The signal carrent source has a source resistance of Rp=25KkQ and the load is Ry = S002. Vesify the design with a computer simulation. Determine Ry and Ry Section 12.6 Transconductance (Serles—Series) Amplifiers, 12.28 The circuit in Figure P12.36 is the ac equivalent circuit ofa series-seties foed- ‘back amplifier. Assume that the bias circuit, which is not shown, results in quiescent collector currents of [cy =0.SmA, Ic = 1mA, and icy =2mA. Assume transistorPan TL Analog Electronics Figure P12.26 parameters of fy = 120and r, = co, Determine the transconductance transfer function Ag hel Ys 012.37 Using a computer simulation analysis, redesign the circuit in Figure P12.36 by changing the value of Ry to acbieve a transconductance guin of Ay = {,/¥, = 120 mA. 12.86 In the circuit in Pigare PI2.38, the transistor parameters are: pe =, 7¥, and Fy = 20. Determine the transconductance transfer function vretov Figure P12.38 12.20 Design a feedback amplifier to supply a current to an LED, The diode current should be J, = 10->¥;, where F; is the amplifier iapwt voltage, which has a range of 0 10 LOV. ‘The volage source has an output resistance of Ry = 1k. The op-amp pa- rameters are = 5kO, Ry = 502, and the low-fiequency open-loop voltage gain is 5x 10, Determine the gain, input resistance, and output resistance, from a computer simulation.Chapler 12 Feedback and Siabilty an Section 12.7 Transresistance (Shunt-Shunt} Amplitiors. 12.40 Considet the common-emitter circuit in Figare P22.49, driven by an ideal signal ‘current source. The transistor patametets are’ fir = 50, Vea(on) =0.7V, and Va 1OD¥. (@) Determine the input and output resistances, Ry and Ry, respectively. (b) Find the transresistance transfer function A.y = vj. (©) What happens inthe feed back network if the capacitenos is finite? Veo $¥ Reet Cae Figure P1240 4241 For the circuit shown in Figure P1241, the transistor parameters are: Vrw = 2V, K, = 020mA/Y", and 4 = 9. Determine: (2) the voltage gain A, = V_/¥, (b) the transresistance transfer function Ag = Vo/Jy (c) the input impedance Ry, and (d) the ‘outpat impedance Ry. Figura PI2at 12.42 Consider the circuit in Figure P(241. The wansisior parameters are Vy = SV and 4 = 0. Determine the sequised value of trensconductance gq such that the magaiuide of the closed-loop voltage gain is within 10 percent of the ideal value when Bn >.Part I Analog Bictronict 12.49 For the circuit in Figure P1243, the wantistor parameters are: Ape = (50, Vag(on) = 0.7 V, and V4 = 00. Determine the value of Ry that will result in a closed- oop voltage gain of A, Figure P1243 1244 Consider the Uhveestage cascade feedback circuit in Figure 12.40, Each stage comesponds to the creuit in Figure P1244, with transistor parameters: re = 18, Fyp(0n)=0.7V, and V, = 00, The soutce resistor is Rs = 1040, and the lond resistor is Ry =4KQ. Determine the valve of Ry such that the closed-loop gain is 4, = volt = 80. Figure P1246 Figure Piz4s 42.48 The op-ampin the circuit in Figure P12.45 has an open-loop differential voltage gain of Ay = 10". Neglect the current into the op-amp, and assume the output resistance Tooking back ino the op-amp is 2er0, Determine: (a) the closed-loop voltage gan ‘A, = V4/¥,,(b) the inpul resistance Ry, and (c} the output resistance Ry 12.46 Design a feedback transresistance amplifier using an op-amp with parameters R,= 10KO, R, = 1008, and a low-frequency opentoop gain of A, = 10° to produce aChapter 12. Feedback and Stability ‘gain of $k. The source resistance is Ry = 5002 and the load resistance is Ry, = 22. Determine the actual gain, input resistance, and output resistance using a computer simulation Section 12.8 Loop Gain 12.47 The op-amp in Figure 12.20 bas an open-loop differential input resistance Ran ‘oper-loop curtent gain A,, and ¢ zero output resistanes. Break the feedback loop at an appropriate point, and derive the expression for the loop gaia. 12.48 The small-signal parameters ofthe transistors in the circuit in Figure P1223 are hire and V., = 00. Derive the expression for the loop gan, 4249 Determine the loop gain T for the circuit in Figure PI2.30, The transistor parameters are: Arg = 100, Vggton) = 0.7 V, and Vg = oo. 12.50 The transistor parameters for the circuit shown in Figure P12.40 ate: Ace = $0, Vac(on) = 0.7 ¥, and Vg = 100. Find the loop gaie T. Section 12.9 Stability of the Feedback Circuit 12.51 A three-pole feedback amplifier bas a loop gain given by a0) yo a a Zz if (Ae) 47h) (@) Determine the frequency fig at which the phase is ~180 degrees. (b) At the fre- quency fin, determine the value of f such that |TUfn)I = t- 12.52 The open-loop gain of an amplifier is given by TU S10 PAT, GOPRE {949)('~"m7) ‘Assuming the feedback function is nota function of frequency, determine the frequercy at which the phase is 180 degrees. Determine the value of the feedback transfer Function al wich the amplifier can break into ossilation. 12.53 A loop gain function is given by - Bde?) O° Brine) ‘Sketch the Nyquist plot for: (a) f = 0.008, and (b) B= 0: unstabie in each case? 12.54 A three-pole feedback amplifier has a loop gain fuaction given by 6) Ts the system stable or AS x10) (45) (ste) {@) Sketch the Nyquist diagram for £ = 0.20, (b) Determine the value of 8 that produces 1 phase margin of 80 degrees. Tus asate Pact IT Anclog Blettonics 42.88 A three-pole feedback ampilier has a loop gain given by Alo") “r)( a) ta) ( Hae) ig, Sketch Bode plots of the loop gain magnitude and phase for: (@) §=0.005, and (b) B= 0.65. () Is the system stable of unstable in each case? If the system is stable, ‘what is the phase margia! 42.98 An amplifier with » Jovstrequency open-loop gain of 10° has poles at $x 10"Hz, 10° Hz, and $x 10’ Hz. Determine the feedback transfer function # and he low-frequency closed-ioop gain for which the phase margin is 60 degrees. 12.57 A two-pole loop gain function is given by mao’) Tory ( ey in) (a) Determine the value of $ that produces a phase margin of 60 degrees. (b) Using the results of part (2), sketch the Bade plots of the loop gain magnitude and phase. 12.88 The open-loop gain of an amplifier has pole frequencies at 10 kFz, 100kHz, and IME. The low-frequency open-loop gain is 500 and te feedback transfer fonction is B=66. Find the phase margin TU) n= 42.69 Sketch the Bode plots of the magnitude and phase of the function K W= wh ) (eG for: (a) K = L, and (b) 10". 42.60 Consider a four-pole Feedback system with a loop gain given by r Determine the value of # that produces a phase margin of 45 degrees. Section 12.10 Frequency Compensation 42.61 A feedback amplifier has 4 low-frequency loop gain of 5000 and three poles at Jon = YOOKHE, fyp = 2 MHz, and fps = 25MHz. A dominant pole is to be added such ‘hat the phase margin if 45 deprees. Assuming the original poks remain fixed, determine the dominant pole frequency. 1282 A feedback amplifier with a compensation capacitor has a low-frequency loog gain of T(0)= 100dB and poles at fn = 10E2, fp) =5MH2, and fy = 1MHe {a) Find the frequency at which [7(/)| = L, and determine the phase margin. (b) If the frequency ff is due to a compensation capacitor Cp = 20pF, determine the new domican. pole frequency fy and phase margin if the compensation capacitor is increased to Ce = 150F 4269 The equivalent cicuit at the interface between the first and saoond stages of an ‘op-ainp is shown io Figure PI2.83, The parameters are Rey = S00K92, Ra = IMO. and C,=2pF. (a) Determine the pole frequency for this part of the circuit. (b) Determine the additional Miller capacitance Cy that would need to be added so that the pole frequency és moved t0 frp = 102.CChapier 12 Foeback ime Stailiry Ry Re GI RG Figure P1263 42.64 The loop gain function of a feedback amplifier has its first two poles at Joy = 2MHz and fp = 12 MH, and has a low-frequency gain of |T(O)l = S0dB, The “amplifier is 10 b¢ stabilized by moving the first pole by using Miller compensation, ‘Assuming that the second pole fz remains fixed, find the frequency to which Jy must bbe changed to produce a 45 degtee phase margia. 1265 A three-pole amplifier has its first wo poles at foi = | MHz and fry = 1OMHz, and has a low-frequency open-loop gain of |4,| = 80dB, A dominant pole is to be inserted such that the closed-loop system remains stable when the closed-loop, low= frequency gain is |4/{0)| = 5. Determine the dominant pole frequency aésuming the initial poles remain constant 12.66 The amplifier described in Problem 12.6] isto be stabilized by moving the fist pole by using Miller compensation. Assuming fr, remains constant, determine the frequency to which fp, must be moved. COMPUTER SIMULATION PROBLEMS 42.67 Using a computer analysis, investigate the loop gain factor for the circuit in Figure 12.24(2). Javestigate the loop gain as a function of Ry and of fgg. 412.68 Consider the multistage feedback cirewit in Figure 12.40. Assume each stage corresponds to the circuit in Figure PI244. Let Re=200k2, Ry = 10K, and Ry, = 442 (a) Investigate the open-loop voltage gain A, = ¥4/¥, a8 a function of the individual transistor current gains Age. (b) Determine the required value of open-loop ‘gain and transistor current gain needed to achieve a closed-loop gain that is within 2 percent of the ideal value. 42.68 Consider the circuit in Figure P1232. From a compater analysis, determine the {oop gain and the closed-loop transfer gain, 42.70 Consider the circuit ia Figure $2.47 with parameters given in Example 12.18. “The citeuit is biased with Voc = IOV, and it includes 0.56 emitter resistors. Inert coupling und emitter bypass capacitors where appropriats. (a) Determine the loop gain versus frequency characteristic. (b) Insert a compensation capacitor, C3 = 30pE, between the collector and base of Qs. Replot the loop gain versus frequency characters istic and determine whether the system is stable oF unstable, 1271 Consider the circuit in Figure 12.16 with parameters: 4, = 10", Kj = 1002, R, = $0 Ry = KR, and Ry = Li. Determine the enact values of voltage gain Ay, input resistance Ry, ard outpat resistance Rey. from a computer analysis.Part Ul Asaleg Electronics DESIGN PROBLEMS (Note: Each design should be correlated with a computer simulation analysis) 712.72. Redesign the circuit shown in Figure 2.45(a) to provide a loop gain of at least 100, What are the values of Icg and Vieng? *012.73 An op-amp has a low-frequency open-loop gain of 10° and a dominant-pole Frequency of $ Hz. Design a cascade of noninverting amplifiers with an overall minimum ‘gain of 800 and a minimum bandwidth of 12 kH2. "12.74 An op-amp hes s low-frequency open-ioop gain of Sx 10" and a dominant- pole frequency of 10H2. Using this op-amp, design a preamplificr system that cam amplify the output of a microphone and produce @ 1 V peak signal over a frequency range from f0Hz to 15kH2. The equivalent circuit of the microphone is voltage souroe in series with an output resistance. The vollage source produces « SmV peak signal and the output resistance is 102. £12.75 ‘The equivaien: circuit of atransciucer that measures the speed of « motoris a ccurreat source in parallel with an output resistance. The curtent source produces an ‘output of LA per revolution of the motor and the output resistance is SOKS2. Desien a discrete transistor circuit that produces a fullscale output of SV for a maximum motor speed of 60 revolutions per second, The nominal transistor current gain is Are = 100 wilh tolerances of 420 percent, The avcuracy of the eutput signalis to remain within +1 percent,Operational Amplifier Circuits 13.0 PREVIEW Thus far, we have considered basic circuit configurations, such as the common emitter, emitter follower, and diff-amp, among others. We kave discussed the basic concepts in design and analysis, including biasing techniques, frequency response, and feedback effects. In this chapter, we combine basic circuit con- figurations to form larger analog circuits that are fabricated as integrated circuits. Operational amplifiers are used extensively in electronie systems, so wwe concentrate on several forms of the operationat amplifier circuit in this chapter. We introduced the ideal op-amp in Chapter 9. Now. we analyze and design the circuitry of the op-amp, to determine how the various circuit configurations can be combined to form a nearly ideal op-amp. The LM741 is an example of an all-bipolar general-purpose op-amp. Even though this op-amp is considered a classic, it still provides a good case study in which we perform a detailed analysis to determine both the de and the small- signal characteristics of the circuit, Since the 741 is an internally compensated op-amp, we derermine the dominant-pole frequency and the unity-gain bandwidth, AILCMOS op-amps can be designed for special cn-chip applications. In general, these op-amps are designed to drive other CMOS citcuits, waich form high capacitive loads. A goal of this chapter is to enable the reader to design CMOS op-arop circuits, including choosing transistor width-1o-width ratios. to meet particular specifications, including power and gain parameters 13.1 GENERAL OP-AMP CIRCUIT DESIGN ‘An operational amplifier, in general, is « three-stage circuit, as shown in Figure 13,1, and is fabricated as an integrated cireuit. The first stage is a differential amplifier, the second stage provides additional voltage gain, and the third stage provides current gain and low output impedance. A feedback capacitor is often inchided in the second stage to provide frequency compensation as discussed in the tast chapter. In some cases, in particular with MOSFET op-amp circuits, only the first two stages are used. We have on numerous occasions made reference to the op-amp. In Chapter 9. we analyzed and designed op-amp circuits using the ideal op-amp a7aie Part f Analog Ebettonics ‘tol 1 Gain ‘Ou Dito bos, | sige stage Figure 13.1. General block diagram ol an operatcnalameliier model. In Chapter 10, we introduced current-source biasing and introduced the active load. The differential amplifie. using current source biasing and active loads was considered in Chapter #1. We also introduced the bipolar Darlington pair in Chapter 11, which is often used as a second gain stage. Previously, in Chapter 8, we considered the class-AB output stage that is often used in opera- tional amplifier circuits. These individual building blocks will now be combined to form the operational amplifier. Tn Chapter 9, as mentioned, we analyzed and designed ideal op-amp ci rational amplifiers. as we will see in this chapter, exhibit acteristics that deviate from the ideal characteristics, Once we have ani- lyzed these practical opamp circuils and determined soie of their nonideal properties, we will then consider, in the next chapter, the effect of these non ideal characteristics on the op-smp circuits. 13.1.1. General Design Philosophy All stages of the operational amplifier vircuit sre dite! coupled. There are no coupling capucitors and there are also no bypass capacitors. These types of capacitors would require extremely large areas on the IC chip and hence are impractical. In addition, resistors whose values are over approximately SOK& are avoided in ICs. since they also require large areas and introduce parasitic effects. Op-amp circuits are designed with transistors having matching, characteristics. ‘We may begin to design a simple bipolar operational amplifier by using the knowledge gained in the previous chapters, Figure 13.2 shows the general configuration of the circuit. The first stage will be a differential pair, Q, and Qs, biased with « Widlar current source, @:, Qs, and Rp, and using a threc- transistor active load, Assuming matched transistors, we expect the de voltage at the collector of Qs to be two base-emitter voltage drops below the positive bias voltage. Therefore, the Darlington pair, Qs and Q,, that forms the second stage should be properly biased. The bias current for Qy is supplied by the ‘Widlar current source, Js, Qyo- und R}. The output stage is the complementary push-pull, emitter-follower configuration of Q;; and Qj». The crossover dis- tortion is eliminated by including the diodes D, and D). The emitter-follower configuration provides Jow output resistance so that the op-amp can drive a load with minimal loading effect. By changing the value of R; slightly, the current through Qjg and Qs can be changed, which will change the collector ‘emitter voltages across these transistors. This part of the circuit then acts as a de voltage shifter such that the output voltage, vo. can be set equal to zero for zero input voltages. From results tha: we have derived previously, we expect the differential- mode voltage gain of the first stage to be in the range of 10-10”, depending onChapter 14 Operational Amplifier Cieuits e Figure 13.2 Asimpte bipotar operational ample: the specific transistor parameters and the voltage gain of the second stage to also be the cange of 10°10. The voltage gain of the output stage. un emitter follower, is essentially unity. The overall voltage gain of the op-amp circuit is then expected to be in the range of 10-10, From our study in Chapter 9. this magnitude of voltage gain is required for the circuit to act essentially as an ideal op-amp. ‘The same op-amp configuration can be designed with MOS transistors. In general, as we have seen, BIT circuits have higher voltage gains, whercas MOSFET circuits have higher input resistances. So, whether a bipolar or MOSFET design is used depends to a large extent on the specific apphcation of the op-amp. 13.4.2 Circuit Element Matching Integrated circuit design is based directly on the ability to fabricate transistors ona chip that have nearly identical characteristics. In the analysis of current mirrors in Chapter 10 and differential amplifiers in Chapter 11, we assumed that transistors in a given circuit were matched. Transistors are matched when they have identical parameters. For bipolar transistors. the parameters are Zs. A.and F. Recall that Zs includes the electrical parameters of the semiconduc- tor material zs well as the cross-sectional area (geometry) of the base-emitter junction. For NMOS transistors, the parameters are V7, Ky. and Aq. and for PMOS trunsistors, the same corresponding parameters must be identicel, Again, recall that the parameter K, contuins semiconductor parameters as well as the width-io-length (geometry) of the transistor, ‘The absolute parameter values of transistors om an IC chip may vary substantially (on the order of £25 percent) from one IC chip to the nextPart Analog Elcuones because of processing variations. However, the variation in parameter values of adjacent of nearby transistors on a given IC chip are usually within a fraction of a percent. In general, much of an amplifier design is based on the ratio of tansistor parameters and on the ratio of resistor values rather than on the absolute values. For this reason, the operational amplifiers described in this chapter can be fabricated as ICs, but are almost impossible to fabricate with discrote circuit elements. Test Your Understanding 13.4 Using a computer sirmulation, determine the de voltages and currents in the Dipolar op-amp circuit in Figure 13.2, Use reasonable resistor values, Adjust the value ‘of Ry such that the output voltage is neatly zero for zero input voltages. 48.2. Consider the basic diff-amp with active lead and current biasing im Figure 13.2, Using a computer simulation. investigate the change in the voltage at the collector of Q3 8 Q; and Q;, and also Qs and Gp, become slightly mismatched 13.2. ABIPOLAR OPERATIONAL AMPLIFIER CIRCUIT ‘The 741 op-amp has been produced since 1966 by many semiconductor device ‘manufacturers. Since then, there have been many advances in op-amp design, but the 741 is still a widely used general-purpose op-amp. Even though ibe 741 is a fairly old design, it still provides a useful case study to describe the general circuit configuration and to perform a detailed de and small-signal analysis. From the ac analysis, we determine the voltage gain and the frequency response of this circuit. 13.2.1 Circuit Description Figure 13.3 shows the equivalent circuit of the 741 op-amp. For easier analysis, we break the overall circuit down into its basie circuits and consider each ore individually As with most op-amps, this circuit consists of three stages: the input dif- lerential amplifier, the gsin stage, and the output stage. Figure 13.3 also shows a separate bias circuit, which establishes the bias curreats throughout the op- amp. Like most op-armps, the 741 is biased with both positive and negative supply voltages. This eliminates the need for input coupling capacitors, which in tum means that the circuit is also a de amplifier. The dc output voltage is zeto when the applied differential inpat signal is zero. Typical supply voltages are Vt = 15Vand F~ = 15, although input voltages as low as 5 V can be used, Input Dit-Amp ‘The input diff-amp stage is more complex than those previously covered. The input stage consists of transistors Q, through Q;, with biasing established by transistors Qy through (12. The two input transistors Qy and Q, act as emitterChapter 13 Operaticnal Ampliier Circuits Noniosering gt npwsage Pal scicit Gainsiane Figure 13.9 Equivalentcireut, 741 0p-amp followers, which results in a high differential input resistance. The differentiat ‘output currents from Q and Q; are the inputs to the common-base amplifier formed by Q; and Qy, which provides a relatively large voltage gain. Transistors Os, Qs, and Gr, with associated resistors Ry, Ry, and Ry, form the active load for the diff-amp. A single-sided outpul at the common collec- tots of Qy and Q, is the input signal to the following gain stage. The de output voltage at the collector of Qe ist a lower potential than the inputs at the bases of Q) and Qa. As the signal passes through the op-amp, the de voltage level shifts several times. By design, when the signal reaches the ‘output terminal, the de voltage should be zero if a zeto differential input signal is applied, The two null terminals on the input siage are used to make appro- priate adjustments to accomplish this design goal. The “null technique” and the corresponding portion of the circuit will be discussed in detail in the next chapter ‘The de current biasing is initiated through the diode-connected transistors Qyz and Qj, and resistor Rs. Transistors Qj, and Qjo. with resistor Ra, form a ‘Widlar curtent source that establishes the bias curremts in the common-base transistors Q; and Q,, as well as the current mirror formed by Qp and Qs. Transistors Q and Qy art lateral pnp devices, which refers to the fabrica- tion process and the geometry of the transistors. Lateral pap transistors pro vide added protection against voltage breakdown, although the current gain is smatler than in apn devices. 2 OutPact 1 Anaiog Electronics Figure 13.4a) shows a basic coramon-emitter differential pair used as the input to a diff-amp. If the input voltage F, were to be connected to a supply voltage of 15¥, with V; st ground potential, then the B-E junction of Q» would be reverse biased by approximately 14.3 V. Since the breakdown voltage of an npn B-E junction is typically in the range of 3-6V. transistor Qs in Figute 13.4(a) would probably enter breakdown and suffer permanent damage. Figure 13.4 (a) Basic common-eminer olteranial pat, with a lage diferent vollage and (©) the 741 input stage, with a farge efierential votage By comparison, Figure 13.4(b) shows the input stage of the 741 op-amp with the same input voltages. The B-E junctions of Q; and Q; ate forward biased, which means that the series combination of B-E junctions of Qs and Qu is reverse biased by approximately 13.6. The breakdown voltage of a lateral pup B-E junction is typically on the order of 50, which means that for this inpui voltage polarity, the B-E junction of Q, provides the necessary break- down protection for the input diff-amp stage. Gain Stage The second, or gain, stage consists of transistors Qyy and Qy7. Transistor Oy, operates as an emitter follower; therefore, the input resistance of the gain stage is large. As previously discussed, a large input resistance to the gain stage minimizes loading effects on the diff-amp stage. Transistor Q,; is effectively two transistors connected in parallel, with coramon base and emitter terminals. The area of Qs, is effectively one-faurth the area of Qr2, and the area of Qjsg is effectively three-fourths that of Qi. Transistor Qiag provides the bias current for Q7 and also acts as.an active load to produce a high-voltage gain, Transistor Qry operates in a common-emiticr ‘configuration; therefore, the vollage at the collector of Qj is the input signal to the output stage. The signal undergoes another de level shifl as it goes through ‘this gain stage. ‘The 741 is internally compensated by the feedback capacitor C, connected between the output and input terminals of the gain stage. This Miller compen- sation technique assures that the 742 op-amp forms stable feedback circuits.CChapier 13. Operational Amplifier Cireaits Output Stage ‘The output stage of an op-amp should provide a low output resistance, as well asa curtent gain, if itis to drive relatively large load currents. The output stage is therefore a class-AB circuit consisting of the complementary emitter-follower Pair Qu and Om. The output of the gain stage is connected to the base of Qz, which oper- ales as an emitter follower and provides a very high input resistance; the gain stage therefore sulTers no significant loading effects due to the output stage. Transistor Qjy4 provides a bias current for Qys, 28 well as for Ors and Qis, which are used to establish a quiescent bias current in the output transistors iq and Qyo. Transistors Qs and Q2) are referred to as short-circuit protection. devices. These transistors are normally off; they conduct only if the output is inadvertently connected to ground, resulting in a very large output current. We ‘will consider the characteristics of the output stage in Seetion 13.2.2. An abbreviated data sheet for the 741 is shown in Table 13.1. During our discussions in this chapter, we will compare our analysis results to the values in the table. A more complete data sheet for the 741 op-amp is given in Appendix C. ‘Table 13.1 Oatalor741 at T = 300°K and supply voltage of +18V Parameter Minioum ‘Typical Maxie Units Input bias current ®0 500 aA Differentiatemode inpus resistance 03 29 Ma Input eapaciance is pF ‘Output short-circuit current 6 mA ‘Opetrlocp gaio (R= 242) 50,000 20990 ww ‘Output resistance 5 a “Unityarin freer 1 Miz ‘Test Your Understanding 49.8 The 741 opamp in Figure 133 is biased at V7 = 15V and V" = -15Y. Assume Vyglapa) = Veslpnp) = 0.6V. Determine the input common-mode voltage range, negeciing voltage drops acioss Ry and Rp. (Ans. -12.6 < vg(em) < 14.4V) 43.4 (a) Ii the 241 opamp in Figure 13,3 is biased at V7 = 15 and V~ = -15¥, estimate the masimam and minimum output voltages such that the op-amp remains biased in its linear region. (b) Repeat part (a) if F* =5V and V~ =—SY, (Ans (@) 132 <9 < I38V (6) 32 < 99 S38V) 13.2.2 DC Analysis In this section, we will analyze the de characteristics of the 741 op-amp to determine the de bias currents. We assume that both the noninverting and inverting input terminals are at ground potential, and that the de supplyPart il Analog Electronics voltages are V7 = 15V and V7 = -15V. As an approximation, we assume Vpg = 0.6V for npn transistors and Vigg = 0.6V for pnp transistors. In most de calculations, we neglect de base currents, although we include base current ‘effects in a few specific cases. ‘Bea Circuit and Input Stage Figure 13.5 shows the bias circuit and input stage portion of the 741 circuit. The reference current, which is established in the bias circuit branch composed Of Qa. Qu, and Rs, is ¥* Vea — Veen — Teer fan fa aan Trarsistors Qi, and Qi and resistor Ry form a Widlar current source. Therefore, fei is determined from the relationship (13.2) where Vis the thermal voltage and Qo and Qj, are assumed to be matched transistors Neglecting base currents, ice = fey = Acro. The quiescent collector cure rents in Q; through Q, are then le few Tex = Hea (13.3) Assuming the de currents in the input stage are exactly balanced, the de voltage at the collector of Qs, which is the input to the second stage, is the same as the de voltage at the collector of Qs, We can write Ves = Vanes + Fare + feoRy + ¥7 3.4) As previously discussed, the de level shifts through the op-amp aa. Example 13.1 objective: Calculate the de cortents in the bias cizeuit and input stage of the 741 op-amp. “The bias circuit aod inpat stage are shown in Figure 13.5. Solution: From Equation (13.1), the referenc: current is. ¥* Vern ~ Vag Vo _ 15-06-06 - (213) Rs ~ cy Current fer is found from Equation (13,2), as follows: FelS) = (0.028) (G2) By tial and error, we find that ‘cio = I9 A. The bias currents in the input stage are then Jace = =0.72mA dey = her = Hes = Fen = 950A From Equation (13.4), the voltage at the collesior of Qs is Fes = Varn + Fase + Hea + V7 3 0.6-+0.6 + (0.0095XI) + (-15)Chapter 13 Operational Amplifier Cucuiss Figure 13.8 Bias circultand input stage portion of 741 opamp circuit or Veg 8-138 Comment: The biascurrents in the input stage are quite small the input base currents al the noninverting and inverting terminals are generally in the nanoampere range. Smalt bias currents mean that the differential input resistance is large. The transistor current gain of the lateral pnp transistors @5, Qs, Qs, and Q» may be relatively small, which means that the base currents in these tran- sistors may not be negligible. To determine the effect of the base currents, consider the expanded input stage shown in Figure 13.6. The base currents in the npn (ransistors are still assumed to be negligible. Current Zip establishes the base currents in @; and Q, which then establish the emitter currents designated as /. At the Qs collector, we have alate 2 Weston tp =lo(143) 3.5) ‘Since Q, and Qy are matched, Jeg = Icy. Then,Po Patt Il Analog Electronics en Figure 13.8 Expanded inputsiage, 741 ¢p-amp, showing basecur uy y u 426,42 = oe p+ 2h, + tem = Tp, tio T+3, (+2) fe (6) 4, Even if the pnp transistor base currents are not negligible, the bias currents in Qs and Q; are, from Equation (13.6), very nearly te: =n Ts z 3.7) ‘This bias current is essentially the same as originally assumed in Equation 3.3), Test Your Understanding 43.8 The current gain f, of the npa transistors in the 74t op-amp input stage in Figure 13.5 i A = 200. Determine the input hase currents to Q, and Qs, (Ans. 47.514) "13.6 Consider the input stage and bias circuit in Figure 13.5, with V! = 15V and V7 =—I15V_ If fs = 10 A for each transisior, determine Inep» Fact» Pero: and Vagw. (ANS. Inep = 0.118MA, Fog = O650V, ae) = 0.556V, Vary = 0.517 V) Gain Stage Figure 13.7 shows the reference portion of the bias circuit and the gain stage. ‘The reference current is given by Equation (13.1); Transistors Qio and Qs‘Chapter 13 Operational Amplifier Cucuils Biascirall j, __ Gansuze Figure 13,7 Reterencecireuitand gain stage. 7410p-ame form a current mirror, and Qirz has a scale factor 0.75 times that of Qi. Neglecting base currents, curtent Fcy3s is then Joys = O75 pee (3.8) ‘The emitter current in Qyg is the sum of the base cuzrent in Qy; and the current in Ry, as follows: lente + Varn 39) Fee ™ nw i Example 19.2 Objective: Caleulate the bias eurrents in the gain stage of the 741 ‘op-amp in Figure 13.7. Solution: In Example 13.1, we determined the reference current to be Jygp = 0.72 mA. From Equation (13.8), the collector current in Qyz is ys = lowe = 0.7 lpg = 0.75(0.72) = 0.5408. ‘Assuming B = 200 for the npn transistor, the collector current in Qyg is, from Equation 39), onry Part Il Analog Electromes He Rut Vans 088 , (OS4K0.1) 4.06 Re 20) aD lent To = 15.808 Comment: The small bias current in Qje, in conjunction with the resistor Ay, ensures: that the input resistance to the gain stage is large, Which minimizes loading effects on the difF-amp stage. The mal bias currencin Qyg also reas thatthe base current in Qe 16 negligible, a8 assumed in (he de analysis of be inpuc stage. fe Output Stage Figure 13.8 shows the basic output stage of the 741 op-amp. This iva class-AB configuration, discussed in Chapter 8. The Faia is supplied by Qia4. and the {input signal is applied to the base of Qz2, which operates as an emitter follower. The combination of Oia and Qyy establishes two B-E voltage drops between the base terminals of Qj, and Qzo, causing the output transistors to be biased slightly in the conducting state. This Vgg voltage produces quiescent collector currents in Oye and Oop, Biasing both Oy and Gay “on” with no signal present ‘at the input ensures thal the output stage will respond linearly when a signal is applied to the op-amp input. Figure 13.8 Gasicoutput stage. 741 op-amp, showing currents andvoltages The collector of Ory hus a scale factor of 0.25 times that of On. Neglecting base currents, current Feasa i8 Foysa = 0.25tage = foie 10)Chapter 13 Operational Amoliier Cieuits ay where fer is given by Equation (13.1). Neglecting base currents, the coilector curtent im Qoz is A180 equtal (0 Taye. The collector current in Qis is tow = 03.1) oe Rw Therefore, Fors = taias ~ ters (13.12) Example 13.3 objective: Calculate the bias currents in the output stage of the 741 op-amp. Consider the output stage shown in Figure 13.8. Assume the reverse saturation currents of Qiy and Qy are Js ~ 9°!" A, and the covers: scturation currents af Qua and Qap are ty = 3 > 10°" A. Neglect base currents. OER Sotution: The reference current, from Example 13.1. Iner = 0:72mA. Current Jessy 's then Leg = OID heey = (025K0.72) # 0. If we assume Msp} = 0.6V. then the current im Rig is 0 The current in Dio is Few % te 0.18 0.012 = 6.168 mA 14 7 dt For this value of collector current, the B-E voltage of Qyy 0,168 x 10-" cn" base current in Qi is Tory _ 109A, Iyyg = Ht = OHA 95 a8 = B= ag EOS HA The current in Qn isnow Jers ¥ lem = Ino + fos = 12 408 = 128A The B E voltage of Oye is therefore i w( 2) = (0.026) in (Sx) Is Vor s4sv ‘The voltage difference gg 1 thus Fag = Varw + Vany = 0.585 +0612 = 1.1570 Since rhe Output transistors Qyg and Qyy are identical, one-half of E junction. The quiescent currents in Qig and Qoy are ag = yd wy ortiz Fea = few = 38 WARe Pant IT Analog Electroutes cement: Using the picevise linear approkimation of 0.6V for the B-E junction voltage does not allow us to determine the quiescent currents it Qia aPd Qn. For a more accurate analysis, the exponential relationship must be used, since the base- fontier areas ofthe output tansisors are larger than those of the other transisiors, and hecause the ouput trancistors ae biased at low quisten curren, Test Your Understanding 43.7 In Figure 13.8, replace the Qi. Qa, und Rye combination by two series diodes with fs = 10°44. Assume that yyy, i the same as previously determined, and let Bx OMA for Qig and Qiy. Calculate Vyy. dees and Fes, (ANS. Vg = 1228Y. S41 mA) As the input signal vy increases, the base voltage of Qty increases since the Vgp voltage remains almost constant. The output voltage increases at approxi- mately the same rate as the input signal, As ¥, decreases, the base voltage of Qzy decreases, and the output volage also decreases. again at approximately the same rate as the input signal. The small-signal voltage gain of the output stage is essentially unity. ‘Short-Cireuit Protection Circuitry “The output stage includes 2 number of transistors that ate off during the normal operation of the amplifier. If the output terminal is at 2 positive voltsge ‘because of an applied input signal, and if the terminal is inadvertently shorted to ground potential, a large current will be induced ia output transistor Qua. A. large current can produce sufficient heating to cause transistor burnout The complete output stage of the 741, including the short-circuit protection devices, js shown in Figure 129, Resistor R, and transistor Qs kit the current in Qje in the event of a short circuit. If the current in Qy4 reaches 201A, the voltage drop across R, is $40mV, which is sulficient to bias Qjs in the con- ducting stage. As Qs turns on. excess base current into Oy is shunted through the collector of Qs. The base current into Qi« is then limited to a maximum value, which limits the collector current ‘The masioum current in Quy is limited by components Ry, Qai.and Qs much the same way as just discussed. A large ouput cursent will result voltage drop across R;. which will be sufficient to bias Q, in its conducting state. Transistors Q;, and Qsy will shunt excessive output current away from Qn. to protect this oviput transistor. 13.23 SmallSignal Analysis We can analyze the small-signal voltage gain of the 741 op-amp by dividi into its basic cireuits and using results previously obtained.Chupter 19 Operational Amplifier Ciseits Figure 13.8 Outputstage.7419p-amp withshort-, Example 13.10 objective: Determine the differential: mode voltage guin of the folded cascode dit-annp in Figure 13.16 ‘Assume circuit and ansistor parameters: Meer = 100wA, &; = 80WA/¥", kp = 4WA/V4, GPL) = 25, and Ap = 2, = DOZVE Solution: The transconductance are determined (o be ew ft fon = toa = YE © iy nrf8 (25950) = 316 WAV and a2 fhe Hy BL ™ faa = 2 Pte = DZ SNS) = HATHA ‘The tcansistor output resistances are found to be 1 t "= 3, * waaay” | MO ra = tee and I ' Mow (0.03\100) SMa. ‘The composite output resistances can be determined as Rs = Kat Verto = OKI = 346 M2 and Roa = koa asMloa Wa (47H ¥0.511) ‘The differential-mode voltage gain is then Ag Bn Reall Rea) = (3Y6X 1499316) 32,000 Comment: This example shows that very high differential mode votlage gains can be achieved in a folded casende CMOS circuit. In actual circuits, the output resistances way be limited by leakage carcents so the very ideal values may not be realizable. However, sutetantally higher differential mode vollage gains can be achieved in the folded cascode configuration than in the simpler diff-arnp ereuisPart il Anslog Electronics Test Your Understanding 43.44 Assume the reference current in the folded cascode circuit shown in Figure 13.16 is Fer = SOWA. Assume the transistor parameters art the same as given in Example 13.10. Delermine the differential-mode voltage gain. (Ans. 64,000) 13.3.3 CMOS Current-Mirror Operational Amplifier Circuit Another CMOS op-amp circuit is shown in Figure 13.17. The differential pair is formed by M, and Mf), The induced ac currents from these transistors drive transistors M; and M,, which are the inpu's of two current mirrors with 2 current multiplication factor B. The current output of Af, is then induced ir ‘Mg by the eurrent-mirrar action of M; and My. The output signal currents then have a multiplication factor B. The differential-mode voltage gain is then Ay = 22 = BgmFosllton) (13.43) ve Figure 13.17 CMOS current-nirror op-amp The factor of B in the gain expression of Equation (13.43) may be slightly misleading. Recall that the individual transistor owiput resistance is inversely proportional to the drain current, Hf the current in the output transistors increases by the factor B, then R, = repli decreases by the facior B so the ifferential-mode voltage gain remains unchanged.(Chapier 13 Operational Amplifier Circuits ‘The advantage of the current-mircor op-amp is an increase in the gain~ bandwidth product, The deminant-pole frequency wilt be determined by the parameters at the output node. The dominant-pole frequency is given by ee RAC, + Op) Iie (13.44) where R, is the output resistance, C; is the load capacitance, and C, is the sum of all other cepacitances at the output node. IC R, decreases by the factor. then the dominant-pole frequency increases by the same factor B. The bandwidth product is GBW = Ay fy (13.45) Since Ay is now independent of & and f,y increases by #, then the gain~ bandwidth product increases by 5 Further analysis of this circuit shows that the phase margin decreases with increasing & As a practical limit, the maximum value of B is limited to approximately 3 Test Your Understanding 19.14 Consider the CMOS curcent-gain op-amp in Figuce 13.17, Assure the bias currents lg = 100A and assume transistor parameters ky =HORA/V', 4OWAIV, and Ay = iy = 0.020". Assume the basic W/L ratio of the transistors is 20 and Kt (a) Determine she smallsigaal vohage gain, ¢b) If the effective capacilanoe at the output node & C, +, =2pF. determine the dominart-pole fre- queney and the gain-bandwidkh product. «Ans, (a) 200, (>) 477kHz, 95 MHz) 133.4 CMOS Cascode Current-Mirror OP-Amp Circuit As we have already seen, the differential-mode gain can be increased by adding cascode transistors in the output portion of the circuit, Figure 13.18 shows the same current-mirror configuration considered previcusly but with cascode transistors added to the output, Transistors Afg-My2 are the cascode transis- tors, The diiferential-mode voltage gain is given by Ag = Pita Ruiall Roz) (13.46) where Raw = knoll ioe) (13.47) and Rony = Bannaltoiata) (13.48) ‘The advantage of this circuit is the increased gaim at low frequency. The gnin— bandwidth product of this circuit is not changed from that of the simple current-mirror op-amp considered previously.Pact Il Analog Electronics Figure 13.18 CMOS cascode current-miror op-amp Test Your Understanding 15 Consider the CMOS cascode curreat-mirror opamp in Figure 13.18. Assume bas curcent and transister parameters are the same as in Exercise 13.14 Repeat parts (ab and (b) of Exercise (3.14 for this crcuit. (Ans. (ab 38.171, (6) 2.50kHRz, 95.4ME2) 13.4 BICMOS OPERATIONAL AMPLIFIER CIRCUITS As discussed in Chapter 11, BiCMOS circuits combine the advantages of bi polar and MOSFET devices in the same circuit. One advantage of MOSFETs is the very high input impedance. Therefore, when MOSFETs form the input differential pait of an op-amp, the input bias currents are exiremely small However, the equivalent noise of the input stage muy be greater than for an all-BUT op-amp. In this section, we will examine two BiCMOS op-amp circuits. The first is 3 variation of the folded cascode configuration analyzed in the last section and the second is the CA3140 BICMOS op-amp. Since we previously fully analyzed the folded cascode circuit, we will discuss, here, the advantages of using the BiCMOS technology. Many features of the CA3140 BiCMOS op-amp are similar to those of the 741. Therefore, we will not analyze this op-amp in as great a detail 4s we did the 741. Instead, we will concentrate on some of its unique features.Chapter 13 Operational Amplifier Circuits 13.4.1 BiCMOS Folded Cascode Op-Amp Figure 13.19 shows an example of 4 BiCMOS folded cascode op-amp. The cascode transistors, Q; and Qj, are now bipolar devices, replacing n-channel MOSFETS. The small-signal voltage gein expression for this iret is identical to that of the alLCMOS design. We have mentioned that the dominant-pole frequency is determined by the circuit parameters at the output node because of the very large output resistance. Nondominant-pole frequencies are then a funetion of the parameters at the other circuit nodes. In particular, one node of interest is at the drain ef an input transistor and emitter of a cascode ‘ransistor. The nondominant-pole frequency can be written as (13.49) Figure 13.19 BICMOS fcidedcascoseampliior here gua is the transconductance of the cascode transistor Q, and Cy is the efllective capacitance at this node. Since the transconductance of a bipolar is usually greater than that of a MOSFET, this 3B frequency is larger for the BICMOS circuit than for the all-CMOS design. This result means that the phase margin of the BICMOS op-armp circuit is farger than that of the ail- (CMOS op-amp.Part It Analog Electronics Test Your Understanding 18.16 Consider the BICMOS folded cascode amplifier in Figure 13.19. Assume the ‘Grcuit and MOS transistor parameters arc the same as in Example 13.10, Assume BIT paranscters of f = 120and F 4 = 80V. (a) Determine the small-signal voltage gain. (b) If lve effective capacitance at the ontpot node is 2pF determine the dominant-pole fre- ‘quency and the gain-bandwidth product. (Aus. (a) 76,343, (b) 329 Hz, 25.1 MHz) 13.4.2 CA3140 BiCMOS Circuil Description Figure 13.20 shows the basic equivalent circvit of the CA3L40 op-amp. Like the 741, this op-amp consists of three hasie stages: the input differential stage, the gain stage, and the output stage. Also shown in the figure are: the bits cireuit, which establishes the de bias currents in the op-amp: and a section referred to as a dynamic current sink, which will be explained fater. Typical supply voltages are F* = 15V and "= ~15V, Input Dift-Amp ‘The input differential pair consists of p-channel transistors Mo and Afi. and transistors Q,, and Q,2 form the active Joad for the diff-amp, A single-sided ‘output at the collector of Qys is the input signal to the following gain slage. Two offset null terminals are also shown, and will be discussed in the Bext chapter. ‘MOS teansistors are very susceptible to damage from electrostatic charge. For example, electrostatic voltage can be inadvertently induced on the gate of a MOSFET during routine handling. These voltages may be grcat enough to induce breakdown in the gate oxide, destroying the device. Therefore, input protection against electrostatic damage is provided by the Zener diodes Ds. Ds, and Ds. I the gate voltage becomes large enough, these diodes will provide a discharge path For the electrostatic charge, thus protecting the gate oxide from breakdown. ‘The de current biasing is initiated in the bias circuit. The elements labeled Dy and Dz ate diode-connected transistors. Transistor Q and dicde Dy are ‘matched, which forces the currents in the two branches of the equal. The current is determined from Q;. R.and M3. The combination of Qs and Q; makes the bias current e¢sentially independent of the power supply voltages. Goin Stage ‘The second stage consisis of Q,, connected in a common-emitter configuration ‘The cascode configuration of transistors @; and Q, provides the bias current for Q1y in addition to acting as the active load. Since Q3 and Q, are connected in a cascode configuration, the resistance looking into the collector of Q, 1s very high,‘Chaplet £3 Operational Ampliier Cieaits @ 4 ‘ | | ve 1 a Rin = 1 | Ske a ‘ a On i } i { ! im 1 ' & 30 ‘ ' na Zin 1 ' Riga : [,_ Saho 1 t 1 1 aoa 1 1 Cc i H he 1 1 wit ' t 1 1 tT 1 Tape ' ‘ \ ' Hl I t ' : ' i i Hl I ‘eeu t i \ t \ i t { ' Nesiincing ) | i ' va [| ' ' ' ' ' i ' : \ I t t ' 7 a | t Hl ' i | eo 1 \ ' \ 1 i i i ' Ofte ll | ' I L ' i | Dynamic ¥ isc) dopo sage {__sewndsings | Owmmesuee | ern ih Figure 13.20 cAsH03iC§CS op-ampaquivstenterrout Output Stage ‘The basic output stage consists of the npn transistors Q); and Qjy. During the positive portion of the output voltage cycle, Oy acts as an emitter follower, supplying a load current. During the negative portion of the output voltage cycle, Qt sinks current from the load. As the output voltage decreases, the source-to-gate voltage on the p-channel M;, MOSFET inereases, producing a larger current in Dy and R; so that the base voltage on Qjq increases. The increase B-E voltage of Qj, allows increased load current sinking. Short-cireuit protection is provided by the combination of A, and Qi. Ifa sufficiently large astws Par Il Analog Eietronies voltage is developed across Ry), Qs turns om and shunts excess base current away from Qu;. ‘An abbreviated data sheet for the CA3140 op-amp is in Table 13.2. As before, we will compare the results of our analysis {0 the values listed in the table Table 122_CASIA0 BICMOS data Parameter Minion Trpical ‘spun bias currene io ‘Opendtoop gure 20.000 100.000 Uity-gain frequency 45 13.43 CA3140 DC Analysis In this section, we will determine the de bias currents in the CAI140 op-amp. As previously stated, we will concentrate on the features that are unique t0 the CA3140 compared to the 747 ‘The basic bias circuit is shown inFigure 13.21. The current mirror con= sisting of Q; and D, ensures that the two branch currents J, and J; are equal. since Q, and D, are maiched, The p-channel MOSFET Af, is to operate in the saturation region, so that we must have Vso > Kau — [Pre 13.80) Figure 19.21 Biascireuit CA3140 8ICMOS op-amp From the figure, we see that Vso = ¥s0+ Vp (13.51)fe 13 Operational Araphiier Circuits or ¥sp = Vsa~ Ko (13.52) ‘Combining Equations (13.52) and (13.50) yields Vs — Vi» Pse —Preb (13.53) which implies that [rp] > Vp. In other words, for Mfg to remain biased in the saturation region, the magnitude of the threshold voltage must be greater than the diode voltage, From the lef branch of the bias circuit, we see that the current can be written Vsq~ Ves hale 0354) RX and from the tight branch, we have: N= Kis — rl? (1355) Since fy = é;, a simultaneous solution of Equations (12.54) and (13.55) deter- tnines the curremts and voltages in this bins circuit. ass Example 13.11 objective: Determine the curents and voltages inthe bias circu of the CA3140 opamo. ‘Consider the bias circuit in Figure 13.21, with parameters: V* = 15V, 2 =—15¥, and Ry = 8k. Assume scansittor parametsis of Fge(apn) = Fea(pnp) = 0.6 ¥ for the bipolats, and K, =0.2mA/¥? and |F rel = 14¥ for the MOSFET My Solution: Set f= Fs. Then, from Equations (13.54) and (13.55), we find hye =249V and oh omA, The voltage atthe colletor of Qe is jus FO 249 = Fae -i25¥ and the voltage at the collestor of Qr is Veg = V9 = ¥en — Vem = 19-06-06 = 13.8V Therefore, the collector-base junctions of hoth Qy und Qy are reverse biased by 13.8 -(-12.5) = 26.3, and both Qe and Q; are biased m the active zegion. Comment: The nominal bias current listed in Table 13.2 is 200A, which correlates well with our calculated value of 236A. As long as the B-C junetions of Qs and Q> romain reverse biased. the bias currents remain constant. This means that the bias ccurtent is independent of F* and V~ over a wide range of voltages, ‘The PSpice analysis, using /s = 2 x 10" A for the BITs shows that the currents in the two branches of the current source are essentially 220A. This compares very favorably with the 236A obtained by the hand analysis Transistors Q) through Q; and diode D, m Figure 13.20 are all matched, which means that Ics = Ica 200A. The current in Ds establishes the diode voltage that also biases Qj, and Qjs. The nominal value of Ieyg is 2A.Part It Analog Electronics 13.4.4 CA3140 Small-Signal Analysis We analyze the small-signal voltage gain of the CA3140 op-amp by dividing ‘the configuration into its basic cireuits and using results previously obtained Input Stege From the results in Chapter [4, the small-signal differential voltage gain can be written Aa = 2K fos oral Racal) (13.56) where Zgs is the biss current supplied by Q, and Qs. Resistance rjyy is the output resistance looking into the drain of Afjp, Ry is the effective resistaree of the active load, and Ris is the input resistance of the gain stage. Example 1312 objectiva; Calculate the small-signal dillerential voltage gam of the CA2140 op-amp input stage ‘Assume a conduction parameter value of Ky = 0.6mA/V" for Min. an npn bipolar current gaia of 8, = 200, anc a bipolar Early voltage of Vy = 50V Solution: The input resistance to the gain stage is Riz = russ Uerefore, Ra sran= = kD Aab’y _ (20040.026) Ton . Resistances fn and Rx) are normally in the hundreds of kilohms or megolim range. so the small value of Rq dominates the parallel res'stance value in the gain expression, We then have 4a [25 lostR Comment: The low inpul resistance of ihe gain stage severely loads the input staze. which ig ture results in 2 relatively low voltage gsin for the input stage VOODOO, Gain Stage ‘The magnitude of the small-signal voltage gain for the second stage is Val = aartaisll Roa ARs} 357) where Ry is the input resistance of the output stage and Ro; is the output resistance of the cascode configuration of Qs and Qu. Transistor Qrz, which is the inpat transistor of the output stage. is connected as an emitter follower. which means that Rj is typically in the megohm range. Similarly, the output resistance Rj, of the cascode configuration is typically in the megohm range: ‘The voliage gain of the second stage is then approximately V4ab = Beaters (13.58)(Chapter 13 Operational Amplifier Circuits Example 13.13 oojecttve: Calculate the small-signal voltage gain of the second stage of the CA3140 op-amnp. Assume an Early voltage of Vy = 150 for Q,5. Solution: The transconductance is ‘and the oulput resisiance is Wy _ to pt a = 0k Jon 05 The voltage gain is therefore Maal = Bo (7.08750) = 5768 ton Comment: The second stage of the CA3140 operational amplifier provides the major ity of the voltage gain ‘Overall Gain ‘Since we have taken the loading effects of each following stage into account, ‘the overall voltage gain is the product of the individual gain factors, or 4y= Aadady 13.59) where 4,3 is the voltage gain of the output stage. If we assume that Ay; & 1 for the emitter-follower output stage, then the overall gain of the CA3140 op-amp is A, = AGA yA = (12. TMSTERYL) = 73.254 3.60) Typical values of the gain of the CA3I40 op-amp are in the area of 100,000; thuss, our calculations are in reasonable agreement with this value. Frequency Response ‘The CA3140 op-amp is internally compensated by the Miller compensation technique to introduce a dominant pole, as was done in the 741 op-amp. The feedback capacitor C, is 12 pF and is connected between the collector and the base of Oy). a8 shown in Figure 13,26, From Miller’s theorem, the effective input capacitance of the second stage is C=C + dal) (3.61) ‘The low-frequency dominant pole is 1 fon = SR where R,, isthe equivalent resistance between the second-stage input node and ground. Since this resistance is dominated by the input resistance to Qj3, We rave Rag % Ra = tot (13.63) (13.62)Part Lt Analog Electronics Example 13.14 onjective: Determine the dominant.pole frequeney and unity gain bandwidth of the CA3140 op-amp. Again, we will use results from previous calculations, Solution: Previously, we determined that [A,,| = 5768; therefore, the effective input ‘capacitance is C=C +14 al) = 1201 + 5768) = 69,228 pF ‘The gain stage input resistance is Ra 6k. which means that 1 L fo0 * SRC, > TQ6 = WNHIB #10) Finally, the unity-gain bandwidth is Fr = food, = (BN T3259 > 6.4 MBE = S8Hz Comment: This unity-giin bandwidth value compares favorably with typical values of 4.5MH¢z listed in the data sheet Figure 13.22. Figure for Exercise 13.19 Test Your Understanding 13.47. Using the CA3140 op-ainp circuit and the transistor parameters given in Example 13-11, determine the minimum supply voltages that will still mainain Qy and p in the active region. Assume V* = —V™. (Ans. "= —V" = 1.86) 49.48 Consider the CA3140 op-amp bias circuit in Figure (3.21. Assume that Vey = O.6V and Ry = SKS Hf the p-channel MOSFET parameters are Xp = 0.3 mA/ VE and [Vppl = 84Y, determine J), f, and Pyg. (Ans, Mg¢ =254¥. hh = by 0.388 mA) 43.49 Assume the gain stage of the CAMA) op-amp is modified to include an emitter resistor. as shown in Figure 13.22. Let 4=0.02V"' for Mf. Assume all ‘ther transistor parameters are the same as those in Example 13,12, If the transistor bias currents in Myy and Q4> art 1003/4 and the current in Q is 200A, determine the new value of the smnal-signal differential voltage gain of the inpat stage. (Ans. 69.1) 13.5 JFET OPERATIONAL AMPLIFIER CIRCUITS “The advantage of using MOSFETs as input devices in a BICMOS op-amp is that extremely small input bias currents can be achieved. However, MOSFET {ates connected to outsice terminals of an IC must be protected against elec- {rostatic damage. Typically. this is accomplished by using back-biased diodes ‘on the input, as was shown in Figure 13.20. Unfortunately, the input op-2mp bias curients are then dominated by the leakage currents in the protection diodes, which means that the small input bias currents cannot be fully realized. JFETs as input devices also offer the advantage of low input currents, and they do not need electrostatic protection devices. Input gate currents in a JFET ureChapter 13 Operational Amplifier Cie usually well below 19, and are often on the order of LOpA. In addition, IFETS offer greatly reduced noise properties. In this section, we will examine two op-amp configurations using !FETs as input devices. Since the analysis is essentially identical to that given in the last ovo sections. we will limit ourselves to a general discussion of the circuit characteristics 13.5.1 Hybrid FET Op-Amp, LH002/42/2 Sories. Figure 13.23 is a simplified circuit diagram of an LHO02/42/52 series op-amp, which uses a pair of JFETs for the input differential pair. Note that the general layout of the circuit is essentially the same as that of the 741 op-amp. ve Figuee 13.23 Equivaientcircuit, | 0022/42/52 series hybrid JFET op-amp The input diff-amp stage consists of transistors J), J;, Qs, and Qu; J and Jz are nechannel JFETS operdting in # source-follower configuration. The differential output signal from .F, and J is the input to the common-base amplifier formed by Q) and @4, which provides a large voltage gain. Transistors Qs, Qs, aad Q; form the active load for the input stage. ‘The gain stage is composed of Qj, and Q,, connected in a Darlington pair ‘configuration. This stage also includes a 30 pF compensation capacitor. The ‘output stage consists of the complementary push-pull emitter-follower config- uration of Og and Ow. Transistors Qiq and Qzy are biased slightly “on” by diodes Qye and Qyy, 10 minimize crossover distortion. Transistors Qjs and Q2, and the associated 2722 and 22.0 resistors provide the short-circuit protection.Part Anaiog Electronics ‘An abbreviated data sheet for an LH0042C op-amp is shown in Table 13.3. Note the very large difYerential-mode input resistance and the low input bias current. ‘Table 13.3 LH0042C data Parameier Minera Typical Mexinum Units Input bas current Cry pA DDilleestial-mode input resistance 10? 2 Inpot capacitance 4 PE ‘Open-toop gain (Ry = 1kG] 25.000 300,000 vw 1 Uity-gain frequency Mi. 13.5.2 Hybrid FET Op-Amp, LF155 Series: Another example of a JFET op-amp is the LF155 BiFET op-amp. A simplified circuit diagram showing the input stage is in Figure 13.24. The input BiFET op-amp stage consists of p-channe! JFETs J, and J; biased by the bipolar transistor Qy. The active load for the input diff-amp consists of the p-channel JFETS J; and Je, for which Vos = 0. Figure 18.24 Equivalertctreuit, LFISB BIFET op-amp inpul sieges.‘Chapter 13 Operational Areplifie Circults 399 A two-sided output from the input diff-smp stage is connected toa second diff-amp stage consisting of Darlington paits Qy through Qj. The second, of gain, stage is biased by bipolar transisior Q;. The cascode configuration of Js and Q> lorm the active load for the gain stage. The circuit has. common-mode feedback loop in the bias circuit. The base of Q, is connected to the collector of Q,. If the drain voltages of 4 and J, increase, the Darlington second stage drives the base veltage of Qg higher. The current in Qy then increases, reducing she drain currents in J, and J}, since Jey is a constant current. Smaller drain currents cause the voltages at the J; and J: drains (o decrease, which then stabilizes the drain voltages. JFET Jy is connected as a current source, which establishes a reference current in Qs. Qg. and Jy. This reference current then produces the bias eur- rents in the current mirrors Qy-Q5 and Q,-Q:--Qs In this BIFET op-amp, we see the advantages of incorporating both JFET and bipolars ta the same circuit. The JFET ingut devices provide a very high input impedance, normally in the range of 10! , The current-comnected tran- sistor J, allows the reference bias current to be controlled without th: use of a resistor. Incorporating bipolar transistors in the second stage takes advantage of their higher transconductance values compared to JFETs, to produce a high second-stage gain, Test Your Understanding 48.20 Consider the LF1SS BiFET input sage in Figure 13.24. The p-chaanel JPET parameters are Ipss = 300A, Vp = 1V, and 40.01 ¥"', The supply voltages are Via SV and P= SY, Let Mpp(opol = 0.60 and Vextpnp)=0.6V. Determine he buts currents fey, fep and fe,-(ANS. Fer = fen = fey = 200A 13.6 SUMMARY 4 In this chapter, we have combined various basic circuit configurations to forma larger ‘operational amplifies citeuits. In general, an op-amp circuit consists of a difhamp imput stage, a second oF gain stage, and an output stage. The design of integrated =—10¥ Assume transistor parameters of [Vrl = L.5¥ (all transistors), QlutsCux = 20HA/V, Weep Cae = HOMALV, 2, = 0.02, and 2,=G.0LV'', Let Rye = 200k, Assume transistor widtb-to-lengi ratios of 10 for Af, and Mand 29 for all other transistors (4) Determine freer, Tq, and For. (b) Find the small-signal voltage gain of the input and second stages, and the overall voltage gain. 18,23 For the CMOS opamp in Figure 13.14, the dc biasing is designed such that Faey = dy = Joy = 200A. The transistor parameters are |¥7| = 1V (all transistors} 2, 0.008V-" 9, = OO1V, DiC = 20NA/V, ard QC = 1ORA/V, The IWansistor width-tG-length ratios are S for Mfs, Mg, and Mf; 10 for Mfy and 3; and 20 for My. Ma, and My. Determine the small-signal voltage gains of the input and second stages, and the overall voltage gai 13.24 Consider the MCI4S73 op-amp in Figure 13.14, with circuit and (ransistor parameters as given in Examples 138 end 139. If the compensation cspacitor is C\ = 12pP, determine the dominamt-pole frequency. 98Pact IL Analog Electronics 13.28 The CMOS opamp in Figure 13.14 has creuit and transistor parameters 2s siven in Problem 1322. Determine the compensation capacitor required such that the omninant-pole frequency is frp = 8Hz, 18.28 Consider the CMOS op-amp in Figure 13.14, with transistor and circuit param- eters as given in Examples 13.8 and 13.9. Determine the output resistance R, of the open-loop circuit, 13.27 A simple output stage for an NMOS op-smp is shown in Figure P13 27, Device ‘M; operates as a source follower. Assume that My and Mf are biased at Zp = O.SmA. (@) Calculate the smalhsignal open-circuit voltage gaia 4, = yo/y. (b) If the output resistance of source vy is 1DK2, determine the output resistance of this output stage "13.28 The CMOS folded cascode circuit in Figure 13.16 is biased at +5 and the teference current is fggs = 504A. The transistor parameters are Vay = 0.5, Vp = OSV, Ky= K,=O05mA/V, and 4, =2_=0015V", (a) Determine the smalbsignal differential voltage gain. (b) Find the output resistance of the circuil. 40) IF the capacitance at the ouiput node is Cz = SPF, determine the unity-gain band ‘width of the amplifier. *ROT.20 The CMOS folded cascode amplifier in Figur 13.16 isto be redesigned to provide a differential voltage gain of 10,000, The biasing is the same at dzsribed in Problem 13.28. The ansstor parameters arc Fry =05V, Vyp=—05Y. ke HAW, k= 35A/Ve, 4, = 00150", and 2, 002V-4, Assume (1/4) 22(H/1), where approptiote so that the electrical parameters of PMOS and NMOS ‘devices are nearly identical °DI3.90 The CMOS fokled cascode amplifier of Figure 13.16 i8 to be cesigned to provide a differential voltage goin of 25,000. The maximum power dissipated in the ireuit it to be limited to 3mW. Assume transistor parameters as described in Problem 1329, except the relation between NMOS and PMOS width-to-lengih ratias need not be ‘maintained, 42.31 The bias current io the CMOS current-gain op-amp in Figure 13.17 is fp = GMA. The transistor parameter: ate Vry = 0.5, Fp = -0.5V, Ky= K,=0.5A/ Wall transistors except M; and 'M,), and X,—hy= 00150" Let B=} (a) Determine the smalhsignal diferental voltage gain. (6) Find the output resistagee of the circuit. (¢) If the toial capacitance at the oucput terminal is SpE, determine the dominant-pole frequeney and the unity-gain bandwidth, ‘ RD1382 The CMOS current gain op-arup in Figure 13.17 is to be redesigned 10 provide a differential voltage gain of 400. The transistor paramters are Vry = OSV. Vr UAW", ky m= 3SWA/V, dy = 0.015 V', and A, bas current is to be Zp = SOWA. Lat B= 2.5. (a) Desig the basic amples to provide the specified voltage gain. (b) Design a current sousce lo provide the necessary bias current. (¢) Determine the usity-gain bandwidth ifthe capacitance at the ourpit ter- rminal is 3 pF. RDISS9_Redesign the CMOS cascode current mitror im Figure 13.18 to provide a iffecential voltage gain of 20,000. The bias current and transistor parameters are the same asin Problem 13.32. (a) Design the basic amplifier to provide the specitied voltage ‘gain. (6) Design a current source to provide the necessary bias current. (e) Determine the unity gain bandwidth if the capacitance at the output terminal is 3 pF.‘Chapter 13 Operational Amplifier Cisuits Section 13.4 BICMOS Operational Amplifier Circults 13.34 A BICMOS amplifier is shown in Figure PI3.4. The transistor paramesers are yp = -0.7V, ky = pA/V?, (JL) = 25, = 0.02", f= 120. and Vy = 20V. ‘The bias current is Ig = 200A. Determine the small-signal differential vollage gain, 2 % “fe 4 TE ” 2 fee gy + Figure 13.34 1013.35 Design # BICMOS amplifier that is complementary to the one in Figure PI3.34 in thatthe inpat devices are NMOS and the load transistors are pnp. Assume transistor parameters of Vzy = OSV, &, = 80WA/V!, (W/L) = 28, =: 0015V"!, B= $0, and V4 =80V. Assume the bias current is = 200A, Determine the siuallsignal differ- ential voltage gain. "43.96. The eeference current in the BICMOS folded caseode amplifier in Figure 13.19 is igge = 200A and the circuit dias voltages are 410V. The MOS transistor parame ters are the same as in Problem 13.23, The BJT parameters are f= [20 and V4 = 80V. (a) Determine the small-signal differential volge gain. (b) Find the output resistance of the circuit. (¢) If ihe capacitance at the output node is SpP, determine the unity-gain bandwidth of the ampli. *D13.37 The BiCMOS folded cascode amplifier in Figure 13.19 is to be designed to provide a differential voltage gain of 25,000. ‘The maxisuum power dissipated in the Circuit isto be limited to 10mW. Assume MOS trensistor parameters as described in Problem 13:29. The BIT parameters are 6 = 120 and Mg = 80. 4838 If the CA3140 op-amp is biased at ¥* = ISV and 7” = ~15¥. determine the input common-mode voltage range. Assume B-F voltages of 0.6V for the bipolar ‘tansistors and [zp = LAV for the MOSFETs, 19.39 Consider the bias circuit portion of the CA3I40 op-amp in Figure 13.21. if Fagr = 0.69 for Qy and Vrp = ~1AY for Af, determine the nevessary conduction parameter for My such that 2) = Jy = 300A.Pat I Acalog Electrones 13.40 Io the tias ciouit portion of the CA3140 op-amp in Figure 13.21, the bipolar twansistor parameters are Vactopn) = 06V and Ves(pap) = 0.6¥, and the MOSFET parameters are [Vrpi = J.4¥ and Kp—0.25mA/V" If the power supply voltages are Vo =~" = Vg, determine the minimum value of Vs such that the bias curcents are independent of the supply voltage, 9.41 Consider the CA3140 op-amp in Figure 13.20. If the bias currents change suck that Ics = fcc = JOD WA, determine the voltage gains ofthe input and second siages, and find the overall voltage gain 13.42 Assume the gain stage of the CA3140 op-amp is modified to include an emitter resistor, as shown in Figure 13.22, Lei 4==0.02V for Mig, If the teansistor bias currents in Afyy and Qy: are 150WA and the current in Qyy is 300uA, determine the domirani-pole frequency and unity-gain bandwidth Section 13.5 JFET Operational Amplifier Circuits 4949. Ia the LF1SS BiFET op-amp in Figure 13 24, the combinaticn of Q3, 44, and Q. establishes the reference bias current. Assume the power supply voltages are ¥"* = 10 and P= —10¥. The transistor parameters ate Fzpion) =0.6V, ¥'ge(on) = 0.6V, and Vp =4Y for Gs, Qa, ated Jy. respectively. Determine the required ing value for J, to establish a seference current of Jggp = 0.8mA. 844 Consider the cixcoit in Figure PI3-44. A TFET diff-amp input siage drives a bipolar Darlington sezord stage. The p- are connected to the bipolar active load transistors Qa and Q,. Assume IFET parameters of Fp = 3V. 1 WA, and 1 = 0.02! The bipolar transistor parameters are = 100 and 50 V. (a) Determine te input resistance Rz to the second stage. (b) Calculate the small signal differential mode voltage gain ofthe input stage. Compare this value tothe 741 and CA3H40 input stage results Figure PIa.44 DIZAS Consider the BIFET differential input stage in Figure P13.45, biased with power supply voltages W" and ¥". Let Y= —V" = Ws, (a) Design the bias circuit such that Jxer: = 100wA for supply voltages in the range 3 = Vg = 12Y. DetermineChapter 13 Operational Amplifier Circuits Figure P13.4s Vag. Ry, and the JFET parameters. () Determine the vale of Re such that foy = 500 pA when ¥* = 12V. 13.48 The BIFET diff-amp input stage in Figure P13.43 is biased at fos = LA. The JFET parameters are Vp = 4V. Joss = I mA. and 2 = 0.02V"!, The bipolar transistor parameters are 8 = 200 and V = 160. (a) For Ry = Ro = 52, determine the min\- imum load resistance R, such that a differentia-mode voltage gain af Ay = 500 is obtained in the input stage. (b) If Ry = 5002, determin the range of resistance values Ry = Ry such thal a diffetentiabmode voltage gain of 4¢ = 700 is obtained i this iaput stage ‘COMPUTER SIMULATION PROBLEMS 13.47 Consider the input stage and bias circuit of the 741 op-amp in Figure 13.5. ‘Transistor Qjy may be replaced by a constant-cusrent source equal to I9WA. Assume: the npn devices have parameters 8 = 200 and ¥,, = 1S0 V: the pnp devices have param- ters f= 50 and V, = $0V; and all transistors have f, = 10" A. (a) Using an appro- priate ae toad at the oolector of Qs, detemnine the differential gain of the input stage. (b) Determine the diferentia-mode input resistance. {c) Determine the commoa-moce input eesistance. 13.48 The output stage of the 741 op-amp is showa in Pigure 13.9. Transistor Qyy may bbe repluced with a constant-current source equal to 0.18mA. The transistor parameters ‘areas given in Prablem (3.47. (a) Plot the vollage transfer Turction vg verus #3. What is the voltage gain’) Has the crossover distortion been eliminated? (b) Apply an input voltage vis that establishes an output vollage of ¥) = 10, for example, and set Ry, = 0. Find the output short-circuit current and the transistor currents,Part Araiog Bectrarics 19.48 The bias circuit and gain sage, including the compensation capacitor, ofthe 74 ‘op-amp i shown in Figue 13.7. Tansistor 1; can be simulated by connecting two pap ‘tansistors in perallel, with relative B-E junction ereas of 025 and 0.75 compered to all other pnp transistors. (a) Determine the low-frequency voltage gin. (0) Plot the magni- tude of the voltage gain versus frequency. Compare the 3B frequency tothe dotinant- pole frequency found in Example 13.7. 19.80 Consider the BICMOS input stage of the CA3t40 op-amp in Figure 13.20 Transistor Qs can be replaced with a coaslant-current source of 200A. Assume: b- polar transistor parameters of 8 = 200, frp = 10" A, and Vz = 50; and MOSFET parameters of A, = 0.6mA/V", [Fp|=1¥, and k = 0.01 V"'. Using an appropriate ac load atthe collector of Qi, determine the differential gain ofthe input stage. Compare the computer analysis results with those in Example 13.12. 1881 Consider the CMOS op-amp in Figure 13.14. Assume the ciceuit and transistor parameters areas given ia Example 13.8, In addition, let = 0.01 V~ for alt wansistors. {a) Determine the overall low-frequency differential voltage gain. Compare these results ‘with those in Example 13.9. ¢b) TE the compensation capacitor is C, = 12pF. plot the magnitude of the voltage gain versus frequency. What is the 34B frequency’) DESIGN PROBLEMS (Note: Each design should be correlated with a computer analysis} "012,52. Redesign the bias circuit of the 741 op-arep such that a current fey = 2SHA is established when #* = ~V~ = 5Y. Limit the power dissipated inthe input stage and ‘the bias cirewit to 2.SmW. "19.53. Consider the bipolar op-amp circuit in Figure P13.53. Design the circuit such that the differential gain és at least 800, and the ouput voltage is zero when the input veensy(Chapter 13 Operational Amplifier Citeuis voltages are zero. The transistor current gains are 120 for all (ramsisiors, and the base emitter voltages are 0.6, where appropriate, *D13.54 Redesign the CMOS op-cmmp in Figure 13.14 to provide a minimum overall voltage gain of at least 50,000. The bias voltages ate ¥* = 10V and V~ = -10V, The threshold voltage is [M71 = 1 for all transistors, and 2 = 0.01V~ for all transistors. Design reasonable width-to-length ratios and bias curcents. “D13.55 Consider the CMOS op-amp in Figure 13.14, Design 4 complementary ‘CMOS circuit in which each element is replaced by its complement. The bias voltages are 25. The threshold voltage is [¥’p| = 0.7 for all ransistors, and 4 w 0.01V" for all transistors, Design reasonable width-tc-length ratios snd bias currents to provide a minimum overall voltage gain of at least 20,0001 Nonideal Effects in Operational Amplifier Circuits 14,0 PREVIEW ‘Chapter § introduced the ideal operational amplifier and covered a few of its many applications. In the previous chapter, we analyzed actual operational amplifier circuits, including the classic 741 op-amp. From those discussions, ‘we can identify sources of nonideal properties in actual op-amps. Although nonideal effects could have been introduced in Chapter 9, that discussion would have been less meaningful since the source of any nonideal effect would not have been completely understood at that time. In particular, the reason for a very low dominant-pole frequency in the basic amplifier would have been a mystery. Therefore, the discussion of nonideal effects in op-amp circuits has been postponed until aow. This chapter opens by discussing and defining several practical op-amp parameters that will be further analyzed as to the effect they have on the nonideal characteristics of op-amp circuits. We have seen how matched transistor characteristics are utilized in the design of diff-amp circuils. However, slight mismatches may occur. One part of this chapier is devoted to determining the effect of these slight transistor mis- matched characteristics on the op-amp properties. ‘A general goal of this chapter is for the reader to understand the source of nonideal effects in op-amps and to be able to minimize their effects in the design of op-amp circuits, 14.1 PRACTICAL OP-AMP PARAMETERS In ideal op-amps, we assume, for example, that the cifferential voltage gain is infinite, the input resistance is infinite, and the output resistance is zero. In practical op-amp circuits, these ideal parameter values are not realized. In this section, we define some of the practical op-amp parameters that will be con- sidered in detail throughout the chapter. We will discuss and analzye the effect of these nonideal parameters in op-amp circuits.an Par IL Analog Etetronics 14.1.1 Practical Op-Amp Parameter Definitions. Input voltage limits. Two input voltage limitations mus: be considered—a dc input voltage limit and a ¢ifferential signal input voltage. All transistors in the input diff-amp stage must be properly biased, so there is a mit in the range ‘of common-mode input voltage that can be applied and still msintain the proper transistor biasing. The maaimum differential input signal voltage that can be applied and still maintain linear cireait operation is limited primarily by the maximum allowed output signal voltage. Output voltage limits, The output voltage of the op-amp can never exceed the limits of the dc supply voltages. In practice, the difference between the bias voltage and output voltage must be greater than 1 to 4V, depending on the design of the output stage. Otherwise, the output voltage saturates and is no fonger a function of input voltage. ‘Output current limitation. The maximum current out of or into the op-amp. is determined by the current ratings of the output transistors. Practical op-amp circuits cannot source or sink an infinite amount of current. Finite open-loop vohage gain, The open-loop gain of the ideal op-amp is assumed to ke infinite. In practice, the open-loop gain of any op-amp circuit is always finite. This nonideal parameter value will affect circuit performance Input resisiance. The input resistance R, is the small-signal resistance between the inverting and noninverting terminals when a differential voltage is applied. Ideally, this parameter is infinite, but, especially for BIT circuits, this parameter is finite, ‘Output resistance. The output resistance is the Thevenia equivalent smell- signal resistance looking back into the output terminal of the op-amp measured with respect to ground. The ideal output resistance is zero, which means there is no loading effect at the output, In practice, this value is not zero. Fintte bendwidth, In the ideal op-amp, the bandwidth is infinite. In prac- tical op-amps, the bandwidth is finite because of capacitances within the op- amp circuit, Stew rate. The slew rate is defined as the mazimum rate of change in output voltage per unit of time. The maximum rate at which the output voltage ccan change is also a function of capacitances within the op-amp circuit. Input offset voltage, In an ideal op-amp, the output voltage is zero for zero differential input signal voltage. However, mismatches between input devices, for example, may create an output voltage with zero input. The input offset voltage is the applied differential input voltage required to induce a zero output voltage, Input bas currents. Sn an ideal op-amp, the input current to the op-amp circuit is assumed to be zero. However, in practical op-amps, especially with BJT input devices, the input bias currents are not zero. The cause of these nonideal op-amp parameters will be discussed in the following sections, as well as the eftect these nonideal parameters have on op- amp circuit performance. A few other nonideal parameters will be considered in the last section of the chapter.Chapter 4 Nooideab Etets in Operational Amplifier Circuits m3 Table 14.1 Nenideat parameter values fr throw.cp-amp circuits TE ‘cali LHC Te Ma Cat Tye Max Ge Ty Mn inp off volage oS vO Average input oe! vokage dit wee 0 wre Input oni current 30 MMA spa pA Average ipa fst current dit Os MAC Input bas curent, oA pot Skew cate oT Nye 9 Nis 3 Mis CMR % o # oo ae Table 14.1 lists a few of the nonideal parameter values for three of the op- amps considered in the previous chapter. We will refer to this table as we discuss each of the ncaideal parameters. 141.2 Input and Output Voltage Limitations For linear circuit operation, all BJTS in an op-amp circuit must be biased in the forward-active region and al! MOSFETs must be biased in the saturation region. For these reasons, there arc limitations to the range of input and output voltages in op-amp circuits. Figure 14.1(a) shows the simple all-BJT op-amp circuit discussed at the beginning of Chapter 13 and Figure 14.1(b) shows the all-CMOS folded cas- code op-amp circuit discussed in the last chapter. We will use these two circuits to discuss the input and output voltage limitations, Input Voltage Limitations ‘Assume that in the BIT circuit of Figure 14.1(2) we apply a common-mode input voltage such that vig = 7) = ¥. AS Yow increases, the base-collector voltages of Q, and Q, decrease, since the collector voltages are fixed at two base-emitter voltage drops below V'*. If we assume the minimum base-collector voltage is zero so that the transistor is stll biased in the active mode, then the maximum value Of gy iS Yom(tnax) = P* — 2¥-¢9(on). ‘AS Yon Gecreases, the collector-emitier voliage of Q; decreases. If we again assume the minimum base-collectot voltage is zero. or the minimum colleetor— ‘emitter voltage is Vae(on), then, taking into account the base-emitter voltage of the input transistors, the minimum value Of Yip iS vg(min) = P+ 2¥'ge(0n), So the maximum range of vim, 's within approximately 1.4 V of each bias vollage ‘The same range of common-mode input voltage can be found for the all- MOSFET diff-amp in Figure 14.1(b). {n this case, all MOSFETs must be biased in the saturation region. We can again define the common-mode input voltage a5 vag = 11 = Ya. NOW, 28 Yen increases, Msp of Myy decreases, The minimums value of Vsp is Vspr (sat) = Vsou1 + Vreu. The maximum value Of Me iS then Yyy(max) = ¥* ~ [ser + (Vso + Vrew)} The gate-to-source voltages can be determined from the transistor parameters and curcemts. AS Yow decreases, the source-to-drain voltage of the input transistors decreases. Assuming that My and Af, are matched to My, then the drain-to- source voltage of these transistors is equal to Vgs15. The minimum common-mm Part II Analog Electronics Mp Mo ag | o Figure 14.10) Sige antipctar apap cre b) at CMOS ded cascade p-mpChapter 14 Nonideal Effects in Operational Armpliir Circuits mode input voltage is then voq(min) = V~ + (Vegi) +(¥sqi + Vrei) ~ Veal: The Veco terms cancel, 50 voq(min) = V" + [Nasa + Vr} Output Voltage Limitations As the output voltage of the BJT cireuit in Figure 14.1(a) increases or decreases, he collector-emitter voltages of the output transistors change. Again, assuming the minimum base-collector voltage is zero for a BJT biased in the forward active region, then the maximum output voltage is _vo(max) = ¥* —[Vep(on) + Vgri1(on)]). The minimum output voltage is similarly found 10 be volmin) = V” + [¥asu(on) + ¥e5,2(0n)). For the all-CMOS circuit in Figure 14.1(b), the maximum output voltage is voimax) = ¥* - (scx + Vrie) + Pscio). The minimum output voltage is volmin) G86 — Fre) + Koss Test Your Understanding 14.4 Using the circuit and transistor parameters of Example 13.10, and assuming. threshold voltages of Vy = 0.5 and Vy» = ~0.5V, determine the maximum range of ‘common-mode input voitage for the allCMOS folded cascove circuit of Figare 14.10). 14,2 Using the same circuit and transistor parameters as in Exercise (4.1, caleulate the maximum range of output vollage for the all-CMOS folded cascode citcut of Figure 14.10 14.2. FINITE OPEN-LOOP GAIN In the ideal op-amp, the open-loop gain is infinite, the input differential resis- {ance is infinite, and the output resistance is zero. None of these conditions exists in actual operational amplifiers. In the lasi chapter, we determined that the open-loop gain and input differential resistance may be large but finite, and the output resistance may be small but nonzeto. In this section, we will deter- mine the effect of a finite opetrloop gain and input resistance on both the inverting and noninverting amplifier characteristics, We will then calculate the output resistance. Sn this section. we limit our discussion of the finits open-loop gain to fow frequency. [n the next section, we consider the effect of finite gain as well as the frequency response of the amplifier. 14.2.1 Inverting Amplifier Closed-Loop Gain ‘The equivalent circuit of the inverting amplifier with a finite open-loop gain is shown in Figure 14.2. If the openloop input resistance is assumed to be infi- nite, then iy = i, or =v. 4.12)WE Anslog Blesronies Figure 14.2 Equivalact chcut, Inverting ampltier wir fiite open-oop gain or Hi ay! & +z) 72, (14.106) Rx Ry Re} Re Since v; = 0, the output voltage is Yo = —Aoim (142) where Ao, is the low-frequency open-loop gain. Solving for v, from Equation (14.2) and substituting the result into Equation (14.1(b)), we find uu (\{)1\_% R--A)G+e)-z ad The closed-loop voltage gain is then «4ay Example 14.1 Objective: Determine the minimum opea-loop voltage gain to achieve a particular accuracy. ‘A presture transducer prodwoss a maxinsum d: voltage signal of 2mV and has an ‘ouput resilarce of Rs = 2k2. The maximum de curreat from the transducer is to be limited to 0.2nA. An inverting amplifier isto be used in conjunction with the transducer to produce an oviput voltage of ~0.10V for a 2mV transducer signal. The error in the ‘output voltage cannot be greater than 0.1 percent. Determine the minimum open-loop gain of the amplifier to meet this specification. Solullon: We must frst determine the resistor values to be used in the inverting ampli- fier. The source resistor is in series with Ry, $0 let Ri=R+Rs ‘The minimum input resistance is found from the maximum input curreat as ie % 2x10? ‘Ritesin) Fray aaa Ox a= tee(Chapter 14 Nonidea! Effe:ts m Operational Amphiier Circuits The resistor R, then needs to be 8kS2. The closed-loop voltage gain requited is =0.10 ahr Ix 3 Aa “The required value of the feedback sesistor is then Ry = S00KA. For the voltage gain to be within 0.1 percent, the mirimum gain (magnitude) is 49.95, Using Equation (14.4), we can determine the minimum value of the open-top gain, We have 95-7 -_—— 14 Gt Fo Aen= whieh yields Ay {min Comment: If the open-loop gaim is grealer than the value of Apg(anin) = 50.949, then (he error in the voltage gain willbe less an 0.1 percent, In the limit as gy —> 00, the closed-loop gain is equal to the ideal value, designated Acz(o0), which for the inverting amplifier is Ag (oo) = = (148) as previously determined. Equation (14.4) is then Aeicod Ae aes) 048) An To determine the variation in closed-loop gain with changes in open-loop tain, we take the derivative of Ac, with respect to Agz. We find Hace, Aei{00Kl = deuce, an din, (Aor +1 = Accel} which ean be rearranged in the form 1 = dextoo) dae, _ dAge Aor. 4 hoe sees ae) 14 (ee Aor Normally, Acy(00)! € [4oc| ard Equation (148) is approximately dey « tAvs I= Ace) tas) dew Aor Aan Equation (14.9) relates the percent change in the closed-loop gain of the inverting amplifier as the result of a change in open-loop gain. Opea-loop gain variations occur when individual ansistor parameters change from one cireuit to another or with temperature. From Equation (14.9), we see that changes in closed-loop gain become smaller as the open-ioop gain becomes larger.Part I Analog Bleotronics Test Your Understanding 44,8. Consider an inverting amplifier in which the op-amp open-loop gain is doy = 5x 10" and the ideal closed-loop amplifier gain is Acz(00) = ~50. (a) Determine the factual closed-loop gain. {b) If the open-loop grin decreases by 10 peroent, find the percent change in closed-loop gain and detetmine the actual closed-loop gsin. (Ans. (a) Acz = ~49.949 (b) 0.0102%, Ace = -49.943) 444 In an inwerting amplifier, the resistors are R; = SOOkQ and R, = 20kQ. Ir the closed-loop gain must be within 0.1 percent of the ideal value, determine the minimum required open-loop op-amp gain. (Ams. 4g, = 25,974) 14.2.2 Noninverting Amplifier Closed-Loop Gain Figure 14.3 shows the equivalent circuit of the noninverting amplifier with a finite open-loop gain. Again, the open-loop input differential resistance is assumed to be infinite, The analysis proseeds in much the same way as in the previous section. We have jy = i, and (14.10{@) 24.100) Figure 14.3. Equvelant circu, noninverting ampltier with finite oper-bop gain The output voltage is Yo = doth — dant Since vy =», voltage can be written % ney age 4.12)(Chapter 14 Nonideal Effects in Opecaticnal Amplifier Cicuits Combining Equations (14.12) and (14.10(b)) and rearranging terms, we have an expression for the closed-loop voltage gain 6 i+ & A= 2 =e 414.13) iy (: + ) dat R In the limit as doy + 00, the ideal closed-loop gain is R Aciloo) = 1+ R (14.14) and Equation (44,13) becomes _ dele) 4c = 7 dae) (14.15) +a Ave ‘Taking the derivative of the closed-loop gain with respect to the open-loop gain and rea/ranging terms, we obtain ox Hos (Aa) Sa 14.1 en Aon Abu es, Equation (14.16) yields the ftactional change in the closed-loop gain of the noninverting amplifier as a result of a change in the open-loop gain. The result, for the noninverting amplifier is very similar to that for the inverting amplifier, ‘Test Your Understanding 44.5. An operational amplifier connected in a noninverting configuration has an opemloop gain of Ag, = 10°. The resistors are A; =495k2 and Ry =SkR. {@) Determine the actual and ideal closed-loop gains (bj If the opencoop gain decreases by 10 percent, determine the percent change in closed-loop gnin and the actusl closed: loop gain. (Ars. (a) dcx = 99.90, Acy(o0} = 100 (b) 0.01%, Act = 99:69) 44.6 A noninverting amplifier has an op-amp with an open-loop guin of Aoy = 10". ‘The closed-loop gain must be within 0.1 percent of the ‘deal valve. Determine the ‘maximum closed-loop gain that will still meet the specificaion. (Ans. dey = 120) 14.23 Inverting Amplifier Closed-loop Input Resistance “The closed-loop input resistance Ry of the inverting amplifier is defined in Figure 14.4(a), and it includes the effect of feedback. The equivalent circt including a finite open-loop gain Agr, finite open-loop input differential resis- tance R;, and nonzero output resistance R,, is shown in Figure 14.4(b). A KCL equation at the output node yields vg, ¥o~ (ALY), Ye oy ee Ry RR Rr ° (14.17)Part IE Analog Electronics o oy Figuee 14.4. (@) Invering ariiier and (b) inverting ampiier equivalent cixcut, for Ccaloulating closedtoop aout resisance Solving for the output voltage, we have (1418) 14.19) (14.20) Equation (14.20) describes the closed-loop input resistance of the inverting amplifier, with a finite open-loop gnin, finite open-loop input resistance, ard nonzero output resistance. In the limit as Agg + 00, we see that 1/Ry — 0, ‘or Ry +6, which means that», > 0, or vis at virtual ground. This is a characteristic of an ideal inverting op-amp. Example 14.2 Objective: Determine the closed-loop input resistance at the inverting terminal of an inverting amplifier. ‘Consider an inverting amplifier with a feedback resistor R; = 10K®, and an op- ‘amp with parameters doz = 10° and R; = 10k. Assume the output resisiance R, of ‘the op-anmp is negligible ‘Solution: If 2, = 0, then Equation (14.20) becomes Ld Dede 1 14108 Ry RY Re =o + 10 420 “The closed-loop input resistance is then Ry # 0.1 2.‘Chapter 14 Novideat Effects in Operational Ampiiie: Circuits Comment: The closedloop input texistance of the inverting ampiiie is a very strong furction of the finite opentoop gain. Equation (14.21% shows that the opensfoop input resistance R, essentially does not affect the closed-loop input resistance. A nonzero closed-loop input resistance Ry in conjunction with a finite ‘opentoop input resistance R, implies that the signal current into the op-armp is not zero, as assumed in the ideal case. From Figure 14.4(b), we see that meARy 4.22) Therefore, ni, (Re grh &) (14.23) ‘The fraction of input signal current shunted away from R) and into the op-amp is (Ry/Ri). ‘Test Your Understanding 14.7 Determine the closed-loop input resistance st the inverting terminal of an fnverting amplifier if Ag, = 16", Rp = R= Ry = T0KQ, and if, (a) Ro=0, and (b) R= 10K. (Ans. (8) Ry = 1 2b) Ry = 3.2) 44.8 Consider the equivalent cirot in Figure 14 4(b). If R, = 10482, determine the percentage of input signal current j shunted from Rp for: 4a) Ry =012, and (©) y= 10S. (Ans. (a) 107% (0) 0.1%) 14.2.4 Noninverting Amplifier Closed-Loop Input Resistance A noninverting amplifier is shown in Figure 14.5(a). The input resistance seen by the signal source is designated Ry. The equivalent circuit, including a finite Figure 145 (2) Noviwering ero ane) neninvening anger equaon cou, fr taledatng conedtogp input reoancePart II Analog Electronics open-loop gain 4oz, finite open-loop input differential resistance R, and nor- zero output resistance R,, is shown in Figure 14.5(t). Writing a KCL equation at the output node vields ¥ , Yo> dots , 0— mM et tee (a2) Solving for the output voltage, we have 1, dows (3425) AKCL eatin ai the v, node yields = Yo a= if pee iz (14.26) ‘Combining Equations (14.25) and (14.26) and rearranging terms, we obtain oeeR) Gera) a) a) a (14.27) From Figure 14.5(b), we see that ne = AR; (14.28) and ea, (14.29) Substituting Equations (14.28) and (14.29) into (14.27) we obtain an equation in jy and y; so that the input resistance Ry can be found as Ry = efi In order to simplify the algebra, we neglect the effect of Rj. which is normally small. Setting R,, = 0 reduces Equation (14.27) to LL). Soave fonts 14.30) a nla, Ri) 439) Substituting Equations (14.28) and (14.29) into (14.30), we find that the input resistance can be written in the form RAL ond 4 (1 2) & R Equation (14.31) describes the closed-loop input resistance of ihe nonin- verting amplifier with a finite open-loop gain and a finite open-loop input resistance. In the limit as Agr — 00, or as the open-loop input resistance ‘approaches infinity, we see that Ry -> oc, which is a property of the ideal Rys (14.31) iy ue(Chapter 14 Nonides! Etfees in Operational Amplifier Cireuits Example 14.3 Otjectve: Determine the closed-loop input resistance at the non- inverting terminal of a noninverting emplifer. ‘Consider an op-amp with an open-loop gain of 4p, = 10° and an input resistance of R, = IKE in a nonitverting emplifier configuration vith resisioe values of R= y= 10k2. ‘Solution: From Equation (34.31), the inpat resistance is RU tage R(14B) so 410) + 10( 1+ R= Ri —____\_ 10 = 1 (1432) 15 or Ry 35x 1AQ = 500M Comment. As expected. the closed-loop input resistance of the noninverling amplifier is very large. Equation (16.32) shows that the input resistance is dominated by the terra Rl-+ Ap). The combination of a large R, and large Ao,. produces an extremeiy large input resistance. as predicted by ideal feedback theory. Test Your Understanding 14.9 Fora nosinverting amplifier, the resistances are R= 99k and Ry = TKS. The op-amp properties are: doz = 16, Ry = 40k and Ky = 0, Determine the closed- loop input reiscance. (Ans. Ry = 4.04 MQ) 14.40 Find the closed-loop input resistance of a voltage follower with op-amp characteristics Age =5 ¥ 10°. R, = 1OKS2, and R, = 0, (Ans. Ry = S000M2) 1425 Nonzero Output Resistance Since the ideal op-amp has @ zero output resistance, the ouiput voltage is independent of the load impedance. ‘The op-amp acts as an ideal voltage source and there is no loading effect. An actual op-amp circuit has a nonzero output resistance, which means that the output voltage, and therefore the closed-loop gain. is a function of the load impedance. Figure 14.6 is the equivalent circuit of both an inverting and noninverting amplifier and is sed to find the output resistance The op-amp has a finite open-loop gain Ap, a nonzero output resistance &,, and an infinite inpac resistance R,, To determine the output resistance, we set the independent input voltages equal to zero, A KCL equation at the output node yields Yor fonta , _% R *R+R Ee)Par It Analog Blecronies Figure 14.8 Equivalert crcul fer calcuiating closedt-loop output resistance The differential input voltage is ry = —v,, where R na (qeag) aes ‘Combining Equations (14.34) and (14.33), we have Ry No [+e 4) tate (14.35(9)) or bot Aon 1 Ry altaetalae Ase Since R, is normally small and doz is normally large, Equation (14.386), 10 a good approximation, is as fotows: set f do Ry LTH RR, Jn most op-amp circuits, the open-loop output resistance R, is on the order of 10022 Since Ao, is normatiy much larger than (1 + Ry/R,), the closedsloen output resistance can be very small. Output resistance values in the milliohm range are easily attained. 6) Example 14.4 objective: Determine the output resistance of an op-amp circu Computer Simulation Solutfon: Figure 14.7 shows an inverting amplifier circuit with a standard 741 op-amp. One method of determining the output resistance is to measure the output voltage for two different values of load resistance connected to the outpat ‘Then, treating the araplifer as a Theverin equivalent circuit with a fixed source in series ‘with ap output resistance, the output resistance can be determined. A 1 mV signal was applied. For a 1082 load, the output voltage is 0.999837 mV, and for a 208 load, tae ‘ovlput voltage is 0:9996132 mV. This gives an output resistance of 1 53m9. Comment, As mentioned, the ouput resistance of ¢ voltage amplifier with negative feedback can be very small. The ideal output resistance is zero, but a practical op-amp (1 +(R/Ry)k therefore, the low-frequency closed-loop gain is R Acta = t+ z (1442) as previously determined. For 4g > Acio, Equation (14.44) 1s approximately (1443) (444) Sine in most cases 4 2 Aczo, the bandwidth of the closed-loop system is substantially larger than the open-loop dominant-pole frequency zp. Note also that Equation (14.44) applies to the inverting, as well as the noninverting, amplifier in which Ac; is the magnitude of the closed-loop gain, We have scea this same bandwidth extension for negative feedback several times previously. 143.2 Gain-Bandwidth Product We can also determine the unity-gain bandwidth of the closed-loop system From Equation (14.43), we can write ie (144s) Sanivs | Vt Liesida/tezal where fixing &s the unity-gain frequency of the closed-loop system. Wf Acyo > b. then Equation (14.45) yields [Ae P= fomin Foxy TE Aeuw (t4.46¢a)y nl) which reduces to Ao Janus = AV salen 22 = fede =r 14.46(b)) Act The unity-gain frequency or bandwidth of the closed-loop system is essentially the same as thal of the open-loop amplifier. ‘The opemloop and closed-loop frequency response curves are shown in Figure 14.10. We observed these same results in Chapter 12 in the discussion on ideal feedback theory.Part Ml Analog Electronics uM Ao} Aaop——s— Tio am Figure 14:10 ode plot, open-loop anc dosedtoop gain magnitude Example 14.5 objective: Determine the unity-pain bandwidth and the maximum closed-loop gain for a specified closed-loop bandw Sth. ‘An audio amplifier system & to use an op-amp with an open-loop gain of Ap = 2 x 10° anda dominant-pole feequency of § Hz. The bandwidth of the audio system isto ‘be 20KHz. Determine the maximum closed-loop gain for the audio araplifir. Solution: The unity-gain bandwidth 1 found as Se =Sepdo = (SK2 x10") = 10 Ha IME Since the gain-bandwidth product is constant, we have Sosa Ace fr where .¢p is the closed-loop bandwidth and A¢r is the closed-loop gain. The maximum closedsloop gain is then fr __ 10h Ace F aw =? Comment: If the closed-loap gain is less than oF equal to 50, then the required band- ‘width of 20kH2 for the andio amplifier willbe realized. Test Your Understanding 44.42 An opamp with open-loop parameters of dion = 10" and fp = S04 is ‘connected in a noninverting amplifier configuration with a low-frequency closed-loop gain of Ayo = 25. Ifan inpot voltage of v, = $0sin(2/9 pV is applied, determine the ‘output vollage peak amplituce for: (a) f = 2kHz, (b)f = 20KHz, and (@) f = LOOKHE. (Ans (a) 125m¥ (b) O.884 mV (6) 0.245 019) 14.3.3 Slew Rate Implicit in the frequency response analysis for the closed-loop amplifier is the assumption that the sinusoidal input signals are small. If a large sinusoidal signal or step function is applied to an op-amp circuit, the input stage can be ‘overdriven and the small-signal mode! will no longer apply.Chapter [4 Nenideal Erfzcts im Operational Amplifier Cireuits Figure 14.L1 shows simplified op-amp circuit. If a large step voltage (greater than 120m¥) is applied at rp with v, held at ground potential, then Q; is effectively cut off, which means fc; #0 and ic) = Ip. The entire bias current is switched 10 Q). Since ica % icy. then icy * Io; since Qx-Qy form a current mirror, then we dlso have ics = fy Figure 14.11 Simplited op-amp for calouiating slew rata The base current into Qy is very small; therefore, the current through the compensation capacitor C) 18 fg = fog = Io. Since the voltage gain of the emitter-follower output stage is essentially unity, the capacitor current can ‘be written as ote van 4 w Hash, fo “The gain of the second stage is large, which means that vq & ¥o. Equation (14.47) then becomes dee eee 48) or to _ le (14.49) at The maximum current through the compensation capacitor is limited to the bias current Jo; consequently, the maximum fate at which the output voltage can change is also limited by the bias current Zo. The maximum rate of change of the output voltage is the slew rate of the op-amp. the units of which are usually given as volts per microsecond. From Equation (14.4%, we have Stew rate (SR) = (&) “2 (14s) as GL Although the rate of change in output voltage can be either positive or nega- live, the slew rate is defined as a positive quantity.art TL Analog Electronics Figure 14.12 shows the slew-rate limited response of en op-amp vollaze follower to 2 rectangular input voltage pulse. Note the trapezoidal shaped output response. The time needed to reach the full-scale response is approxi- mately Yotmax)/SR. ° Tie Figure 14.32 Slewrate-imted response of votage follower to rectangular inpul vellage pulse Example 18.6 objecive: Calculate the slew rate of the 741 op-armp. From the previous chapier. the bias current in the 741 op-amp is fg = 194A and he internal frequency compensation capacitor is Cy = 39, Solution; From Equation (14.50), the slew rate is 0.53 « Int V/s 2.63 V8 Comment: The parvial data sheet in Table 14.1 for the 741 opamp lists the typicat slew rate as 0.7 V's, which is in clase agreement with cur caleuiaied valu. “Typical slew-rate valves for the CA3140 BiCMOS and LH9082C BIFET ‘op-amps are also given in Table 14.1. The BICMOS circuit has a typical slew rate of 9 Vjis, and the BiFET opamp has a typical value of 3V/s. The slew rates are larger in the FET op-amps because the bias currents are larger than in the 741 circuit and the gain of the FET input stage is smaller than that of the 741 input stage ‘The slew rate is dircetly related to the unity-gtin bandwidth. To explain, the unity-gain bandwidth is directly proportional (o the dominant-pole fre- quency, oF fr & fap. In turn, the.dominant-pole frequency is inversely propor- tional to R,,C). where Ry, is the equivalent resistance at the node of the second stage input and C, is the compensation capacitance. The equivalent resistance R, is & function of the second stage input resistance and the diff-amp stage output resistance, both of which ate inversely proportional to fg. Then, 4st) where Io/C, is the slew rate, Equation (14.51) shows that the slew rate is directly proportional to the unity-gain bandwidth.(Chapter {4 Nonideal Effects ip Operatioual Arplifer Circuits Now consider what happens when a sinosoidal input signal is applied, for example, to the noninverting amplifier shown in Figure 14.9. If v; = V,sinaot, then vot = Hof 1482) sino = Vp, siner 1452 d= V1 im where Vp, i€ the ideal peak value of the sinusoidal output voltage. The rate at which the ovlput voltage changes is 00 ay, cost 1483) dr Therefore. the maximum rate of change is oVyy. Figure (4.13 shows 1wo Sinusoidal waveforms of the same frequency but different peak amplitudes, The maximum rate of change, or slope. occurs as the curves cross the zero axis, The waveform with the larger peak value has a larger maximum slope. Curve a in Figure 14.13 has a maximum slope corresponding to the slew rate; curve b, with a smaller peak value, has a maximum slope tess than the slew rate I the maximum slope, oq, is greater than the slew rate SR, then the op-amp is skewerate-limited and the output sigral is distorted, ott Figure14.13 Two sinusvidal wavalonne of ine same frequency with alerent peak ‘olkagss, showing diferent maximum slopes, ‘Thus, the manimum frequency at which the op-amp can operate without being slew-rate-limited is a function of both the frequency and peak amplitude of the signal. We have that gn Me (14.54(a)) or SR inv, 4.540), [As the output voltage peak amplitude increases, the maximum frequency at which slew-rate-fimiting occurs decreases. The futl-pawer bandwidth (FPBW) is the frequency a: which the op-amp output becomes slew-rate-limited. The FPBW is the fia frequency from Equation (14.54(b)), or SR FPBW= ae (14.85) The fullkpower bandwidth can be considerably less than the smalbsignal bandwidth. a9Part tI Analog Electronics Example 14.7 onjectve: Determine the small-sigral bandwicth of an amplifier ‘and the fullpower bandwidth that wili produce an undistorted output voltage. Consider an amplifier with a unity-gain bandwidth of fy = I MHz and a low. frequency closed-loop gain af Aca = 10, Assume che opamp siew rate is SR = 1V/ys and the desired pesk ourput veltage is ¥,, = 1OY. Solution: The small-signal closed-loop bandwidth is, from Equation (14.44), Fee The full power bandividth, based on slew-rate limitation, from Equations (14 S4MbM snd (14.59), is SR _ (V/s 10" ws/s) ieee 778 2n( 10) = 1S9tHe Comment: The fuil-power bandwidth, or the actual maximum fteqiency at which the system can be operated and sill produce a large, undistorted output signal. is consier- ‘ably smaller than the bandwidth under small-signal nonslew-rate-limiting conditions, Test Your Understanding 43 A.1¥ input sep function is applied toa noninverting umpliier witha closed- loop gain of § The slew race of the opamp is 2 ¥)ps. Determine the ume needed for the ‘output voltage to reich its fullscale response. (Ans. 2.513) 14.44 Foca 74l op-amp with a slew rate 9.63 Vins find the fullpower bandwidth fot a peak undistorted output voltage of: (a) IV. and (b) 10V, (Ans. (a) 10D kHz (bh) TokHz) 14.45 An op-amp with a low-frequency open-loop gain af Ag; = 10" and a domi- nant-pole Frequency of frp = KHz is used in a ooninverting amplifier configuration with a lowefrequency closed-loop gain of Accy = 50, The slew rate of the op-amp ts: O8Vjus, Determine the maximum andistorted output voltage amplitude such that fax = foray. (AMS. 6.37) 14.4 OFFSET VOLTAGE In Chapter 11, we analyzed the basic difference amplifier, which is the input stage of the op-amp. In that analysis. we assumed the input differential-pair transistors to be identical. or matched. If the «wo input devices are mismatched, the currentsin the two branches of the diff-amp are unequal and this affects the diftamp de output voltage. In fact. the internal circuitry of the entire op-amp usually contains imbalances and asymmetries, all of which can cause a nonzero output voltage for a zero input differential voltage. The output de offset voltage is the measured open-loop output voltage when the input voltage 1s zero, This configuration is shown in Figure 14.14 “The inpat de offset voltage is defined as the input differential voltage that must be applied to the open-loop op-amp (o produce a zero output voltage. This‘Chapier [4 Nonideat Esfects in Operational Amplifier Cievits ot Figure 4.14 Circuit Figure ta.1s Circuit for or measuring ouput measuiing ingul ovat let volage vollage configuration is shown in Figure 14.15. The input offset voltage is the param- exer most often specified and is usually referred to simply as the offset voltage Offset voltage values have a statistical distribution among op-amips of the same type, and the offset voltage polarity may vary from one op-amp te another. The offset voltage specification for an ep-amp is the magnitude of the maximum offset voltage for a particular type of op-amp, The offset voltage is a de value, generally in the range of 1-2mV for bipolar op-amps, stthough some op-amps may have offset voltages in the range of -J0mV. Further, the maximum offset voltage specification for a precision op-amp may be as low as 1Owy. In this section we will analyze offset voltage effects in the input diff-amp stage and will then consider varicus techniques usec! (o compensate for offset voltage 14.4.1 Input Stage Offset Voltage Effects Several possible mismatches-in the input diff-amp stage can produce offset, voltages. We will analyze offset voltage effects in two bipolar input stages and in a MOSFET input iff-amp circuit. Gasic Bipolar Diff-Amp Stage ‘A basic bipolar diff-amp is shown in Figure 14.16. The differential pair is biased with a constant-current source. If Q, and Q; are matched, then for 1 =; =0, Ip splils evenly between the two transistors and icy = icq. If a two-sided output is defined as the difference in voltage between the two col lector terminals, then % = 0 when the transistors are matched and the collec- (or resistors are matched, which means that the offset voltage is zero The collector curtents can be written as fe = tye! (14.56(@)) (14.56(b)) where [51 and Jy, are related to the reverse-saturation currents in the B-E junctions and are functions of the electrical and geometric transistor proper- ties. If the two transistors are exactly matched, then Jey = dso; if there is any mismatch in the electrical or geometric parameters, then Isy # /52-84 Pert Ml Analog Elecronic: 18 Basic bipolar diference ampitiet The input offset voltage is defined as the input differential voltage required to produce a zero output voltage, or in this case to produce icy =écr. Figure: 14.17 shows the ic versus ype characteristics of two unmatched transistors. Slightly different B-E voltages must be applied to produce equal collecior currents that will result in a zero output voltage in the diff-amp. fe Figure 14.17° The i vermus vec characteris for two unmaiched bipolar ransisors For icy = cz. we have IgyePt0 = Lege YF 487) or ier 2 (1458) sy ‘We define the offset voltage as Yee) — Yan: = Vos Since »,~ 9 vaei — Yaen then the offset voltage Vos is the differential input voltage that must be applied to produce ic; = fcr(Chapter 14 Nonideal Effects in Opersional Amplifier Cxcute Equation (14.58) can then be written as ante a As (14.59(8)) or Fos = Vr n( 2) (14.59(0)) Ast Example 14.8 ovjective: Calculate the offiet voltage in a bipolar diff-amp for a given mismatch between the input transistors, ‘Consider the diff-amp in Figure 14.16 with transistor parameters fs, = 10“ A and Tog = 1.05 210A, Solution: From Equation (14 59(6}), the offset voltage is - aren} = 0,00127V se 1.27 mV ¥os= Fria Ts Comment: A S percent difference in fs for Q, and for Q produces an offset voltage of 1.27 mY. Since the offset voltage is defined as a positive quantity, if in the previous example #5) were 5 percent larger than Isp, the offset voltage would also be 1.27 mv. {1 should be cautioned that the offset voltage in this example is one com- ponent of the offset voltage for the entire op-amp. For example, if the two collector resistors are not equal, then the two-sided output voltage vp will not be zero even if the two transistors are identical. Nevertheless, the calculation provides information on one source of offset voltage, as well as the resulting magnitude of Vos, Test Your Understanding 44.46 Consider the bipolar diff-amp in Figure 14.16 with transistor parameters "A and Isp = 1.85 x 10" A, Calculate the offset voltage. (Ans, 203m¥) Bipolar Active Load Ditt-Amp Stage Figure 14.18 shows a bipolar diff-amp with a simple two-transistor active load As before. this input stage is biased with a constant-current source. If Q and @z are matched and if Q, and Q, are matched, then fg splits evenly between Qy and Qy for v) =v, and the E-C voltages of Qy and Q, are equal. The one- sided de output voltage vo will therefore be one E~B voltage below V7. I, however, Q, and Q, are not exactly matched, then ic; atid icy may not bbe equal since the active load infuuences the split in the bias current, even if Q, and Q; are matched. This effect is caused by a finite Early voltage. Taking thePart U Analog Bectronics Figure 14.18 Basic bipctar ditamp with acive toed Early voltages into account, but neglecting base currents, we can write the collector currents a5 rate™"9(1 +2) Var 2 tert +) ing =i (14.60(2)) and fa ica=olere")(14 7222) Van 2 Iggfetnl Yece Isale' ( + 2) (14.60(b)), If we assume that Q, and Q; are matched, then fo, = is =/s and Vay = Van Vay. Assume that Q, and Q, are slightly mismatched, so that f53 # foq bUL still assume that V43 = Vas = Vap. For ¥; = v9, WE BAVE Vet = YeRD also, p93 = test = Yecs = Yes. Taking the ratio of Equations (14.60(a)) ard (14.60(6)) produces Yet 14s a 1g (4s) Van Equation (1461) can be rearranged in the form ees 14 fs Y (14.62) Tou 1 4 ES ‘ar‘Chapter 14 NonidealEffecis ir Operational Amplifier Cecits on Since Qy is connecied as a diode, veg) is a constant for a given bias current and supply veltage, which means that the ieft side of Equation (14.62) is a constant. If Zs = Fsa, then vere = veer and Yeci = Vea = becy. However, if Jeu # Isa then the collector-emitter voltages on Qz and Qy must change, IM, (or example, 453 > Isa, then sce is larger than rca. If, on the other hand, Ugg > Isp, then Vgca is smaller than ¥ce;, and Q, may be driven into satur by the mismatch. Example 14.9 obfectve: Celculate the change in output voltage for a given mix match in the active load transistors, Consider the dffamp in Figure 14.18 with V* = 10. Ascume that Q, and Q, are matched with sei = vari = 0.6, and assume that Yegi = vans = ¥ecs = 0.6V. Let Jgy = LOSTsg, Also assume that Vay = Fp = SOV. Solution: Since veg) = 0.6V res then for vy = ¥y = 0. veer eV = 10 ‘The left side of Equation (14.62) is therefore rete 0 = 8 «1.186 Tes = 08 7, ty We have that Yece + ¥en = V* + ¥en = WEY 10.6 — Yc vee Equation (14.62) then becomes 14 106= 200 rigs 2195)? Sy which yields Comment A 5 percent difference between the properties of Qs and Qy produces a change from 0.6 10 1.94 V in the E-C voltage of Oy. Computer Simulation Verification: A PSpice analysis of the offset voltage effects in the active load diff-amp was performed. The two input terminsls areat ground potential. Using Js = 5x 10" A for ail transistors, the PSpice analysis shows that Yen = O.654V rather than the assumed valve of O.6V. Also, vaca is L19¥ tat than equal to veg). This oveurs because the circuit is slightly unbalanced: that it fy includes the base currents of Qs and Qy, and icy does not. When Q; and Qy are not matched and fs) = 1 0S/sy = 525 x 10° A, then vzca increases to 2.51 ¥, compared to 19NV from the hand analysis. I, however, fqy = O.95/zq = 4.75 x 107A, then Oy ‘8086 into saturation.Part I Aaatog Electronics An offset voltage that will slightly change ic and icp will allow the EC voltage of Q, to be adjusted back to its original value. As shown in actual op-amp circuits, resistors are usually included in the ‘emitters of the active load transistors, By producing a slight imbalance in the two resistor values, we can change the ratio of ic) {0 icp, causing a change in the output voltage. This is discussed in the next section when offset voltage null adjustment is discussed. Test Your Understanding A7 Consider the active loud bipolar diff-amp stage in Figure 14.18. Assume the circuit and tronsistor parameters are as given in Example 14.9. Using Equations (14.60(a)) and (14.60(5)}, determine the offset voltage Fos = Ivar ~ Yael such that een (Ans. 1.27 mV) MOSFET Ditf-Amp Stage Figure 14.19 shows a basic MOSFET diff-amp in which the differential pair is biased with a constant-current source. If My and Mf; are matched, then for v= 2 = 0 dy splits evenly between the two transietors and ip, = ipp. Since a two-sided output is the voltage difference between the two drain terminals, then for this symmetrical situation, vo = 0 and the offset voltage is zero. Figure 14.39 Basic MOSFET dt-amp The drain currents can be written as toy = Kloss ~ Venu)? (14.6340) and Ketos: — Vaw2? (14.63(6)) io‘Chapser 14 Nonideal Effects im Operational Amplifier Circuits As previously stated, the conduction parameters yy and K,p are functions of the clectrical and geometric properties of the two transistors, and the thresh old vollages Vy, and Fy» are also functions of the transistor electrical prop- erties, Iftheve isa mismatch in electrical or geometric parameters, then we may have Ku # Kp and ray # Vrw2. ‘As with the bipotar diff-amp, the input offset voltage is defined as the input differential voltage that must be applied to produce a zero output voltage, or Vos (1444) ‘When the offset voltage is applied, ip: = tna = Zo) tors are equal, then vp = 0. Solving Equations (14.63(a)) and (14.63(b)) for ves and Y¢5) and substituting the results into Equation (14.64), we find (14.65) ‘The various difference and average quantities are defined as follows: AK, = Kai — Kaa (14.66(a)) - Sette (14.6600)) OV yy = Von — Vawe (14.67%(a)) and Yew Fou +h (asi) Combining Equations (14.66(a)) and (14.66(b)), we have Ky = Ket af (14.68(a)) and Ka=K, oe (14.6800)) Similarly, Vivi = Vay + OH (14.690)) and Fo = Viv a (04.690)) Noting that ip) =p =/g/2 and substituting Equations (14.68(a)) through (14.69(b)) into Equation (14,65), we obtain 1 Ol estan RAT; 14.70) Slee resem) ** ™ ae FosPart tI Analog Eocteonics If we assume that AK, <& XK, then Equation (14.70) reduces to 1 fig (aK, Ves=-} se (Ge) + 4h any Equation (14.71) is the offset voltage in @ MOSFET diff-amp as a function of the differences in conduction pazameters and threshold voltages. Example 14,10 objective: Calculate the offset voltage in a MOSFET dif stage for @ given mismatch between inpot transistors, ‘Consider the diffamp in Figure 14.19 with transistor parameters Ky = 105 wA/V Ke, = WOOWALY!, and Mra = Ving. Assume fy = 200 pA, Solutton: From Equation (14.56(a). the difference in conduction parameters i AK, = Ky ~ Kyy = 105-~ 100= 5pA/¥? From Equation (14 66(b)), the average of the conduction parameters is oq Kan + Kg _ 105 +100 ar) ‘The magnituce of the offset voltage is. Grom Equation (14.71), [to (aXe) 1 [32m (5 ne) 2102.5) A Comment: A 5 percent ifference in conduction parameter values between the inpul (MOS transistors produces an offset voltage af 24.L mV. Ky, = 1.suayv? Wosl = = 00241 V = 24.1. mV Test Your Understanding 44.48 Assume the MOSFET diff-amp shown in Figure 1.19 is biased with a cur- rent = 150pA. Let Fy51 = Pry. Assumme the nominal conduction parameter valee is K, = 50WA/V", Deiermice the maximum variation AX, such that the offset voltage is limited 10 Vos = 20mV. |Ans. AK, = L63RA/¥?) ‘Compating the results of Examples 14.8 and 14.10 shows that typically the ‘offset voltage for a MOSFET diff-amp is substantially larger than that of @ bipolar diffamp. The difference can be explained by comparing Equation (14,71) for the MOSFET diff-amp and Equation (14.59(b)) for the bipelar Jiff-amp. The offset voltage for the MOSFET diff-amp is directly proportional to the percent change in conduction parameter values, whereas the offset volt- age for the bipolar diff-amp is proportional to the logarithm of the percent change in the /s current parameters. In addition, the offset voltage for the MOSFET pair is proportional to VT@IKa = Vos Vrs which is typically in the range of 1-2 V. In contrast, the offsei voliage for the ar pair is proportional to ¥, = 26mV