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II Mid Examination Answer All The Questions: Quality Analysis of Question Paper

This document contains the details of a mid-term exam for the second year EEE branch students. It has 3 questions worth a total of 30 marks. Question 1 (10 marks) asks students to implement and design Boolean functions A, B, C, and D using PAL. Question 2 has two parts - part a (3 marks) asks students to construct a JK flip flop using a D flip flop and multiplexer, and part b (7 marks) asks students to draw the schematic of an RS master slave flip flop and provide its truth table. Question 3 also has two parts - part a (3 marks) asks about capabilities and limitations of finite state machines, and part b (7 marks)

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114 views

II Mid Examination Answer All The Questions: Quality Analysis of Question Paper

This document contains the details of a mid-term exam for the second year EEE branch students. It has 3 questions worth a total of 30 marks. Question 1 (10 marks) asks students to implement and design Boolean functions A, B, C, and D using PAL. Question 2 has two parts - part a (3 marks) asks students to construct a JK flip flop using a D flip flop and multiplexer, and part b (7 marks) asks students to draw the schematic of an RS master slave flip flop and provide its truth table. Question 3 also has two parts - part a (3 marks) asks about capabilities and limitations of finite state machines, and part b (7 marks)

Uploaded by

srinu247
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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II B.

Tech II Sem
Date: 12/04/16

1
.

Academic Year: 2015-2016


II Mid Examination
Max.Marks: 30
Branch: EEE
Sub: STLD
Time: 90 Mins.
Answer All the Questions
Implement and Design the following Boolean functions using PAL
[10M][BT L6] [C2222.4]
A(x,y,z) = (1, 2, 4, 6)
B(x,y,z) = (0, 1, 6, 7)
C(x,y,z) = (2,6)
D(x,y,z) = (1, 2, 3, 5, 7)

2
.

a. Construct a JK flip flop using a D flip flop, a 2x1 multiplexer and an inverter. [3M][BT L3] [C2222.5]
b. Draw the schematic circuit of RS master slave flip flop. Give its truth table and justify
the entries in the truth table.
[7M][BT L3] [C2222.5]

3
.

a. Write capabilities and limitations of Finite- State machine

[3M][BT L2] [C2222.6]

b. For the given Moore model machine obtain Mealy reduced state - table and hence draw the state diagram
[7M][BT L3] [C2222.6]

Quality Analysis of Question Paper


Course

STLD

Question
No
1
2.a
2.b
3.a
3.b
Total

L1

L2

L3 L4

L5

L6
1

1
1
1
1

1
3

Remarks by
Subject Expert

Signature of
Faculty

HOD

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