APPENDIX B

INSTRUCTION SET SUMMARY

This appendix contains two tables: the first identifies all of the 8051 's instructions in
alphabetical order; the second table lists the instructions according to theirhexadecimal opcodes and lists the assembly language instructions that produced that
opcode.
.
The alphabetical listing also includes documentation of the bit pattern, flags
affected, number of machine cycles per execution and a description of the instructions operation and function. The list below defines the conventions used to identify
operation and bit patterns.
Abbreviations and Notations Used

A
AB
B
bit address
page address
relative offset
C
code address
data
data address
DPTR
PC
Rr
SP
high
low
i-j
.n
aaa aaaaaaaa
bbbbbbbb
dddddddd

""'"'

mmmmmmmm
00000000

r orrrr
AND
NOT
OR
XOR

(X)

X))

<>
<
>

Accumulator
Register Pair
Multiplication Register
8051 bit address
11-bit code address within 2K page
S-bit 2' s complement offset
Carry Flag
Absolute code address
Immediate data
On-chip 8-bit RAM address
Data pointer
Program Counter
Register (r=0-7)
Stack pointer
High order byte
Low order byte
Bits i through j
Bit n
Absolute page address encoded in instruction and operand byte
Bit address encoded in operand byte
Immediate data encoded in operand byte
One byte of a 16-bit address encoded in operand byte
Data address encoded in operand byte
Relative offset encoded in operand byte
Register identifier encoded in operand byte
Logical AND
Logical complement
Logical OR
Logical exclusive OR
Plus
Minus
Divide
Multiply
The contents of X
The memory location addressed by (Xl (The contents of X)
Is equal to
Is not equal to
Is less than
Is greater than
Is replaced by

B-1

Instr\1ction Set Summary

MeS-51

Table B-1. Instruction Set Summary

Mnemonic
Operation

B-2

Cycles

Binary
Code

Flags
P OV AC C

Function

ACALL code addr

(PC) <- (PC) + 2
(SP) <- (SP) + 1
SP <- (PC) low
(SP) <- (SP) + 1
SP <- (PC) high
(PC) 0-10 <- page address

aaa10001
aaaaaaaa

ADD A,ldata
(A) <- (A) + data

00100100
dddddddd

P OV AC C Add immediate
data to A

ADD A,@Rr
(A) <- (A) + Rr

0010011r

P OV AC C Add contents of
indirect address to
A

ADD A,Rr
(A) <- (A) + (Rr)

00101rrr

P OV AC C Add register to A

ADD A,data addr

(A) <- (A) + (data address)

00100101
mmmmmmmm

P OV AC C Add contents of
data address to A

ADDC A,ldata
(A) <- (A) + (C) + data

00110100
dddddddd

P OV AC C Add Cand
immediate data to
A

ADDC A,@Rr
(A) <- (A) + (C) + Rr

0011011r

P OV AC C Add C and contents

of indirect address
to A

ADDC A,Rr
(A) <- (A) + (C) + (Rr)

00111rrr

P OV AC C Add C and reg ister

toA

ADDC A,data addr

(A) <- (A) + (C) + (data address)

00110101
mmmmmmmm

P OV AC C Add C and contents

of data address to
A

AJMP codeaddr
(PC) 0-10 <- code address

aaaOOO01
aaaaaaaa

ANL A,ldata
(A) <- (A) AND data

01010100
dddddddd

Logical AND
immediate data to
A

ANL A,@Rr
(A) <- (A) AND Rr

0101011r

Logical AND
contents of indirect
address to A

ANL A,Rr
(A) <- (A) AND (Rr)

01011rrr

Logical AND
register to A

ANL A,data addr

(A) <- (A) AND (data address)

01010101
mmmmmmmm

Logical AND
contents of data
address to A

ANL C,bitaddr
(C) <- (C) AND (bit address)

10000010
bbbbbbbb

C Logical AND bit to

C

ANL C,lbitaddr
(C) - (C) AND NOT (bit address)

10110000
bbbbbbbb

C Logical AND
complement of bit
toC

ANL data addr,ldata

(data address) <(data address) AN D data

01010011
mmmmmmmm
dddddddd

Logical AND
immediate data to
contents of data
address

ANL dataaddr,A
(data address) <(data address) AN D A

01010010
mmmmmmmm

Logical AND A to
contents of data
address

Push PC on stack,
and replace low
order 11 bits with
low order 11 bits of
code address.

Replace low order

11 bits of PC with
low order 11 bits
code address

Instruction Set Summary

MCS-Sl

Table B-1. Instruction Set Summary (Cont'd.)

Mnemonic
Operation

Cycles

Binary
Code

Flags
P OV AC C

Function

C If immediate data
and contents of
indirect address
are not equal, jump
to code address

CJNE @Ar,ldata,codeaddr
(PC) - (PC) + 3
IF Ar)) < >data
THEN
(PC) - (PC) + relative offset
IF Ar)) <data
THEN(C)-l
ELSE(C)-O

CJNE A,ldata,codeaddr
(PC) - (PC) + 3
IF (A) < >data
THEN
(PC) - (PC) + relative offset
IF (A) <data
THEN (C)-l
ELSE(C)-O

CJNE A,dataaddr,codeaddr
(PC) - (PC) + 3
IF (A) < > (data address)
THEN
(PC) - (PC) + relative offset
IF (A) < (data address)
THEN(C)-l
ELSE(C)-O

CJNE Ar,lIdata,codeaddr
(PC) - (PC) + 3
IF (Ar) < >data
THEN
(PC) - (PC) + relative offset
IF (Ar) <data
THEN(C)-l
ELSE(C)-O

CLR A

11100100

11000011

CLR bitaddr
(bit address) - 0

11000010
bbbbbbbb

CPL A

11110100

10110011

10110010
bbbbbbbb

11010100

DEC @Ar
Ar))- Ar)) -1

00010111

DEC A

00010100

DEC Ar
(Ar) - (Ar) -1

00011rrr

Decrement register

DEC data addr

(data address) (data address) - 1

00010101
mmmmmmmm

Decrement
contents of data
address

DIV AB
(AB) - (A) I (B)

10000100

1011011r
dddddddd
00000000

C If immediate data
and Aare not
equal, jump to code
address

10110100
dddddddd
00000000

10110101
mmmmmmmm

C If contents of data
address and A are
not equal, jump to
code address

00000000

10111rrr
dddddddd

C If immediate data
and register are not
equal, jump to code
address

00000000

Set A to zero (0)

(A)-O
CLR C

C Set C to zero (0)

(C)-O
Set bit to zero (0)
Complements each
bit in A

(A)-NOT(A)
CPL C

C Complement C

(C)-NOT(C)
CPL bltaddr
(bIt address) -

Complement bit

NOT (bit address)

DA A

C Adjust A aiter a
BCD add

(See description in Chapter 3)

Decrement
contents of indirect
address
P

Decrement A

(A)-(A)-l

OV

C Divide A by B
(multiplication
register)

B-3

Instruction Set Summary

MeS-51

Table B-1. Instruction Set Summary (Cont'd.)

Mnemonic
Operation

Cycles

Binary
Code

Flags
P OV AC C

DJNZ Ar,codeaddr
(PC) - (PC) + 2
(Ar) - (Rr)1
IF (Rr) < >0
THEN
(PC) - (PC) + relative offset

1 1011rrr

DJNZ data addr ,code addr

(PC) - (PC) + 3
(data address) (data address) - 1
IF (data address) = 0
THEN
(PC) - (PC) + relative offset

INC @Rr
Rr - Rr + 1

0000011r

INC A

000-00100

INC DPTR
(DPTR) - (DPTR) + 1

10100011

Increment 16-bit
data pointer

INC Rr

00001rrr

Increment register

INC data addr

(data address) (data address) + 1

00000101
mmmmmmmm

Increment contents
of data address

JB bit addr,code addr

(PC) - (PC) + 3
IF (bit address) = 1
THEN
(PC) - (PC) + relative offset

00100000
bbbbbbbb

If bit is one, n jump

to code address

J BC bit addr ,code addr

(PC) - (PC) + 3
IF (bit address) = 1
THEN
(PC) - (PC) + relative offset
(bit address) - 0

JC codeaddr
(PC) - (PC) + 2
IF (C) = 1
THEN
(PC) - (PC) + relative offset

JMP @A+DPTR
(PC) - (A)

01110011

Add A to data
pOinter and jump to
that code address

IN B bit addr ,code addr

(PC) - (PC) + 3
IF (bit address) = 0
THEN
(PC) - (PC) + relative offset

00110000
bbbbbbbb

If bit is zero, n jump

to code address

JNC codeaddr
(PC) + (PC) + 2
IF(C)=O
THEN
(PC) - (PC) + relative offset

JNZ codeaddr
(PC) - (PC) + 2
IF(A) < >0
THEN
(PC) - (PC) + relative offset

Function
Decrement
register, if not zero
(0), then jump to
code address

00000000

11010101
mmmmmmmm

Decrement data
address, if zero (0),
then jump to code
address

00000000

Increment contents
of indirect address
P

Increment A

(A) -(A) +1

R) - (Rr)

8-4

+1

00000000

00010000
bbbbbbbb
00000000

01000000
00000000

+ (DPTR)

If bit is one, n clear

bit and jump to
code address

If C is one, then
jump to code
address

00000000

01010000
00000000

01110000
00000000

If C is zero (0), n
jump to code
address

If A is not zero (0), n

jump to code
address

Instruction Set Summary

MCS-Sl

Table B-1. Instruction Set Summary (Cont'd.)

Cycles

Binary
Code

JZ codeaddr
(PC) - (PC) + 2
IF(A)=O
THEN
(PC) - (PC) + relative offset

01100000

LCALL code addr

(PC) - (PC) + 3
(SP) - (SP) + 1
SP)) - PC)) low
(SP) - (SP) + 1
SP)) - (PC) high
(PC) - code address

00010010
I I I I I I I It
I I I I I I I It

Push PC on stack
and replace entire
PC value with code
address

LJMP codeaddr
(PC) - code address

00000010
I I I I I I I It
I I I I I I I It

Jumpto code
address

MOV @Rr,#data
Rr)) -data

0111011r
dddddddd

Move immediate
data to indirect
address

MOV @Rr,A
Rr))-(A)

1111011r

Move A to indirect
address

MOV @Rr,dataaddr
Rr)) - (data address)

1010011r
mmmmmmmm

Move contents of
data address to
indirect address

MOV A,#data
(A) -data

01110100
dddddddd

Move immediate
data to A

MOV A,@Rr
(A)-Rr))

1110011r

Move contents of
indirect address to
A

MOV A,Rr
(A)-(Rr)

11101rrr

Move register to A

MOV A,data addr

(A) - (data address)

11100101
mmmmmmmm

Move contents of
data add ress to A

MOV C,bit addr

(C) - (bit address)

10100010
bbbbbbbb

MOV DPTR,#data
(DPTR) - data

10010000
d d d d d d d dt
d d d d d d d dt

Move two bytes of

immediate data
pOinter

MOV Rr,#data
(Rr)-data

01111rrr
dddddddd

Move immediate
data to register

MOV Rr,A
(Rr)-(A)

1 1 1 1 1 r r r

Move A to register

MOV Rr,dataaddr
(Rr) - (data address)

10 1 01 r r r
mmmmmmmm

Move contents of
data address to
register

MOV bitaddr,C
(bftaddress) - (C)

10010010
bbbbbbbb

Move Cto bit

MOV data addr ,#data

(data address) -data

01110101
mmmmmmmm
dddddddd

Move immediate
data to data
address

MOV data addr,@Rr

(data address) - Rr))

1000011r
mmmmmmmm

Move contents of
indirect address to
data address

MOV dataaddr,A
(data address) - (A)

11110101
mmmmmmmm

Move A to data
address

Mnemonic
Operation

Flags
P OV AC C

Function

If A is zero (0), then

jump to code
address

00000000

Move bit toC

The high order byte of the 16-bit operand is in the first byte following the opcode. The low order byte is
in the second byte following the opcode.

B-S

MeS-51

Instruction Set Summary

Table B-1. Instruction Set Summary (Cont'd.)

Mnemonic
Operation

Binary
Code

Flags
P OV AC C

Function

MOV data addr, Ar

(data address) - (Ar)

10001rrr
mmmmmmmm

Move register to
data address

MOV data addr1 ,data addr2

(data address 1) (data address2)

100D0101
mmmmmmmm*
mmmmmmmm*

Move contents of
second data
address to first
data address

MOVC A,@A+DPTR
(A) - A) + (DPTR

10010011

Add A to DPTR and

move contents of
that code address
with A

MOVC A,@A+PC
(A) - A) + (PC

10000011

Add A to PC and
move contents of
that code address
with A

MOVX @DPTR,A
DPTR)) - (A)

11110000

Move A to external
data location
addressed by
DPTR

MOVX @Rr,A
Rr)) - (A)

1111001r

Move A to external
data location
addressed by
register

MOVX A,@DPTR
(A) - DPTR

11100000

Move contents of
external data location addressed by
DPTR to A

MOVX A,@Ar
(A) - Rr))

1110001r

Move contents of
external data loca"
tion addressed by
register to A

MUL AB
(AB) - (A) '(B)

10100100

NOP

00000000

ORL A,ldata
(A) - (A) OR data

01000100
dddddddd

Logical OR
immediate data to
A

ORL A,@Ar
(A) - (A) OR Rr))

0100011r

Logical OR
contents of indirect
address to A

ORL A,Rr
(A) - (A) OR (Ar)

01001rrr

Logical OR register
toA
\

ORL A,data addr

(A) - (A) OR (data address)

01000101
mmmmmmmm

Logical OR
contents of data
address to A

ORL C,bit addr

(C) -(C) OR (bit address)

01110010
bbbbbbbb

C Logical OR bit to C

ORL C,lbitaddr
(C) -(C) OR NOT (bit address)

10100000
bbbbbbbb

C Logical OR
complement of bit
toC

ORL da.ta addr ,#data

(data address) (data addreSs) OR data

01000011
mmmmmmmm
dddddddd

Logical OR
immediate data to
data address

ORL dataaddr ,A
(data address) (data address) OR A

01000010
mmmmmmmm

Logical OR A to
data address

B-6

Cycles

P OV

C Multiply A by B
(multiplication
register)
Do nothing

The source data address (second data address) is encoded In the first byte following the opcode. The
destination data address is encoded in the second byte following the opcode.

\,

Instruction Set Summary

MeS-51

Table B-1. Instruction Set Summary (Cont'd.)

Mnemonic
Operation

Cycles

Binary
Code

Flags
P OV AC C

Function

POP data addr

(data address) - SP))
(SP) - (SP) -1

11010000
mmmmmmmm

Place top of stack

at data address and
decrement SP

PUSH data addr

(SP) - (SP) + 1
SP)) - (data address)

11000000
mmmmmmmm

Increment SP and
place contents of
data address at top
of stack

RET

00100010

Return from
subroutine call

00110010

Return from
interrupt routine

00100011

Rotate A left one

position

00110011

00000011

00010011

11010011

SETS bit addr

(bit address) - 1

11010010
bbbbbbbb

Set bit to one (1)

SJMP codeaddr
(PC) .... (PC) + relative offset

10000000

Jumptocode
address

SUSS A,lkiata
(A)"" (A) - (C) -data

10010100
dddddddd

P OV AC C Subtract immediate
data from A

SUSS A,@Ar
(A) - (A) - (C) - Ar))

1001011r

P OV AC C Subtract contents
of indirect address
from A

SUSS A,Ar
(A) - (A) - (C) - (Ar)

10011rrr

P OV AC C Subtract register
from A

SUSS A,data addr

(A) - (A) - (C) - (data address)

10010101
mmmmmmmm

P OV AC C Subtract contents
of data address
from A

SWAP A
(See description in Chapter 3)

11000100

XCH A,@Ar
temp - Ar))
Ar))-(A)
(A)-temp

1100011r

Move A to indirect
address and vice
versa

XCH A,Ar
temp -(Ar)
(Rr)-(A)
(A)-temp

11001rrr

Move A to register
and vice versa

XCH A,data addr

temp - (data address)
(data address) - (A)
(A) .... temp

11000101
mmmmmmmm

Move A to data
address and vice
versa

(PC) high - SP))

(SP) - (SP) -1
(PC) low - SP))
(SP) - (SP) - 1
RETI
(PC) high - SP))
(SP) - (SP) -1
(PC) low - SP))
(SP) .... (SP) -1
RL A
(See description in Chapter 3)
RLC A

(See description in Chapter 3)

RR A

Rotate A right one

position

(See description in Chapter 3)

RRC A

(See description in Chapter 3)

-SETS C
(C)-l

C Rotate A through C
left one position

C Rotate A through C
right one position
C SetC to one (1)

00000000

Exchange low
order nibble with
high order nibble in
A

B-7

MeS-51

Instruction Set Summary

Table B-1. Instruction Set Summary (Cont'd.)

Mnemonic
Operation

B-8

Cycles

Binary
Code

Flags
P OV AC C

XCHD A,@Rr
temp - Rr)) 0-3
Rr)) 0-3 - (A) 0-3
(A) 0-3 - temp

1 1 01011r

Move low order of

A to low order
nibble of indirect
address and vice
versa

XRL A,lIdata
(A) - (A) XOR data

01100100
dddddddd

Logical exclusive
OR immediate data
toA

XRL A,@Rr
(A) - (A) XOR Rr))

0110011r

Logical exclusive
OR contents of
indirect address to
A

XRL A,Rr
(A) - (A) XOR (Rr)

01101rrr

Logical exclusive
OR register to A

XRL A,data addr

(A) - (A) XOR (data address)

01100101
mmmmmmmm

Logical exclusive
OR contents of data
address to A

XRL data addr ,lIdata

(data address) (data address) XOR data

01100011
mmmmmmmm
dddddddd

Logical exclusive
OR immediate data
to data address

XRL data addr,A

(data address)(data address) XOR A

01100010
mmmmmmmm

Logical exclusive
OR A to data
address

Function

Instruction Set Summary

MeS-51

Table B-2. Instruction Opcodes in Hexadecimal

Hex
Code

00
01
02
03
04
05
06
07
08
09
OA
OB
OC
00
OE
OF
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
10

1E
1F
20
21
22
23
24
25
26
27
28
29

2A
2B
2C
20
2E
2F
30
31
32
33
34
35
36
37
38

39
3A
38

Number
of Bytes

1
2
3
1
1
2
1
1
1
1
1
1
1
1
1
1
3
2
3
1
1
2
1
1
1
1
1
1
1
1
1
1
3
2
1
1
2
2
1
1
1
1
1
1
1
1
1
1

3
2
1
1
2
2
1

1
1
1
1
1

Mnemonic

NOP
AJMP
LJMP
RR
INC
INC
INC
INC
INC
INC
INC
INC
INC
INC
INC
INC
JBC
ACALL
LCALL
RRC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
JB
AJMP
RET
RL
ADD
ADD
ADD
ADD
ADD
ADD
ADD
ADD
ADD
ADD
ADD
ADD
JNB
ACALL
RETI
RLC
ADDC
ADDC
ADDC
AD DC
ADDC
ADDC
ADDC
ADDC

Operands

codeaddr
codeaddr

A
A
dataaddr

@RO
@R1
RO
R1
R2
R3
R4
R5
R6
R7
bit addr ,code addr
codeaddr
codeaddr

A
A
dataaddr

@RO
@R1
RO
R1
R2
R3
R4
R5
R6
R7
bit addr ,code addr
codeaddr

A
A,#data
A,dataaddr

A,@RO
A,@R1
A,RO
A,R1
A,R2
A,R3
A,R4
A,R5
A,R6
A,R7
bit addr ,code addr
codeaddr

A
A,ldata
A,dataaddr

A,@RO
A,@R1
A,RO
A,R1
A,R2
A,R3

B-9

MeS-51

Instruction Set Summary

Table B-2. Instruction Opcodes in Hexadecimal (Cont'd.)
Hex
Code

3C
3D
3E
3F
40
41
42
43
44
45
46
47
48
49
4A
48
4C
40
4E
4F
50
51
52
53
54
55
56
57
58

59
5A
58
5C
50
5E
5F
60
61
62
63
64
65
66
67
68
69
6A
68
6C
60
6E
6F
70
71

72
73
74
75
76
77

B-I0

Number
of Bytes

1
1
1
1
2
2
2
3
2
2

1
1
1
1
1
1
1
1
1
1
2
2
2
3
2
2
1
1
1
1
1
1
1
1
1
1
2
2
2
3
2
2

1
1
1
1
1
1

1
1
1

1
2
2
2
1

2
3
2
2

Operands

Mnemonic

ADDC
ADDC
ADDC
ADDC
.,IC
AJMP
ORL
ORL
ORL
ORL
ORL
ORL
ORL
ORL
ORL
ORL
ORL
ORL
ORL
ORL
JNC
ACALL
ANL
ANL
ANL
ANL
ANL
ANL
ANL
ANL
ANL
ANL
ANL
ANL
ANL
ANL
JZ
AJMP
XRL
XRL
XRL
XRL
XRL
XRL
XRL
XRL
XRL
XRL
XRL
XRL
XRL
XRL
JNZ
ACALL
ORL
JMP
MOV
MOV
MOV
MOV

A,R4
A,R5
A,R7
A,R7
codeaddr
codeaddr
data addr, A
data addr,#data
A,tldata
A,dataaddr

A,@RO
A,@R1
A,RO
A,R1
A,R2
A,R3
A,R4
A,R5
A,R6
A,R7
codeaddr
codeaddr
data addr, A
data addr,tldata
A,lIdata
A,dataaddr

A,@RO
A,@R1
A,RO
A,R1
A,R2
A,R3
A,R4
A,R5
A,R6
A,R7
codeaddr
codeaddr
dataaddr,A
data addr,lIdata
A,lIdata
A,dataaddr

A,@RO
A,@R1
A,RO
A,R1
A,R2
A,R3
A,R4
A,R5
A,R6
A,R7
codeaddr
codeaddr
C,bitaddr

@A+DPTR
A,#da ta
data addr ,lIdata
@RO,lIdata
@R1,#data

Instruction Set Summary

MeS-51

Table B-2. Instruction Opcodes in Hexadecimal (Cont'd.)

Hex
Code
78
79
7A
7B
7C
70
7E
7F
80
81
82
83
84
85
86
87
88
89
8A
8B
8C
80
8E
8F
90
91
92
93
94
95
96
97
98
99
9A
9B
9C
90
9E
9F
AD
A1
A2
A3
A4
A5
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
BO
B1
B2
B3

Number
of Bytes

Mnemonic

2
2
2
2
2
2
2
2
2
2
2
1
1
3
2
2
2
2
2
2
2
2
2
2
3
2
2
1
2
2
1
1
1
1
1
1
1
1
1
1
2
2
2
1
1

MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
SJMP
AJMP
ANL
MOVC
OIV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
ACALL
MOV
MOVC
SUBB
SUBB
SUBB
SUBB
SUBB
SUBB
SUBB
SUBB
SUBB
SUBB
SUBB
SUBB
ORL
AJMP
MOV
INC
MUL

2
2
2
2
2
2
2
2
2
2
2
2
2

MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
ANL
ACALL
CPL
CPL

Operands
RD,itdata
R1,itdata
R2,itdata
R3,itdata
R4,itdata
R5,itdata
R6,itdata
R7,itdata
codeaddr
codeaddr
C,bitaddr
A,@A+PC
AB

data addr,data addr

data addr,@RO
data addr,@R1
data addr, RD
data addr, R1
data addr, R2
data addr, R3
data addr,R4
data addr, R5
data addr,R6
data addr,R7
OPTR,itdata

codeaddr
bitaddr,C
A,@A+OPTR
A ,itdata

A,dataaddr
A,@RO
A,@R1
A,RD
A,R1
A,R2
A,R3
A,R4
A,R5
A,R6
A,R7

C,lbitaddr
codeaddr
C,bitaddr
OPTR
AB

reserved

@RD,dataaddr
@R1 ,data addr
RD,data addr
R1 ,data addr
R2,data addr
R3,data addr
R4,data addr
R5,data addr
R6,data addr
R7,data addr
C,lbitaddr
codeaddr
bitaddr
C

B-l1

Instruction Set Summary

MeS-51

Table B-2. Instruction Opcodes in Hexadecimal (Cont'd.)

Hex
Code
B4
B5
B6
B7
B8
B9
BA
BB
BC
BO
BE
BF
CO
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CO
CE
CF
DO
01
02
03
04
05
06
07
08
09
OA
DB
DC
DO
DE
OF
EO
E1
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF

B-12

Number
of Bytes
3
3
3
3
3
3
3
3
3
3
3
3
2
2
2
1
1
2
1
1
1
1
1
1
1
1
1
1
2
2
2
1
1
3
1
1
2
2
2
2
2
2
2
2
1
2
1
1
1
2
1
1
1
1
1
1
1
1
1
1

Mnemonic
CJNE
CJNE
CJNE
CJNE
CJNE
CJNE
CJNE
CJNE
CJNE
CJNE
CJNE
CJNE
PUSH
AJMP
CLR
CLR
SWAP
XCH
XCH
XCH
XCH
XCH
XCH
XCH
XCH
XCH
XCH
XCH
POP
ACALL
SETB
SETB
OA
OJNZ
XCHO
XCHO
OJNZ
OJNZ
OJNZ
OJNZ
OJNZ
OJNZ
OJNZ
OJNZ
MOVX
AJMP
MOVX
MOVX
CLR
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV

Operands
A,#data ,code addr
A,data addr ,code addr
@RO,#data,codeaddr
@R1 ,#data ,code addr
RO,#data ,code addr
R1 ,#data ,code addr
R2,#data ,code addr
R3,#data ,code addr
R4,#data ,code addr
R5,#data ,code addr
R6,#data ,code addr
R7,#data ,code addr
dataaddr
codeaddr
bitaddr

C
A
A,dataaddr

A,@RO
A,@R1
A,RO
A,R1
A,R2
A,R3
A,R4
A,R5
A,R6
A,R7
dataaddr
codeaddr
bitaddr

C
A
data addr ,code addr

A,@RO
A,@R1
RO,code addr

R1 ,code addr
R2,code addr
R3,code addr
R4,codeaddr
R5,code addr
R6,code addr
R7,codeaddr

A,@OPTR
codeaddr

A,@RO
A,@R1
A
A,dataaddr

A,@RO
A,@R1
A,RO
A,R1
A,R2
A,R3
A,R4
A,R5
A,R6
A,R7

Instruction Set Summary

MeS-51

Table B-2. Instruction Opcodes in Hexadecimal (Cont'd.)

Hex
Code
FO
F1
F2
F3
F4
F5
F6
F7
Fa
F9
FA
FB
FC
FD
FE
FF

Number
of Bytes
1

2
1
1
1

2
1
1
1
1
1
1
1
1
1
1

Mnemonic
MOVX
ACALL
MOVX
MOVX
CPL
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV

Operands
@DPTR,A
codeaddr
@RO,A
@R1,A
A
dataaddr,A
@RO,A
@R1,A
RO,A
R1,A
R2,A
R3,A
R4,A
R5,A
R6,A
R7,A

B-13

MEMORY, ADDRESSING, INSTRUCTION SET

iable 32. 8051 InstiUction Set Summary

Interrupt Response Time: To finish execution of current instruction, respond to the interrupt request, push the PC
and to vector to the first instruction of the interrupt service
program requires 38 to 81 oscillator periods (3 to 7,.,.s @ 12
MHz).

Notes on instruction set and addressing modes:

Rn
- Register R7-RO of the currently selec.ted
Register Bank.
data
- 8-bit internal data location's address. This
could be an Internal Data RAM location
(0-127) or a SFR [i.e. 110 port, control
register, status register, etc. (128-255)].
@Ri
- 8-bit internal data RAM location (0-255) addressed indirectly through register RI or RO.
#data
- 8-bit constant included in instruction.
#data 16 -16-bit constant included in instruction
addrl6
-16-bit destination address. Used by LCALL &
LJMP. A branch can be anywhere within the
64K-byte Program Memory address space.
addrll
-II-bit destination address. Used by ACALL &
AJMP. The branch will be within the same
2K-byte page of program memory as the first
byte of the following instruction.
reI
- Signed (two's complement) 8-bit offset byte.
Used by SJMP and all conditional jumps.
Range is -128 to + 127 bytes relative to first
byte of the following instruction.
bit
- Direct Addressed bit in Internal Data RAM or
Special Function Register.
- New operation not provided by 8048/8049.

INSTRUCTIONS THAT AFFECT FLAG SETTINGS'

INSTRUCTION

ADD
ADDC
SUBB
MUL

FLAG
COY AC
X X X
X X X
X X X
o X

DIY

DA
RRC
RLC
SETB C

X
X
X

INSTRUCTION

CLR C
CPL C
ANL C,bit
ANL C,/bit
ORL C,bit
ORL C,bit
MOY C,bit
CJNE

FLAG
COY AC

X
X
X

X
X
X

'Note that operations on SFR byte address 208 or bit addresses 209-215 (i.e. the PSW or bits in the PSW) will also
affect flag settings.

ARITHMETIC OPERATIONS Cont.

ARITHMETIC OPERATIONS

ADD

Mnemonic
A,Rn

ADD

A,direct

ADD

A,@Ri

ADD

A,#data

ADDC

A,Rn

ADDC

A,direct

ADDC

ADDC

SUBB

A,@Ri

A,#data

A,Rn

Byte
Description
Add register to
I
Accumulator
Add direct
2
byte to
Accumulator
Add indirect
Ram to
Accumulator
Add immediate 2
data to
Accumulator
Add register to
Accumulator
with Carry
Add direct
2
byte to
Accumulator
with Carry
Add indirect
RAM to
Accumulator
with Carry
Add immediate 2
data to Acc
with Carry
Subtract
register from
Accwith
borrow

Oscillator
Period
12

Byte
Description
Subtract direct
2
byte from Acc
with borrow
Subtract
indirect RAM
from Acc with
borrow
Subtract
2
immediate data
from Acc with
borrow
Increment
Accumulator
Increment
register
2
Increment
direct byte
Increme.nt
indirect RAM
Decrement
Accumulator
Decrement
Register
Decrement
2
direct byte
Decrement
indirect RAM

Mnemonic
SUBB
A,direct

12
SUBB

A,@Ri

SUBB

A,#data

INC

INC

Rn

INC

direct

INC

@Ri

DEC

DEC

Rn

DEC

direct

DEC

@Ri

12

12

12

12

12

12

12

All mnemonics copyrighted

3-6

,<

Oscillator
Period
12

12

12

12
12
12
12
12
12
12
12

Intel Corporation 1980

AFN-01739A

MEMORY, ADDRESSING, INSTRUCTION SET

MEMORY, ADDRESSING, INSTRUCTION SET

Table 32. Instruction Set Summary (continued)

OAT A TRANSFER Cont.

DATA TRANSFER

Description Byte
Move register
1
to
Accumulator
A,direct
Move direct
2
byte to
Accumulator
A,@Ri
Move indirect
RAM to
Accumulator
A,#data
Move
2
immediate data
to
Accumulator
Rn,A
Move
Accumulator
to register
Rn,direct
Move direct
2
byte to register
Rn,#data
Move
2
immediate data
to register
direct,A
Move
2
Accumulator
to direct byte
Move register
2
direct,Rn
to direct byte
direct,direct
Move direct
byte to direct
direct,@Ri
Move indirect
2
RAM to direct
byte
direct,#data
Move
immediate data
to direct byte
@Ri,A
Move
Accumulator
to indirect
RAM
@Ri,direct
Move direct
2
byte to indirect
RAM
@Ri,#data
Move
2
immediate data
to indirect
RAM
DPTR,#dataI6 Load Data
Pointer with a
16-bit constant
A,@A+DPTR Move Code
byte relative to
DPTR to Acc
A,@A+PC
Move Code
byte relative to
PC and Acc
A,@Ri
Move External
RAM (8-bit
addr) to Acc
A,@DPTR
Move External
RAM (16-bit
addr) to Acc

Mnemonic
MOV
A,Rn

MOV

MOV

MOV

MOV

MOV
MOV

MOV

MOV
MOV
MOV

MOV

MOV

MOV

MOV

MOV

MOVC

MOVe

MOVX

MOVX

Oscillator
Period
12

Mnemonic
MOVX @Ri,A

12

MOVX

@DPTR,A

12

PUSH

direct

POP

direct

XCH

A,Rn

XCH

A,direct

XCH

A,@Ri

XCHD

A,@Ri

12

12

24
12

12

24

Description Byte
Move Acc to
1
External RAM
(8-bit addr)
Move Acc to
External Ram
(l6-bit addr)
Push direct
2
byte onto stack
Pop direct byte 2
from stack
Exchange
register with
Accumulator
Exchange
2
direct byte
with
Accumulator
Exchange
indirect RAM
with
Accumulator
Exchange loworder Digit
indirect RAM
with Acc

Oscillator
Period
24

24

24
24
12

12

12

12

24
24

24

12

24

12

24

24

24

24

24
All mnemonics copyrighted Intel Corporation 1980

3-8

AFN-01739A

MEMORY, ADDRESSING, INSTRUCTION SET

Table 32. Instruction Set Summary (continued)

PROGRAM BRANCHING Cont.

BOOLEAN VARIABLE MANIPULATION

Mnemonic
CLR
C
CLR
bit
SETB
C
SETB
bit
CPL
C
CPL

bit

ANL

C,bit

ANL

C,/bit

ORL

C,bit

ORL

C,/bit

MOY

C,bit

MOY

bit,C

JC

rei

JNC

rei

JB

bit,rel

JNB

bit,rel

JBC

bit,rel

Oscillator
Description Byte Period
12
Clear Carry
1
12
Clear direct bit
2
12
Set Carry
1
12
Set direct bit
2
12
Complement
1
Carry
12
Complement
2
direct bit
AND direct bit
24
2
to Carry
AND
24
2
complement of
direct bit to
Carry
OR direct bit
24
2
to Carry
OR
2
24
complement of
direct bit to
Carry
Move direct bit 2
12
to Carry
24
Move Carry to
2
direct bit
Jump if Carry
2
is set
Jump if Carry
24
2
not set
Jump if direct
24
Bit is set
Jump if direct
24
Bit is Not set
Jump if direct
24
3
Bit is set &
clear bit

JNZ

Mnemonic
rei

CJNE

A,direct,rel

CJNE

A,#data,rel

CJNE

RN ,#data,rel

CJNE

@Ri,#data,rel

DJNZ

Rn,rel

DJNZ

direct,rel

NOP

Description Byte
Jump if
2
Accumulator is
Not Zero
Compare direct
byte to Acc
and Jump if
Not Equal
Comare
3
immediate to
Acc and Jump
if Not Equal
Compare
immediate to
register and
Jump if Not
Equal
Compare
immediate to
indirect and
Jump if Not
Equal
Decrement
3
register and
Jump if Not
Zero
Decrement
3
direct byte and
Jump if Not
Zero
No Operation

Oscillator
Period
24

24

24

24

24

24

24

12

PROGRAMING BRANCHING

Mnemonic
ACALL addrll

LCALL addr16

RET
RETI
AJMP
LJMP
SJMP

addrl1
addr16
rel

JMP

@A+DPTR

JZ

rel

Description Byte
Absolute
2
Subroutine
Call
Long
Subroutine
Call
Return for
Subroutine
Return for
interrupt
Absolute Jump 2
Long Jump
3
Short Jump
2
(relative addr)
Jump indirect
relative to the
DPTR
Jump if
2
Accumulator is
Zero

Oscillator
Period
24

24

24
24
24
24
24
24

24
All mnemonics copyrighted Intel Corporation 1980

3-9

AFN-01739A