CR-1 : @GALILEO_LIB.

GALILEO(SCH_1):PAGE1

D
D

GALILEO GEN2
INTEL QUARK X1000

FAB H

PB: H48142-207
PBA:H48125-800

LB6V1

LB1
EMPTY

LB3
LABEL

LABEL

WEEE_LABEL_9X5MM
A

WEEE

1500X500_TARGET
SERIAL NUMBER

1375X250_TARGET
MAC ADDRESS LABEL

INTEL CORPORATION
2111 NE 25TH AVENUE
HILLSBORO OR 97124

TITLE

DESIGN TITLE PAGE

Wed May 21 10:12:25 2014

8

GALILEO Gen2

DOCUMENT NUMBER

REV

H38681

2.0

SHEET 1 OF 28
1

CR-2 : @GALILEO_LIB.GALILEO(SCH_1):PAGE2

TABLE OF CONTENTS
SHEET NUMBER
D

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28

SHEET NAME

SHEET NUMBER

SHEET NAME

DESIGN TITLE PAGE

TABLE OF CONTENTS
DISCLAIMER
SYSTEM BLOCK DIAGRAM
QUARK DDR3 & PCIE
QUARK GPIO
QUARK MISC
QUARK POWER
QUARK DECOUPLING
SDRAM 1
SDRAM 2
SDRAM TERMINATION
MINI PCIE CONNECTOR
MICRO SD CONNECTOR
USB CONNECTORS
UART 1 & JTAG
LAN
SPI: ADC&FLASH
QUARK STRAPS
EXTERNAL IO MUXING 1
EXTERNAL IO MUXING 2
LVL B BUFFER
LVL C BUFFER
AMUX & EXTERNAL IO
VOLTAGE REGULATORS
VOLTAGE REGULATORS
VOLTAGE REGULATORS
POWER BUTTONS & MISC

INTEL CORPORATION
2111 NE 25TH AVENUE
HILLSBORO OR 97124

Thu Mar 03 10:58:31 2011

TITLE:

DOCUMENT NUMBER:

GALILEO Gen2

REV:

TABLE OF CONTENTS
2

2.0

H38681

SHEET 2 OF 28
1

CR-3 : @GALILEO_LIB.GALILEO(SCH_1):PAGE3

D
D

INTEL CORPORATION
2111 NE 25TH AVENUE
HILLSBORO OR 97124

TITLE:

DOCUMENT NUMBER:

GALILEO Gen2
DISCLAIMER

REV:

2.0

H38681

SHEET 3 OF 28
1

CR-4 : @GALILEO_LIB.GALILEO(SCH_1):PAGE4

D
D

INTEL CORPORATION
2111 NE 25TH AVENUE
HILLSBORO OR 97124

TITLE:

DOCUMENT NUMBER:

GALILEO Gen2

REV:

SYSTEM BLOCK DIAGRAM

2

2.0

H38681

SHEET 4 OF 28
1

CR-5 : @GALILEO_LIB.GALILEO(SCH_1):PAGE5

QUARK_X1000_R1P2

BGA393

U2A5
12D7<>

11C6<

BI

M_BS<2..0>

OUT
OUT
OUT
BI

M_CAS_N
M_RAS_N
M_WE_N
M_MA<15..0>

10B6<

2
1
0

D
12A8<>
11B6< 10B6<
12B8<>
11B6< 10B6<
12A8<>
11B6< 10A6<
12D7<>
11C3< 10C3<>

12D3<

11B6<

10D3<

10B6<

12C3<

11B6<

10C3<

10B6<

12A8<>

11B6<

10B6<

12A8<>

11B6<

10B6<

12A8<>

V1P5_S0

6A6>
6A6>

R2A8
1
2
7.5K 1%
0402LF CH

11B6<

M_DQ<15..0>

DDR3

15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0

AR13
AT26
AP26

DDR3_BS<2>
DDR3_BS<1>
DDR3_BS<0>

AN29
AR27
AP28

DDR3_CASB
DDR3_RASB
DDR3_WEB

AT14
AP14
AR29
AR15
AN15
AN24
AP16
AR17
AN17
AR20
AN20
AT21
AP21
AR22
AN22
AR24

DDR3_MA<15>
DDR3_MA<14>
DDR3_MA<13>
DDR3_MA<12>
DDR3_MA<11>
DDR3_MA<10>
DDR3_MA<9>
DDR3_MA<8>
DDR3_MA<7>
DDR3_MA<6>
DDR3_MA<5>
DDR3_MA<4>
DDR3_MA<3>
DDR3_MA<2>
DDR3_MA<1>
DDR3_MA<0>
DDR3_CK<1>
DDR3_CK<0>

DDR3_DQ<15>
DDR3_DQ<14>
DDR3_DQ<13>
DDR3_DQ<12>
DDR3_DQ<11>
DDR3_DQ<10>
DDR3_DQ<9>
DDR3_DQ<8>
DDR3_DQ<7>
DDR3_DQ<6>
DDR3_DQ<5>
DDR3_DQ<4>
DDR3_DQ<3>
DDR3_DQ<2>
DDR3_DQ<1>
DDR3_DQ<0>

AR11
AT10
AN5
AT5
AP10
AR9
AP4
AT3
AK12
AH12
AJ6
AG6
AH15
AL15
AK11
AL11

15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0

DDR3_DQS<1>
DDR3_DQS<0>

AN6
AK7

1
0

DDR3_DQSB<1>
DDR3_DQSB<0>

AR6
AH7

1
0

BI

M_CKE<0>

AP12
AN11

DDR3_CKE<1>
DDR3_CKE<0>

BI

M_ODT<0>

AT32
AT31

DDR3_ODT<1>
DDR3_ODT<0>

RESERVED
RESERVED

AK19
AH19

RSVD_0
RSVD_1

DDR3_CSB<1>
DDR3_CSB<0>

RESERVED
RESERVED

AK17
AL17

RSVD_2
RSVD_3

DDR3_IDRAM_PWROK
DDR3_ISYSPWRGOOD

RESERVED
RESERVED

AT34
AR35

RSVD_4

DDR_PWROK
DDR_ISYSPWRGOOD

AK25
AH25

PCIE_IRCOMP

AE10
AA10

RSVD_5
RSVD_6

PCIE_RBIAS

INTERNAL REFCLK USED ON PCIE

AE2
AE4

PCIE_REFCLKP
PCIE_REFCLKN

ONLY 1 PCIE IS USED

AK2
AK4

PCIE_PERP_1
PCIE_PERN_1

PCIE_PETP_1
PCIE_PETN_1

AH4
AH2

PCIE0_RX0_P
PCIE0_RX0_N

AM2
AN1

PCIE_PERP_0
PCIE_PERN_0

PCIE_PETP_0
PCIE_PETN_0

AD3
AD1

PCIE_IRCOMP
RESERVED
RESERVED

11C3<>

VREF
R3L6

AJ1

AJ3

IN
IN

11C3<>

0
0

OUT
OUT

11C3<
10C3<

BI

10A6<

R3L8
R3L9

274 1%
0402LF CH
R3L7
11B6<

34 1%
0402LF CH
R3L5
32.4 1%
0402LF CH

EMPTY
EMPTY

V1P5_S0

R2B1
10K 5%
0402LF CH

PCIE

PCIE_RBIAS

13B3<
13B3<

10C3<>

DDR3_ODTPU
DDR3_DQPU
DDR3_CMDPU

BI

IN
IN

BI

AM29
AL19
AH23
AK23

DDR3_VREF
DDR3_ODTPU
DDR3_DQPU
DDR3_CMDPU

5A7>
5A7>

M_DQS_N<1..0>

DDR3_DRAMRSTB

DDR3_CKB<1>
DDR3_CKB<0>

M_CS_N<0>

11C3<>

M_DRAMRST_N

AH29
AL30

BI

10C3<>

AL25

M_CK_N<0>

10B6<

BI

DDR3_DM<1>
DDR3_DM<0>

M_CK<0>

AP31
AN31

M_DQS<1..0>

DDR3_DM1
DDR3_DM0

BI

10C3<>

AP7
AL12

AG30
AJ30

BI

R2A10
EMPTY
R3L10
R3L14
EMPTY

0
0
0402LF

7.5K 1%
0402LF CH

C3A4

PCIE0_TX0_P_C
PCIE0_TX0_N_C

0.1UF 10%
16V
X7R
0402LF

1 OF 5

C3A3

IC

0.1UF 10%
16V
X7R
0402LF

PCIE0_TX0_P

OUT

13B3>

PCIE0_TX0_N

OUT

13B3>

V1P5_S3
A

1 R4L2
1K
1%
2 CH
0402LF
1/16W

1 R4L1
1K
1%
2 CH
0402LF
1/16W
DDR_PWROK
DDR_ISYSPWRGOOD

OUT

5B7<

6A6>

OUT

5B7<

6A6>

INTEL CORPORATION
2111 NE 25TH AVENUE
HILLSBORO OR 97124
GALILEO Gen2
TITLE:
QUARK DDR3 & PCIE

DOCUMENT NUMBER:
REV:

2.0

H38681
SHEET 5 OF 28
1

CR-6 : @GALILEO_LIB.GALILEO(SCH_1):PAGE6

V3P3_S0

1 R3A13
2.2K
5%
2 CH
0402LF
1/16W

D
QUARK_X1000_R1P2

R2B8

19D5>

18B4<

OUT

SPI0_SCK

33.2

R2B11 CH SPI0_SCK_R

21C6<
23B1<

19D4>
6C7<>

OUT
IN

SPI1_MOSI
SPI1_MISO

33.2

R2B9 CH SPI1_MOSI_R

21D3<

19D3>

OUT

SPI1_SCK

33.2

R3M6 CH SPI1_SCK_R

19B1>

18D6<
18C1>
18C6<
18C6<

19A6>
22A2> 21D3<
23C7< 23C2<>
22B2> 21B6<
22C2> 21A8<
13B6< 13A7<
13B6< 13A6<

MUX2_I0
MUX1_I0
SPI1_MISO
MUX0_I0
LVL_C_A1
MUX7_I0
UART0_RXD
MUX6_I0
EXP2_INT
SPI0_CS_N

1K
1K
1K
1K
1K
1K
1K
1K
33.2
33.2

18PF 5%
0402LF COG

1 R2A9
10M
5%
2 CH
0402LF
1/16W

Y2A1
32.768KHZ
XTAL
RTCX2

CAD NOTE:
TRACE TO CRYSTAL HAS
TO BE LENGTH MATCHED

R2L9
2
10K 5%
0402LF CH

C3L8
1UF
10%
6.3V
X5R
0402LF

RTC_EXT_CLK_EN_B

MUX8_I0_R
LVL_C_A2_R
MUX5_I0_R
MUX3_I0_R

J15
G15
E15
J12
E12
G11

GPIO_SUS<5>
GPIO_SUS<4>
GPIO_SUS<3>
GPIO_SUS<2>
GPIO_SUS<1>
GPIO_SUS<0>

MUX2_I0_R
MUX1_I0_R
SPI1_MISO_R
MUX0_I0_R
LVL_C_A1_R
MUX7_I0_R
GPIO3_R
MUX6_I0_R
EXP2_INT_R
SPI0_CS_N_R

W33
V34
V32
U33
T34
T32
R35
R33
N34
N32

GPIO<9>
GPIO<8>
GPIO<7>
GPIO<6>
GPIO<5>
GPIO<4>
GPIO<3>
GPIO<2>
GPIO<1>
GPIO<0>

G3
J2

RTCX2
RTCX1

VCCRTCEXT

J11

IVCCRTCEXT

J7
E11
A4
G7

V3P3_RTC

28C5<

R2L10
2
1K 1%
0402LF EMPTY

C2L1
1UF
10%
6.3V
X5R
0402LF

6A6<
6A6<

IN
IN

28D7>
19A3>
13B8>

IN
IN
IN

RESET_N
EC_PWRBTN_N
WAKE_N

D6
L2
A5
B4

RESET_BTN
PWR_BTN
WAKE_B
GPE_B

GPE_N NOT USED (INTERNAL PU)

OUT
OUT
IN

S3_1V5_EN
S3_3V3_EN
S3_PGOOD

K1
K3
J4

S3_1V5_EN
S3_3V3_EN
S3_PG

28B8< 26A8< 6A6<

28B7< 27C6< 26B3<
26D3<
28B6> 6A6<

OUT
OUT
OUT
IN

S0_1V0_EN
S0_1V5_EN
S0_3V3_EN
PG_V1P0_S0

F4
F2
E4
D2

S0_1V0_EN
S0_1V5_EN
S0_3V3_EN
S0_1P0_PG

J30
H30

VNNSENSE
VSSSENSE

28A6>

RTCRST_N

5B7<
5B7<

5A7>
5A7>

OUT
OUT

DDR_PWROK
DDR_ISYSPWRGOOD

ODRAM_PWROK
OSYSPWRGOOD

B6
C7

TCK
TDI
TDO
TMS
TRST_B

M3
N4
R1
N2
L4

PRDY_B
PREQ_B

E7
B2

RESERVED
RESERVED

V3P3_S5

I2C_SDA
I2C_SCL
JTAG_TCK
JTAG_TDI
JTAG_TDO
JTAG_TMS
JTAG_TRST_N

16A4>
16A5>
16A5<
16B4>
16A5>

IN
IN
OUT
IN
IN

TP1

CAD NOTE:
PLACE NEAR QUARK

T_POINT1

TP

TP

AA2
AB1

RESERVED
RESERVED

B1
A2

REF0_OUTCLK_P
REF0_OUTCLK_N

M8
M6

REF1_OUTCLK_P
REF1_OUTCLK_N

J6
H6

REF1_P
REF1_N

CKSYS25OUT

W7

CKSYS25OUT

FLEX0_CLK
FLEX1_CLK
FLEX2_CLK

V4
V2
U3

FLEX0_CLK
FLEX1_CLK
FLEX2_CLK

RMII_REF_CLK_OUT

T4

RMII_REF_CLK_R

RESERVED
RESERVED
PAD_BYPASS_CLK

Y3L1

CLN_XTAL_IN
CLN_XTAL_OUT

XTAL_IN
XTAL_OUT

V7
V5

R3L2
2
1M 5%
0402LF CH

TP2A1

T_POINT1

HPLL_REFCLK_P
HPLL_REFCLK_N

TP2

TP0
TP1

AT2
AR1

W3

R2L21
49.9
1%
EMPTY
0402LF

PRDY_B
PREQ_B

TP2A2

OSC_COMP

13B2<>
20A2<>
20B4<>
13B2< 20A2< 20B4<>

BI
BI

RSVD_7
RSVD_8

R3A24

25.000MHZ
EMPTY

REF0_OUTCLK
REFCLK0_P
REFCLK0_N
R3L11
110

OUT
OUT

C3L5
18PF
5%
50V
COG
0402LF

13C3<
13C3<

CH

XTAL
G91801-001
2

C3L6
18PF
5%
50V
COG
0402LF

R2L11
10K
5%
CH
0402LF

25D3>

6B6<

S5_PGOOD

R2A5

00
0402LF CH

OUT

17B8<

R2A12
49.9
1%
CH
0402LF
1/16W

R3L3

EXT_REFCLK_HPLL
0

RMII_REF_CLK_OUT

R3L12

10K 5%
0402LF CH

EMPTY

V1P5_S5

R2A13
49.9
1%
CH

R2A14
49.9
1%
CH

R3L13
49.9
1%
CH

NOT USED

AC4

2 OF 5

1 R2A11
7.5K
1%
2 CH
0402LF

IC
TP5

T_POINT1

28A6>

S3_PGOOD
6B6< S0_PGOOD
6A6<

28B8<

26A8<
28B6>

6A6> S0_1V0_EN
6A6< PG_V1P0_S0

INTEL CORPORATION

TP7

2111 NE 25TH AVENUE

HILLSBORO OR 97124

T_POINT1

1
TP6
T_POINT1

TP8

TITLE

T_POINT1

GALILEO Gen2
QUARK GPIO

25MHZ - NOT USED

OSC_COMP

AF11 RSVD_9
AD11 RSVD_10

100MHZ

T_POINT1

28A5>

R3
T2

TP4

28C5<

RTCRST_B
RTC_EXT_CLK_EN_B
S0_PG
S5_PG

RTC32K_CLK_SEL
S0_PGOOD
S5_PGOOD

26B5<
26D5<
6A6<

28A8<

0: EXTERNAL CLOCK FROM RTCX1/RTXC2

1: INTERNAL CLOCK

LSPI_MOSI
LSPI_MISO
LSPI_SS_B
LSPI_SCK

PWRMGMT

R2B21 CH
R2B20 CH
R3M14 CH
R3M10 CH
R3M8 CH
R3M5 CH
R3M13 CH
R2B7 CH
R2B29 CH
R2B14 CH

28A5>
25D3>

V3P3_RTC

CH
CH
CH
CH

AK32
AN35
AM33
AM35

RTC

C3A10
2

C3L13
0.1UF
10%
16V
X7R
0402LF

R2M5
R39
R12
R3M2

SPI1_MOSI
SPI1_MISO
SPI1_SS_B
SPI1_SCK

RTCX1

18PF 5%
0402LF COG

BI
BI
BI
BI
BI
BI
IN
BI
IN
OUT

1K
1K
1K
1K

LSPI_MOSI_R
LSPI_MISO
LSPI_CS_N_R
LSPI_SCK_R

AH32
AK34
AJ33
AH34

I2C_DATA
I2C_CLK

GPIO

22C2> 21B8<
22D2> 21C8<
23B7< 23B1< 6C7<
22D2> 21D8<
23D2<>
23C7< 21B3<
22A2> 21A6<
23D2<>
23C7< 7B7<
22B2> 21B6<
20B5>
18A5<

C2A6
2

MUX8_I0
LVL_C_A2
MUX5_I0
MUX3_I0
WIFI_DISABLE_N
PCIE_RESET_N

BI
BI
BI
BI
BI
BI

OUT
IN
OUT
OUT

SPI0_MOSI
SPI0_MISO
SPI0_SS_B
SPI0_SCK

I2C

OUT
IN

AG35
AG33
AE34
AE32

SPI

23B7<

18A4<
18A1>

CH SPI0_MOSI_R

DFX

19D7>

ON-BOARD ADC

33.2

CRU/PLL

U2A5
SPI0_MOSI
SPI0_MISO

BGA393

1 R3A15
2.2K
5%
2 CH
0402LF
1/16W

DOCUMENT NUMBER

REV

H38681

2.0

SHEET 6 OF 28
1

CR-7 : @GALILEO_LIB.GALILEO(SCH_1):PAGE7

USBH0_DP_R
USBH0_DN_R

7D4<>
7D4<>

PLACE USB CAPS AS CLOSE

AS POSSIBLE TO SOC.

QUARK_X1000_R1P2

NOT USED, LEAVE FLOATING

D9
B9
C10

NOT USED (INTERNAL PU)

R3A20
10K
1%
CH
0402LF

14C6<>

14C6<>
14C6<
14C6>
14A5<

BI
OUT

CLN_SD_CMD
CLN_SD_CLK

IN
OUT

CLN_SD_CD_N
SD_LED

23C7<

6B7<
IN
21A6<
OUT

16C5>
16C5<
21B1>
21C3< 16C5<

IN
OUT
IN
OUT

R2L4

CH CLN_SD_CLK_R

B22
J19
G19
E19
E17
G17

SD_CMD
SD_CLK
SD_WP
SD_CD_B
SD_LED
SD_PWR

UART0_RXD
UART0_TXD

AD29
AC27
AA32
W29
AD28
W30
AA34
W35

SIU0_CTS_B
SIU0_DCD_B
SIU0_DSR_B
SIU0_DTR_B
SIU0_RI_B
SIU0_RTS_B
SIU0_RXD
SIU0_TXD

UART1_CTS_N
UART1_RTS_N
UART1_RXD
UART1_TXD

AB33
AD33
AC34
AC32

SIU1_CTS_B
SIU1_RTS_B
SIU1_RXD
SIU1_TXD

USBH1_DP
USBH1_DN

P29
P30

USBH1_DP
USBH1_DN

USBH0_DP
USBH0_DN

V30
V29

USBH0_DP_R
USBH0_DN_R

7D3<
7D3<

USBD_DP
USBD_DN

M29
M31

USBH2_DP_R
USBH2_DN_R

7D3<
7D3<

USB_CLK96P
USB_CLK96N

M35
M33

RESERVED
RESERVED

L34
L32

USB0_OC_B
USB1_OC_B

G35
J32

USB_OC0_N
USB_OC1_N

USBH0_PWR_EN
USBH1_PWR_EN

F34
G33

USB_PWR_EN0

IUSBCOMP_N18
OUSBCOMP_P18

K33
J34

USBCOMP

RMII_REF_CLK

C16

RMII_REFCLK

MAC0_TXEN
MAC0_TXDATA<1>
MAC0_TXDATA<0>
MAC0_RXDV
MAC0_RXDATA<1>
MAC0_RXDATA<0>

C21
D22
A21
C18
B20
D20

RMII_S0_TX_EN_R
RMII_S0_TXD1_R
RMII_S0_TXD0_R
RMII_S0_RX_DV
RMII_S0_RXD1
RMII_S0_RXD0

MAC0_MDC
MAC0_MDIO

D17
B17

RMII_S0_MDC_R
RMII_S0_MDIO_R

MAC1_TXEN
MAC1_TXDATA<1>
MAC1_TXDATA<0>
MAC1_RXDV
MAC1_RXDATA<1>
MAC1_RXDATA<0>

C12
B15
D15
C14
B13
D13

MAC1_MDC
MAC1_MDIO

B11
D11

13B3<>
13B3<>

BI
BI

RMII_S1_TXD1
RMII_S1_TXD0

R2B28

OUT

IN
33.2
33.2
33.2

15C6<>
15C6<>

R76
CH

R78

CH

USBH2_DP
USBH2_DN

BI
BI

15B6<>
15A6<>

C54
18PF
5%
25V
0201LF

R3B4
10K
5%
CH
0402LF
1/16W

15C5>
15C8<

1 R2B2
22.6
1%
2 CH
0402LF
1/16W

17B5>

33.2
33.2
OUT
OUT

BI
BI

V3P3_S0

EMPTY
IN

0
C51
18PF
5%
0201LF

INTERNAL CLOCKS USED FOR USB

LEAVE FLOATING PER USB TEAM INPUT
RSVD_11
RSVD_12

USBH0_DP
USBH0_DN

USBH2_DP_R
USBH2_DN_R

7C4<>
7C4<>

CH

19B4>
19D1>

R2M12 CH
R2M14 CH
R2M8 CH

RMII_S0_TX_EN
RMII_S0_TXD1
RMII_S0_TXD0

R2M7 CH
R2M11 CH

RMII_S0_MDC
RMII_S0_MDIO

OUT 17C4<
OUT 17C4<
OUT 17C4<
IN 17C1>
IN 17C1>
IN 17C1>
OUT
BI

19B7>
19B6>

17C4< 17C7>
17C2<>
17C6<>

ONLY USED FOR STRAPS

B

UART

23D2<>

33.2

3
2
1
0

SD_DATA<7>
SD_DATA<6>
SD_DATA<5>
SD_DATA<4>
SD_DATA<3>
SD_DATA<2>
SD_DATA<1>
SD_DATA<0>

SDIO

19A7>

CLN_SD_DAT<3..0>

BI

C28
B27
D27
A26
C26
B24
D24
C23

CLK14
THRM_B
SMI_B

LEGACY

PD_CLK14

USB

TS_IREF_N
R3L4
8.06K
1%
2 CH
0402LF
1/16W

RESERVED
RESERVED
TS_IREF_N
TS_TDA
TS_TDC

TS

AA4
W5
W9
AC7
AC5

BGA393

ETHERNET

U2A5

R79

R77

CH

C53
18PF
5%
25V
EMPTY
0201LF

C52
18PF
5%
25V
EMPTY
0201LF

CAD NOTE:
D

TXD OUTPUT FROM QUARK

3 OF 5
A

IC

INTEL CORPORATION
2111 NE 25TH AVENUE
HILLSBORO OR 97124

TITLE:

DOCUMENT NUMBER:

GALILEO Gen2

REV:

QUARK MISC

2.0

H38681

SHEET 7 OF 28
1

CR-8 : @GALILEO_LIB.GALILEO(SCH_1):PAGE8

V1P0_S0

V3P3_S0
V1P0_S3_IVR
D

FB3L1
1

V1P0_S5
C3L21
1UF
10%
6.3V
X5R
0402LF

TP15
TP13

T_POINT1

T_POINT1

TP18

0.5A 10

C3L14
1UF
10%
6.3V
X5R
0402LF

AB14
AD14
AB13
P14
T13
V16
V14
AD13
Y14
T11
P11
V11

V1P5_S0
V1P8_S3_IVR

TP12

TP17
T_POINT1

T_POINT1

TP10

T18

T_POINT1

V1P0_S5

V1P5_S3

V1P5_S5

V1P05_S0_IVR
TP16
T_POINT1

TP14

V1P8_S5_IVR

T_POINT1

V1P8_S0_IVR

1
2 V1P5_S3_LC

FB3M1 0.5A 10

TP11
T_POINT1

R26
T24
V13
R10
AD31
AD5
AT28

VCCFSOC_1P05
VCCFHVSOC_1P05
VCCAICLKSSC1_1P0
VCCAICLKSFR_1P5
VCCSFRPLLDDR_1P5
VCC1P5_S0
VCCCLKDDR_1P5

1
TP9
T_POINT1

K14
P5

VCC3P3_S0
VCC3P3_S0
VCC3P3_S0

AA26
AB24
AD24

VCCRTC3P3
VCCAICLKSE_3P3
VCC3P3_A
VCC3P3_USB_S3
VNN
VNN
VNN
VNN
VNN
VNN
VNN

TP21
T_POINT1

TP19

TP22

T_POINT1

T_POINT1

E1

P7
F30
K16
AB18
AB20
Y18
V18
Y20
Y16
V20

OVOUT_1P05_S0
OVOUT_1P0_S3
OVOUT_1P0_S5

P24
M14
T14

OVOUT_1P8_S0
OVOUT_1P8_S3
OVOUT_1P8_S5

P18
M18
K11

OVOUT_1P8_SLDO

K24

VSSA_USB

P16

V1P0_S0
TP20

V1P05_S0_IVR

T_POINT1

V1P8_S0_IVR

V1P0_S3_IVR

V1P8_S3_IVR

1
TP3
1

V1P0_S5_IVR

V1P8_S5_IVR

T_POINT1

4 OF 5

CAD NOTE
PLACE AS CLOSE AS POSSIBLE TO SIGNAL VIAS

STITCHING CAPS FOR SPLIT PLANES

V1P5_S5

V3P3_RTC

IC

C3M3
1UF
10%
6.3V
X5R
0402LF

VCCAUSB_1P8_S3
VCCAA_1P8
VCCAUSB_1P8
VCC1P8_S0
VCC1P8_S0
VCC1P8_S3
VCC1P8_S5

VCC3P3_S3
VCC3P3_S5

VCCAVISA_1P0
VCCDDR_1P5
VCCDDR_1P5
VCCDDR_1P5
VCCDDR_1P5

K20
K22
P22
P20
T20
K18
K13

V3P3_S5

VCCADDR_1P0
VCCADLLDDR_1P0
VCCACLKDDR_1P0
VCC1P0_S3
VCC1P0_S5
VCC1P0_S0
VCC1P0_S0
VCCPLLDDR_1P0
VCCAPCIE_1P0
VCCAICLKCB_1P0
VCCDICLKDIG_1P0
VCCAICLKDBUFF_1P0

AT12
AT16
AT18
AT23

V3P3_S3

BGA393

U2A5

V1P0_S0_FLT

T_POINT1

QUARK_X1000_R1P2

STITCHING CAPS FOR SIGNAL REFERENCE TRANSITION

V3P3_S5

V3P3_S5

V3P3_S3

V3P3_S0

V1P0_S0

C2A10

V3P3_S3

C1L3
0.1UF
10%
16V
X7R
0402LF

V3P3_S0

C4B7
0.1UF
10%
16V
X7R
0402LF

0.1UF 10%
16V
X7R
0402LF

C1M13
0.1UF
10%
16V
X7R
0402LF

V3P3_S5

C1M14
0.1UF
10%
16V
X7R
0402LF

VBUS1

C3A22
0.1UF
10%
16V
X7R
0402LF

V5_ALW_ON

C3M12
0.1UF
10%
16V
X7R
0402LF

C2M10
0.1UF
10%
16V
X7R
0402LF

V3P3_S0

C3B18
0.1UF
10%
16V
X7R
0402LF

C4A3
0.1UF
10%
16V
X7R
0402LF

C3M13
0.1UF
10%
16V
X7R
0402LF

V1P5_S3

V1P5_S5

C1B1
0.1UF
10%
16V
X7R
0402LF

C2A8
0.1UF
10%
16V
X7R
0402LF

C2A7
0.01UF
10%
50V
X7R
0402LF

C2A9
0.1UF
10%
16V
X7R
0402LF

C3A23
0.1UF
10%
16V
X7R
0402LF

C3A20
0.01UF
10%
50V
X7R
0402LF

C3A21
0.01UF
10%
50V
X7R
0402LF

C3B16
0.01UF
10%
50V
X7R
0402LF

C4B6
0.01UF
10%
50V
X7R
0402LF

C2B13
0.01UF
10%
50V
X7R
0402LF

C3B17
0.01UF
10%
50V
X7R
0402LF

C3A24
0.1UF
10%
16V
X7R
0402LF

INTEL CORPORATION
2111 NE 25TH AVENUE
HILLSBORO OR 97124

TITLE:

C2B12
0.01UF
10%
50V
X7R
0402LF

DOCUMENT NUMBER:

GALILEO Gen2

REV:

QUARK POWER

2.0

H38681

SHEET 8 OF 28
1

CR-9 : @GALILEO_LIB.GALILEO(SCH_1):PAGE9

V3P3_S0

RECOMMENDATION FROM PD STUDY

QUARK_X1000_R1P2

V3P3_S3

U2A5
D

C3M1
1000PF
10%
50V
2 X7R
0402LF
A36096-046

1
2

C3M2
1000PF
10%
50V
X7R
0402LF

C3L30
1000PF
10%
50V
X7R
0402LF

C3M8
1000PF
10%
50V
X7R
0402LF

C3M7
1000PF
10%
50V
X7R
0402LF

C3M6
1000PF
10%
50V
X7R
0402LF

C3M5
1000PF
10%
50V
X7R
0402LF

C3L19
0.01UF
10%
50V
X7R
0402LF

V3P3_S5

1
2

C3L9
1UF
10%
6.3V
X5R
0402LF

C3L10
1UF
10%
6.3V
X5R
0402LF

V1P8_S3_IVR

RECOMMENDATION FROM PD STUDY

V1P5_S3

V1P5_S5

1
1
2

C3L23
2.2UF
10%
6.3V
X5R
0603LF

C3M4
2.2UF
10%
6.3V
X5R
0603LF

1
2

C3L16
2.2UF
10%
6.3V
X5R
0603LF

C3L25
1000PF
10%
16V
X7R
0201LF
D70538-001

C3L12
2.2UF
10%
6.3V
X5R
0603LF

C3L27
1000PF
10%
16V
X7R
0201LF

C3L11
1UF
10%
6.3V
X5R
0201LF

RECOMMENDATION FROM PD STUDY

V1P0_S0

A7
A10
A12
A14
A16
A18
A23
A31
AB3
AB11
AB16
AD35
AB35
AC2
AC9
AC29
AC30
AD18
AD6
AD8
AD16
AN13
AE26
AF13
AF22
AF24
AG1
AG3
AH11
AH17
AK15
AJ35
AK29
AF20
AL6
AL23
AM1
AM4
AM7
AM32
AN9
E32
D33
D31
D29
F32

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

AP23
AP33
AT7
AN27
AP18
F6
H17
B33
D5
U1
V27
G1
G12
J25
K35
M1
M11
M5
M16
M13
M22
M28
P9
AD20
P13
P27
Y22
T16
T22
U35
V9
V22
W1
W27
Y11
Y13
AP2
C1
A28
A34
B29
C35
E35
B31
B35
A32

M26
E25
J23
M24
Y24
G25
AF16
G23
M20

NC
NC
NC
NC
NC
NC
NC
NC
NC

NC
NC
NC
NC
NC
NC
NC
NC
NC

AD22
AF14
AB22
V24
E23
G29
AF18
J29
E29

C3B10
22UF
20%
6.3V
2 X5R
0603LF
602433-081

1
2

C2B2
22UF
20%
6.3V
X5R
0603LF

C3L22
10UF
20%
4V
X5R
0402LF
A36096-108

C3L17
1UF
20%
4V
X5R
0201LF

C3L15
1UF
20%
4V
X5R
0201LF

C3L18
1UF
20%
4V
X5R
0201LF

C3L20
1UF
20%
4V
X5R
0201LF

C3L26
1UF
20%
4V
X5R
0201LF

C3L24
1UF
20%
4V
X5R
0201LF

C3L29
1UF
20%
4V
X5R
0201LF
C83410-012

BGA393

C3L28
1UF
20%
4V
X5R
0201LF

5 OF 5

IC

INTEL CORPORATION
2111 NE 25TH AVENUE
HILLSBORO OR 97124

TITLE:

DOCUMENT NUMBER:

GALILEO Gen2

REV:

QUARK DECOUPLING
2

2.0

H38681

SHEET 9 OF 28
1

CR-10 : @GALILEO_LIB.GALILEO(SCH_1):PAGE10

V1P5_S3

V1P5_S3

CAD NOTE:
PLACE 0.1UF DECOUPLING AS CLOSE AS POSSIBLE TO DRAM POWER PINS
1
D

C1A19
22UF
20%
6.3V
X5R
0805LF

1
2

V1P5_S3

C1A15
0.1UF
10%
16V
X7R
0402LF

1
2

C4M3
0.1UF
10%
16V
X7R
0402LF

C1A25
0.1UF
10%
16V
X7R
0402LF

C1A24
2.2UF
10%
6.3V
X5R
0603LF

12D3<

11B6<

10B6<

5C7<>

IN

M_CK<0>
1
2

VREF

C1A23
0.1UF
10%
16V
X7R
0402LF

12C3<

2
1

C4M4
0.1UF
10%
16V
X7R
0402LF

12A8<>
12A8<>

B
12D3<
12C3<

11B6<
11B6<
12A8<>

C1A22
0.1UF
10%
16V
X7R
0402LF

B9
C1
E2
E9

VDDQ
VDDQ
VDDQ
VDDQ

A2
A9
D7
G2
G8
K1
K9
M1
M9

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

J8

VREFCA

E1

VREFDQ

J3
K8
J2

BA<2>
BA<1>
BA<0>

M_BS<2..0>

11C6< 5D7<>
12D7<>

IN

11B6<

IN

M_ODT<0>

G1

ODT

IN

M_CKE<0>

G9

CKE

H8

ZQ

11B6<

10D3<
10C3<
11B6<

5C7<>
5C7<>

5C7<>
5C7<>
5B7<>

2
1
0

IN

M_CK<0>

IN

M_CK_N<0>
M_CS_N<0>

IN

R4M1
240 1%
0402LF CH

ZQ_1

F7

CK

G7

CK_N

H2

CS_N

G3

CAS_N

12A8<>

11B6<

5D7>

IN

M_CAS_N

12B8<>

11B6<

5D7>

IN

M_RAS_N

F3

RAS_N

12A8<>

11B6<

5D7>

IN

M_WE_N

H3

WE_N

IN

M_DRAMRST_N

N2

RESET_N

A3
F1
F9
H1
H9
J7
N7

NC_A3
NC_F1
NC_F9
NC_H1
NC_H9
NC_J7
NC_N7

11B6<

5C3<>

10B6<

5C7<>

IN

M_CK_N<0>

MT41K128M8

U1B5

VREF

11B6<

C4M1
1PF
.25PF
25V
COG
0402LF

DM/TDQS
NF/TDQS_N

B7
A7

DDR3_DM0

IN

DQS
DQS_N

C3
D3

DQ<7>
DQ<6>
DQ<5>
DQ<4>
DQ<3>
DQ<2>
DQ<1>
DQ<0>

E7
D2
E8
E3
C8
C2
C7
B3

M_DQS<0>
M_DQS_N<0>
M_DQ<7:0>

BI
BI
BI

5C3<>
5C3<>
5D3<>

M_MA<15:0>

BI

5D7<>

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC_N
A13

K3
L7
L3
K2
L8
L2
M8
M2
N8
M3
H7
M7
K7
N3

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

B2
B8
C9
D9
D1

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

A1
A8
B1
D8
F2
F8
J1
J9
L1
L9
N1
N9

7
6
5
4
3
2
1
0

5C3>

11C3<

12D7<>

0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

DESIGN NOTE:
A14, A15 ALLOW FOOTPRINT COMPATIBILITY WITH
2GBIT(256MBIT X 8) AND 4GBIT (512MBIT X8) DEVICES
A

IC
G83568-001

SDRAM 1
INTEL CORPORATION
2111 NE 25TH AVENUE
HILLSBORO OR 97124
GALILEO Gen2
TITLE:
SDRAM 1

DOCUMENT NUMBER:
REV:

2.0

H38681

SHEET 10 OF 28
1

CR-11 : @GALILEO_LIB.GALILEO(SCH_1):PAGE11

V1P5_S3

CAD:
PLACE 0.1UF DECOUPLING AS CLOSE AS POSSIBLE TO DRAM PINS

V1P5_S3

VREF

C1A16
0.1UF
10%
16V
X7R
0402LF

C4M2
0.1UF
10%
16V
X7R
0402LF

C1A21
0.1UF
10%
16V
X7R
0402LF

C4L3
0.1UF
10%
16V
X7R
0402LF

C1A14
2.2UF
10%
6.3V
X5R
0603LF

MT41K128M8

U1A1
VREF

12D7<>

10B6<

5D7<>

C1A13
0.1UF
10%
16V
X7R
0402LF

C1A20
0.1UF
10%
16V
X7R
0402LF

B9
C1
E2
E9

VDDQ
VDDQ
VDDQ
VDDQ

A2
A9
D7
G2
G8
K1
K9
M1
M9

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

J8

VREFCA

E1

VREFDQ

J3
K8
J2

BA<2>
BA<1>
BA<0>

M_BS<2..0>

IN

2
1
0
12A8<>
12A8<>

10B6<
10B6<

5C7<>
5C7<>

IN

M_ODT<0>

G1

ODT

IN

M_CKE<0>

G9

CKE

H8

ZQ

F7

CK

R4L19
240 1%
0402LF CH

ZQ_2

12D3<

10D3<

10B6<

5C7<>

IN

M_CK<0>

12C3<

10C3<

10B6<

5C7<>

IN

M_CK_N<0>

G7

CK_N

12A8<>

10B6<

5B7<>

IN

M_CS_N<0>

H2

CS_N

IN

M_CAS_N

G3

CAS_N

IN

M_RAS_N

F3

RAS_N

IN

M_WE_N

H3

WE_N

IN

M_DRAMRST_N

N2

RESET_N

A3
F1
F9
H1
H9
J7
N7

NC_A3
NC_F1
NC_F9
NC_H1
NC_H9
NC_J7
NC_N7

12A8<>

10B6<

5D7>

12B8<>

10B6<

5D7>

12A8<>

10A6<
10A6<

5D7>
5C3<>

DM/TDQS
NF/TDQS_N

B7
A7

DQS
DQS_N

C3
D3

DQ<7>
DQ<6>
DQ<5>
DQ<4>
DQ<3>
DQ<2>
DQ<1>
DQ<0>

E7
D2
E8
E3
C8
C2
C7
B3

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC_N
A13

K3
L7
L3
K2
L8
L2
M8
M2
N8
M3
H7
M7
K7
N3

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

B2
B8
C9
D9
D1

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

A1
A8
B1
D8
F2
F8
J1
J9
L1
L9
N1
N9

15
14
13
12
11
10
9
8

DDR3_DM1
M_DQS<1>
M_DQS_N<1>

IN
BI
BI

5C3>
5C3<>
5C3<>

M_DQ<15:8>

BI

5D3<>

M_MA<15:0>

0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

IN

5D7<>

10C3<>

12D7<>

DESIGN NOTE:
A14, A15 ALLOW FOOTPRINT COMPATIBILITY WITH
2GBIT(256MBIT X 8) AND 4GBIT (512MBIT X8) DEVICES

IC
G83568-001

SDRAM 2
INTEL CORPORATION
2111 NE 25TH AVENUE
HILLSBORO OR 97124
GALILEO Gen2
TITLE:
SDRAM 2

DOCUMENT NUMBER:
REV:

2.0

H38681

SHEET 11 OF 28
1

CR-12 : @GALILEO_LIB.GALILEO(SCH_1):PAGE12

VTT

11C6<

10B6<

5D7<>

BI

M_BS<2:0>

R1A20

36.5 R4L23

36.5 R4L22
36.5
0402LF

11C3<

10C3<>

5D7<>

BI

M_MA<15..0>

VTT
C

C1A7
0.1UF
10%
16V
X7R
0402LF

C1A8
0.1UF
10%
16V
X7R
0402LF

C1A10
0.1UF
10%
16V
X7R
0402LF

C1A6
0.1UF
10%
16V
X7R
0402LF

C1A9
0.1UF
10%
16V
X7R
0402LF

CAD:
DITRIBUTE DECOUPLING AMONG
TERMINATION RESISTORS

VTT

C1A5
0.1UF
10%
16V
X7R
0402LF

1%
CH

VTT

15

36.5

R1A19

14

36.5

R4L7

13

36.5

R1A18

12

36.5

R4L21

11

36.5

R4L20

10

36.5

R4L14

36.5

R4L8

36.5

R4L18

36.5

R1A2

36.5

R1A3

36.5

R4L17

36.5

R1A5

36.5

R1A4

36.5

R4L6

36.5

R4L5

36.5

R4L16

11B6<

10D3<

10B6<

5C7<>

IN

M_CK<0>

11B6<

10C3<

10B6<

5C7<>

IN

M_CK_N<0>

R4L11
30.1
0402LF

1%
CH

M_CK_CAP

C4L2
0.1UF
10%
16V
X7R
0402LF

R4L10
30.1
0402LF

1%
CH

1%
G73524-001

M_RAS_N

36.5

R4L12

BI

M_CAS_N

36.5

R4L13

36.5

R4L15

11B6<

10B6<

5D7>

BI

11B6<

10B6<

5D7>

11B6<

10A6<

5D7>

BI

M_WE_N

11B6<

10B6<

5C7<>

BI

M_CKE<0>

36.5

R4L3

36.5

R4L4

36.5

R1A6

11B6<

10B6<

5B7<>

BI

M_CS_N<0>

11B6<

10B6<

5C7<>

BI

M_ODT<0>

INTEL CORPORATION
2111 NE 25TH AVENUE
HILLSBORO OR 97124

TITLE:

DOCUMENT NUMBER:

GALILEO Gen2

REV:

SDRAM TERMINATION
2

2.0

H38681

SHEET 12 OF 28
1

CR-13 : @GALILEO_LIB.GALILEO(SCH_1):PAGE13

MH1

MTG_HOLE_4V
1
3
4
5
6
D
D

CONN
MH2

MH4

MTG_HOLE_4V

MTG_HOLE_4V

1
3
4
5
6

V1P5_S0

1
3
4
5
6

PCIE SLOT 0

CONN

CONN

C3A25
0.1UF
10%
16V
X7R
0402LF

V3P3_S3

C3A26
0.1UF
10%
16V
X7R
0402LF

C3A1
22UF
20%
6.3V
X5R
0805LF

C3A2
0.1UF
10%
16V
X7R
0402LF

C3A7
0.1UF
10%
2 16V
X7R
0402LF
A36096-030

R2A1
1K
1%
CH
0402LF
1/16W

DYNAMIC CLK MANAGMENT OUTPUT

IS NOT SUPPORTED ON GALILEO

J2L1

MPCIE_52P_LATCH_KIT
FULL_MINI_CARD

+1.5V

+3.3VAUX

WAKE_N

CLKREQ_N

3
5

COEX1
COEX2

REFCLK+
REFCLK-

13
11

UIM_DATA
UIM_CLK
UIM_RESET
UIM_PWR
UIM_VPP

10
12
14
8
16

GND
GND
GND

REFCLK0_P
REFCLK0_N

IN
IN

6B2>
6B2>

USER IDENTITY MODULE (EXTENSION OF SIM)

NOT SUPPORTED BY QUARK

4
9
15

KEY
6B6<

OUT

WAKE_N

28
48

+1.5V
+1.5V

PETP0
PETN0

33
31

PCIE0_TX0_P
PCIE0_TX0_N

OUT
OUT

5B2>
5A2>

24
39
41
52

+3.3VAUX
+3.3VAUX
+3.3VAUX
+3.3VAUX

PERP0
PERN0

25
23

PCIE0_RX0_P
PCIE0_RX0_N

IN
IN

5B7<
5B7<

LED_WPAN_N
LED_WLAN_N
LED_WWAN_N

46
44
42

USB_D+
USB_D-

38
36

SMB_DATA
SMB_CLK

32
30

B
13A7<
13A6<

6C7<>
6C7<>

IN

WIFI_DISABLE_N

20

W_DISABLE_N

IN

PCIE_RESET_N

22

PERST_N

RESERVED PINS, NO CONNECT

17
19
45
47
49
51

RESERVED/UIM_C8
RESERVED/UIM_C4
RESERVED
RESERVED
RESERVED
RESERVED

MP1
MP2

V3P3_S3

V3P3_S3

R27
1K
5%
CH
0402LF
1/16W

MP1
MP2

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

18
21
26
27
29
34
35
37
40
43
50

USBH1_DP
USBH1_DN
SLT0_SDA
SLT0_SCL

BI
BI

7D3<>
7D3<>

R3A4
2
R3A3 I2C_SDA
1
2 I2C_SCL
0
0402LF EMPTY
0
0402LF EMPTY
1

BI
IN

6D2<> 20A2<>
20B4<>
6D2<> 20A2< 20B4<>

KIT_PARTS=(LATCH: QTY=1)

C59768-003
R52
1K
5%
CH
0402LF
1/16W

WIFI_DISABLE_N

6C7<>

13B6<

PCIE_RESET_N

6C7<>

13B6<

INTEL CORPORATION
2111 NE 25TH AVENUE
HILLSBORO OR 97124

TITLE:

DOCUMENT NUMBER:

GALILEO Gen2

REV:

MINI PCIE CONNECTOR

2

2.0

H38681

SHEET 13 OF 28
1

CR-14 : @GALILEO_LIB.GALILEO(SCH_1):PAGE14

V3P3_S0

U1L1
CM1230_02
D

B2

VP

A2

CH1

D
CH2

B1

VN

A1

CH2

B1

VN

A1

IC
U1L2
CM1230_02
TP25
T_POINT1

TP

B2

VP

A2

CH1

TP24

MICRO SD CONNECTOR

T_POINT1

TP

V3P3_S0

IC

CONN_SDCARD_8P_PP
J4A2

C
BI
BI
BI

CLN_SD_DAT<2>
CLN_SD_DAT<3>
CLN_SD_CMD

IN

CLN_SD_CLK

7B7<>
7B7<>

BI
BI

7B8<

OUT

7B7<>
7B7<>
7B8<>
19A7>

1
2

C1L1
1UF
10%
6.3V
X5R
0402LF

C1L2
1UF
10%
6.3V
X5R
0402LF

7B8>

33.2
33.2
33.2

R2L13 CH
R2L6 CH
R2L12 CH

CLN_SD_DAT2_R
CLN_SD_DAT3_R
CLN_SD_CMD_R

CLN_SD_DAT<0>
CLN_SD_DAT<1>

33.2
33.2

R2L7 CH
R2L8 CH

CLN_SD_DAT0_R
CLN_SD_DAT1_R

CLN_SD_CD_N

33.2

R2L5 CH

CLN_SD_CD_N_R

1
2
3
4
5
6
7
8

V3P3_S0

U1L3
CM1230_02

B2

VP

A2

CH1

CH2

B1

VN

A1

DAT2
CD/DAT3
CMD
VDD
CLK
VSS
DAT0
DAT1

9
10

CARD_DET_SW
CARD_DET_SW

G1
G2
G3
G4

G1
G2
G3
G4
CONN
G46739-001
B

V3P3_S0

IC
U1L4
CM1230_02

B2

VP

A2

CH1

CH2

B1

VN

A1

IC
7B8>

IN

SD_LED

SILKSCREEN:
SD ACTIVITY
DS4A2
2
1

R1L10
2
1K 1%
0402LF CH

LED_SD

GREEN
E16297-001

CAD NOTE:
PLACE SD LED CLOSE TO THE SDIO CONN

INTEL CORPORATION
2111 NE 25TH AVENUE
HILLSBORO OR 97124
GALILEO Gen2
TITLE:
MICRO SD CONNECTOR

DOCUMENT NUMBER:
REV:

2.0

H38681

SHEET 14 OF 28
1

CR-15 : @GALILEO_LIB.GALILEO(SCH_1):PAGE15

CAD NOTE:
PLACE C2B11 AS CLOSE AS
POSSIBLE TO U3B1 PIN5
V5_ALW_ON

VBUS1
LED_VBUS1

1 R2B15
10K
5%
2 CH
0402LF
1/16W

SOT23LF
U3B1

IN

USB HOST

R3B12
1K
0402LF

1%
CH
C2M7
100UF
20%
6.3V
X5R
1210LF

DS3B1
GREEN
LED

C3M11
47UF
20%
6.3V
X5R
0805LF

1
2

NOTE:
TYPE A CONN
J2B3
CONN

C3B14
470PF
10%
50V
X7R
0603LF

USB_PWR_EN0

IN
EN

OUT

OC_N

GND

MH1

USB_OC0_N

OUT

7C3<

1
2
3
4

USBH0_DN_CH
USBH0_DP_CH

CAD NOTE:
PLACE CHOKE AND DIODES CLOSE TO USB CONN
L3M2
90OHM

MH2

CHOKE_4P

R3B3 1
10K
5%
CH 2
0402LF
1/16W

CONN4_D23040001

TPS2051BDBVR

5
7C3>

V3P3_S0

C2B11
0.1UF
10%
2 16V
X7R
0402LF

IC
E58210-001

7D1<>

BI

USBH0_DN

7D1<>

BI

USBH0_DP

D23040-001

3
C

IND
E53905-001

V5_ALW_ON

U2B2
CM1230_02

B2

VP

A2

CH1

CH2

B1

VN

A1

IC
D30400-001

VCC_USB1

L3M1
90OHM

7D1<>

NOTE:
TYPE B CONN
J3B2

CHOKE_4P

7D1<>

USB CLIENT

BI

USBH2_DP

BI

USBH2_DN

3
IND
E53905-001

CAD NOTE:
PLACE CHOKE AND DIODES CLOSE TO USB CONN

MICRO_USB_5P_SMT

USBH2_DN_CH
USBH2_DP_CH

V5_ALW_ON

VCC

2
3

DD+

ID

GND

U2B3

B2

VP

A2

CH1

MT1
MT2
MT3
MT4
MT5
MT6

HDR
G58911-001

CM1230_02

MT
MT
MT
MT
MT
MT

CH2

B1

VN

A1

IC

INTEL CORPORATION
2111 NE 25TH AVENUE
HILLSBORO OR 97124

TITLE:

DOCUMENT NUMBER:

GALILEO Gen2

REV:

USB CONNECTORS
2

2.0

H38681

SHEET 15 OF 28
1

CR-16 : @GALILEO_LIB.GALILEO(SCH_1):PAGE16

D
D

V3P3_S5

V3P3_S5

CR1

R81
22K
5%
0402LF
~1/16W

BAT15

SOT23C

DIO
C

7A7>
21C3<

21B3<
7A7>
7A7<

IN

UART1_RTS_N

OUT
IN
OUT

UART1_RXD_MUX
UART1_TXD
UART1_CTS_N

R40
240

J3

1X6HDR
1%

R41
240

1%

UART1_RTS_N_R
R42
240
R43
240

1%
1%

UART1_RXD_MUX_R
UART1_TXD_R
UART1_CTS_N_R

1
2
3
4
5
6

HDR

R80
0
0
EMPTY
0402LF
1/20W

V3P3_S5
B

R2L1
1K
1%
EMPTY
0402LF
1/16W

V3P3_S5
J2
CONN

conn_2x5_shrd_male

C4A1
0.1UF
10%
2 16V
X7R
0402LF

1
3
5
7
9

1
3
5
7
9

2
4
6
8
10

2
4
6
8
10

H32748-001

R1L1
1K
1%
EMPTY
0402LF
1/16W

R1L3
1K
1%
CH
0402LF
1/16W

R1L5
33.2 1%
R1L7
33.2 1%

JTAG_TMS_R
JTAG_TCK_R
JTAG_TDO
JTAG_TDI
JTAG_TRST_N

JTAG_TMS

OUT

6C2<

JTAG_TCK

OUT

6C2<

6C2>
IN
OUT 6C2<
OUT 6C2<

R1L2
1K
1%
EMPTY
0402LF
1/16W

CAD NOTE:
PLACE CONNECTOR ON SOLDER-SIDE.

INTEL CORPORATION
2111 NE 25TH AVENUE
HILLSBORO OR 97124

TITLE:

DOCUMENT NUMBER:

GALILEO Gen2

REV:

UART 1 & JTAG

2.0

H38681

SHEET 16 OF 28
1

CR-17 : @GALILEO_LIB.GALILEO(SCH_1):PAGE17

V3P3_S0_A

V3P3_S0

V5_ALW_ON

1 R4B1
4.7K
5%
2 CH
0402LF
1/16W

1 R4B2 1 R4B3
1.5K
1.5K
1%
1%
2 CH
2 CH
0402LF
0402LF
1/16W
1/16W

R1M3
2.2K
5%
CH
0402LF
1/16W

VSHLD_S5

J1A6

PLACE NEAR ETHERNET PORT.

PIN3 SILK= +3.3V

V3P3_S5

V3P3_S0_A

V3P3_S0
1 C1M8
1UF
10%
2 X5R
0402LF

C1M7
0.1UF
10%
2 X7R
0402LF

PIN1 SILK= +5V

HDR

V3P3_S0_A

CAD NOTE:

1X3HDR
1
2
3

FB1M1
2
FB

V3P3_S0

AGND_VCC

RMII_S0_MDC

17C4<

R1M9
49.9
1%
CH
0402LF

C1M9
0.1UF
10%
2 X7R
0402LF

R1M7
49.9
1%
CH
0402LF

RMII_S0_RDP
RMII_S0_TDN
RMII_S0_TDP

BI

17A3<>

BI
17A3<>

17C5<>

17C7>

BI

17B7<>
17B8<>

17A3<>

BI
17A3<>

IN

17C2>

17C2<>

IN

RMII_S0_PFB

17A3<>
17A3<>

7C2>
7B2>
7C2>

7B2>

IN
IN
IN
IN

RMII_S0_TX_EN
RMII_S0_TXD0
RMII_S0_TXD1

IN

RMII_S0_MDC

RMII_S0_TDN
BI
RMII_S0_TDP
BI
R4B4
2
1 PHY_RBIAS
4.87K 1%
0402LF CH
17B6< RMII_I_X1

C1M3
C1M5
0.1UF
0.1UF
10%
10%
X7R 2 2 X7R
0402LF
0402LF

17C2<>

17C5<>

CAD NOTE:

PLACE RESISTOR AND

CAPAS CLOSE TO RMII PHY

RMII_REF_CLK_OUT

1
2
22.6 1%
0402LF

R3A6

R3A7
1
2
22.6 1%

VIN_POE

RMII_VC3

17A4<

U16
EMPTY

RMII_VC4
RMII_VC1
1

17A4<
17A4<

RMII_VC2

D2
esd_diode
SMAJ58CA

R44
0
5%
EMPTY
0402LF
1/16W

1
2
3
4
5
6

VA1
VA2
VB1
VB2
CP1
CP2

ADJ

VPOE_ADJ

0 5%
0402LF EMPTY

14
15

TDTD+

20
16
30

RBIAS
PFBIN1
PFBIN2

28
27

X1
X2

13
17

AGND
AGND

VDC

RMII_REFCLK

OUT

NC
GND

10
7

ETH_BLINK
RMII_S0_RX_DV_R

24

RMII_S0_MDIO

BI

7B2<>

RDRD+

11
12

RMII_S0_RDN
RMII_S0_RDP

BI
BI

17A3<>
17A3<>

PFBOUT

19

RMII_S0_PFB

LED_SPEED/AN1
LED_LINK/AN0

21
22

LED_SPEED
LED_LINK

DGND
IOGND
THPAD

29
40
41

33.2
33.2
33.2

RMII_S0_RXD0_R
RMII_S0_RXD1_R

R2M13 CH
R2M10 CH

RMII_S0_RXD0
RMII_S0_RXD1

OUT

7B2<

OUT
OUT

7B2<
7B2<

17C6<>

17C6<>
17B7<>

OUT

17C5<

17A1<
17A1<

1 C4B5
10UF
10%
16V
2 TANT
0805LF
G63888-001

C1M4
0.1UF
10%
2 X7R
0402LF

LED SIGNALS HAVE INTERNAL PU

CAD NOTE:

PLACE CAPACITORS CLOSE TO PFBOUT(PIN23)

R1M6
2
00
0603LF CH

V3P3_S0

7C3<

DESIGN NOTE:

C44
470UF
20%
16V
10MMLF

J4B1
SINGATRON_2TJ582_010111H

C1M12
0.1UF
10%
2 X7R
0402LF

U16 IS DESIGNED FOR SILVERTEL

AG9712S COMPONENT.

17C6<>
17A8<>

RMII_VC4

17A8<>

RMII_VC3

17A8<>

RMII_VC1

17A8<>

RMII_VC2

AGND_VCC

RMII PHY

R2M15
4.7K
5%
CH
0402LF
1/16W

8
R47
620
1206LF
1/2W

17D6>
IN
CH
RMII_S0_RX_DV
R2M9

33
32
31
35
36
37
38
39

TBD
R45

CRS/CRS_DV/LED_CFG
RESET_N RX_DV/MII_MODE
TX_CLK
RX_CLK
TX_EN
COL/PHYADO
TXD_0
RXD_0/PHYAD1
TXD_1
RXD_1/PHYAD2
TXD_2
RXD_2/PHYAD3
TXD_3
RXD_3/PHYAD4
RX_ER/MDIX_EN
MDC
MDIO

2.2K 5%
0402LF CH

8
9
10

RMII_I_X1

LENGHT MATCH CLOCK SPLIT. TRACE BETWEEN PIN 1 OF RESISTORS SHOULD BE SHORT

D1
esd_diode
SMAJ58CA

23
2
3
4
5
6
7
34
25

RESERVED
RESERVED
RESERVED

H31881-001

CAD NOTE:

17A4<

IOVDD
AVDD33
IOVDD33

AGND_VCC
17C4<

6A2>

19B6>
19B7>

C1M1
0.1UF
10%
2 X7R
0402LF

R1M8
49.9
1%
CH
0402LF

RMII_S0_RDN

17C7>

RMII_S0_RST_N

dp83848j

1
18
26

17C2<>

PLACE CAPACITORS C1M3 & C1M5 CLOSE TO PFBIN(PIN18&37)

7B2>

OUT

CAD NOTE:

V3P3_S0

R1M10
49.9
1%
CH
0402LF

17C4<
7B2<>

OUT
BI

17C2<

R1

FB1

17B8<>
17C5<>
17B7<>
17C5<>
17B7<>
17C2<>
17C2<>

RMII_S0_CT1

BI

RMII_S0_TDP

D1+

J1

BI

RMII_S0_TDN

D1-

J2

BI

RMII_S0_RDP

D2+

J3

BI

RMII_S0_RDN

D2-

RMII_VC4_R

10

VC4

RMII_VC3_R

VC3

FB FB3
FB

FB2

MMZ2012R102A
1K-OHM 0.5A

FB

FB4

FB

CT

GND

VC1

RMII_VC2_R

VC2

V3P3_S0
L2

LED_SPEED

L1

LED_RJ45_C1

J6

L4

LED_LINK

J4

L3

LED_RJ45_C2

J5

RMII_VC1_R

YELLOW

RMII_S0_RST_N
RMII_S0_MDIO

OUT

U4B1
IC

GREEN

RMII_S0_RX_DV_R

1 C1M6
C1M10
C1M2
1UF
0.1UF
0.1UF
10%
10%
10%
2 X5R
2 X7R
2 X7R
0402LF
0402LF
0402LF

17C2<

R1M1
110

1%

17C2<

R1M2
110
0402LF

J7

J8

MH1
MH2

11
12

CONN

R46
0 5%
0402LF EMPTY

INTEL CORPORATION
2111 NE 25TH AVENUE
HILLSBORO OR 97124

TITLE:

1%
CH

DOCUMENT NUMBER:

GALILEO Gen2

REV:

LAN

2.0

H38681

SHEET 17 OF 28
1

CR-18 : @GALILEO_LIB.GALILEO(SCH_1):PAGE18

V3P3_S0
CR3M1
2
VCC_FLASH

3
VCC_DEDIPROG

BAT54C
SOT23C
DIO

J1B2
2X4HDR7

1
3
5

C4M5
0.1UF
10%
2 16V
X7R
0402LF

19B1>

2
4
6
8

2
6C6>

6C6>

HDR
A91836-079

C4M6
4.7UF
10%
2 6.3V
X5R
0603LF

IN

IN

1
R3M15
4.7K
5%
CH
0402LF

19A6>

6C6>

IN

U2B4

R2B5
1
2
33.2 1%
0402LF CH

LSPI_MOSI_R

W25Q64FV_8P

R2B6
1
2
33.2 1%
0402LF CH

LSPI_CS_N_R

LSPI_CS_N HAS INTERNAL 20K PU IN QUARK

C

R4M2
4.7K
5%
CH
0402LF

VCC

AT25_WP_N

WP_N

LSPI_CS_N

CS_N

LSPI_MOSI

DI

LSPI_SCK

CLK

AT25_HOLD_N

HOLD_N

R2B18
1
2
33.2 1%
0402LF CH

LSPI_SCK_R

DO

GND

R2B10
1
2
33.2 1%
0402LF CH

LSPI_MISO_R

LSPI_MISO

6C6<

OUT

IC
H10285-001

FLASH
BIOS STORAGE
V5_ALW_ON

FB5
.28A
120
FB
V5_ALW_ON_FIL

V3P3_S0

1
B

R2B30
10K
5%
CH
0402LF

C5
1UF
20%
10V
X5R
0402LF

C2B1
0.1UF
10%
16V
X7R
0402LF

CAD NOTE:
PLACE DECOUPLING CAPACITORS AS CLOSE AS POSSIBLE TO ADC

C3M9
1UF
20%
10V
X5R
0402LF

C3M10
0.1UF
10%
16V
X7R
0402LF

U11
IC
2
13

24B2<>
24B2<>
24B2<>
24B2<>

20B5>
20B5>
20B5>
20B5>
24C8>
24C8>

IN
IN
IN
IN
IN
IN

22
22
22
22
22
22

ANALOG_A0
ANALOG_A1
ANALOG_A2
ANALOG_A3
AVIN4
AVIN5

R1A11
R1A16
R1A13
R1A10
R1A1
R1A7

19D5>
19D7>

6B7>
IN
ANALOG_A0_R
ANALOG_A1_R
ANALOG_A2_R
ANALOG_A3_R
AVIN4_R
AVIN5_R

C38
0.001UF
10%
10V
X5R
0402LF

C39
0.001UF
10%
10V
X5R
0402LF

C40
0.001UF
10%
10V
X5R
0402LF

C41
0.001UF
10%
10V
X5R
0402LF

6D7>
6D7>

IN
IN

C42
0.001UF
10%
10V
X5R
0402LF

SPI0_SCK
SPI0_MOSI
SPI0_CS_N

C43
0.001UF
10%
10V
X5R
0402LF

adc108s102
VA
VD

16
14
1

SCLK
DIN
CS_N

4
5
6
7
8
9
10
11

IN0
IN1
IN2
IN3
IN4
IN5
IN6
IN7

DOUT

15

AGND
DGND

3
12

SPI0_MISO_R

33.2

R3M11

CH

SPI0_MISO

6D7<

OUT

H31902-001

INTEL CORPORATION
2111 NE 25TH AVENUE
HILLSBORO OR 97124
GALILEO Gen2
TITLE:
SPI: ADC&FLASH

DOCUMENT NUMBER:
REV:

2.0

H38681

SHEET 18 OF 28
1

CR-19 : @GALILEO_LIB.GALILEO(SCH_1):PAGE19

V3P3_S0

TP23

V3P3_S0

R2B16
10K
1%
CH
0402LF
1/16W
SPI0_MOSI

6D7>

OUT

R2B12
10K
1%
CH
0402LF
1/16W

SPI0_SCK

OUT

6D7>

SPI1_MOSI

18B4<

R2B19
10K
1%
CH
0402LF
1/16W

SILK=FWR
DESIGN NOTE:
SHORT TO GND TO ENTER
RECOVERY MODE.

V3P3_S0

R3M9
10K
1%
EMPTY
0402LF
1/16W

18A4<

OUT

6D7>

21C6<

R2B17
10K
1%
EMPTY
0402LF
1/16W

BIT1

OUT

6C7>

RMII_S1_TXD0

21D3<

(LOW) PUNIT BASE ADDRESS

(LOW) MEMORY DOWN CONFIG

01 - 1GBIT SDRAM

7B4>

OUT

R3A17
10K
1%
CH
0402LF
1/16W

R3M7
10K
1%
EMPTY
0402LF
1/16W

BIT0

(HIGH) X8 DDR SDRAM

SPI1_SCK

V3P3_S0

R4B8
10K
1%
CH
0402LF

RMII_S0_TXD1

OUT

7C2>

RMII_S0_TXD0

17C4<

R4B6
100K
1%
CH
0402LF
1/16W

OUT

7B2>

RMII_S1_TXD1

17C4<

R4B5
100K
1%
EMPTY
0402LF
1/16W

OUT

LSPI_MOSI_R

7B4>

R3A14
10K
1%
CH
0402LF
1/16W

CLN_SD_CLK

OUT

BIT0

BIT1
000 - QUARK SKU SETTINGS

7B8>

LSPI_SCK_R

14C6<

OUT

6C6>

EC_PWRBTN_N

18C6<

6B6<

OUT

R3A10
10K
1%
CH
0402LF
1/16W

R2B13
10K
1%
CH
0402LF
1/16W

(LOW) POWER BUTTON NOT USED

BIT1
BIT0
00 - REMOVABLE CARD SLOT FOR SDIO

INTEL CORPORATION
2111 NE 25TH AVENUE
HILLSBORO OR 97124

TITLE:

18D6<

(LOW) SINGLE RANK DDR3 SDRAM

R1L11
10K
1%
CH
0402LF
1/16W

6C6>

R2B4
10K
1%
CH
0402LF
1/16W

BIT2

OUT

DOCUMENT NUMBER:

GALILEO Gen2

REV:

QUARK STRAPS

2.0

H38681

SHEET 19 OF 28
1

CR-20 : @GALILEO_LIB.GALILEO(SCH_1):PAGE20

VSHLD_S5

VSHLD_S5

R3
4.7K
5%
EMPTY
0402LF
1/16W

VSHLD_S5
U1
IC

21
20C6<

20B8<
24C6<>
20B8<>
24C6<>

20C6<>

20B2<>
20D3<
20B2<>
20D3<>

BI

LVL_I2C_SCL

BI

LVL_I2C_SDA

19
20

C1
0.1UF
10%
16V
X7R
0402LF

24
23
18

VSHLD_S5
9
25

R59
22K
R51 5%
22K CH
5%
CH

R67
22K
5%
R64 CH
22K
5%
CH
R69
R61
22K
22K
5%
5%
CH
CH

PCAL9535AHF

P0_0
P0_1
SCL
P0_2
SDA
P0_3
P0_4
P0_5
P0_6
P0_7
P1_0
A2
P1_1
A1
P1_2
A0
P1_3
P1_4
P1_5
P1_6
VSS
P1_7
THPAD INT_N
VDD

H47895-001

R72
22K
5%
R71 CH
22K
5%
CH
LVL_B_OE0_N
LVL_B_OE1_N
LVL_B_OE2_N
LVL_B_OE3_N
LVL_B_OE4_N
LVL_B_OE5_N
LVL_B_OE6_N
LVL_B_OE7_N

EXP0

1
2
3
4
5
6
7
8
10
11
12
13
14
15
16
17
22

21

20B2<>
20B2<>
24C6<>

LVL_I2C_SCL
LVL_I2C_SDA

19
20

C3
0.1UF
10%
16V
X7R
0402LF

24
23
18

VSHLD_S5
9
25

R63
R70
22K
22K
5%
5%
R60 CH
R68 EMPTY
22K
22K
5%
5%
CH
R66 EMPTY
R57
22K
MUX5_SEL
22K
5%
MUX7_SEL
5%
EMPTY
CH
MUX8_SEL
R50
LVL_C_OE0_N
22K
5%
LVL_C_OE1_N
CH
LVL_C_OE2_N
LVL_C_OE5_N
R73
22K
5%
CH R74
22K
5%
CH

OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT

20C7<
22D6<
20C7<
22D6<
20C7<
22D6<
20C7<
22D6<
20C7<
22A6<
20C7<
22A6<
20C7<
22A6<
20C7<
22B6<

20D8<>
20D3< 20B8<
20D8<>
20D3<>
20B8<>

22C7<

22D3<>

22C3<>

22C7<

22C3<>

22C7<

22C3<>

22C7<

22B3<>

22B7<

22B3<>

22B7<

22A3<>

22B7<

22A3<>

22B7<

20B2<>
20B2<>
24C6<>

24C6<>
20D8<>
20C6<>
20B8<>
24C6<>
20D8<>
20C6< 20B8<

PCAL9535AHF

P0_0
P0_1
SCL
P0_2
SDA
P0_3
P0_4
P0_5
P0_6
P0_7
P1_0
A2
P1_1
A1
P1_2
A0
P1_3
P1_4
P1_5
P1_6
VSS
P1_7
THPAD INT_N

H47895-001

EXP2

20C3>
20C3>
20C3>
20C4>
20C4>
20C4>
20C3>

21B6<
21A6<
21D3<
23C5< 23D2<>
23C2<>
23C5<
23C2<>
23C5<
23B2<>
23C5<

1
2
3
4
5
6
7
8
10
11
12
13
14
15
16
17
22

R8
4.7K
5%
EMPTY
0402LF

VSHLD_S5
U3
IC
PCAL9535AHF

21

LVL_I2C_SCL
LVL_I2C_SDA

19
20

C4
0.1UF
24
10%
16V
23
X7R
0402LF 18

9
25

EXP1_INT

LVL_C_OE0_N
LVL_C_PU0
LVL_C_OE1_N
LVL_C_PU1
LVL_C_OE2_N
LVL_C_PU2

1
2
3
4
5
6
7
8
10
11
12
13
14
15
16
17
22

P0_0
P0_1
SCL
P0_2
SDA
P0_3
P0_4
P0_5
P0_6
P0_7
P1_0
A2
P1_1
A1
P1_2
A0
P1_3
P1_4
P1_5
P1_6
VSS
P1_7
THPAD INT_N
VDD

20A7< 23C5< 23D2<>

23D5<
20A7< 23C2<>
23C5<
23D5<
20A7< 23C2<>
23C5<
23D5<

OUT
OUT
OUT
OUT
OUT
BI

IO7_PU

20A5<

IO8_PU
LVL_C_OE5_N
LVL_C_PU5
MUX5_SEL
MUX7_SEL
MUX8_SEL
SW_RESET_N_SHLD

20A4<

IO7
IO8

OUT
OUT
OUT
OUT
OUT

20A7<
23B5<
20A7<
20A7<
20A7<
20A5<

23B2<>

OUT

24C3<>

ANALOG_A0R
ANALOG_A1R
ANALOG_A2R
ANALOG_A3R
AMUX2_NO1_R
AMUX2_NO2_R

22K
0402LF
22K
0402LF
22K
0402LF
22K
0402LF
22K
0402LF
22K
0402LF

MUX_IO2
MUX_IO3
RESET_N_SHLD
EXP2_INT

R7
0
5%
CH
0402LF
1/16W

OUT
OUT

SW_RESET_N_SHLD

R34
R35
R36
R37
R2
R38

20A5<
6B7<

OUT

18A7<

24B2<>

ANALOG_A1

OUT

18A7<

24B2<>

ANALOG_A2

OUT

18A7<

24B2<>

ANALOG_A3

OUT

18A7<

24B2<>

AMUX2_NO1

OUT

24C8<>

AMUX2_NO2

OUT

AMUX1_IN

OUT
0

24A5<>
24A6<>

24C8<>
24C6<
20A5<

R26
CH

R10
CH

R62
22K
5%
CH
0402LF
1/16W

AMUX1_IN
RESET_N_SHLD

24
23

SDA
SCL

20

OE_N

22

EXTCLK

26
27
28
1
2
21

AO
A1
A2
A3
A4
A5

11
29

VSS
THPAD

24C3<>
20B5>

20B5>

3
4
5
6

MUX0_SEL
MUX0_I1
MUX1_SEL
MUX1_I1

OUT
OUT
OUT
OUT

21D8<
21D8<
21C8<
21C8<

LED4
LED5
LED6
LED7

7
8
9
10

MUX2_SEL
MUX2_I1
MUX3_SEL
MUX3_I1

OUT
OUT
OUT
OUT

21B8<
21B8<
21A8<
21A8<

LED8
LED9
LED10
LED11

12
13
14
15

MUX4_SEL
MUX4_I1
MUX6_SEL
MUX6_I1

OUT
OUT
OUT
OUT

21C6<
21C6<
21A6<
21B6<

LED12
LED13
LED14
LED15

16
17
18
19

MUX9_SEL
MUX10_SEL
AMUX2_IN1
AMUX2_IN2

OUT
OUT
OUT
OUT

21C3<
21B3<
24C8<
24C8<

OUT

20A4<

24C3<>

21B6<
21A6<
21D3<

VSHLD_S5

20A2<

13B2<

6D2<>

BI

20A2<>

13B2<>

6D2<>

BI

OUT
OUT

23C3<>
22C4<>

24C3<>
24C3<>

IO2
IO3

R5
1.8K
5%
CH
0603LF
1/10W

I2C_SCL
Q1L2
FET
I2C_SDA

Q1L1
FET

R6
1.8K
5%
CH
0603LF
1/10W
LVL_I2C_SCL

BI

20B8<

LVL_I2C_SDA

BI

20B8<>

20C6<

20D3<

20C6<>

20D8<>

20D3<>

20C3>

24C6<

24A5<>

20C4<>

IO7_PU

IO7

R31
22K
5%
CH
0402LF
1/16W

C12
0.1UF
10%
16V
X7R
0402LF

IO8_PU
20B4<>
13B2<
20B4<>
13B2<>

R32
22K
5%
CH
0402LF
1/16W

20C3> IO8
24C3<>

24C6<>

6D2<>
6D2<>

R33
10K
5%
CH
0402LF
1/16W

I2C_SCL
I2C_SDA

U8
IC
cat24c08hu4i

VCC

6
5
3
7

SCL
SDA
A2
WP

NC
NC

2
1

VSS
THPAD

4
9

H31877-001

24A6<>

TITLE:

V3P3_S0

2111 NE 25TH AVENUE

HILLSBORO OR 97124

24C6<>

20D8<>

INTEL CORPORATION

20C4<>

20C4<>

R65
22K
5%
CH
0402LF
1/16W

VDD

V3P3_S5

VSHLD_S5

R75
22K
5%
CH

LED0
LED1
LED2
LED3

pca9685

25

23C5<

EXP1

ANALOG_A0

U4
IC

H29123-001
20A5<

H47895-001

R4
4.7K
5%
CH
0402LF
1/16W

VDD

LVL_I2C_SDA
LVL_I2C_SCL

20B2<>
20B2<>

VSHLD_S5

20D6> 22C7< 22D3<>

20D6> 22C3<>
22C7<
20D6> 22C3<>
22C7<
20D6> 22C3<>
22C7<
20D6> 22B3<>
V3P3_S0
22B7< 20C6> 22B3<>
20C6> 22B7<
22A3<>
22B7< 20C6> 22A3<>
22B7<

U2
IC

20D8<>
20D3< 20C6<
20D8<>
20D3<>
20C6<>

EXP0_INT

24C6<>

VSHLD_S5

24C6<>

C6
0.1UF
10%
16V
X7R
0402LF

LVL_B_OE0_N
LVL_B_PU0
LVL_B_OE1_N
LVL_B_PU1
LVL_B_OE2_N
LVL_B_PU2
LVL_B_OE3_N
LVL_B_PU3
LVL_B_OE4_N
LVL_B_PU4
LVL_B_OE5_N
LVL_B_PU5
LVL_B_OE6_N
LVL_B_PU6
LVL_B_OE7_N
LVL_B_PU7

DOCUMENT NUMBER:

GALILEO Gen2

REV:

EXTERNAL IO MUXING 1
2

2.0

H38681

SHEET 20 OF 28
1

CR-21 : @GALILEO_LIB.GALILEO(SCH_1):PAGE21

V3P3_S5

I1

U9
74LVC1G157
REV=1
VCC

I0

22D2>

20D1>
6C7<>
20D1>

IN

MUX0_I1

IN

MUX0_I0

IN

MUX0_SEL

GND

IC

MUX0

V3P3_S5

MUX0_Y

21C3<

V3P3_S5

C14
0.1UF
10%
16V
X7R
0402LF

V3P3_S5

20D1>

IN

MUX1_I1

IN

MUX1_I0

I1

20D1>

IN

MUX4_I1

I1

U19
74LVC1G157
REV=1
VCC

21B4>

MUX5_Y

I0

IN

MUX4_SEL

GND

6C7<>
20D1>

IN

MUX1_SEL

I0
S

GND

IC

MUX1

MUX1_Y
C15
0.1UF
10%
16V
X7R
0402LF

22C2>

6C7<>
20D1>

IN

MUX2_I1

I1

IN

MUX2_I0

I0

IN

MUX2_SEL

GND

5
4
2

IC

MUX2

MUX2_Y

MUX3_I1

I1

22C2>

6C7<>

IN

MUX3_I0

20D1>

IN

MUX3_SEL

REV=1

VCC

I0

GND

IC

MUX3

22B2>

6C7<>

20C3>

20A7<

IN

SPI1_MOSI

I1

IN

MUX5_I0

I0

IN

MUX5_SEL

GND

I1

22A2>

6C7<>

IN

MUX8_I0

I0

20C3>

20A7<

IN

MUX8_SEL

GND

MUX4_Y

OUT

OUT

16C5<

IC

22B2>

OUT

IN

MUX6_I1

I1

6B7<>

IN

MUX6_I0

20C1>

IN

MUX6_SEL

REV=1

VCC

I0

GND

MUX6

22C8<

C17
0.1UF
10%
16V
X7R
0402LF

IC

UART1_TXD

I1

21D6>

MUX0_Y

I0

IN

MUX9_SEL

GND

MUX9_Y

OUT

22C8<

OUT

7A7<

C26
0.1UF
10%
16V
X7R
0402LF

23C7<

6C7<>

IN

LVL_C_A1

I1

16C5>

IN

UART1_RXD_MUX

I0

MUX10_SEL

IN

GND

UART1_RXD

C27
0.1UF
10%
16V
X7R
0402LF

IC

MUX10
OUT

IN

UART0_TXD

I1

6B7<>

IN

MUX7_I0

I0

20A7<

IN

MUX7_SEL

GND

7B7>
22A2>
20C3>

MUX7

22B8<

C23
0.1UF
10%
16V
X7R
0402LF

IC

5
MUX7_Y

OUT

22B8<

C24
0.1UF
10%
16V
X7R
0402LF

INTEL CORPORATION
2111 NE 25TH AVENUE
HILLSBORO OR 97124

TITLE:

V3P3_S5
U22
74LVC1G157
REV=1
VCC

22B8<

C25
0.1UF
10%
16V
X7R
0402LF

IC

U25
74LVC1G157
REV=1
VCC

20C1>

MUX6_Y

OUT

V3P3_S0

U21
74LVC1G157
20C1>

IN

21C5<

V3P3_S5

MUX3_Y

7A7>

U24
74LVC1G157
REV=1
VCC

MUX9

23D2<>

MUX8_Y

V3P3_S5

20C1>

C22
0.1UF
10%
16V
X7R
0402LF

22B8<

C20
0.1UF
10%
16V
X7R
0402LF

MUX5_Y

IC

MUX8

22C8<

C16
0.1UF
10%
16V
X7R
0402LF

U14
74LVC1G157
IN

6D7>

U20
74LVC1G157
REV=1
VCC

MUX5

V3P3_S5

20D1>

V3P3_S5

V3P3_S5

20D1>

SPI1_SCK

22C8<

OUT

19D4>

U13
74LVC1G157
REV=1
VCC

IC

MUX4

C
22D2>

IN

19D3>

20C1>

U10
74LVC1G157
REV=1
VCC

6C7>

U23
74LVC1G157
REV=1
VCC

DOCUMENT NUMBER:

GALILEO Gen2

REV:

EXTERNAL IO MUXING 2
2

2.0

H38681

SHEET 21 OF 28
1

CR-22 : @GALILEO_LIB.GALILEO(SCH_1):PAGE22

EU3
IC
74LVC126A

1
20D6>
20D6>
20D6>
20D6>

LVL_B_PU3
LVL_B_PU2
LVL_B_PU1
LVL_B_PU0

IN
IN
IN
IN

LVL_B_OE0_N

LVL_B_OE1_N

4
21C1>
21C6>
21B6>
21A6>
21C3>
21B3>
21A3>
21D1>

IN
IN
IN
IN
IN
IN
IN
IN

MUX9_Y
MUX1_Y
MUX2_Y
MUX3_Y
MUX4_Y
MUX6_Y
MUX7_Y
MUX8_Y

22D3<>

U17
IC
20
2
3
4
5
6
7
8
9
1
19

22C3<>

sn74lv541at
VCC
A1
A2
A3
A4
A5
A6
A7
A8
OE1_N
OE2_N

20D6>

20C7<
20C7<

20D6> 20C7<
22C3<>
22C3<>
20D6> 20C7<

Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8

18
17
16
15
14
13
12
11

GND
THPAD

10
21

H31894-001
B

20D6>

IN

LVL_B_OE0_N

IN

LVL_B_OE1_N

IN

LVL_B_OE2_N

IN

LVL_B_OE3_N

BUF_IO3
BUF_IO5
BUF_IO6
BUF_IO9
BUF_IO11
BUF_IO10
BUF_IO1
BUF_IO13
OUT 23B7<
20C7<
20D6>
22B3<>
IN
20C6>
20C7<
22B3<>

VCC

1
2
4
5
10
9
13
12

1OE_N
1A
2OE_N
2A
3OE_N
3A
4OE_N
4A

IO3

2Y

IO5

3Y

IO6

11
7
15

IO9

H29265-001

LVL_B_OE4_N

IN

LVL_B_OE5_N

22A3<>

20C7<

20C6>

IN

LVL_B_OE6_N

22A3<>

20C7<

20C6>

IN

LVL_B_OE7_N

sn74lv125a

VCC

1
2
4
5
10
9
13
12

1OE_N
1A
2OE_N
2A
3OE_N
3A
4OE_N
4A

BI
BI

24D3<>
24C3<>

BI
BI

24D3<>
24A1> 24D3<>

IO11

2Y

IO10

3Y

IO1

11
7
15

IO13

C30H29265-001
0.1UF
10%
16V
X7R
0402LF
IN
IN
IN
IN

LVL_B_PU7
LVL_B_PU6
LVL_B_PU5
LVL_B_PU4

R20
22K
5%
CH
0402LF
1/16W

R23
R25
22K
22K
5%
5%
CH
CH
0402LF 0402LF
1/16W 1/16W

LVL_B_OE2_N

BI
BI

MUX3_I0

11

20C7<

20D6>

21C8<
22C7<

6C7<>

OUT
20C7<

20D6>

21B8<
22C7<

LVL_B_OE3_N

6C7<>

OUT
20C7<

20D6>

C88413-002
VCC=V3P3_S0;GND=GND;TH=GND
EU2
IC
74LVC126A

MUX5_I0

LVL_B_OE4_N

OUT
20C7<

21A8<
22C7<

6C7<>
20D6>

C88413-002
VCC=V3P3_S0;GND=GND;TH=GND

21B6<
22B7<

EU2
IC
74LVC126A

24D3<>
24A5<>
24C3<>

MUX6_I0

LVL_B_OE5_N

OUT
20C6>

6B7<>
20C7<

C88413-002
VCC=V3P3_S0;GND=GND;TH=GND

21B6<
22B7<

EU2
IC
74LVC126A
V3P3_S0

C32
0.1UF
10%
16V
X7R
0402LF

MUX7_I0

8
10

20C6>
20C6>
20C6>
20C6>

R18
22K
5%
CH
0402LF
1/16W

6C7<>

OUT

C88413-002
VCC=V3P3_S0;GND=GND;TH=GND

12

1Y

4Y
GND
THPAD

22C7<

EU3
IC
74LVC126A

U15
IC
14

MUX2_I0

24C3<>
20B4>
24C3<>

BI
BI

1Y

4Y
GND
THPAD

21D8<

EU3
IC
74LVC126A

R24
22K
5%
CH
0402LF
1/16W

C28
0.1UF
10%
16V
X7R
0402LF

sn74lv125a

14

R22
22K
5%
CH
0402LF
1/16W

20D6>

C88413-002
VCC=V3P3_S0;GND=GND;TH=GND

U18
IC

R21
22K
5%
CH
0402LF
1/16W

MUX1_I0

10

V5_ALW_ON

R17
22K
5%
CH
0402LF
1/16W

20C7<

C88413-002
VCC=V3P3_S0;GND=GND;TH=GND

13

C29
0.1UF
10%
16V
X7R
0402LF

6C7<>

OUT

EU3
IC
74LVC126A

C31
0.1UF
10%
16V
X7R
0402LF

VSHLD_S5

MUX0_I0

V3P3_S0

LVL_B_OE6_N

OUT
20C6>

6B7<>
20C7<

C88413-002
VCC=V3P3_S0;GND=GND;TH=GND

21A6<
22B7<

EU2
IC
74LVC126A
12

MUX8_I0

13

11

LVL_B_OE7_N

OUT

6C7<>

21D3<

20C6>

20C7<

22B7<

C88413-002
VCC=V3P3_S0;GND=GND;TH=GND

INTEL CORPORATION
2111 NE 25TH AVENUE
HILLSBORO OR 97124

TITLE:

DOCUMENT NUMBER:

GALILEO Gen2

REV:

LVL B BUFFER

2.0

H38681

SHEET 22 OF 28
1

CR-23 : @GALILEO_LIB.GALILEO(SCH_1):PAGE23

EU4
IC
74LVC126A

LVL_C_PU2
LVL_C_PU1
LVL_C_PU0

IN
IN
IN

23D2<>
7B7<
23D2<>
21B3<
23C2<>
23B1<

6C7<

6B7<
6C7<>
6C7<>

IN
IN
IN

UART0_RXD
LVL_C_A1
LVL_C_A2

6C7<>
22B6>

IN
IN

SPI1_MISO
BUF_IO13

23D2<>

U12
IC
20
2
3
4
5
6
7
8
9
1
19

sn74lv541at
VCC
A1
A2
A3
A4
A5
A6
A7
A8
OE1_N
OE2_N

Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8

18
17
16
15
14
13
12
11

GND
THPAD

10
21

20C4>

20A7<

IN

LVL_C_OE0_N

23C2<>

20C4>

20A7<

IN

LVL_C_OE1_N

23C2<>

20C4>

20A7<

IN

LVL_C_OE2_N

23B2<>

20C3>

20A7<

IN

LVL_C_OE5_N

BUF_IO0
BUF_IO2
BUF_IO4

sn74lv125a

14

VCC

1
2
4
5
10
9
13
12

1OE_N
1A
2OE_N
2A
3OE_N
3A
4OE_N
4A

IO0

2Y

IO2

3Y

IO4

CAD NOTE:
PLACE AT LED AREA

IO13_LED_R

20C3>

IN

23C7<

LVL_C_OE1_N
20A7<
C88413-002
VCC=V3P3_S0;GND=GND;TH=GND

20C4>

23C5<

LVL_C_A2

6C7<>

23C7<

LVL_C_OE2_N
20A7<
C88413-002
VCC=V3P3_S0;GND=GND;TH=GND

20C4>

23C5<

EU4
IC
74LVC126A

H31894-001
R2A3
330
5%
CH
0402LF
1/16W

21B3<

24C3<>

BI

11
7
15

R30
22K
5%
CH
0402LF
1/16W

24C3<>
20B4>
24C3<>

BI
BI

H29265-001

BUF_IO12
IO13_LED

6C7<>

EU4
IC
74LVC126A

R29
22K
5%
CH
0402LF
1/16W

1Y

4Y
GND
THPAD

23C5<

6 LVL_C_A1
4

C33
0.1UF
10%
16V
X7R
0402LF

U26
IC

R28
22K
5%
CH
0402LF
1/16W

IO12

11

12
13

R11
22K
5%
CH
0402LF
1/16W

23C7<

20C4>

10

C34
0.1UF
10%
16V
X7R
0402LF

V5_ALW_ON

7B7<

EU4
IC
74LVC126A

C36
0.1UF
10%
16V
X7R
0402LF

VSHLD_S5

6B7<

LVL_C_OE0_N
20A7<
C88413-002
VCC=V3P3_S0;GND=GND;TH=GND

1
20C3<>
20C4>
20C4>

UART0_RXD

V3P3_S0

BI

24A5<>
24D3<>

BUF_SPI1_MISO

33.2

R56
CH

SPI1_MISO

6C7<>

6C7<

23B7<

C88413-002
VCC=V3P3_S0;GND=GND;TH=GND
LVL_C_OE5_N

LVL_C_PU5

20A7<

20C3>

23C5<

DS2A1
GREEN
LED

INTEL CORPORATION
2111 NE 25TH AVENUE
HILLSBORO OR 97124

TITLE:

DOCUMENT NUMBER:

GALILEO Gen2

REV:

LVL C BUFFER

2.0

H38681

SHEET 23 OF 28
1

CR-24 : @GALILEO_LIB.GALILEO(SCH_1):PAGE24

J2B1
THLF
1X10RCPT

V5_ALW_ON

C2
0.1UF
10%
16V
X7R
0402LF

V5_ALW_ON

U28
IC

C9
0.1UF
10%
16V
X7R
0402LF

TS5A23159
8

20C1>
20B5>
18A7<

IN
BI
OUT

AMUX2_IN1
AMUX2_NO1
AVIN4

1
2
9

20C1>
20B5>
18A7<

IN
BI
OUT

AMUX2_IN2
AMUX2_NO2
AVIN5

5
4
7

VP
IN1
NO1
NC1
IN2
NO2
NC2

COM1
COM2
GND

10

20B5>

20B8<>
20D3<>

6
3

20A5<

AMUX2_COM1

20B2<>
20C6<>
20D8<>
20B2<>
20C6<
20D8<>

AMUX1_IN

BI

LVL_I2C_SDA

1
2
9

LVL_I2C_SCL

5
4
7

BI

G63512-001

TS5A23159
8

VP
IN1
NO1
NC1
IN2
NO2
NC2

COM1

10

ANALOG_A4

24B2<>

24D3<>

BI
BI

22B4<>
23B3<>
22B4<>
22B4<>
22C4<>
20C3> 20A4<

BI
BI
BI
BI
BI
BI

COM2

ANALOG_A5

24B2<>

24D3<>

GND

ANALOG_A5
ANALOG_A4
IO13
IO12
IO11
IO10
IO9
IO8

33.2
33.2
33.2
33.2
33.2

R3M16
R3M17
R3M18
R3M19
R3M20

10
9
AREF 8
7
6
5
4
3
2
1

IO13_R
IO12_R
IO11_R
IO10_R
IO9_R
C2B5
0.1UF
10%
16V
X7R
0402LF

DIGITAL
DIGITAL
DIGITAL
DIGITAL
DIGITAL
DIGITAL

13
12
11
10
9
8

CONN
G79666-001

J1B1
1X8RCPT

G63512-001

AMUX2

24B2<>
24B2<>

24A5<>
24A5<>
24A1>

U7
IC

IN

AMUX2_COM2

20B8<
20D3<

24C4<>
24C4<>

20C3>

20A5<
22C4<>
22C4<>
23C3<>
22C4<>
20B4>
23C3<>
20B4>
22B4<>
23C3<>

AMUX1

IO7
IO6
IO5
IO4
IO3
IO2
IO1
IO0

BI
BI
BI
BI
BI
BI
BI
BI

33.2
33.2
33.2
33.2
33.2
33.2
33.2

R1B2
R4M12
R4M11
R4M10
R4M9
R4M8
R4M7

DIGITAL
DIGITAL
DIGITAL
DIGITAL
DIGITAL
DIGITAL
DIGITAL
DIGITAL

8
7
6
5
4
3
2
1

IO6_R
IO5_R
IO4_R
IO3_R
IO2_R
IO1_R
IO0_R

7
6
5
4
3
2
1
0

CONN

CAD NOTE: PLACE RESISTORS CLOSE TO CONNECTOR.

THLF
J1A5
1X6RCPT
20B5> 18A7<
20B5> 18A7<
20B5> 18A7<
20B5> 18A7<
24D3<>
24C4<>
24D3<>
24C4<>

VSHLD_S5

1
2
3
4
5
6

CONN
G79672-001
V5_ALW_ON

R1A21
100K
1%
CH
0402LF
1/16W

VSHLD_S5

BI
BI
BI
BI
BI
BI

ANALOG_A0
ANALOG_A1
ANALOG_A2
ANALOG_A3
ANALOG_A4
ANALOG_A5

J1
CONN

CONN6_H18587001
V3P3_S5
V5_ALW_ON

J2A1
THLF
1X8RCPT
1 PIN1:OPEN
2 PIN2:IO REF
RESET_N_SHLD
3
4
5
6
VIN
7
8

CONN
G79625-001

24D3<>
23B3<>
24D3<>
22B4<>
24A6<>
20B5> 20A5<

BI
BI
BI

IO12
33.2
IO13
33.2
RESET_N_SHLD

IO12_ICSP_R
IO13_ICSP_R

R13
R14

2
4
6

1
3
5

IO11_ICSP_R

BI

20A5<

20B5>

S1

24A5<>

SILK=RESET
1

22B4<>

24D3<>

SILK=ICSP HDR

SWSPSTPB
SW
D90553-001
2

C13
1UF
10%
6.3V
X5R
0402LF

C37
0.1UF
10%
25V
X5R
0402LF

OUT

H18587-001

INTEL CORPORATION
2111 NE 25TH AVENUE
HILLSBORO OR 97124

TITLE:

R15 IO11

33.2

DOCUMENT NUMBER:

GALILEO Gen2

REV:

AMUX & EXTERNAL IO

2

2.0

H38681

SHEET 24 OF 28
1

CR-25 : @GALILEO_LIB.GALILEO(SCH_1):PAGE25

V3P3_S5

EN_V3P3_S5
1

EN_V1P5_S5

25C6<

C2L7
4700PF
10%
50V
X7R
0402LF

EN_V1P0_S5

25B6<

C2M5
10NF
10%
16V
X7R
0402LF

25B6<

C45
6800PF
10%
25V
X7R
0402LF

R4A2
10K
5%
CH
0402LF

VO = (R1/R2)*0.8 + 0.8

S5_PGOOD
V5_ALW_ON
C3B4
1
V3V

U3A1

PLACE CLOSE TO
INPUT PINS

C2L8
10UF
10%
16V
X5R
0805LF

C2L9
10UF
10%
16V
X5R
0805LF

1
2

BST_V3P3_S5

25C3<>

1
2

1
2
B

C3B6
4700PF
10%
50V
X7R
0402LF
1

C3A14
4700PF
10%
50V
X7R
0402LF

C3A15
4700PF
10%
50V
X7R
0402LF

NOTE:

25B3<>

25B3<>

1 R3B2
180K
1%
2 0402LF

CURRENT LIMIT
V3P3_S5 @ 2.45A DC
V1P5_S5 @ 1.80A DC
V1P0_S0 @ 2.50A DC

25D7<

C3A18 2

BST1_1

25C3<

.047UF 10%
16V
X7R
0603LF

BST_V1P5_S5

C3A19 2
.047UF 10%
16V
X7R
0603LF

BST_V1P0_S5

1 R3A21
147K
1%
2 0402LF

SS1_1
RLIM1_1

SS1_2
RLIM1_2
BST1_2

25D7<

25B3<

C4A2 2
.047UF 10%
16V
X7R
0603LF

1 R4A7
147K
1%
2 0402LF

SS1_3
RLIM1_3

25D6<

BST1_3

25B3<

EN_V3P3_S5
VR1_FB1

EN_V1P5_S5
VR1_FB2

EN_V1P0_S5
VR1_FB3

R3A19
1
2
ROSC_VR
180K 1%
0402LF R2M1 F_PWM
0
0
0402LF
CH

V3V
V7V
PGOOD
13
9
10
11
12
7

VIN1
SS1
RLIM1
EN1
BST1
FB1

COMP1
LX1_1
LX1_2

18
22
21
20
19
24

VIN2
SS2
RLIM2
EN2
BST2
FB2

COMP2
LX2_1
LX2_2

38
2

VIN3
SS3
RLIM3
EN3
BST3
FB3

40
39
4

6
25

29
28
27

10UF 10%
16V
0805LF

8 VR1_COMP1
14
15

6B6<

MAX LOAD: 2.0A

V3P3_S5

IHLP1212BZER2R2M11

10UF 10%
C3B3
1
2
V7V

TPS652510

C2L12
10UF
10%
16V
X5R
0805LF

OUT

6A6<

L3A1
2.2UH 3A
1

DISCRETE

VR1_FB1

25C6<

25A8<

BST_V3P3_S5

1 R3A16
40.2K
1%
2 CH
0402LF
1/16W

C3A11
4700PF
10%
50V
X7R
0402LF

R3A18
1
2
12.7K 1%
0402LF CH

25C7<

1
C2L6
22UF
20%
6.3V 2
X5R
0805LF

C2L11
22UF
20%
6.3V
X5R
0805LF

C2L4
22UF
20%
6.3V
2 X5R
0805LF
C97875-001

MAX LOAD: 1.3A

V1P5_S5

VR1

ROSC
F_PWM

23 VR1_COMP2
16
17

25A7<

L2M1
2.2UH 3A
1

DISCRETE

BST_V1P5_S5

COMP3
LX3_1
LX3_2

3 VR1_COMP3
36
37

UC
UC
UC
UC
UC
UC
UC
UC

5
26
30
31
32
33
34
35

POWERPAD

41

25B7<

25A6<

25B6< VR1_FB2

1 R2M4
40.2K
1%
2 CH
0402LF
1/16W

1
2

C2M6
4700PF
10%
50V
X7R
0402LF

R2M6
1
2
45.3K 1%
0402LF CH

C3B1
22UF
20%
6.3V
X5R
0805LF

C3B7
22UF
20%
6.3V
X5R
0805LF

MAX LOAD: 2.1A

V1P0_S5

1
BST_V1P0_S5

L4B1
2.2UH 3A
1

DISCRETE

25B7<

25B6<

IC
G43225-001

VR1_FB3

R2L19
40.2K
1%
CH
0402LF

C2L14
4700PF
10%
50V
X7R
0402LF

1
2
R2L20

C3B9
22UF
20%
6.3V
X5R
0805LF

C3B11
22UF
20%
6.3V
X5R
0805LF

158K 1%
0402LF CH

VR1_COMP1
25C4>
R3A22
1
2 VR1_COMP1_R
24.9K 1%
0402LF CH
1 C3A16
10PF
5%
2 COG
0402LF

1 C3A12
1000PF
10%
2 X7R
0402LF

VR1_COMP2
25C4>
R3B1
1
2 VR1_COMP2_R
24.9K 1%
0402LF CH
1 C3B2
10PF
5%
2 COG
0402LF

1 C3B8
1000PF
10%
2 X7R
0402LF

VR1_COMP3
25B4>
R3A23
1
2 VR1_COMP3_R
24.9K 1%
0402LF CH
1 C3A17
10PF
5%
2 COG
0402LF

1 C3A13
1000PF
10%
2 X7R
0402LF

INTEL CORPORATION
2111 NE 25TH AVENUE
HILLSBORO OR 97124

TITLE:

DOCUMENT NUMBER:

GALILEO Gen2

REV:

VOLTAGE REGULATORS
2

2.0

H38681

SHEET 25 OF 28
1

CR-26 : @GALILEO_LIB.GALILEO(SCH_1):PAGE26

V3P3_S5
V3P3_S5

V3P3_S3

U2L1

V3P3_S0
U2M1

TPS22920

C2L10
1UF
10%
6.3V
X5R
0402LF

V3P3_S5 IS GENERATED W ON-BRD REGULATOR

6A6>

IN

S3_3V3_EN

TPS22920

A2

VIN1

VOUT1

A1

B2

VIN2

VOUT2

B1

C2

VIN3

VOUT3

C1

GND

D1

D2

ON

C2L13
1UF
10%
6.3V
X5R
0402LF

C2L5
1UF
10%
6.3V
X5R
0402LF
6A6>

IN

S0_3V3_EN

IC

R2L2
10K
5%
CH
0402LF

VIN1

VOUT1

A1

B2

VIN2

VOUT2

B1

C2

VIN3

VOUT3

C1

D2

ON

GND

D1

V1P5_S3

V1P5_S0

V1P5_S5 IS GENERATED W ON-BRD REGULATOR

28A8<

6A6>

IN

S3_1V5_EN

B2
C2
D2

VOUT1

A1

VIN2

VOUT2

B1

VIN3

VOUT3

C1

GND

D1

VIN1

ON

U2A2
TPS22920

A2

V1P5_S5

U2A4

C2A4
1UF
10%
6.3V
X5R
0402LF

C3B5
1UF
10%
6.3V
X5R
0402LF

IC

R2L18
10K
5%
CH
0402LF

V1P5_S5
C

A2

28B7<

TPS22920

C2A2
1UF
10%
6.3V
X5R
0402LF

C2A5
1UF
10%
6.3V
X5R
0402LF
27C6<

6A6>

IN

S0_1V5_EN

A2

VIN1

VOUT1

A1

B2

VIN2

VOUT2

B1

C2

VIN3

VOUT3

C1

D2

ON

GND

D1

C2A1
1UF
10%
6.3V
X5R
0402LF

1
R2A7
10K
5%
CH
0402LF

V1P0_S5 IS GENERATED W ON-BRD REGULATOR

B

IC

R2A6
10K
5%
CH
0402LF

IC

CAD NOTE:
PLACE DECOUPLING CAPS AS CLOSE AS POSSIBLE TO SWITCH PINS

V1P0_S5
V1P0_S0
U5
C7
1UF
10%
6.3V
X5R
0402LF

28B8<

6A6< 6A6>
28C5<

IN

S0_1V0_EN

V1P0_S3 IS GENERATED INTERNALLY

TPS22920

A2

VIN1

VOUT1

A1

B2

VIN2

VOUT2

B1

C2

VIN3

VOUT3

C1

D2

ON

GND

D1

V1P0_S0 IS GENERATED W ON-BRD REGULATOR

C8
1UF
10%
6.3V
X5R
0402LF

R9
IC
10K
5%
CH
0402LF

INTEL CORPORATION
2111 NE 25TH AVENUE
HILLSBORO OR 97124

TITLE:

DOCUMENT NUMBER:

GALILEO Gen2

REV:

VOLTAGE REGULATORS
2

2.0

H38681

SHEET 26 OF 28
1

CR-27 : @GALILEO_LIB.GALILEO(SCH_1):PAGE27

V1P5_S0

V3P3_S5

V3P3_S5

VTT
1
D

C1A2
10UF
10%
6.3V
X7R
0805LF

V1P5_S3

1 1
2 2

C1A1
10UF
10%
6.3V
X7R
0805LF

1
R4L9
10K
1%
CH
0402LF
2 A93548-034

C3L2
4.7UF
10%
6.3V
X5R
0603LF

U2A3
TPS51200

10

VIN

REFIN_VTT_REG

28B7<

C3L1
1000PF
10%
2 50V
X7R
0402LF
A36096-046

26B3<

6A6>

S0_1V5_EN

IN

VCC_USB1
D

C3L4
10UF
10%
6.3V
X7R
0805LF

PGOOD

VO

VOSNS

REFOUT

GND
PGND

8
4

VLDOIN

REFIN

EN

1
R3L1
10K
1%
CH
0402LF

R2A4
10K
5%
CH
0402LF

THP

PG_3P3_S5_NU

11
2

IC
E17764-001

C2A3
0.1UF
10%
16V
X7R
0402LF

1 1
2 2

C3L3
10UF
10%
6.3V 2
X7R
0805LF

C3L7
10UF
10%
6.3V
X7R
0805LF

V5_ALW_ON

R48
1K
5%
EMPTY
0402LF

VREF

C3B15
0.1UF
10%
10V
EMPTY
0402LF

DS1
RED
EMPTY

REFOUT IS INDEPENDENT OF ENABLE PIN

USB_PWR_FAULT_N

U29
EMPTY
TPS2552DRV-1

3
4

FAULT_N
EN_N

R58
10K
5%
EMPTY
0402LF

OUT
ILIM

1
2

GND
THPAD

5
7

IN

R49
49.9K
1%
EMPTY
0603LF

H31893-001

OPTION TO POWER FROM USB

RECOMMENDED POWER SUPPLY:

PHIHONG PSA15R-120PV

VIN_POE

C35
.01UF
10%
25V
X7R
0402LF

C4B4
0.1UF
10%
25V
X5R
0402LF

C4B3
1UF
10%
25V
X5R
0603LF

CONN
D33700-002

C46
.01UF
10%
25V
X7R
0402LF

NORMALLY CLOSED

D3
schottky_diode
DB2W31900L
DISCRETE

U6

C18
10UF
10%
25V
X5R
0805LF

TPS62130

11
12
10
13

V5_ALW_ON
V5_ALW_ON

C3B13
1UF
10%
2 10V
X5R
0402LF

C4B1
47UF
20%
16V
X5R
1210LF

1
2

C4B2
47UF
20%
16V
X5R
1210LF

C10
0.1UF
10%
25V
X5R
0402LF

C48
.01UF
10%
25V
X7R
0402LF

C19
3300PF
10%
50V
EMPTY
0402LF

PVIN_11
PVIN_12
AVIN_10

SW
SW_2
SW_3
VOS

EN

1
2
3

V5_ALW_ON_L

PG_V5_ALW_ON

DEF

FB

FB_V5_ALW_ON

FSW

EPAD
AGND

17
6

PGND_15
PGND_16

15
16

SS/TR

8
7

REV=1

1 OF 1

DISCRETE

D5
schottky_diode
DB2W31900L
DISCRETE
B

V5_ALW_ON_D

C21

R19
100K
5%
CH
0402LF

14

PG

L1
2.2UH 3A

C47
0.1UF
10%
25V
X5R
0402LF

VIN_D

VIN
1

C50
0.1UF
10%
25V
EMPTY
0402LF

1
3
2

C49
0.1UF
10%
25V
EMPTY
0402LF

PWR_JACK
1
3
2

V5_ALW_ON
D4
schottky_diode
DB2W31900L
DISCRETE

J4A3

VIN

22UF
10V
20%
X5R
0805

R53
57.6K
1%
EMPTY
0402LF

R55
54.9K
1%
CH
0402LF

R54
10.5K
1%
CH
0402LF

IC

INTEL CORPORATION
2111 NE 25TH AVENUE
HILLSBORO OR 97124

TITLE:

DOCUMENT NUMBER:

GALILEO Gen2

REV:

VOLTAGE REGULATORS
2

2.0

H38681

SHEET 27 OF 28
1

CR-28 : @GALILEO_LIB.GALILEO(SCH_1):PAGE28

NOTE: RESET_N HAS AN INTERNAL PU TO V3P3_S3

D

SS:
REBOOT BUTTON

S1A1

SWSPSTPB

SW
D90553-001
1

2
RESET_N

OUT

6B6<
28B8<

26A8<

6A6<

6A6>

IN

S0_1V0_EN

C4L1
1UF
10%
2 6.3V
X5R
0402LF

VOH:2.25V
VOL:0.15V
R4A9
330
5%
CH
0402LF
1/16W

CAD NOTE:
PLACE AT LED AREA

S0_1V0_EN_LED

DS4A1
2

GREEN
LED

26A8<

6A6< 6A6>
28C5<

IN

S0_1V0_EN

R16
24.9K
1%
CH
0402LF
B

V3P3_S5

PG_V1P0_S0

V3P3_RTC

6A6<

OUT

R3A9
0
0402LF

C11
0.1UF
10%
16V
X7R
0402LF

0
EMPTY

CR3A1
C52251-001

2
27C6<

26B3<

6A6>

IN

S0_1V5_EN

3
BAT_DIO
R3A1
24.9K
1%
CH
0402LF

26B5<

6A6>

IN

S3_1V5_EN

R3A2
24.9K
1%
CH
0402LF

S0_PGOOD

OUT

6A6<

6A6<

OUT

C3A6
0.1UF
10%
16V
X7R
0402LF

6B6<

J3A1
BAT_POS

C3A9
.1UF SS:
10% V3P3_RTC
16V
EMPTY
0402LF

CAD NOTE:
PUT THE SILKSCREEN
NEXT TO THE CAP

HDR
CAD NOTE:
LABEL "+" AND "-" TERMINALS ON 2 PIN HDR

PG DELAY

OFF-BOARD BATTERY

INTEL CORPORATION
2111 NE 25TH AVENUE
HILLSBORO OR 97124

TITLE:

C3A8
.1UF
10%
16V
EMPTY
0402LF

1X2HDR

PG DELAY
8

DIO
BAT54C
SOT23C

R3A11
1K
1%
CH
0402LF
1/16W

C3A5
0.1UF
10%
16V
X7R
0402LF
S3_PGOOD

DOCUMENT NUMBER:

GALILEO Gen2

REV:

POWER BUTTONS & MISC

2

2.0

H38681

SHEET 28 OF 28
1