VHDL- A Hardware Discription Language

Manish Kumar Jaiswal

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Department of Electronics Engineering
ICFAI-Tech, Dehradun

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Typical Design Flow

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Design Abstraction Level

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Design Abstraction Level

Lowest Level
Transistor Level Design

Next Upper Level

Gate Level

Next Higher Level

RTL (Registre Transfer Logic) Level

Highest Level
Behaviour Level Design (wrtie a HDL program)

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Design Abstraction Level

Lowest Level
Transistor Level Design

Next Upper Level

Gate Level

Next Higher Level

RTL (Registre Transfer Logic) Level

Highest Level
Behaviour Level Design (wrtie a HDL program)

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Design Abstraction Level

Lowest Level
Transistor Level Design

Next Upper Level

Gate Level

Next Higher Level

RTL (Registre Transfer Logic) Level

Highest Level
Behaviour Level Design (wrtie a HDL program)

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Design Abstraction Level

Lowest Level
Transistor Level Design

Next Upper Level

Gate Level

Next Higher Level

RTL (Registre Transfer Logic) Level

Highest Level
Behaviour Level Design (wrtie a HDL program)

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Design Abstraction: Example of a MUX
Behaviour Level
do passes to y when s=0, and
d1 passes to y when s=1

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Design Abstraction: Example of a MUX

Gate Level
y = sdo + s d1

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Design Abstraction: Example of a MUX

Transistor Level

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Introduction to VHDL

VHDL Stands for:

VHSIC-HDL (Very High Speed Integrated Circuit - Hardware
Description Language)

Jointly sponsored and developed by the U.S. Department of

Defense and the IEEE (International Society for Electrical &
Electronics Engineers) in the mid-1980s.
Standardized by the IEEE in 1987 (VHDL-87), and later extended
in 1993 (VHDL-93), and currently we have VHDL-2001.
Verilog-HDL, Another very popular HDL, was first introduced in
1984, and later in 1988, as a proprietary hardware description
language by the two companies Synopsys and Cadence Design
Systems. Currently we have Verilog-2001.
In this course we will go through the VHDL.
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Introduction to VHDL, Cont’d

VHDL is similar to a regular computer programming language,

such as C,C++. For exp, it has constructs for variable
assignments, conditional statements, loops, functions, etc..
In a computer programming language, a compiler is used to
translate the high-level source code to machine code. In VHDL,
however, a synthesizer is used to translate the source code to a
description of the actual hardware circuit that implements the
code. From this description, which we call a netlist, the actual
physical digital device that realizes the source code can be made
automatically.
Functional and timing simulation of the code is also possible in
order to test the correctness of the circuit.

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Basic VHDL Structure

Library IEEE;
Use IEEE.std_logc_1164.all;
entity entity_name is
port{
in1, in2 : in std_logic;
out1 : out std_logic;
};
end entity_name;
architecture arch_name of entity_name is
- -signal-declaration
begin
- -concurrent-statement
end arch_name;

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Sample Example
Library IEEE;
Use IEEE.std_logc_1164.all;
entity and_2 is
port{
in1, in2 : in std_logic;
out1 : out std_logic;
};
end and_2;
architecture dataflow_arch of and_2 is
begin
out1 <= in1 and in2;
end dataflow_arch;
--------
architecture behav_arch of and_2 is
begin
out1 <= ’1 when in1=1 & in2=1 else
’0’;
end behav_arch;

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Basic Language Elements

Comments
- - - - - - This is a comment.

Identifiers
A sequence of one or more uppercase letters, lower case letters,
digits and the underscore.
Case insensitive
First character must be a letter.
The last character cannot be a underscore.
Two underscore can not be together.

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Basic Language Elements
Data Objects: Signal , Variable, and constant
SIGNAL represents logic signals on a wire in the ckt. A signal
does not have memory, thus if source of the signal is removed, the
signal will not have a value.
A VARIABLE objects remember its content and is used for
computation in a behaviour model. The scope of a VARIABLE is
local to the corresponding PROCESS.
A CONSTANT object must be initialized with a value when
declared and this value cann’t be changed.

Example
SIGNAL x : BIT;
VARIABLE y: INTEGER;
CONSTANT one: std_logic_vector(3 downto 0) := "0001"’
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Basic Language Elements
Data Objects: Signal , Variable, and constant
SIGNAL represents logic signals on a wire in the ckt. A signal
does not have memory, thus if source of the signal is removed, the
signal will not have a value.
A VARIABLE objects remember its content and is used for
computation in a behaviour model. The scope of a VARIABLE is
local to the corresponding PROCESS.
A CONSTANT object must be initialized with a value when
declared and this value cann’t be changed.

Example
SIGNAL x : BIT;
VARIABLE y: INTEGER;
CONSTANT one: std_logic_vector(3 downto 0) := "0001"’
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Basic Language Elements

Data Types
BIT & BIT_VECTOR (Predefined in VHDL. Can have Value ’0’ or
’1’).
STD_LOGIC & STD_LOGIC_VECTOR (Not Predefined n VHDL)
Can have 9-value 0,1,Z,-,L,H,U,X,W.
Need to add these lines.
Library IEEE;
Use IEEE.std_logic_1164.all;
INTEGER (Predefined, Uses 32-bits to represents the binary
numbers.)
BOOLEAN (Predefined, having two value TRUE & FALSE)

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Basic Language Elements

Data Types
Enumeration TYPE (Allow user to specify the values that the data
can have)
Syntax: TYPE identifier IS (value1, value2, ...);
Example:
TYPE state_type IS (S1, S2, S3);
SIGNAL state: state_type;
state <= S1;
ARRAY (Groups single data objects of same type together into
one-diamentional or multidiamentional array)
Syntax: TYPE identifier IS ARRAY (range) of TYPE;
Example: TYPE byte IS ARRAY (7 downto 0) of BIT;

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Basic Language Elements

Data Types
SUBTYPE (A subset of TYPE)
Syntax: SUBTYPE identifier IS TYPE RANGE range;
Example: SUBTYPE integer4 IS INTEGER RANGE -8 TO 7;
SUBTYPE cell IS STD_LOGIC_VECTOR(3 downto 0);

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Basic Language Elements

Data Operators
LOGICAL (AND, OR, NOT, NAND, NOR, XOR, XNOR)
Arithmetic (a+b, a-b, a*b, a/b,a MOD b, a REM b, a**b,
’a’&’b’(concatenation))
Relational (=, /=, <, <=, >, >=)
Shift (SLL(Shift left Logic), SRL, SLA(Shift Left Arithmetic), SRA,
ROL(Rotate Left), ROR)

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VHDL Terms

Entity: Declares the external & users interface of the module.

Architecture: Defines the actual implementation of the functionality of
entity.
Configuration: Used to bind a component instance to an
entity-architecture pair.
Package: Is a collection of commonly used data types and
subprograms used in design.
Generic: An information passed to ENTITY as a parameter, e.g for
a generalised design.
Process: A basic unit of execution. All operation that performs are
broken into single or mutliple processes.

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VHDL Terms
ENTITY
Syntax
entity entity_name is
port {
- -list of port names and types;
};
end entity_name;
Example
Library IEEE;
Use IEEE.std_logic_1164.all;
entity module is
port {
M,N,O: in std_logic;
S: out std_logic };
end module;
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VHDL Terms

ARCHITECTURE
Syntax(Data Flow Model)
architecture arch_name of entity_name is
signal declaration;
begin
concurrent statements;
end arch_name;
Example
architecture data_arch of module is
signal t1: std_logic;
begin
t1 <= M or O;
S <= t1 and N;
end arch_name;

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VHDL Terms

ARCHITECTURE
Syntax(Behavioural Model)
architecture arch_name of entity_name is
signal declaration;
function declaration;
procedure declaration;
begin
PROCESS-blocks;
concurrents statements;
end arch_name;

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VHDL Terms

ARCHITECTURE
Example(Behavioural Model)
architecture behav_arch of module is
signal t1: std_logic;
begin
PROCESS(M,N,O)
BEGIN t1 <= M or O;
S <= t1 and N;
end PROCESS
end arch_name;

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VHDL Terms

ARCHITECTURE
Syntax(Structural Model)
architecture arch_name of entity_name is
signal declaration;
component declaration;
begin
instance-name: PORT MAP-statement;
concurrents statements;
end arch_name;

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VHDL Terms

ARCHITECTURE
Example(Structural Model)
architecture struct_arch of module is
COMPONENT OR2 {
in1, in2: in std_logic; out1: out std_logic };
end COMPONENT
signal t1: std_logic;
begin
U0: OR2 PORT MAP (M, O, t1);
S <= t1 and N;
end arch_name;

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VHDL Terms
GENERIC
Syntax
entity entity_name is
GENERIC (identifier: type); - - no default value
GENERIC (identifier: type:=constant); - - with default value
port { - -list of port names and types;
};
end entity_name;
Example
entity adder is
GENERIC (n: integer:=4); - - with default value of 4
port { A,B: in std_logic_vector(n-1 downto 0);
Sum: out std_logic_vector(n-1 downto 0);
Cout: out std_logic };
end adder;
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VHDL Terms

GENERIC
Component Declaration Syntax
COMPONENT entity_name
GENERIC (identifier: type:=constant); - - with an optional value
given by the constant
port { - -list of port names and types;
};
end COMPONENT;

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VHDL Terms

PACKAGE
A PACKAGE provides a mechanism to group together and share
declarations that are used by several entity units.
A package itself includes a declaration and, optionally, a body.
The PACKAGE declaration and body usually are stored together
in a separate file from the rest of the design units.
The file name given for this file must be the same as the package
name.

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VHDL Terms

PACKAGE Declaration Syntax

PACKAGE package-name is
type-declarations;
subtype-declarations;
signal-declarations;
variable-declarations;
constant-declarations;
component-declarations;
function-declarations;
procedure-declarations;
END package-name;

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VHDL Terms

PACKAGE BODY Declaration Syntax

PACKAGE BODY package-name is
function-definitions; - - For the function declared in package
declaration
procedure-definitions; - - For the procedure declared in package
declaration
END package-name;

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VHDL Terms

PACKAGE Example
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
PACKAGE my_package IS
SUBTYPE bit4 IS STD_LOGIC_VECTOR(3 DOWNTO 0);
FUNCTION Shiftright (input: IN bit4) RETURN bit4; – declare a function
SIGNAL mysignal: bit4; – a global signal
END my_package;
PACKAGE BODY my_package IS
– implementation of the Shiftright function
FUNCTION Shiftright (input: IN bit4) RETURN bit4 IS
BEGIN
RETURN ’0’ & input(3 DOWNTO 1);
END shiftright;
END my_package;

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VHDL Terms

Using a PACKAGE
LIBRARY WORK;
USE WORK.my_package.ALL;
entity test_package is
PORT }
x:in bit4; y:out bit4 };
end test_package;
architecture behav_arch of test_package is
begin
mysignal <= x;
y <= shiftright(mysignal);
behav_arch

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 References

References

I [1] VHDL Primer by J. Bhasker.

I [2] VHDL Programing by Example by Douglas L. Perry, TMH
Publcation.
I [3] Digital Logic and Microprocessor Design with VHDL by Enough
O. Hwang.

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 Thank you

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