STATIC MOS DESIGN

The most widely used logic is complementary CMOS logic due to advantages associated with it like Low sensitivity
to noise, Low power consumption with no static power dissipation, Good performance and Robustness [1]. These
properties lead to implementation of large fan in logic circuits using same devices.

Static MOS circuits design includes complementary CMOS, ratioed logic (pseudo NMOS and DCVSL) and pass
transistor logic.

COMPLEMENTRY CMOS

Static CMOS gates are implemented by using combination of two networks, the pull up network (PUN) and
pull down network (PDN).Static CMOS is characterized by very good current driving capabilities and high
noise margins.[4] In Static CMOS design, at every point in time, each gate output is connected to either Vdd
or Vss via a low-resistance path. Also, the outputs of the gate assume at all times the value of the Boolean
function implemented by the circuit.[15]

A Static CMOS gate is a combination of two networks, the pull up network (PUN) and the pull down
network (PDN). The function of the PDN is to provide a connection between the output and Vdd when the
output of the logic gate is supposed to be 1. Similarly, the PDN connects the output to Vss when the output
is expected to be 0. The PUN and PDN networks are constructed in a mutually exclusive manner such that
one and only one of the networks are conducting in steady state.

The Static CMOS gates have rail-to-rail swing, no static power dissipation. The speed of the static CMOS
circuit depends on the transistor sizing and the various parasitic that are involved with it. The problem with
this type of implementation is that for N fan-in gate 2N number of transistors are required, i.e., more area
required to implement logic. This has an impact on the capacitance and thus the speed of the gate.

inputs

Fig Static complementary gate structure [2]

In constructing PUN and PDN following point should be considered.

1. A transistor can be assumed as a switch controlled by gate voltage. NMOS operates on positive gate
voltage and PMOS operate on application of negative gate voltage.

2. The PDN is realized by using NMOS while PUN is by using PMOS transistors. This is due to the fact that
NMOS produce ‘strong 0s’ and PMOS device generate ‘strong1s’ [1]
 Fig [2]. Pulling up and pulling down of a node using PMOS and NMOS switches

Conceder the diagram for PDN the capacitor is initially charged to VDD . A NMOS device pulls the output
down to Ground while the PMOS do not lowers the output less than VTP and the PMOS turns off at that
point and stop contributing discharge current. The NMOS transistors are thus preferred in PDN. Similarly
NMOS device fails to raise output above VDD – VTh , Thus PMOS transistors are preferably used in a PUN.

For constructing logic function following set of rules will be helpful [1].

 NMOS devices connected in series corresponds to AND function while NMOS transistors connected
in parallel represents OR function. Similarly PMOS devices connected in series neither corresponds
to NOR does function while PMOS connected in parallel represent NAND function.

 The pull up and pull down network in a complementary CMOS circuit are dual networks this means
that parallel connection of transistors in pull up network corresponds to a series connection of
corresponding device in pull down network and vice-versa.

 The complementary gates are naturally inverting, Implementing only functions such as NAND, NOR
and XNOR. The realization of non inverting Boolean functions such as AND, OR and XOR is not
possible in single step and these circuits can be realized only by using an extra inverter stage.

 The minimum number of gate required to implement an N input logic gate is 2N. So for realizing an
N input function using CMOS logic the number of transistors required will be at least twice of the
inputs.
STATIC PROPERTIES OF COMPLEMENTRY CMOS LOGIC GATES:

1. They exhibit rail to rail swing with VOH = VDD and VOL = GND

2. The circuit has no static power dissipation, since the circuit are designed such as pull up pull down
network are mutually exclusive

3. The Analysis of DC voltage transfer characteristics and the noise margin is more complicated than for the
inverter as these parameters depends on the input data pattern applied to the gate.

Ratioed Logic
Although, the static CMOS logic style is highly robust and scalable with technology but it requires 2N
transistors in implementation of an N-input logic gate. Also, the load capacitance is significant since each
gate drives two transistors (a PMOS and an NMOS) per fan-out. Ratioed logic is an alternate method to
reduce the number of transistors required to implement a given logic function, at the cost of reduced
robustness and extra power dissipation. It is one method to reduce the circuit complexity of static CMOS.
Here, the logic function is built in the PDN and used in combination with a simple load device.

Fig schematic for ratioed Logic [10]

The need of the PUN in complementary CMOS is to provide a conditional path between VDD and the output,
when the PDN is turned off. In ratioed logic, the entire PUN is replaced with a single load device that pulls
up the output when the PDN is turned off. Ratioed logic, which uses a grounded PMOS load and referred to
as a pseudo-NMOS style. Instead of a combination of active pull-down and pull-up networks, such a gate
consists of an NMOS pull-down network that realizes the logic function, and a simple load device.
This has resulted in a wide variety of possible load configurations such as Simple resistor, Depletion load
and Pseudo-NMOS.

Pseudo NMOS Logic

Pseudo-NMOS logic can be implemented using a PMOS transistor simply as a pull-up device for an NMOS
network block. The advantage of pseudo-NMOS logic are its high speed (especially, in large-fan-in NOR
gates) and low transistor count.

On the negative side is the static power consumption of the pull-up transistor as well as the reduced output
voltage swing and gain, which makes the gate more susceptible to noise. At a second glance, when pseudo-
NMOS logic is combined with static CMOS in time critical signal paths only, the overall speed
improvement can be substantial at the cost of only a slight increase of static-power consumption.
Furthermore, when the gate of the pull-up transistor is connected to a appropriate control signal it can be
turned off, i.e., pseudo-NMOS supports a power-down mode at no extra cost.

Fig Pseudo-NMOS [9]

DCVSL (Differential Cascade Voltage Switch Logic)

Differential Cascade Voltage Switch Logic consists of two parts complementary NMOS pull down network
and PMOS load transistors [5]. Logical functions are performed only using the NMOS transistor. The
PMOS pull up stage is required to produce the correct logic levels to the output. The DSVSL allows a
logical function and its implementation by sharing parts of NMOS trees. The logic depth of DCVSL can be
quite high and reliability as well as noise immunity is quite good. Dual rail wiring and high transistor count
in some functions and ratioed nature are major drawbacks of this logic style.

Differential Cascode voltage switch (DCVS) [12] is claimed to have advantages over the traditional static
CMOS design in terms of circuit delay, layout area, logic flexibility, and power dissipation [13], [14].
DCVS also has an inherent self testing property which can provide coverage for stuck-at and dynamic faults.
 Fig Differential Cascade Voltage Switch Logic [9]

Differential Cascode Voltage Switch with Pass-Gate logic (DCVSPG)

It combines the best properties of both pass gate logic and DCVSL. In pass gate logic NMOS transistors are
utilized the electronic values which pass the desired logical value to output. Both NMOS and PMOS
transistors contribute to the pull up of the output nodes therefore the DCVSPG is more immune to floating
node effect inherent in DCVSL. [7]

Fig DCVSPG AND circuit [9]

Push Pull Cascode logic (PPCL)
A Cascode logic circuit provides a pair of differential output nodes that are pulled up by a pair of cross-
coupled P-channel output transistors.[6] The output nodes are connected to outputs of an N-channel
combinatorial network that receives a differential input and functions to connect one of the output nodes to a
positive supply and the other to ground, depending upon the differential input, thus providing a push-pull
effect. The output nodes may be connected to the differential output of the combinatorial network by source-
drain paths of separate N-channel transistors, with the gates of these transistors connected to the positive
supply to capacitive isolate the output nodes from the combinatorial network; alternatively, the gates of
these transistors may be clocked. A fully static latch is provided by adding cross-coupled N-channel
transistors connecting the output nodes to ground, so the low side of the output is held down instead of being
allowed to float. The channel types of the transistors may be reversed in another embodiment; the pull-down
transistors of the differential amplifier may be N-channel and the logic and latching transistors P-channel.

PASS transistor logic (PTL)

PASS transistors are used to reduce the layout complexity of logic circuits by using PASS transistors
connected to pass a first and second input function to an output node in response to selected CONTROL
signals, thereby to generate a selected output function on the output node.[8] The PASS transistor comprises
a transistor capable of passing an input function in response to a CONTROL signal applied to the transistor
thereby to generate an output function related to the input function. In general, the input function comprises
less than all of a set of input variables and the CONTROL function comprises one or more of the remainder
of the set of input variables. It is a good alternate to complementary CMOS circuits. This family tries to
reduce the number of transistors required by allowing the primary input to drive gate terminals as well as
source drain terminals. The main advantage is the reduced number of transistors and no static power
consumption.

Fig Pass-Transistor Logic [11]

 Fig Pass-Transistor Logic AND Gate [11]

References:

[1]. VLSI Design 2nd edition by Albert Raj/latha Pg 159

[2] Adapted from Rabaey’s Digital Integrated Circuits, ©2002, J. Rabaey

[3] Lecture 5 Circuit Optimization for Speed High-Speed Logic Families B.Nikoli UC Berkeley

[4]Comparison of static logic styles for low voltage design by Mika Kontiala

[5]JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.10, NO.1, MARCH, 2010

[6] Push-pull Cascode logic, United States Patent 5023480 Gieseke, Bruce A. (Natick, MA), Conrad, Robert A.
(Millbury, MA), Montanaro, James J. (Princeton, MA), Dobberpuhl, Daniel W. (Shrewsbury, MA)

[7]Design and implementation of Differential Cascade Voltage Switch with Pass-Gate Logic by F S Lai.

[8] Combinational logic structure using PASS transistors, United States Patent 4541067

[9] Adapted from Design and Implementation of Differential Cascode Voltage Switch with Pass-Gate (DCVSPG)
Logic for High-Performance Digital Systems by Fang-shi Lai and Wei Hwang

[10] Adapted from www.vlsi.uwaterloo.ca/~manis/ece637/lecture13.pdf

[11] Pass-Transistor Logic www.ece.sunysb.edu/~adoboli/355/class_7.ppt

[12] L. G. Heller, W. R. Griffin, J. W. Davis, and N. G. Thoma, “Cascode voltage switch logic: A differential CMOS
logic family,” in Dig. Tech.Papers, ISSCC, 1984, pp. 16–17.

[13] K. M. Chu and D. I. Pulfrey, “A comparison of CMOS circuit techniques: Differential cascode voltage switch
logic versus conventional logic,” IEEE J. Solid-State Circuits, vol. SC-22, pp. 528–532, 1987.

[14] “Design procedures for differential cascode voltage switch circuits,” IEEE J. Solid-State Circuits, vol. SC-21, pp.
1082–1087, 1986

[15] DESIGNING COMBINATIONAL LOGIC GATES IN CMOS

bwrc.eecs.berkeley.edu/classes/icdesign/ee141_f01/Notes/chapter6.pdf