KNL 1253

DIGITAL ELECTRONICS

Counters

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 Overview
• Counters are important components in computers
– The increment or decrement by one in response to input
• Two main types of counters
– Ripple (asynchronous) counters
– Synchronous counters
• Ripple counters
– Flip flop output serves as a source for triggering other flip
flops
• Synchronous counters
– All flip flops triggered by a clock signal
• Synchronous counters are more widely used in industry.

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 Counters
• Counter: A register that goes through a prescribed series of
states
• Binary counter
– Counter that follows a binary sequence
– N bit binary counter counts in binary from n to 2 n-1
• Ripple counters triggered by initial Count signal
• Applications:
– Watches
– Clocks
– Alarms
– Web browser refresh

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Another Asynchronous Ripple Counter

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 Cont…
• Operation:
– Clock is applied only to FF A. J and K are high in all FFs.
– Output of FF A is CLK of FF B and so forth.
– FF outputs D, C, B, and A are a 4 bit binary number with D as
the MSB.
– After the NT of the 15th clock pulse the counter recycles to 0000.
• This is an asynchronous counter because state is not changed in
exact synchronism with the clock.
• Schematics are normally drawn from left to right, but counters will
be drawn from right to left so that the MSB and LSB appear in the
appropriate positions.

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 Mod number

• MOD number is equal to the number of

states that the counter goes through before
recycling.
• Adding FFs will increase the MOD number.

Mod number = 2N

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 Frequency Division
• Frequency division – each FF will have an output
frequency of ½ the input. The output frequency of
the last FF of any counter will be the clock
frequency divided by the MOD of the counter.

Output A –8kHz square wave

Output B –4kHz square wave

Output C–2kHz square wave

Output D –1kHz square wave

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Counter waveforms showing frequency division by 2 for each FF
 Counters with mod numbers <2N

• The MOD of a counter can be changed by

designing the counter to normal parts of the
counting sequence.

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Cont… 1. NAND output:
High – no effect on the counter
Low- it will clear all the FF so that the
counter immediately goes to the 000 state
2. When outputs B and C are high the
counter will be reset.
3. Counting sequence is therefore:
CBA
000
001
010
011
100
101
Temporary state needed to
110
clear counter
4. Notice the “glitch” in the waveform
when the count reaches 6. This represents
the brief time required to reset the counter.

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 State Transition Diagram
•No arrow into 111 state because the counter
never advance to that state
•111 state can occur on power –up when the
FFs come up in random state
•If that happen, 111 condition will produce
a LOW at the NAND gate output and
immediately clear the counter to 000
•111 state is also a temporary condition that
ends up at 000

(a) State transition diagram for the MOD-6 counter

of Figure 7-4.

(b) LEDs are often used to display the statesrohana

of a counter.
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 To construct a counter that is < 2N

1. Construct as little counter as you can together.

2. Connect the NAND gate output to the asynchronous
CLEAR input for all counter.
3. Determine which counter’s output will be in high
state when it reaches the mod you desire.
4. Then connect those counter that are in high state to
the NAND gate input.

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Example for MOD-14 Ripple Counter
U1 U2 U3 U4
SET SET SET SET
J Q J Q J Q J Q

K ~Q K ~Q K ~Q K ~Q

RESET RESET RESET RESET

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 Exercise

Construct a MOD-10 (decade) counter

using JK flip flop.

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 Solution
U1 U2 U3 U4
SET SET SET SET
J Q J Q J Q J Q

K ~Q K ~Q K ~Q K ~Q

RESET RESET RESET RESET

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 Asynchronous Down Counter
• Counted upward from zero = up counters
• Construct asynchronous (ripple) down counters, which
will count downward from maximum count to zero
• Counting down rather than up simply requires cascading
the clocks using the inverted outputs
• Count-down sequence for a three-bit down counter
CBA
(7) 111
(6) 110
(5) 101
(4) 100
Recycles
(3) 011
(2) 010
(1) 001
(0) 000
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Cont…

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 Propagation delay in ripple counter

• Ripple counters are simple, but the

cumulative propagation delay can cause
problems at high frequencies
• For proper operation the following apply:
– TclockN x tpd
– Fmax=1/(N x tpd)

Number of FFs
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Cont…

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 Synchronous (Parallel) Counters
• All FFs are triggered by clock pulse simultaneously.
• Each FF has J and K inputs connected so they are
HIGH only when the outputs of all lower-order FFs
are HIGH.
• The total propagation delay will be the same for any
number of FFs.
• Synchronous counters can operate at much higher
frequencies than asynchronous counters.

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 Synchronous counters

A flip-flop must change states at each NGT. For this reason, its J & K inputs are permanently
HIGH (J=K=1)
B flip-flop must change states on each NGT that occurs while A=1. This operation is
accomplished by connecting output A to the J & K input of B, so that J=K=1 only when A=1
C flip-flop must change states on each NGT that occurs while A=B=1. This operation is
accomplished by connecting the logic signal AB to FF C’s J & K input, this FF will toggle only
when A=B=1
D flip-flop must change states on each NGT that occurs while A=B=C=1. This operation is
accomplished by connecting the logic signal ABC to FF D’s J & K input, this FF will toggle only
when A=B=C=1
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Circuit operation
• Count value increments on each
negative edge
• Note that low-order bit (A)
toggles on each clock cycle
• The basic principle for
constructing synchronous
counter:
– Each FF should have its J
and K inputs connected so
that they are HIGH only
when the outputs of all
lower-order FFs are in the
HIGH state
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Advantage of synchronous counter over
asynchronous
• Total delay is the same no matter how many FFs are
in the counter and it will generally be much lower
than with an asynchronous counter with the same
number of FFs
total delay = FF tpd + AND gate tpd
• Synchronous counter can operate at much higher
input frequency
• Circuitry of synchronous counter is more complex

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Cont…

a) MOD-8 synchronous up/down

counter.
b) The counter counts up when the
control input Up/Down = 1; it
counts down when the control
input = 0.

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 Presettable counter

• Many synchronous (parallel) counters that are

available as ICs are designed to be presettable;
in other words, they can be preset to any
desired starting count either asynchronously or
synchronously
• This presetting operation is also referred to as
parallel loading the counter

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Binary Counter with Parallel Load and Preset
• Presettable parallel counter with asynchronous
preset.

If PL’ = 0, load P into flops

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 Binary Counter with Parallel Load and Preset
• Commercial version of binary counter

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 Decoding a Counter
• Decoding is the conversion of a binary output to a
decimal value.
• The active high decoder shown in figure 7-27
could be used to light an LED representing each
decimal number 0 to 7
• Active low decoding is obtained by replacing the
AND gates with NAND gates.
– Decoder output produce a normal HIGH signal, which
goes LOW only when the number being decoded occur

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 Cont…

Using AND gates to

decode a MOD-8 counter
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 Decoding Glitches
• Glitches or spikes are caused by delays between FF
transitions.
• Figure 7-30 describes the problem.
• The spikes may not cause problems in many
applications due to the short duration.
• If glitches cannot be tolerated, a parallel counter can
be used.
• Strobing uses a strobe signal to keep decoding AND
gates disabled until all FFs have reached a stable
state. Refer to figure 7-31.

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Cont…

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 Strobing
• Method for eliminating the decoder spikes
• Use a signal called strobe signal to keep the decoding
AND gates disabled (outputs at 0) until all of the FFs have
reached a stable state in response to negative clock
transition

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 Cascading BCD Counters
• To count to larger decimal value, can cascade BCD
counter stages
• Operation of a decimal 000 to 999 BCD counter
– Initially all counters are reset to 0
– Each input pulse advances the first counter once.
– The 10th input pulse causes the counter to recycle, which
advances the second counter 1.
– This continues until the second counter (10’s digit)
recycles, which advances the third counter 1.
– The cycle repeat until 999 is reached and all three counters
start again at zero.

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 • Initially all counters are reset to 0
• Each input pulse advances the first counter once

Cont… • The 10th input pulse causes the counter to recycle, which
advances the second counter 1
• This continues until the second counter (10’s digit) recycles,
which advances the third counter 1
• The cycle repeat until 999 is reached and all three counters
start again at zero

Cascading BCD counters to count and display numbers from 000 to 999
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 Synchronous Counter Design

• Basic idea:
– J-K excitation table

Transition at output PRESENT State NEXT State J K

Q(N) Q(N+1)
00 0 0 0 x
01 0 1 1 x
10 1 0 x 1
11 1 1 x 0

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 Synchronous Counter Design

Example:
Design a three-bit synchronous counter
the count 000 to 100 and the sequence
does not include the 101, 110, and 111
states.

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 Design procedure
• Step 1: Determine the desired number of bits (FF)
the desired counting sequence
– Example: design a three-bit counter that goes
through the sequence shown in Table 7.3.
C B A
0 0 0
0 0 1 Notice that this sequence
does not include 101,110,
0 1 0
and 111 states
0 1 1
1 0 0
0 0 0
0 0 1 rohana sapawi/digital electronics 36
 Cont…
• Step 2: Draw the state transition diagram showing
all possible states, including those that are not part
of the desired counting sequence

State transition diagram for the

synchronous counter design example.

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 Cont…
• Step 3: Use the state transition diagram to set up a
table that lists all PRESENT states and their
NEXT states
PRESENT State NEXT State
C B A C B A
Line 1 0 0 0 0 0 1
2 0 0 1 0 1 0
3 0 1 0 0 1 1
4 0 1 1 1 0 0
5 1 0 0 0 0 0
6 1 0 1 0 0 0
7 1 1 0 0 0 0
8 1 1 1 0 0 0
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 Cont…
• Step 4 : Add a column to this table for each J and K input. For
each PRESENT state, indicate the level required at each J and K
input in order to produce the transition to the NEXT state

PRESENT NEXT State

State
C B A C B A JC KC JB KB JA KA
Line 1 0 0 0 0 0 1 0 x 0 x 1 x
2 0 0 1 0 1 0 0 x 1 x x 1
3 0 1 0 0 1 1 0 x x 0 1 x
4 0 1 1 1 0 0 1 x x 1 x 1
5 1 0 0 0 0 0 x 1 0 x 0 x
6 1 0 1 0 0 0 x 1 0 x x 1
7 1 1 0 0 0 0 x 1 x 1 0 x
8 1 1 1 0 0 0 x 1 x 1 x 1
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 Cont…
• Step 5: Design the logic circuit needed to generate
the levels required at each J and K input

JA  C
KA 1
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 Cont…

(a) K maps for the JC and KC logic circuits; (b) K maps for the JB and KB logic circuits.

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JA  C
KA 1
Cont…
J C  AB
KC  1
J B  AC
KB  A  C

Final implementation of the synchronous counter design example.

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 Synchronous Counter Design
• Determine desired number of bits and desired counting
sequence
• Draw the state transition diagram showing all possible states
• Use the diagram to create a table listing all PRESENT states
and their NEXT states
• Add a column for each JK input. Indicate the level required
at each J and K in order to produce transition to the NEXT
state.
• Design the logic circuits to generate levels required at each
JK input.
• Implement the final expressions

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 Summary
• Binary counters can be ripple or synchronous
• Ripple counters use flip flop outputs as flop triggers
– Some delay before all flops settle on a final value
– Do no require a clock signal
• Synchronous counters are controlled by a clock
– All flip flops change at the same time
• Up/Down counters can either increment or decrement a stored
binary value
– Control signal determines if counter counts up or down
• Counters with parallel load can be set to a known value before
counting begins.

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