Standard VHDL Packages
Standard VHDL Packages
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_textio.all;
use IEEE.std_logic_arith.all;
use IEEE.numeric_bit.all;
use IEEE.numeric_std.all;
use IEEE.std_logic_signed.all;
use IEEE.std_logic_unsigned.all;
use IEEE.math_real.all;
use IEEE.math_complex.all;
library STD;
use STD.textio;
std_logic_arith_syn.vhd
defines types signed and unsigned and
has arithmetic functions that operate on signal types
signed and unsigned and std_logic_vector and std_ulogic_vector,
but adding A to B of std_logic_vector type, needs
unsigned(A) + unsigned(B).
Click on std_logic_arith_syn to see the functions defined
std_logic_arith_ex.vhd
has arithmetic functions that operate on signal types
std_logic_vector and std_ulogic_vector
Click on std_logic_arith_ex to see the functions defined