COURSE FILE

FOR
DSP PROCESSORS AND ARCHITECHTURES
FOR IV YEAR II SEMISTER B.TECH
(ECE)

SWAMI RAMANANDA TIRTHA

INSTITUTE OF SCIENCE & TECHNOLOGY

JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY

HYDERABAD
IV Year B.Tech. ECE.II-Sem T
P C
4+1* 0 4
DSP PROCESSORS AND ARCHITECTURES
(ELECTIVE â IV)
UNIT I
INTORODUCTION TO DIGITAL SIGNAL PROCESING : Introduction, A Digital signal-proce
ssing system, The sampling process, Discrete time sequences. Discrete Fourier Tr
ansform (DFT) and Fast Fourier Transform (FFT), Linear time-invariant systems, D
igital filters, Decimation and interpolation, Analysis and Design tool for DSP S
ystems MATLAB, DSP using MATLAB.
UNIT II
COMPUTATIONAL ACCURACY IN DSP IMPLEMENTATIONS : Number formats for signals and c
oefficients in DSP systems, Dynamic Range and Precision, Sources of error in DSP
implementations, A/D Conversion errors, DSP Computational errors, D/A Conversio
n Errors, Compensating filter.
UNIT III
ARCHITECTURES FOR PROGRAMMABLE DSP DEVICES : Basic Architectural features, DSP C
omputational Building Blocks, Bus Architecture and Memory, Data Addressing Capab
ilities, Address Generation Unit, Programmability and Program Execution, Speed I
ssues, Features for External interfacing.
UNIT IV
EXECUTION CONTROL AND PIPELINING : Hardware looping, Interrupts, Stacks, Relativ
e Branch support, Pipelining and Performance, Pipeline Depth, Interlocking, Bran
ching effects, Interrupt effects, Pipeline Programming models.
UNIT V
PROGRAMMABLE DIGITAL SIGNAL PROCESSORS : Commercial Digital signal-processing De
vices, Data Addressing modes of TMS320C54XX DSPs, Data Addressing modes of TMS32
0C54XX Processors, Memory space of TMS320C54XX Processors, Program Control, TMS3
20C54XX instructions and Programming, On-Chip Peripherals, Interrupts of TMS320C
54XX processors, Pipeline Operation of TMS320C54XX Processors.
UNIT VI
IMPLEMENTATIONS OF BASIC DSP ALGORITHMS : The Q-notation, FIR Filters, IIR Filte
rs, Interpolation Filters, Decimation Filters, PID Controller, Adaptive Filters,
2-D Signal Processing.
UNIT VII
IMPLEMENTATION OF FFT ALGORITHMS : An FFT Algorithm for DFT Computation, A Butte
rfly Computation, Overflow and scaling, Bit-Reversed index generation, An 8-Poin
t FFT implementation on the TMS320C54XX, Computation of the signal spectrum.
UNIT VIII
INTERFACING MEMORY AND I/O PERIPHERALS TO PROGRAMMABLE DSP DEVICES :
Memory space organization, External bus interfacing signals, Memory interface, P
arallel I/O interface, Programmed I/O, Interrupts and I/O, Direct memory access
(DMA). A Multichannel buffered serial port (McBSP), McBSP Programming, a CODEC
interface circuit, CODEC programming, A CODEC-DSP interface example.
TEXT BOOKS :
1. Digital Signal Processing â Avtar Singh and S. Srinivasan, Thomson Publications,
2004.
2. DSP Processor Fundamentals, Architectures & Features â Lapsley et al. S. Chand &
Co, 2000.
REFERENCES :
1. Digital Signal Processors, Architecture, Programming and Applications â B. Venkat
a Ramani and M. Bhaskar, TMH, 2004.
2. Digital Signal Processing â Jonatham Stein, John Wiley, 2005.
SRTIST, NALGONDA
IV-B.TECH (ECE) II-SEM LECTURE SCHEDULE
SUBJECT: DSP Processors And Architectures
FACULTY: Miss.T.Hima bindu
Lect. No Unit Topic
I INTORODUCTION TO DIGITAL SIGNAL
PROCESING
1 Introduction, A Digital signal-processin
g system
2 The sampling process, Discrete time sequ
ences
3 Discrete Fourier Transform (DFT) and Fas
t Fourier Transform (FFT)
4 Linear time-invariant systems, Digital filters
5 Decimation and interpolation, Analysis and Design tool for DSP Systems
MATLAB
6 DSP using MATLAB
II COMPUTATIONAL ACCURACY IN DSP IMPLEMENTA
TIONS
1 Number formats for signals and coefficie
nts in DSP systems
2 Dynamic Range and Precision
3 Conversion errors, DSP Computational err
ors
4 A/D Conversion errors, DSP Computational
errors
5 D/A Conversion Errors, Compensating filter.

III ARCHITECTURES FOR PROGRAMMABLE DSP DEVICES

1 Basic Architectural features
2 DSP Computational Building Blocks, Bus Architecture and Memory
3 Data Addressing Capabilities, Address Generation Unit
4 Programmability and Program Execution
5 Speed Issues, Features for External interfacing.

IV EXECUTION CONTROL AND PIPELINING

1 Hardware looping, Interrupts
2 Stacks, Relative Branch support, Pipelining and
Performance
3 Pipeline Depth, Interlocking,
4 Branching effects, Interrupt effects
5 Pipeline Programming models

V PROGRAMMABLE DIGITAL SIGNAL PROCESSORS

1 Commercial Digital signal-processing Devices
2 Data Addressing modes of TMS320C54XX DSPs
3 Data Addressing modes of TMS320C54XX Processors
4 Memory space of TMS320C54XX Processors
5 Program Control, TMS320C54XX instructions and Pr
ogramming
6 On-Chip Peripherals, Interrupts of TMS320C54XX p
rocessors
7 Pipeline Operation of TMS320C54XX Processors.
VI IMPLEMENTATIONS OF BASIC DSP ALGORITHMS
1 The Q-notation, FIR Filters
2 IIR Filters, Interpolation Filters
3 Decimation Filters, PID Controller
4 Adaptive Filters, 2-D Signal Processing.

VII IMPLEMENTATION OF FFT ALGORITHMS

1 An FFT Algorithm for DFT Computation, A Butterfly Computation
2 Overflow and scaling, Bit-Reversed index generation
3 An 8-Point FFT implementation on the TMS320C54XX,
4 Computation of the signal spectrum.

VIII INTERFACING MEMORY AND I/O PERIPHERALS TO PROGRAMMABLE DSP DEVIC

ES
1 Memory space organization, External bus interfacing signals
2 Memory interface, Parallel I/O interface
3 Programmed I/O, Interrupts and I/O
4 Direct memory access (DMA). A Multichannel buffered serial por
t (McBSP)
5 McBSP Programming, a CODEC interface circuit
6 CODEC programming, A CODEC-DSP interface example
.

DSP PROCESSORS AND ARCHITECHTURES

OVERVIEW
UNIT-I

INTORODUCTION TO DIGITAL SIGNAL PROCESING

Digital Signal Processing, as the term suggests, is the processing of signals by

digital means. A signal in this context can mean a number of different things.
A signal is a stream of information representing anything from stock prices to
data from a remote-sensing satellite. The term "digital" comes from "digit", mea
ning a number. A digital signal consists of a stream of numbers in binary form.
In this unit we discuss about relation between DFT and FFT. In this we are desig
ning the digital filters (FIR, IIR).
This unit also deals with decimation and interpolation topics. There are some pr
ograms using MATLAB.

UNIT-II
COMPUTATIONAL ACCURACY IN DSP IMPLEMENTATIONS

The processing of a digital signal is done by performing numerical calculations

. In a DSP, signals are represented as numbers from the input stage along throug
h intermediate processing stages to the output. In this unit there 4 ways to rep
resent numbers, we will discuss about that briefly here. And also we cover the d
ynamic range and precision topics. We discuss about A/D conversion errors and D/
A conversion errors and also compensating filters.

UNIT-III
ARCHITECTURES FOR PROGRAMMABLE DSP DEVICES
The architecture of a digital signal processor is optimized specifically for dig
ital signal processing. Most also support some of the features as an application
s processor or microcontroller, since signal processing is rarely the only task
of a system. Some useful features for optimizing DSP algorithms are outlined bel
ow. In this unit we study the basic architectural features of DSP and memory. Da
ta Addressing Capabilities and Address Generation Unit topics discussed. This un
it also deals with Programmability and Program Execution and Speed Issues and Fe
atures for External Interfacing.
.
UNIT-IV
EXECUTION CONTROL AND PIPELINING
Execution control refers to the rules or mechanisms used in a processor for dete
rmining the next instruction to execute. In this unit we study several features
of execution control that are important to DSP processors. Among these a Hardwar
e Looping, Interrupt Handling, Stacks and Relative Branch Support. Execution Con
trol is related to pipelining. Pipelining is a technique for increasing the perf
ormance of the processor by breaking the operations. In this unit we discuss abo
ut pipeline depth, Branching and Interrupt Effects and pipeline programming mode
ls.
UNIT-V
PROGRAMMABLE DIGITAL SIGNAL PROCESSORS
In this unit we discuss about the Architectural requirements of a Digital Signal
Processor. The basic Architectures of three commonly used commercial DSP famili
es and features were discussed. And we study about the Texas InstrumentsTMS320C5
4XX Processors Data Addressing Modes, Memory Space, On Chip peripherals and pipe
lining operation using this Texas Processor.
UNIT-VI
IMPLEMENTATIONS OF BASIC DSP ALGORITHMS
In this chapter we deal with implementations of DSP Algorithms. We also study ab
out Q- notation, Fir filters, IIR filters, Interpolation filters and Decimation
Filters. The PID Controller uses the error to generate input to the plant. An Ad
aptive filter is a filter whose coefficients can be updated online to counter va
rying signal distortions. And also we discuss about 2-D Signal Processing.
UNIT-VII
IMPLEMENTATION OF FFT ALGORITHMS
In this chapter we cover the implementations of FFT algorithms for DET computati
on and related issues. A general DIT FFT Butterfly computation, Overflow and Sca
ling methods are used to avoid overflow in any stage of butterfly computations.
In this unit we also study Bit Reversed Index Generation, An 8-point FFT Implem
entation on the TMS320C54XX and Computation of the signal spectrum.

UNIT-VIII
INTERFACING MEMORY AND I/O PERIPHERALS TO PROGRAMMABLE DSP DEVICES
In this chapter we discuss the Interfacing signals of the TMS320C54XX processors
and use of these signals for parallel interfacing of memory and peripherals. We
also discuss the topics memory interface, programmed I/O, interrupts and DMA. I
n this chapter we also deal the multi channel buffered serial port (McBSP) and a
Codec DSP interface.

UNIT-I

INTORODUCTION TO DIGITAL SIGNAL PROCESING

SHORT ANSWER QUESTIONS

1. Explain about the digital signal processing system?

2. Explain the sampling process?
3. What are the differences between DFT & FFT?
4. Write a program for linear convolution using MATLAB?
5. Explain about digital filters?
6. What is decimation and interpolation?

LONG ANSWER QUESTIONS

1. Find the DFT of the sequence {1, 1, 1, 1, 2, 2 ,2, 2} using radix-2 Deci
mation â
in â Frequency FFT.
2. Compare FIR and IIR filter.
3. What is the need for FFT?
4. The signal sequence x(n) = [ 0 2 4 6 8] is interpolated using the interp
olation
filter sequence bk = [0.5 1 0.5] and the interpolation factor is 2. Determine th
e
interpolated sequence y(n).
5. b) Determine the periods for the periodic sequences i) e jn p/8 ii) e jn
- 3 8 p/
6. Design and also realize a high pass FIR filter with a cutoff frequency o
f 1.3
rad/sec and N=9. (16)

UNIT-II
COMPUTATIONAL ACCURACY IN DSP IMPLEMENTATIONS
SHORT ANSWER QUESTIONS
1. Show that the dynamic range of a signal increases by 6 db for each additional
bit used to represent its value?
2. Compute the dynamic range and percentage resolution of a signal that uses
i) 16- point fixed point format
ii) 32-point floating point format with 24 bits for the mantissa and 8 bits for
the exponent?
3. Compute the dynamic range and percentage resolution for a block floating poin
t format with a 4 bit exponent used in a 16 bit fixed point processor?
4. Explain about A/D and D/A conversion errors?

LONG ANSWER QUESTIONS

1. Explain the DSP addressing modes with suitable examples.
2. Compute the dynamic range and the percentage resolution for a block floa
ting point format with a 4-bit exponent used in a 16-bit fixed point processor.
3. Show that the dynamic range of a signal increases by 6 db for each addit
ional bit used to present its value.
4. Write about the different sources of error in DSP implementation.
5. Write about the different number formats for signals and coefficients in
DSP systems.
6. What are the various DSP computational building blocks? Explain any two
of them.

UNIT-III
ARCHITECTURES FOR PROGRAMMABLE DSP DEVICES
SHORT ANSWER QUESTIONS
1. What distinguishes a digital signal processor from a general purpose mic
ro processor with regard to basic capabilities
2. Draw a structure similar to that of 8 X 8 unsigned binary multiplier
3. How will you implement an 8 X 8 multiplier using 4 X 4 multipliers as th
e building blocks?
4. What is the bit reversed sequence of 32 samples x0,x1,x2⠦⠦..x31 as obtained by
ampling a signal?
5. What is meant by overflow in an arithmetic computation? How is an overfl
ow condition detected in an ALU?
LONG ANSWER QUESTIONS
1. What are the various DSP computational building blocks? Explain any two
of them.
2. Explain about multiply and accumulate unit
3. List the essential peripherals required to implement the following DSP s
ystems.
i) Speech processing system
ii) A biomedical instrumentation system
iii) An image processing system
4. What is the difference between a micro coded program control and a hardw
ired program control? Why is the later preferred for DSP implementation?
5. List the major architectural features used in a digital signal processor
to achieve high speed of program.
6. Explain about different branching effects.

UNIT-IV
EXECUTION CONTROL AND PIPELINING
SHORT ANSWER QUESTIONS
1. Explain about hard ware looping?
2. Explain the pipelining concepts?
3. What are the interrupts and stacks in DSP Processor?
4. Define Pipe line depth?
5. Explain the pipeline programming models?
LONG ANSWER QUESTIONS
1. Explain about different branching effects.
2. What is hardware looping? Explain in detail.
3. Explain about various pipeline programming models.
4. What is pipelining and explain the different pipeline programming models
.
5. What are the various DSP computational building blocks? Explain any two
of them.

UNIT-V
PROGRAMMABLE DIGITAL SIGNAL PROCESSORS
SHORT ANSWER QUESTIONS
1. Explain the differences between the internal and external modes of clock
ing TMS320C54XX processors. How do you vary the clock frequency in each case?
2. Write the addressing modes of TMS320C54XX processors?
3. Explain the pipeline operation in TMS320C54XX processor?
4. Write a TMS320C54XX program to mask the lower 6 bits of a word stored in
the data memory and write the modified work back at the same location?
LONG ANSWER QUESTIONS
1. Write a sequence of TMS320C54xx instructions to configure a circular buf
fer with a start address at 0200h and an end address at 021fh with current buffe
r pointer (AR6) pointing to address 0205h.
2. What will be the contents of accumulator A after the execution of the in
struction LD * AR4, 4, A if the current AR4 points to a memory location whose co
ntents are 8b0eh and the SXM bit of the status register STI is set?
3. Identify the addressing mode of the source operand in each of the follow
ing instructions.
a) ADD *AR2, A
b) READA *AR2
c) ADD *AR2+%, A
d) ADD #0ffh, A
e) ADD 1234h, A
f) ADD *AR2+0B, A
g) ADD *+AR2, A
h) LD *(1000h), A
4. Explain the various data addressing modes of TMS320C54xx processors with
suitable examples.
5. Explain the difference between the internal and external modes of clocki
ng TMS320C54xx processors. How do you vary the clock frequency in each case?
UNIT-VI
IMPLEMENTATIONS OF BASIC DSP ALGORITHMS
SHORT ANSWER QUESTIONS
1. Determine the value of each of the following 16 bit numbers represented
using the given Q- notation a) 4400h as a Q0 number b) 4400h as a Q15 number c)
4400h as a Q7 number?
2. Explain about the IIR and FIR filters?
3. Explain about interpolation filter and decimation filter?
4. What is an adaptive filters and 2d signal processing?
LONG ANSWER QUESTIONS
1. Determine the linearly interpolated sequence from the given sequence x(n
) = [ 0 4 8 12 16 8 4 0] for an interpolation factor of 3. What interpolating se
quence h(n) can achieve the specified interpolation.
2. Represent each of the following as 16 â bit numbers in the desired Q â notation
a) 0.3125 as a Q15 number
b) -0.3125 as a Q15 number
c) 3.125 as a Q7 number
d) -352 as a Q0 number
3. Develop a decimation filter program that can be used to decimate by a fa
ctor of 25 using a subroutine to decimate by a factor of 2 in conjunction with a
ppropriate filters.
4. Implement the IIR filter represented by the following difference equatio
n on the TMS320C54xx. Assume that Q15 notation is used to represent the values o
f coefficients and Q0 to represent the signal samples.
UNIT-VII
IMPLEMENTATION OF FFT ALGORITHMS
SHORT ANSWER QUESTIONS
1. Derive the optimum scaling factor for the DIF FFT butterfly?
2. How can the program can be modified so that the scaling is done only whe
n is needed?
3. What is the minimum size FFT must be used to compute a DFT of 40 points?
What must be done to the samples before the chosen FFT is applied?
4. Explain the FFT algorithm for the DFT computation?
LONG ANSWER QUESTIONS
1. Derive the optimum scaling factor for the DIF FFT butterfly.
2. What minimum size FFT must be used to compute a DFT of 40 points? What m
ust be done to the samples before the chosen FFT is applied?
3. Determine the following for a 128-point FFT computation:
a. number of stages
b. number of butterflies ion each stage
c. number of butterflies needed for the entire computation
d. number of butterflies that need no twiddle factors
e. number of butterflies that require real twiddle factors
f. number of butterflies that require complex twiddle factors
4. A time domain sequence of 73 elements is to be convolved with another ti
me domain sequence of 50 elements using DFT to transform the two sequences, mult
iplying them, and then doing IDFT to obtain the resulting time domain sequence.
To implement DFT or IDFT, the DIT-FFT algorithm is to be used. Determine the tot
al number of complex multiplies needed to implement the convolution. Assume that
each butterfly computation requires one complex multiplication.

UNIT-VIII
INTERFACING MEMORY AND I/O PERIPHERALS TO PROGRAMMABLE DSP DEVICES
SHORT ANSWER QUESTIONS
1. How does DMA help in increasing the processing speed of a DSP Processor/
2. What is the range of addresses that can be decoded if A19 is pulled low
in a processor with 20 address lines?
3. How many address lines are required to success all locations of an 16K X
16 SRAM?
4. Explain about CODEC programming?
5. Explain CODEC interface circuit and McBSP Programming?
LONG ANSWER QUESTIONS
1. Design a circuit to interface 64k words of the program memory space from
0FFFFFh to 0F0000h for the TMS320C5416 processor using 16K x 16 memory chips.
2. What are the various classifications of interrupts for the TMS320C5416 p
rocessor?
3. How does the interrupt handling in the TMS320C54xx DSP differ for a soft
ware and a hardware interrupt?
4. What is DMA? Explain its role and operation in a DSP processor.
5. How does DMA help in increasing the processing speed of a DSP processor?
6. Write a TMS320C54xx code to initialize the DMA channel 5 destination reg
ister to #5555h without using auto increment; Rewrite the code using auto increm
ent for the same operation.