PCI-X & PCI Core

Getting Started: ASIC

Version 7.2.0 April 2008

Copyright © PLDA 1996-2008
 PCI-X & PCI Core Getting Started

PCI-X & PCI Core

Getting Started

Documentation Change History

Date Version Number Changes

April 2008 7.2.0 • Re-formatted and updated documentation

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Words and logos marked with ® or ™ are registered trademarks or trademarks owned by PLDA SA. Other brands
and names mentioned herein may be the trademarks of their respective owners.
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adapted or reproduced in any material form except with the prior written permission of the copyright holder.
The product described in this document is subject to continuous developments and improvements. All particulars
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“as is” with no warranties whatsoever, including any warranty of merchantability, non infringement, fitness for any
particular purpose, or any warranty otherwise arising out of any proposal, specification, or sample.
This document is intended only to assist the reader in the use of the product. PLDA shall not be liable for any loss
or damage arising from the use of any information in this document, or any error or omission in such information,
or any incorrect use of the product. Nor shall PLDA be liable for infringement of proprietary rights relating to use of
information in this document. No license, express or implied, by estoppel or otherwise, to any intellectual property
rights is granted herein.

Product Status
The information in this document is final content pertaining to the PLDA PCI-X & PCI Core.

Web Address
http://www.plda.com

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PCI-X & PCI Core Getting Started

Table of Contents

List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
About this document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Additional Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Feedback and Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Chapter 1 Before you Start... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

1.1 System Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.2 EDA Tools Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.3 Package Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.4 Installing the Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.4.1 Windows 2000, XP, or Vista . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.4.2 UNIX/Linux platform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

1.5 Exploring the Installed Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Chapter 2 Frontend Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

2.1 Creating a Parameterized Instance of the Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.2 Simulation with ModelSim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.3 Simulation with NCSim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.4 Timing Compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Chapter 3 Reference Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

3.1 Reference Design Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.2 Directory Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.3 File Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.4 Detailed Modules Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.5 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.6 Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

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 PCI-X & PCI Core Getting Started

List of Tables

Table 1: EDA Tools Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Table 2: Directory structure for the installed package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 3: Timing compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 4: Reference Design Directory structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 5: Detailed modules description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 6: Registers description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

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PCI-X & PCI Core Getting Started

List of Figures

Figure 1: PCI-X & PCI Wizard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

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 PCI-X & PCI Core Getting Started

Preface

About this document

Intended Audience
This document has been written for design managers, system engineers, and designers of ASICs who are
evaluating or using the PLDA PCI-X & PCI IP Core.

Scope
This document provides information to enable designers to integrate the PLDA PCI-X & PCI IP into their design
flow as quickly as possible (installing, customizing, integrating, and simulating the Core). Accompanied by the
Reference Manual, these two documents comprise all of the documentation for the PLDA PCI-X & PCI Core.

Typographical Conventions

italic Highlights important notes or publications

bold Highlights interface elements.

COURIER NEW DENOTES TEXT USED IN A CODE EXAMPLE OR A SIGNAL.

Additional Reading
This section lists additional resources from PLDA and third-parties.
PLDA periodically updates its documentation. Please contact PLDA at [email protected] or check the Web site
at http://www.plda.com for current versions.

PLDA Publications
Please refer to the following documents for further information:
• PCI-X & PCI Reference Manual: The Reference Manual provides the complete functional description of the
PLDA PCI-X & PCI Core.
• PCI-X & PCI Testbench Reference Manual: This document describes PLDA’s PCI-X & PCI Testbench.
• Build History: The Build History lists changes made in each version and build of the Core.

Other Publications
Please refer to the following documents for information on specification standards:
• PCI-X Addendum to the PCI Local Bus Specification , revision 2.0a - PCI SIG, July 2003
• PCI Local Bus Specification , revision 3.0 - PCI Special Interest Group, February 2004
• PCI Compliance Checklist , revision 3.0 - PCI Special Interest Group, March 2004
• PCI Mobile Design Guide, revision 1.1 - PCI Special Interest Group, December 1998
• PCI Bus Power Management Interface, revision 1.2 - PCI SIG, March 2004
• CompactPCI Hot Swap Specification , revision 1.0 - PICMG, August 1998
• MiniPCI Specification , revision 1.0 - PCI Special Interest Group, October 1999
• PC Cards Standard , release 8.0 - PCMCIA Association, April 2001

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PCI-X & PCI Core Getting Started

Feedback and Contact Information

Feedback about this Document

PLDA welcomes comments and suggestions pertaining to this documentation. Please contact PLDA at
[email protected] and provide the following information:
• the title of the document
• the page number to which your comments refer
• a description of your comments

Contact information
Corporate Headquarters
PLDA
Parc club du golf - Bât. 11a
Rue Guillibert
13856 Aix-en-Provence Cedex 3 - France

Tel: USA +1 408 273 4528 - International +33 442 393 600
Fax: +33 442 394 902

Sales
For sales questions, please contact [email protected].

Technical Support
For technical support questions, please contact [email protected].

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Before you Start... PCI-X & PCI Core Getting Started

Chapter 1 Before you Start...

1.1 System Requirements

To install the PCI-X & PCI package, you need:

• Memory: 1 Gb of RAM or greater

• Operating System: Windows 2000/XP/Vista or any UNIX/Linux platform supporting Java
• Hard Disk: 1 GB for core installation and component design

1.2 EDA Tools Requirements

Table 1 describes EDA Tools Requirements unique to Windows, unique to Unix / Linux, and common to both
operating systems.

Table 1: EDA Tools Requirements

Windows 2000/XP/Vista Unix/Linux

NCSim version 5.50 p004

• ModelSim PE or SE 6.1d or later

1.3 Package Features

The PCI-X & PCI Core is available for Windows or Unix/Linux in one of the following packages:
• ASIC Source
• Windows: pcixpci_vXXX_bYYY_asic_source.zip
• Unix / Linux: pcixpci_vXXX_bYYY_asic_source.tar.gz
• ASIC Board/Eval
• Windows: pcixpci_vXXX_bYYY_asic_board_eval.zip
• Unix / Linux: pcixpci_vXXX_bYYY_asic_board_eval.tar.gz

1.4 Installing the Package

1.4.1 Windows 2000, XP, or Vista

To install the Core package, unzip pcixpci_vXXX_bYYY_ZZZ.zip to your hard drive; “XXX” is the Core version
number, “YYY” is the build number, and “ZZZ” is the supported technology.

1.4.2 UNIX/Linux platform

1. Open a shell and set the working directory to the directory where the core package has been download
from the PLDA web site.
2. Unzip the tar.gz file using unzip software, such as WinRAR or 7-Zip.
3. Create an empty directory.
4. At the prompt, type:
tar -xzf pcixpci_vXXX_bYYY_ZZZ.tar.gz -C <your directory path>
Where “XXX” is the Core version number, “YYY” is the build number, and “ZZZ” is the supported
technology.

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PCI-X & PCI Core Getting Started Before you Start...

1.5 Exploring the Installed Files

Table 2: Directory structure for the installed package

• core
• pci
• source
• vhdl/vlog: RTL clear-text core source code

• simulation
• Modelsim
• vhdl/vlog: pre-compiled simulation library
• ncsim
• vhdl/vlog: compiled simulation library
• VCS
• vhdl/vlog:compiled simulation library

• documentation
build_history.pdf
revision_history.pdf
getting_started.pdf
reference_manual.pdf
testbench_reference_manual.pdf
• appnotes
• application notes and sample source code

• testsuite
• Testsuite environment

• ref_design
• Reference Design for simulation

• software
• plda_api: Application Programming Interface files
• tools_source: C++ examples of PLDA tools
• windows: PCI drivers and PLDA tools executables

• testbench: PLDA PCI-X & PCI Testbench

• pci
• source
• vhdl/vlog: RTL clear-text core source code

• simulation
• Modelsim
• vhdl/vlog: pre-compiled simulation library
• ncsim
• vhdl/vlog: compiled simulation library
• VCS
• vhdl/vlog:compiled simulation library

• wizard: TxRx interface wizard provided for creating a top-level instance of the Core.

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Frontend Design PCI-X & PCI Core Getting Started

Chapter 2 Frontend Design

2.1 Creating a Parameterized Instance of the Core

The PCI Wizard is a graphical environment that must be used to create a customized core. It creates a VHDL or
Verilog wrapper that instantiates the core with custom parameter values, input ports and output ports. PCI Wizard
is a standalone software that can be launched from the computer's desktop:
• Windows: Browse to the /wizard directory and run the run_wizard_pcixpci.bat batch file to launch
the Wizard GUI.
• Unix/Linux: Open a terminal window and type: /bin/sh run_wizard_pcixpci.sh (located in the ../wizard
installation directory
Once launched, the Wizard invites you to enter a name for the wrapper to create or browse and select a wrapper
that has already been created (for editing/modifying):
Subsequent pages allow you to define a custom interface according to your design's requirements. The first page
allows you to define the core main characteristics:

Figure 1: PCI-X & PCI Wizard

Click the <Help> button anytime for detailed information about each option.

2.2 Simulation with ModelSim

The Core package contains all the elements required for VHDL or Verilog simulation with Mentor ModelSim
version 6.1 and newer. Functional models for core and PCI-X Testbench are provided as pre-compiled libraries.
Follow these steps to create and simulate a PCI design:
1. Start ModelSim and create a new project
2. Add source files to the project and include PCI Wizard-generated instance of the core
3. Type the following commands at Modelsim prompt in order to map and update PCI-X & PCI core and
testbench libraries :

VHDL
vmap pcixpcitestb_lib
install_path/testbench/pci/modelsim/vhdl/pcixpcitestb_lib
vcom –force_refresh -work pcixpcitestb_lib

vmap pcixpcicore_lib
install_path/core/pci/modelsim/vhdl/pcixpcicore_lib
vcom –force_refresh –work pcixpcicore_lib

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PCI-X & PCI Core Getting Started Frontend Design

Verilog
vmap pcixpcitestb_lib
install_path/testbench/pci/modelsim/vlog/pcixpcitestb_lib
vlog –force_refresh -work pcixpcitestb_lib

vmap pcixpcicore_lib
install_path/core/pci/modelsim/vlog/pcixpcicore_lib
vlog –force_refresh –work pcixpcicore_lib
It is now possible to simulate any custom instance of PCI-X & PCI core and backend logic with the PCI-X
testbench. Refer to the PCI-X & PCI Testbench Reference Manual for more information.

2.3 Simulation with NCSim

Core package contains all the elements required for VHDL or Verilog simulation with Cadence NCSim or Incisive
Unified Simulator version 5.5p004 and later. Libraries must be built before starting simulating. Follow the
instructions below to build simulation libraries:
1. Create and map libraries named “pcixpcitestb_lib” and “pcixpcicore_lib”
2. Enter following commands at NCLaunch prompt in order to build PCI-X & PCI core and testbench
libraries :

VHDL
ncvhdl –93 -work pcixpcicore_lib -update
install_path/core/pci/ncsim/vhdl/pcixpcicore_lib.vhdp
ncvhdl –93 -work pcixpcitestb_lib -update
install_path/testbench/pci/ncsim/vhdl/pcixpcitestb_lib.vhdp

Verilog
ncvlog –work pcixpcicore_lib -update
install_path/core/pci/ncsim/vlog/pcixpcicore_lib.vp
ncvlog –work pcixpcitestb_lib -update
install_path/testbench/pci/ncsim/vlog/pcixpcitestb_lib.vp

2.4 Timing Compliance

PCI & PCI-X specifications impose stringent timing requirements on PCI signals, as detailed in the table below:

Table 3: Timing compliance

33MHz PCI 66MHz PCI 66MHz PCI-X 133MHz PCI-X

Tsu (set-up time to clock) 7ns* 3ns** 1.7ns 1.2ns

Tco (clock-to-output time) 11ns 6ns 3.8ns 3.8ns

Th (hold time) 0ns 0ns 0.5ns 0.5ns

Thz (OE-to-output time) 28ns 14ns 7ns 7ns

* 10ns for point-to-point signals (REQ#, GNT#)

** 5ns for point-to-point signals (REQ#, GNT#)

PCI Wizard creates a project setup Tcl script from the user-entered information which generates all necessary
constraints once launched in QuartusII (see section 2.3 for detail).
66MHz PCI designs require additional constraints to be added (like logic placement) in order to meet the PCI

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Frontend Design PCI-X & PCI Core Getting Started

timing requirements. PLDA provides custom optimization services for 66MHz PCI designs that are detailed in the
Core License Agreement.

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PCI-X & PCI Core Getting Started Reference Design

Chapter 3 Reference Design

This Reference Design is a complete application that implements PLDA PCI-X & PCI core. Core is interfaced to
some peripherals such as memories and I/Os. It allows designers to understand core operation and provides a
comprehensive environment for building their own PCI-X or PCI based applications.
This Reference Design can be tested on hardware using PLDA PCI or PCI-X boards.

3.1 Reference Design Architecture

Towards PCI bus T wards Application

Reference Design

PCI-PCIX Core
DMA
FIFO

DMA management
module

Slave management
module LEDs

Reference Design implements the following modules:

• DMA management: handles two independent DMA channels, one that reads data from host memory, the
other that writes it back to host memory. Both channels use the PCI core scatter-gather (DMA chaining)
capability.
• Slave management: handles target-mode read and writes accesses to a memory-mapped on-chip SRAM
memory (memory read is performed with split in PCI-X mode) and registers including a mailbox register.

3.2 Directory Structure

Table 4: Reference Design Directory structure

• sim: ModelSim simulation environment

• script
• simulation scripts (xx_script.txt)

• src: source files

• vhdl: design files
• vlog: design files

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Reference Design PCI-X & PCI Core Getting Started

3.3 File Structure

The Sources directory contains the VHDL design files shown below:

pcixpci_core_64
pcixpci_core_32

(Core Module
instance)
ref_design_64
ref_design_32

(top level) slave_mgt dcrambe

manages memory model

int memory
and registers

dm a_mgt scfifo dcram

Performs DMA FIFO model Memory model

transfers

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PCI-X & PCI Core Getting Started Reference Design

3.4 Detailed Modules Description

Table 5: Detailed modules description

Module Description

dcram Generic DCRAM model available in ASIC (RTL description) and Stratix (uses
Altera memory primitives).

scfifo Generic Single Clock FIFO model

dcrambe Generic DPRAM with Byte Enable model available in ASIC (RTL description)
Stratix (uses Altera memory primitives) versions.

dma_mgt DMA management module handles two DMA channels that connect to the Core
Master interface through a 64-bit X 256 Words FIFO. The FIFO uses PLDA’s
scfifo general purpose single-clock FIFO model. A set of memory-mapped
registers (accessible from the PCI bus) is used to set up DMA registers and start
transfers.

slave_mgt Slave management module instantiates a 1-KB synchronous dual-port RAM

using PLDA’s plda_dpram general purpose DPRAM model. the memory is
mapped in BAR 2/3 address space and can be read to or written from the PCI
bus. The registers are mapped in the BAR 0 / 1 address space.

ref_design_32 Reference Design top-level that connects the peripheral modules together with
ref_design_64 32-bit or 64_bit datapath

pcixpci_core_32 ToPCI-X & PCI core instance generated with the PCI Wizard. This wrapper
pcixpci_core_64 contains custom core settings for this design. The core is configured to support
the following options:
• DMA0: Write to FIFO, read from PCI
• DMA1: Read from FIFO, write to PCI
• BAR 0/1: 4 KB memory space (registers)
• BAR 2/3: 4 KB memory space (internal SRAM)

refdesign_xxx Top-level for a specific board, connects board specific resource to the design.

3.5 Registers
The table below describes the registers used by the Reference Design, mapped in BAR0/1 space.

Table 6: Registers description

Register Description Offset

DMA0_ADDR32 DMA0 address bits [31:0] 00h

DMA0_ADDR64 DMA0 address bits [63:32] 04h

DMA0_SIZE DMA0 transfer size in bytes. Bits [19:0] are implemented, other bits are 08h
tied to ‘0’ so maximum size is 512KB.

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Reference Design PCI-X & PCI Core Getting Started

Table 6: Registers description

Register Description Offset

DMA0_CTRL DMA Control 0Ch

• DMA0_CTRL[1]: Enables demo mode
• DMA0_CTRL[2]: Starts DMA
• DMA0_CTRL[3]: Abort transfer and clear FIFO
• DMA0_CTRL[4]: Enable scatter-gather
• DMA0_CTRL[7:5]: reserved
• DMA0_CTRL[11:8]: Reports DMA0 channel state
• DMA0_CTRL[9:15]: reserved
• DMA0_CTRL[31:16]: Reports number of DMA finished per 50 ms period
(demo mode)

DMA1 DMA1 control registers (same layout as DMA0) 10h..1Ch

STATUS_REG Bits [7:0] report Reference Design version. 20h

MAILBOX_REG General purpose 32-bit read / write register. Bits [2:0] are connected to 24h
onboard LEDs

INT_REG Bit 0 indicates an interrupt request; writing 1 to this bit clears interrupt 34h

reserved -- other

3.6 Simulation
A simulation environment is provided for Modelsim, NCSim & VCS. PCI-X & PCI testbench reads the pci_script.txt
and pci_mem.txt files and executes the specified commands. These files can be modified to generate different
patterns. Different scripts can be found in the script sub-directory.
Follow these steps to simulate the Reference Design with Modelsim :
1. Open Modelsim
2. Change working directory to ../ref_design/sim (File → Change Directory)
3. Run following script:
do simulate.tcl model $language $busmode $scenario
Where $language can be “vhdl” or “vlog”, $busmode can be “pci” or “pcix” and $scenario can be “target”, “dma” or
“sg”

Follow these steps to simulate the Reference Design with NCSim :

1. Open a shell
2. Change working directory to ../ref_design/sim (File → Change Directory)
3. Run following script :
sh simulate.tcl ncsim $language $busmode $scenario
Where $language can be “vhdl” or “vlog”, $busmode can be “pci” or “pcix” and $scenario can be “target”, “dma” or
“sg”

Follow these steps to simulate the Reference Design with VCS :

1. Open a shell
2. Change working directory to ../ref_design/sim (File → Change Directory)
3. Run following script :
sh simulate.tcl vcs vlog $busmode $scenario
Where $busmode can be “pci” or “pcix” and $scenario can be “target”, “dma” or “sg”

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PCI-X & PCI Core Getting Started Reference Design

The sequence of operations performed by the simulation script is:

• Install the PCIXPCI core and testbench libraries
• Refresh the libraries (in case an earlier version of Modelsim is used)
• Compile design files from the ../sources directory
• Load the design top-level and set-up simulation. Simulation will run until all commands from pci_script.txt
have been parsed
• Simulation results can be viewed on the waveform or from the generated pci_master_log.htm and
pci_target_log.htm files.

17