EXPERIMENT NO:-1(A)

AIM: - To write a program in VHDL to Implement XOR gate

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity xorgate is
Port ( x,y : in BIT;
z : out BIT);
end xorgate;

architecture Behavioral of xorgate is

begin
z<= x xor y;
end Behavioral;
TRUTH TABLE

X Y Z

0 0 0
0 1 1
1 0 1
1 1 0

WAVEFORM:
 EXPERIMENT NO:-1(B)

AIM: - To write a program in VHDL to Implement OR gate

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity orGATE is
Port ( x,y : in BIT;
z : out BIT);
end orGATE;

architecture dataflow of orGATE is

begin
z <= x or y;
end dataflow;
TRUTH TABLE

x y z
0 0 0
0 1 1
1 0 1
1 1 1

WAVEFORM:
 EXPERIMENT NO:-1(C)

AIM: - To write a program in VHDL to Implement NOR gate

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity norgate is
Port ( x,y : in BIT;
z : out BIT);
end norgate;

architecture Behavioral of norgate is

begin
z <= x nor y;
end Behavioral;
TRUTH TABLE

x y z
0 0 1
0 1 0
1 0 0
1 1 0

WAVEFORM:
 EXPERIMENT NO:-1(D)

AIM: - To write a program in VHDL to Implement NAND gate

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity nandgate is
Port ( x,y : in BIT;
z : out BIT);
end nandgate;

;
architecture Behavioral of nandgate is
begin
z <= x nand y;
end Behavioral;
TRUTH TABLE

x y z

0 0 1
0 1 1
1 0 1
1 1 0

WAVEFORM:
 EXPERIMENT NO:-1(E)

AIM: - To write a program in VHDL to Implement NOT gate

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity notgate is
Port ( x : in BIT;
z : out BIT);
end notgate;

architecture Behavioral of notgate is

begin

z<= not x;
end Behavioral;
TRUTH TABLE

x z

0 1

1 0

WAVEFORM:
 EXPERIMENT NO:-1(F)

AIM: - To write a program in VHDL to Implement AND gate

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity and23 is
Port ( x,y : in BIT;
z : out BIT);
end and23;

architecture dataflow of GATE is

begin
C <= A xor B;
end dataflow;
TRUTH TABLE

x y z
0 0 0

0 1 0

1 0 0

1 1 1

WAVEFORM:
 EXPERIMENT NO:-2(A)

AIM: - To write a program in VHDL to Implement Half Adder

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ha1 is
Port ( i : in STD_LOGIC;
j : in STD_LOGIC;
k : out STD_LOGIC;
l : out STD_LOGIC);
end ha1;

architecture dataflow of ha1 is

begin
k<=i xor j;
l<=i and j;
end dataflow;
TRUTH TABLE

i j k l
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

WAVEFORM
 EXPERIMENT NO:-2(B)

AIM: - To write a program in VHDL to Implement full Adder

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity fa5 is
Port ( i : in STD_LOGIC;
j : in STD_LOGIC;
k : in STD_LOGIC;
l : out STD_LOGIC;
m : out STD_LOGIC);
end fa5;

architecture Behavioral of fa5 is

begin
l<=(i xor j xor k);
m<=(i and j) or (j and k) or(k and i);
end Behavioral;
TRUTH TABLE

i j k l m
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

WAVEFORM
 EXPERIMENT NO:-3(A)

AIM:-To Write a Program in VHDL to Implement MULTIPLEXER

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity mux is
Port ( k : in STD_LOGIC;
b : in STD_LOGIC;
c : in STD_LOGIC;
d : in STD_LOGIC;
s : in STD_LOGIC_VECTOR (0 to 1);
z : out STD_LOGIC);
end mux;

architecture dataflow of mux is

begin
with s select
z<= k when "00",
b when "01",
c when "10",
d when "11",
'X' when others;
end dataflow;
TRUTH TABLE
s(0) s(1) k b c d z(output)
X X 0 0 0 0 X
0 0 1 0 0 0 1
0 1 0 1 0 0 1
1 0 0 0 1 0 1
1 1 0 0 0 1 1

WAVEFORM:

EXPERIMENT NO:-3(B)
AIM:-To Write a Program in VHDL to Implement DEMULTIPLEXER
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity demux is
Port ( X0 : in STD_LOGIC;
X1 : in STD_LOGIC;
W0 : in STD_LOGIC;
S0 : out STD_LOGIC;
S1 : out STD_LOGIC;
S2 : out STD_LOGIC;
S3 : out STD_LOGIC);
end demux;

architecture Behavioral of demux is

begin
process (X0,X1)
begin
if (X0 = '0') and (X1 = '0') then
S0 <=W0;
elsif (X0 = '0') and (X1 = '1') then
S1 <=W0;
elsif (X0 = '1') and (X1 = '0') then
S2 <= W0;
else
S3 <= W0;
end if;
end process;
end Behavioral;

TRUTH TABLE

X0 X1 W0 S3 S2 S1 S0
(o/p) (o/p) (o/p) (o/p)
0 0 1 0 0 0 1

0 1 1 0 0 1 0

1 0 1 0 1 0 0

1 1 1 1 0 0 0

WAVEFORM:
EXPERIMENT NO:-4(A)
 AIM:-To Write a Program in VHDL to Implement Encoder

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity ENCODE is
Port ( p : in STD_LOGIC_VECTOR (7 downto 0);
q : out STD_LOGIC_VECTOR (2 downto 0));
end ENCODE;

architecture Behavioral of ENCODE is

begin
process(p)
begin
if p = "00000001" then q <= "000";
elsif p = "00000010" then q <= "001";
elsif p = "00000100" then q <= "010";
elsif p = "00001000" then q <= "011";
elsif p = "00010000" then q <= "100";
elsif p = "00100000" then q <= "101";
elsif p = "01000000" then q <= "110";
else q <= "111";
end if;
end process;
end Behavioral;
TRUTH TABLE

p(7) p(6) p(5) p(4) p(3) p(2) p(1) p(0) q(2) q(1) q(0)
0 0 0 0 0 0 0 1 0 0 0
0 0 0 0 0 0 1 0 0 0 1
0 0 0 0 0 1 0 0 0 1 0
0 0 0 0 1 0 0 0 0 1 1
0 0 0 1 0 0 0 0 1 0 0
0 0 1 0 0 0 0 0 1 0 1
0 1 0 0 0 0 0 0 1 1 0
1 0 0 0 0 0 0 0 1 1 1

WAVEFORM:-
 EXPERIMENT NO:-4(B)

AIM:-To Write a Program in VHDL to Implement DECODER

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity DECODE is
Port (m: in bit_vector (2 downto 0);
n: out bit_vector (7 downto 0));
end DECODE;

architecture Behavioral of DECODE is

begin
process(m)
begin
if m = "000" then n <= "00000001";
elsif m = "001" then n <= "00000010";
elsif m = "010" then n <= "00000100";
elsif m = "011" then n <= "00001000";
elsif m = "100" then n <= "00010000";
elsif m = "101" then n <= "00100000";
elsif m = "110" then n <= "01000000";
else n <= "10000000";
end if;
end process;
end Behavioral;
TRUTH TABLE

m(2) m(1) m(0) n(7) n(6) n(5) n(4) n(3) n(2) n(1) n(0)
0 0 0 0 0 0 0 0 0 0 1
0 0 1 0 0 0 0 0 0 1 0
0 1 0 0 0 0 0 0 1 0 0
0 1 1 0 0 0 0 1 0 0 0
1 0 0 0 0 0 1 0 0 0 0
1 0 1 0 0 1 0 0 0 0 0
1 1 0 0 1 0 0 0 0 0 0
1 1 1 1 0 0 0 0 0 0 0

WAVEFORM:
 EXPERIMENT NO:-5

AIM: - To write a program in VHDL to Implement ONE BIT

COMPARATOR

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity comp1 is
port(x,y:in bit;
p:out bit_vector(2 downto 0));
end comp1;

architecture Behavioral of comp1 is

begin
process(x,y)
begin
if(x>y)then
p(0)<='0';
p(1)<='0';
p(2)<='1';
elsif(x=y)then
p(0)<='0';
p(1)<='1';
p(2)<='0';
elsif(x<y)then
p(0)<='1';
p(1)<='0';
p(2)<='0';
end if;
end process;
end Behavioral;

TRUTH TABLE

x y P(2) P(1) P(0)

0 0 0 1 0
0 1 0 0 1
1 0 1 0 0

1 1 0 1 0

WAVEFORM:
 EXPERIMENT NO:-6

AIM: - To write a program in VHDL to Implement SEVEN SEGMENT

DISPLAY

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity seg is
Port ( lmn : in BIT_VECTOR (0 to 3);
abc : out BIT_VECTOR (0 to 6));
end seg;

architecture Behavioral of seg is

begin
process(lmn)
begin
case lmn is
when "0000" =>abc<="1111110";
when "0001" =>abc<="0110000";
when "0010" =>abc<="1101101";
when "0011" =>abc<="1111001";
when "0100" =>abc<="0110011";
when "0101" =>abc<="1011011";
when "0110" =>abc<="1011111";
 when "0111" =>abc<="1110000";
when "1000" =>abc<="1111111";
when "1001" =>abc<="1111011";
when others =>abc<="0000000";
end case;
end process;
end Behavioral;

TRUTH TABLE

lmn lmn lmn abc abc abc abc abc abc abc
(0) (1) (2) (0) (1) (2) (3) (4) (5) (6)

0 0 0 1 1 1 1 1 1 0
0 0 1 0 1 1 0 0 0 0
0 1 0 1 1 0 1 1 0 1
0 1 1 1 1 1 1 0 0 1
1 0 0 0 1 1 0 0 1 1

1 0 1 1 0 1 1 0 1 1

1 1 0 1 0 1 1 1 1 0

1 1 1 1 1 1 0 0 0 0
WAVEFORM
 EXPERIMENT NO:-7

AIM:-To Write a Program in VHDL to Implement D FLIP FLOP

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity dff is
Port ( d,clk,rst : in bit;
q : inout bit);
end dff;

architecture Behavioral of dff is

begin
process(d,clk,rst,q)
begin
if( clk = '1' and clk 'event) then
if ( rst = '1') then
q <= '0';
else if (rst = '0') then
q <= d;
end if;
end if;
end if;
end process;
end behavioral;

TRUTH TABLE

Q D Q[T+1]
0 0 0
0 1 1
1 0 0
1 1 1

WAVEFORM:
 EXPERIMENT NO:-8

AIM:-To Write a Program in VHDL to Implement SISO Register

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity SISO is
Port ( e,p,c,clk : in bit;
z : out bit);
end SISO;
architecture structural of SISO is
component dff
port(in1, in2, in3, in4 : in bit; out1 : out bit);
end component;
signal q : bit_vector( 2 downto 0);
begin
d0 : dff port map (e,p,c,clk,q(0));
d1 : dff port map (q(0),p,c,clk,q(1));
d2 : dff port map (q(1),p,c,clk,q(2));
d3 : dff port map (q(2),p,c,clk,z);
end structural;

WAVEFORM:
 EXPERIMENT NO:-9(A)

AIM:-To Write a Program in VHDL to Implement Half subtractor

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity HS is
Port ( u,v : in bit;
d,b : out bit);
end HS;

architecture dataflow of HS is
begin
d <= u xor v;
b <= not u and v;
end dataflow;

TRUTH TABLE

u v d b
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0

WAVEFORM:
 EXPERIMENT NO:-9(B)

AIM:-To Write a Program in VHDL to Implement Full subtractor

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity fs1 is
Port ( x,y,z : in bit;
diff,borr : out bit);
end fs1;
architecture dataflow of fs1 is
begin
diff <= (not x and not y and z) or(not x and not y and not z) or (x and y and z) or ( x and not y
and not z);
borr <= (not x and y) or ( not x and z) or (y and z);
end dataflow;

TRUTH TABLE

x y z diff borr
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1
WAVEFORM: