Basic FPGA

Architecture

© 2005 Xilinx, Inc. All Rights Reserved

 Objectives
After completing this module, you will be
able to:
• Identify the basic architectural resources of the
Virtex™-II FPGA
• List the differences between the Virtex-II, Virtex-II
Pro, Spartan™-3, and Spartan-3E devices
• List the new and enhanced features of the new
Virtex-4 device family

Basic FPGA Architecture 2 - 2 © 2005 Xilinx, Inc. All Rights Reserved

For Academic Use Only
 Outline
• Overview
• Slice Resources
• I/O Resources
• Memory and Clocking
• Spartan-3, Spartan-
3E, and Virtex-II Pro
Features
• Virtex-4 Features
• Summary
• Appendix

Basic FPGA Architecture 2 - 3 © 2005 Xilinx, Inc. All Rights Reserved

For Academic Use Only
 Overview
• All Xilinx FPGAs contain the same basic resources
– Slices (grouped into CLBs)
• Contain combinatorial logic and register resources
– IOBs
• Interface between the FPGA and the outside world
– Programmable interconnect
– Other resources
• Memory
• Multipliers
• Global clock buffers
• Boundary scan logic

Basic FPGA Architecture 2 - 4 © 2005 Xilinx, Inc. All Rights Reserved

For Academic Use Only
 Virtex-II Architecture
Block I/O Blocks (IOBs)
SelectRAM™
resource

Programmable
interconnect
Dedicated
multipliers
Configurable
Logic Blocks
(CLBs)

• Virtex™-II architecture’s
core voltage Clock Management
operates at 1.5V
(DCMs, BUFGMUXes)

Basic FPGA Architecture 2 - 5 © 2005 Xilinx, Inc. All Rights Reserved

For Academic Use Only
 Outline
• Overview
• Slice Resources
• I/O Resources
• Memory and Clocking
• Spartan-3, Spartan-
3E, and Virtex-II Pro
Features
• Virtex-4 Features
• Summary
• Appendix

Basic FPGA Architecture 2 - 6 © 2005 Xilinx, Inc. All Rights Reserved

For Academic Use Only
 Slices and CLBs
• Each Virtex -II CLB COUT COUT
BUFT
contains BUF T
four slices Slice S3
– Local routing provides
feedback between slices
Slice S2
in the same CLB, and it Switch SHIFT
provides routing to Matrix

neighboring CLBs
Slice S1
– A switch matrix provides
access
Slice S0
to general routing Local Routing

resources
CIN CIN

Basic FPGA Architecture 2 - 7 © 2005 Xilinx, Inc. All Rights Reserved

For Academic Use Only
 Simplified Slice Structure
• Each slice has four outputs
– Two registered outputs,
two non-
registered outputs Slice 0
– Two BUFTs associated PRE
with each CLB, accessible LUT Carry D
CE
Q

by all 16 CLB outputs CLR

• Carry logic runs vertically,
up only
– Two independent
carry chains LUT Carry D PRE
per CLB CE Q

CLR

Basic FPGA Architecture 2 - 8 © 2005 Xilinx, Inc. All Rights Reserved

For Academic Use Only
 Detailed Slice Structure
• The next few slides
discuss the slice
features
– LUTs
– MUXF5, MUXF6,
MUXF7, MUXF8
(only the F5 and
F6 MUX are shown
in this diagram)
– Carry Logic
– MULT_ANDs
– Sequential Elements

Basic FPGA Architecture 2 - 9 © 2005 Xilinx, Inc. All Rights Reserved

For Academic Use Only
 Look-Up Tables
• Combinatorial logic is stored in Look- A B C D Z
Up Tables (LUTs) 0 0 0 0 0
– Also called Function Generators (FGs) 0 0 0 1 0
– Capacity is limited by the number of 0 0 1 0 0
inputs, not by the complexity 0 0 1 1 1
0 1 0 0 1
• Delay through the LUT is constant
0 1 0 1 1
. . .
Combinatorial Logic
1 1 0 0 0
A 1 1 0 1 0
B
Z 1 1 1 0 0
C 1 1 1 1 1
D

Basic FPGA Architecture 2 - 10 © 2005 Xilinx, Inc. All Rights Reserved

For Academic Use Only
 Connecting Look-Up Tables
MUXF8 combines the
CLB

F8
two MUXF7 outputs

F5
(from the CLB above
Slice S3 or below)
MUXF6 combines

F6
slices S2 and S3

F5
Slice S2

MUXF7 combines the

F7

two MUXF6
Slice S1
F5

outputs
MUXF6 combines slices S0 and S1
F6

Slice S0
F5

MUXF5 combines LUTs in each slice

Basic FPGA Architecture 2 - 11 © 2005 Xilinx, Inc. All Rights Reserved

For Academic Use Only
 Fast Carry Logic
• Simple, fast, and COUT COUT
To S0 of the
complete next CLB
To CIN of S2 of the next
CLB
arithmetic Logic SLICE
– Dedicated XOR S3
First Carry CIN
gate for single- Chain COUT
level sum
completion SLICE
S2
– Uses dedicated
routing resources SLICE
– All synthesis tools CIN
S1
Second
can infer carry COUT
Carry
logic Chain
SLICE
S0
CIN CIN CLB

Basic FPGA Architecture 2 - 12 © 2005 Xilinx, Inc. All Rights Reserved

For Academic Use Only
 MULT_AND Gate
• Highly efficient multiply and add implementation
– Earlier FPGA architectures require two LUTs per bit to
perform the multiplication and addition
– The MULT_AND gate enables an area reduction by
performing the
multiply and the add in one LUT per bit
LUT

A S CO
DI
CY_MUX
CI

CY_XOR

MULT_AND

AxB

LUT

B LUT

Basic FPGA Architecture 2 - 13 © 2005 Xilinx, Inc. All Rights Reserved

For Academic Use Only
 Flexible Sequential Elements
• Either flip-flops or latches FDRSE_1
• Two in each slice; eight in each D S Q
CLB CE

• Inputs come from LUTs or from an R

independent CLB input
FDCPE
• Separate set and reset controls
– Can be synchronous or D PRE Q
CE
asynchronous
• All controls are shared within a CLR

slice
– Control signals can be inverted LDCPE

locally within a slice D PRE Q

CE
G
CLR

Basic FPGA Architecture 2 - 14 © 2005 Xilinx, Inc. All Rights Reserved

For Academic Use Only
 Shift Register LUT
(SRL16CE)
• Dynamically addressable LUT
serial shift registers D D Q
CE
CE
– Maximum delay of 16 clock CLK
cycles per LUT (128 per
D Q
CLB) CE

– Cascadable to other LUTs or

CLBs for longer shift D Q Q
CE
registers
• Dedicated connection from
Q15 to D input of the next
SRL16CE
– Shift register length can
LUT
D Q
CE
be changed
asynchronously A[3:0]
Q15 (cascade out)
by toggling address A

Basic FPGA Architecture 2 - 15 © 2005 Xilinx, Inc. All Rights Reserved

For Academic Use Only
 Shift Register LUT Example
• The SRL can be used to create a No Operation (NOP)
– This example uses 64 LUTs (8 CLBs) to replace 576
flip-flops (72 CLBs) and associated routing and delays

12 Cycles

Operation A Operation B
64
4 Cycles 8 Cycles
64
Operation C Operation D -
NOP
3 Cycles 9 Cycles
Paths are Statically
Balanced
12 Cycles

Basic FPGA Architecture 2 - 16 © 2005 Xilinx, Inc. All Rights Reserved

For Academic Use Only
 Outline
• Overview
• Slice Resources
• I/O Resources
• Memory and Clocking
• Spartan-3, Spartan-
3E, and Virtex-II Pro
Features
• Virtex-4 Features
• Summary
• Appendix

Basic FPGA Architecture 2 - 17 © 2005 Xilinx, Inc. All Rights Reserved

For Academic Use Only
 IOB Element
• Input path
IOB
– Two DDR registers Input
DDR MUX
Reg
• Output path OCK1 Reg
– Two DDR registers ICK1
– Two 3-state enable Reg
OCK2 3-state Reg
DDR registers
ICK2
• Separate clocks and
clock enables for I and O DDR MUX
Reg
• Set and reset signals OCK1
PAD
are shared
Reg
OCK2 Output

Basic FPGA Architecture 2 - 18 © 2005 Xilinx, Inc. All Rights Reserved

For Academic Use Only
 SelectIO Standard
• Allows direct connections to external signals of varied
voltages and thresholds
– Optimizes the speed/noise tradeoff
– Saves having to place interface components onto your
board
• Differential signaling standards
– LVDS, BLVDS, ULVDS
– LDT
– LVPECL
• Single-ended I/O standards
– LVTTL, LVCMOS (3.3V, 2.5V, 1.8V, and 1.5V)
– PCI-X at 133 MHz, PCI (3.3V at 33 MHz and 66 MHz)
– GTL, GTLP
– and more!

Basic FPGA Architecture 2 - 19 © 2005 Xilinx, Inc. All Rights Reserved

For Academic Use Only
 Digital Controlled
Impedance (DCI)
• DCI provides
– Output drivers that match the impedance of the
traces
– On-chip termination for receivers and transmitters
• DCI advantages
– Improves signal integrity by eliminating stub
reflections
– Reduces board routing complexity and component
count by eliminating external resistors
– Eliminates the effects of temperature, voltage, and
process variations by using an internal feedback
circuit

Basic FPGA Architecture 2 - 20 © 2005 Xilinx, Inc. All Rights Reserved

For Academic Use Only
 Outline
• Overview
• Slice Resources
• I/O Resources
• Memory and
Clocking
• Spartan-3, Spartan-
3E, and Virtex-II Pro
Features
• Virtex-4 Features
• Summary
• Appendix

Basic FPGA Architecture 2 - 21 © 2005 Xilinx, Inc. All Rights Reserved

For Academic Use Only
 Other Virtex-II Features
• Distributed RAM and block RAM
– Distributed RAM uses the CLB resources (1 LUT = 16
RAM bits)
– Block RAM is a dedicated resources on the device (18-
kb blocks)
• Dedicated 18 x 18 multipliers next to block RAMs
• Clock management resources
– Sixteen dedicated global clock multiplexers
– Digital Clock Managers (DCMs)

Basic FPGA Architecture 2 - 22 © 2005 Xilinx, Inc. All Rights Reserved

For Academic Use Only
 Distributed SelectRAM
Resources
• Uses a LUT in a slice as RAM16X1S

memory
D
WE
WCLK
• Synchronous write LUT A0 O
A1
• Asynchronous read A2
A3
– Accompanying flip-flops
can be used to create RAM32X1S RAM16X1D
synchronous read D D
WE WE
• RAM and ROM are initialized Slice A0
WCLK
O A0
WCLK
SPO
during A1 A1

configuration LUT
A2
A3
A2
A3

Data can be written to RAM

A4 DPRA0 DPO
–
DPRA1

after configuration DPRA2

DPRA3
• Emulated dual-port RAM LUT
– One read/write port
– One read-only port

Basic FPGA Architecture 2 - 23 © 2005 Xilinx, Inc. All Rights Reserved

For Academic Use Only
 Block SelectRAM Resources
• Up to 3.5 Mb of RAM in 18-kb
18-kb block SelectRAM memory
blocks
DIA
– Synchronous read and write DIPA
• True dual-port memory ADDRA
WEA
– Each port has synchronous read
ENA
and write capability SSRA DOA
– Different clocks for each port CLKA DOPA
• Supports initial values
DIB
• Synchronous reset on output DIPB
latches ADDRB
WEB
• Supports parity bits ENB
– One parity bit per eight data bits SSRB DOB
CLKB DOPB

Basic FPGA Architecture 2 - 24 © 2005 Xilinx, Inc. All Rights Reserved

For Academic Use Only
 Dedicated Multiplier Blocks
• 18-bit twos complement signed operation
• Optimized to implement Multiply and Accumulate
functions
• Multipliers are physically located next to block
SelectRAM™ memory
Data_A
(18 bits) 4 x 4 signed

18 x 18 Output 8 x 8 signed
Multiplier (36 bits)

Data_B 12 x 12
(18 bits) signed
18 x 18
signed
Basic FPGA Architecture 2 - 25 © 2005 Xilinx, Inc. All Rights Reserved
For Academic Use Only
 Global Clock Routing
Resources
• Sixteen dedicated global clock multiplexers
– Eight on the top-center of the die, eight on the
bottom-center
– Driven by a clock input pad, a DCM, or local routing
• Global clock multiplexers provide the following:
– Traditional clock buffer (BUFG) function
– Global clock enable capability (BUFGCE)
– Glitch-free switching between clock signals
(BUFGMUX)
• Up to eight clock nets can be used in each clock
region of the device
– Each device contains four or more clock regions

Basic FPGA Architecture 2 - 26 © 2005 Xilinx, Inc. All Rights Reserved

For Academic Use Only
 Digital Clock Manager (DCM)
• Up to twelve DCMs per device
– Located on the top and bottom edges of the die
– Driven by clock input pads
• DCMs provide the following:
– Delay-Locked Loop (DLL)
– Digital Frequency Synthesizer (DFS)
– Digital Phase Shifter (DPS)
• Up to four outputs of each DCM can drive onto
global clock buffers
– All DCM outputs can drive general routing

Basic FPGA Architecture 2 - 27 © 2005 Xilinx, Inc. All Rights Reserved

For Academic Use Only
 Outline
• Overview
• Slice Resources
• I/O Resources
• Memory and Clocking
• Spartan-3, Spartan-
3E, and Virtex-II Pro
Features
• Virtex-4 Features
• Summary
• Appendix

Basic FPGA Architecture 2 - 28 © 2005 Xilinx, Inc. All Rights Reserved

For Academic Use Only
 Spartan-3 versus Virtex-II
• Lower cost • More I/O pins per package
Only one-half of the slices
Smaller process = lower
•
•
support RAM or SRL16s
core voltage (SLICEM)
– .09 micron versus .15 • Fewer block RAMs and
micron multiplier blocks
– Vccint = 1.2V versus – Same size and functionality
1.5V • Eight global clock multiplexers
• Different I/O standard • Two or four DCM blocks
support • No internal 3-state buffers
– 3-state buffers are in the I/O
– New standards: 1.2V
LVCMOS, 1.8V HSTL, and
SSTL
– Default is LVCMOS,
versus LVTTL

Basic FPGA Architecture 2 - 29 © 2005 Xilinx, Inc. All Rights Reserved

For Academic Use Only
 SLICEM and SLICEL
• Each Spartan™-3 CLB Right-Hand SLICEL
Left-Hand SLICEM
contains four slices COUT COUT

– Similar to the Virtex™-II

• Slices are grouped in Slice X1Y1
pairs
– Left-hand SLICEM
Slice X1Y0
(Memory) SHIFTIN
Switch
• LUTs can be configured Matrix
as memory or SRL16
– Right-hand SLICEL Slice X0Y1

(Logic)
• LUT can be used as logic Fast Connects
Slice X0Y0
only

CIN
SHIFTOUT CIN

Basic FPGA Architecture 2 - 30 © 2005 Xilinx, Inc. All Rights Reserved

For Academic Use Only
 Spartan-3E Features
• More gates per I/O than • 16 BUFGMUXes on left
Spartan-3 and right sides
• Removed some I/O – Drive half the chip
standards only
– Higher-drive LVCMOS – In addition to eight
– GTL, GTLP global clocks
– SSTL2_II
– HSTL_II_18, HSTL_I, HSTL_III
• Pipelined multipliers
– LVDS_EXT, ULVDS • Additional
• DDR Cascade configuration modes
– Internal data is presented – SPI, BPI
on a single clock edge – Multi-Boot mode

Basic FPGA Architecture 2 - 31 © 2005 Xilinx, Inc. All Rights Reserved

For Academic Use Only
 Virtex-II Pro Features
• 0.13 micron process
• Up to 24 RocketIO™ Multi-Gigabit Transceiver (MGT)
blocks
– Serializer and deserializer (SERDES)
– Fibre Channel, Gigabit Ethernet, XAUI, Infiniband
compliant transceivers, and others
– 8-, 16-, and 32-bit selectable FPGA interface
– 8B/10B encoder and decoder
• PowerPC™ RISC processor blocks
– Thirty-two 32-bit General Purpose Registers (GPRs)
– Low power consumption: 0.9mW/MHz
– IBM CoreConnect bus architecture support

Basic FPGA Architecture 2 - 32 © 2005 Xilinx, Inc. All Rights Reserved

For Academic Use Only
 Outline
• Overview
• Slice Resources
• I/O Resources
• Memory and Clocking
• Spartan-3, Spartan-
3E, and Virtex-II Pro
Features
• Virtex-4 Features
• Summary
• Appendix

Basic FPGA Architecture 2 - 33 © 2005 Xilinx, Inc. All Rights Reserved

For Academic Use Only
 Virtex-4 Features
• New features
– Dedicated DSP blocks
– Phase-matched clock dividers (PMCD)
– SERDES built into the Virtex™-4 SelectIO™ standard
– Dynamic reconfiguration port (DRP)
• Enhanced features
– Block RAM can be configured as a FIFO
– Advanced clocking networks, including regional clock
buffers and source- synchronous support
– 11.1 Gbps RocketIO™ Multi-Gigabit Transceiver (MGT)
blocks
– Enhanced PowerPC™ processor blocks

Basic FPGA Architecture 2 - 34 © 2005 Xilinx, Inc. All Rights Reserved

For Academic Use Only
 Outline
• Overview
• Slice Resources
• I/O Resources
• Memory and Clocking
• Spartan-3, Spartan-
3E, and Virtex-II Pro
Features
• Virtex-4 Features
• Summary
• Appendix

Basic FPGA Architecture 2 - 35 © 2005 Xilinx, Inc. All Rights Reserved

For Academic Use Only
 Review Questions
• List the primary slice features
• List the three ways a LUT can be configured

Basic FPGA Architecture 2 - 36 © 2005 Xilinx, Inc. All Rights Reserved

For Academic Use Only
 Answers
• List the primary slice features
– Look-up tables and function generators (two per slice,
eight per CLB)
– Registers (two per slice, eight per CLB)
– Dedicated multiplexers (MUXF5, MUXF6, MUXF7,
MUXF8)
– Carry logic
– MULT_AND gate
• List the three ways a LUT can be configured
– Combinatorial logic
– Shift register (SRL16CE)
– Distributed memory

Basic FPGA Architecture 2 - 37 © 2005 Xilinx, Inc. All Rights Reserved

For Academic Use Only
 Summary
• Slices contain LUTs, registers, and carry logic
– LUTs are connected with dedicated multiplexers and
carry logic
– LUTs can be configured as shift registers or memory
• IOBs contain DDR registers
• SelectIO™ standards and DCI enable direct
connection to multiple I/O standards while reducing
component count
• Virtex™-II memory resources include the following:
– Distributed SelectRAM™ resources and distributed
SelectROM (uses CLB LUTs)
– 18-kb block SelectRAM resources

Basic FPGA Architecture 2 - 38 © 2005 Xilinx, Inc. All Rights Reserved

For Academic Use Only
 Summary
• The Virtex™-II devices contain dedicated 18x18
multipliers next to each block SelectRAM™ resource
• Digital clock managers provide the following:
– Delay-Locked Loop (DLL)
– Digital Frequency Synthesizer (DFS)
– Digital Phase Shifter (DPS)

Basic FPGA Architecture 2 - 39 © 2005 Xilinx, Inc. All Rights Reserved

For Academic Use Only
 Where Can I Learn More?
• User Guides
– www.xilinx.com → Documentation → User Guides

• Application Notes
– www.xilinx.com → Documentation → Application Notes

• Education resources
– Designing with the Virtex-4 Family course
– Spartan-3E Architecture free Recorded e-Learning

Basic FPGA Architecture 2 - 40 © 2005 Xilinx, Inc. All Rights Reserved

For Academic Use Only
 Outline
• Overview
• Slice Resources
• I/O Resources
• Memory and Clocking
• Spartan-3, Spartan-
3E, and Virtex-II Pro
Features
• Virtex-4 Features
• Summary
• Appendix

Basic FPGA Architecture 2 - 41 © 2005 Xilinx, Inc. All Rights Reserved

For Academic Use Only
 Double Data Rate Registers
• DDR registers can be clocked
– By Clock and NOT(Clock) if the duty cycle is 50/50
– By the CLK0 and CLK180 outputs of a DCM

D1
Clock Reg DDR MUX OBUF
OCK1
PAD
D2
Reg
OCK2 FDDR
• If D1 = “1” and D2 = “0”, the output is a copy of Clock
– Use this technique to generate a clock output that is
synchronized to DDR output data

Basic FPGA Architecture 2 - 42 © 2005 Xilinx, Inc. All Rights Reserved

For Academic Use Only
 Dual-Port Block RAM
Configurations
• Configurations Configuratio Depth Data Bits Parity Bits
available on n
each port
16k x 1 16 kb 1 0
8k x 2 8 kb 2 0
4k x 4 4 kb 4 0
2k x 9 2 kb 8 1
1k x 18 1 kb 16 2
• Independent configurations
512 x 36 512 32 4
on ports A and B
Port A: 8
– Supports data-width IN 8 bit bits
conversion, including parity
bits
OUT 32 bit
Port B: 32
bits

Basic FPGA Architecture 2 - 43 © 2005 Xilinx, Inc. All Rights Reserved

For Academic Use Only
 Clock Buffer Configurations
• Clock buffer (BUFG)
– Low-skew clock distribution
I O
• Clock enable buffer (BUFGCE) G
F
U
B

– Holds the clock output Low

when Clock Enable (CE) is
inactive I O
E
C
G
F
U
B
– CE can be active-High or
active-Low CE
– Changes in CE are only
recognized when the clock
input is Low to avoid glitches
and short clock pulses

Basic FPGA Architecture 2 - 44 © 2005 Xilinx, Inc. All Rights Reserved

For Academic Use Only
 Clock Buffer Configurations
• Clock multiplexer
I0
(BUFGMUX)

BUFGMUX
– Switches from one O
clock to another, I1
glitch-free S
– After a change on S,
the BUFGMUX waits
for the currently S
Wait for low
selected clock input I0
to go Low Switch
I1
– The output is held
Low until the newly O

selected clock goes

Low, then switches

Basic FPGA Architecture 2 - 45 © 2005 Xilinx, Inc. All Rights Reserved

For Academic Use Only