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Eightyfiftyone 3

This document provides information about various modes and configurations of the 8051 shift register for transmitting and receiving serial data. It describes Mode 0 which uses a single pin for transmitting and receiving data at a fixed baud rate. Mode 1 implements a standard UART with start, stop and data bits. Mode 2 enables multiprocessor communication by examining the 9th data bit and interrupt flag. It also covers baud rate calculation, interrupts, and reset states of special function registers.

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rjohnhenrypaul
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© Attribution Non-Commercial (BY-NC)
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Download as PPTX, PDF, TXT or read online on Scribd
38 views

Eightyfiftyone 3

This document provides information about various modes and configurations of the 8051 shift register for transmitting and receiving serial data. It describes Mode 0 which uses a single pin for transmitting and receiving data at a fixed baud rate. Mode 1 implements a standard UART with start, stop and data bits. Mode 2 enables multiprocessor communication by examining the 9th data bit and interrupt flag. It also covers baud rate calculation, interrupts, and reset states of special function registers.

Uploaded by

rjohnhenrypaul
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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MODE0 – SHIFT REGISTER

MODE
HERE ; THROUGH THE PIN RXD WE TRANSMITT OR RECEIVE DATA . IT MEANS
SBUF & RECEIVE SBUF IS CONNECTED TO A SINGLE POINT RXD.
TRANSMIT

THE TXD PIN IS CONNECTED TO THE INTERNAL SHIFT FREQUENCY PULSE SOURCE TO
SUPPLY SHIFT PULSES TO EXTERNAL CIRCUITS.THE SHIFT FREQUENCY OR BAUD RATE IS
FIXED AT 1/12
OF THE OSCILLATOR FREQUENCY.

THE TXD SHIFT CLOCK IS A SQUARE WAVE THAT IS LOW FOR MACHINE CYCLE STATES
S3 - S4 - S5 S6 - S1 - S2
AND HIGH FOR

WHEN TRANSMITTING DATA IS SHIFTED OUT OF RXD;THE DATA CHANGES ON THE FALLING
EDGE OF .
S6 OF P2
WHEN RECEIVING ON RXD DATA IS SAMPLED ON THE FALLING EDGE OF
. AND S5 OF P2
SHIFTED INTO SBUF ON THE RISING EDGE OF THE SHIFT CLOCK.

MODE0 IS INTENDED NOT FOR DATA COMMUNICATION BETWEEN COMPUTERS ,BUT AS A HIGH
SPEED SERIAL DATA COLLECTION METHOD USING DISCRETE LOGIC TO ACHIVE HIGH DATA
RATES.
SERIAL DATA MODE1 – STANDARED UART
I N THIS MODE SBUF BECOMES A 10-BIT FULL-DUPLEX RECEIVER/TRANSMITTER THAT MAY
RECEIVE & TRANSMIT DATA AT THE SAME TIME.
PIN RXD ------- RECEIVES ALL DATA PIN TXD ------ TRANSMITS ALL DATA
TRANSMISSION STARTS WITH FIRST START BIT THEN LSB GOES OUT UNTIL MSB FINALLY
ONE STOP BIT.
START BIT IS ALWAYS LOW.
STOP BIT IS ALWAYS HIGH
EACH BIT INTERVAL IS THE INVERSE OF BAUD RATE FREQUENCY ,AND EACH BIT IS
MAINTAINED
HIGH OR LOW OVER THAT INTERVAL.
RECEPTION BEGINS WHEN A HIGH TO LOW TRANSITION SENSED ON RXD . DATA BITS ARE
SAMPLED AT THE BAUD RATE IN THE CENTER OF THE BIT DURATION PERIOD.THE RECEIVED
CHARACTER IS LOADED INTO SBUF AND THE STOP BIT INTO SCON BIT2 RB8

THE DATA WORD WILL BE READ FROM THE SBUF BY THE PROGRAM IF THE FOLLOWING
CONDITIONS ARE TRUE: 1)RI MUST BE 0 2)MODEBIT SM2 IS 0 3)IF IT RECEIVES NORMAL
STATE
OF STOP BITS.
SM2 SET TO 0 ENABLES THE RECEPTION OF A BYTE WITH ANY STOP BIT STATE.SM2 SET
TO ONE
FORCES RECEPTION OF ONLY GOOD STOP BITS.

RI SET TO ZERO IMPLIES THAT THE PROGRAM HAS READ THE PREVIOUS DATA BYTE AND IS
READY TO RECEIVE THE NEXT.
BAUD RATE IN 8051
EN CRYSTAL FREQUENCY = 11 . 0592
MACHINE CYCLE FRQ =
11 . 0592 / 12 MHz
E UART CIRCUITARY DIVIDES THE MACHINE CYCLE F
BY 32 ONCE MORE BEFORE IT IS USED BY
TIMER1
TO SET THE BAUD RATE

BAUD RATE =_________


11 . 0592 / 12
MHz
32
UD FREQ FOR RUNNING TIMER1 IN AUTORELOA
MODE
SMOD
fbaud Fosc / 12 ()/256 – ( TH1 )
=2 (_______________
32
R RUNNING TIMER1 IN MODES 0 & 1

2
SMOD

fbaud =___ ( Timer1 overflow frequenc


32
MODE - 2 THE MULTIPROCESSOR
MODE
1 2 3 4 5 6 7 8 9 ONE
STOP
START

BIT
STATE
IDLE

BIT

Bit time = 1 / f ELEVEN TRANSMITTED BITS 9BITSDATA


DURING TRANSMISSION BIT TB8 IN SCONIS COPIED TO BIT9 AND GET TRANSMITTED.
WHEN RECEIVING DATA DATA BIT9 IS COPIED INTO RB8.OF SCON

fbaud=__
2
SMOD
CRYSTAL FREQUENCY
64
DURING RECEPTION RI MUST BE ZERO BEFORE THE LAST BIT IS RECEIVED
IF SM2 = 1 THEN THE NINTH DATA BIT MUST BE A 1.
SETTING RI BASED ON THE STATE OF SM2 AND THE STATE OF BIT 9 IN THE
TRANSMITTED
MESSAGE MAKES MULTIPROCESSING POSSIBLE BY ENABLING SOME RECEIVERS TO BE
INTERRUPTED BY CERTAIN MESSAGES ,WHILE WE CAN MAKE OTHER RECEIVERS TO IGNORE
THOSE MESSAGES
INTERRUPT ENABLE
-IE
7
3
EA ----- ET2 ES ET1 EX1 ET0
6
2
5
1
4
0
EX0
EA ------ ENABLE ALL: IF CLEARED TO ZERO IT DISABLES ALL INTERRUPTS.

ES ----- ENABLE SERIAL PORT INTERRUPT

ET1 ------- ENABLE TIMER1 INTERRUPT

EX1 -------ENABLE EXTERNAL INTERRUPT1 INT1

------- ENABLE TIMER0 INTERRUPT


ET0
------- ENABLE EXTERNAL INTERRUPT0 INT0
EX0
INTERRUPT PRIORITY - IP
7 6 5 4
3 2 1 0
---- ---- PT2 PS PT1 PX1 PT0 PX0
PS PRIORITY SERIAL
IF TWO INTERRUPTS WITH SAME PRIORITY OCCUR AT THE
SAME TIME THEN THEY HAVE THE FOLLOWING RANKING.

PT1 PRIORITY TIMER1


IE0
 0003
PRIORITY EXTERNAL1
PX1 TFO
 000B
PRIORITY TIMER0
PT0 IE1
 0013
PRIORITY EXTERNAL0
PX0 TF1
 001B

SERIAL 0023

TI TERMINAL SESSION
EXTERNAL INTERRUPTS PRACTICAL
INPUTS CONSIDERATIONS
ON INT0 & INT1 PINS CAN SET THE INTERRUPTS FLAGS IE0
AND IE1 IN THE TCON REGISTER TO 1 BY TWO DIFF METHODS .
1 ) THE IEX FLAGS MAY BE SET WHEN THE INTX PIN SIGNAL REACHES
A LOW LEVEL .
2 ) THE FLAGS MAY BE SET WHEN A HIGH TO LOW TRANSITION TAKES
PLACE ON THE
INTX PIN LOW - LEVEL
8051 IS SET TO SENSE INTERRUPT
WHEN BITS IT0 AND IT1 IN TCON IS
SET TO 0
FLAGS IEX WILL BE RESET WHEN A TRANSITION GENERATED
INTERRUPT IS ACCEPTED BY
THE PROCESSOR AND THE INTERRUPT SUBROUTINE IS ACCESSED .

IT IS THE RESPONSIBILITY OF THE PROGRAMMER TO


RESET ANY LEVEL GENERATED EXTERNAL INTERRUPTS WHEN
THEY ARE SERVICED BY THE PROGRAM . THE EXTERNAL
CIRCUIT MUST REMOVE THE LOW LEVEL
BEFORE AN RETI IS EXECUTED .

FAILURE TO REMOVE THE LOW LEVEL WILL RESULT IN AN


REGISTER
PC VALUE
0000
DPTR 0000
A 00
B 00
SP 07
PSW 00
P0 TO P3 FF
IP XXX0000b
IE 0XX00000b
RESET STATE OF SFRS
TCON 00
TMOD 00
TH0 00
TL0 00
TH1 00
TL1 00
SCON 00
SBUF XX
PCON 0XXXXXXXb
NOTES ON DATA MOVE INSTRUCTION
8051 MNEMONICS ARE WRITTEN WITH THE DESTINATION ADDRESS NAMED FIRST FOLLOWED
BY THE SOURCE ADDRESS.

DIum satellite
THE WAYS BY WHICH THESE ADDRESSES ARE SPECIFIED ARE CALLED THE ADDRESSING
MODES

DATA MOVES ARE ALL OF FOLLOWING TYPES


1) MOV DESTINATION,SOURCE
2)PUSH SOURCE
3)POP DESTINATION
4)XCH DESTINATION , SOURCE

THE FOLLOWING FOUR ADDRESSING MODES ARE USED TO ACCESS DATA


1)IMMEDIATE ADDRESSING MODE
AN INSTRUCTION USING #.

2)REGISTER ADDRESSING MODE


INSTRUCTION USING R0 TO R7 OF CURRENT BANK.

3)DIRECT ADDRESSING MODE


INSTRUCTIONS USING RAM ADDRESS.

4)INDIRECT ADDRESSING MODE


INSTRUCTION USING @R0 OR @R1 OF CURRENT BANK.

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