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Successive Approximation ADC (SAR) First Year Project Project Description

This document describes a project to design and implement a successive approximation register (SAR) analog-to-digital converter (ADC). SAR ADCs use a binary search algorithm to convert an analog input voltage to a digital output. The project involves: 1) Designing a finite state machine to perform the binary search operation. 2) Implementing the FSM using discrete ICs and testing it. 3) Replacing the digital-to-analog converter with an IC and testing it. 4) Implementing the full SAR ADC circuit and testing its functionality.

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Marwan Ahmed
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32 views

Successive Approximation ADC (SAR) First Year Project Project Description

This document describes a project to design and implement a successive approximation register (SAR) analog-to-digital converter (ADC). SAR ADCs use a binary search algorithm to convert an analog input voltage to a digital output. The project involves: 1) Designing a finite state machine to perform the binary search operation. 2) Implementing the FSM using discrete ICs and testing it. 3) Replacing the digital-to-analog converter with an IC and testing it. 4) Implementing the full SAR ADC circuit and testing its functionality.

Uploaded by

Marwan Ahmed
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Successive Approximation ADC (SAR)

First Year Project

Project Description:
Analog to digital converters (ADCs) are devices that convert a continuous quantity (analog) to a
discrete quantity (digital). ADCs are very important in the data acquisition systems which handle
an analog continues time signals (such as voice and temperature) and approximates it to a digital
discrete time signal to be eligible to be stored in computers. There are many methods to design
ADCs, these methods provides the same functionality but with different performance
(conversion speed, IC area (design complexity), power consumption). In this project, you are
required to design and implement an ADC using one of these methods called Successive
Approximation.

There are many variations for implementing a SAR ADC but the basic architecture is quite
simple (see Figure). The analog input voltage (VIN) is held constant. To implement the binary
search algorithm, the N-bit register is first set to midscale (that is, 100... .00)b, where the MSB is
set to 1). This forces the DAC output (VDAC) to be VREF/2, where VREF is the reference
voltage provided to the ADC. A comparison is then performed to determine if VIN is less than,
or greater than, VDAC. If VIN is greater than VDAC, the comparator output is logic high, or 1,
and the MSB of the N-bit register remains at 1. Conversely, if VIN is less than VDAC, the
comparator output is a logic low and the MSB of the register is cleared to logic 0. The SAR
control logic then moves to the next bit down, forces that bit high, and does another comparison.
The sequence continues all the way down to the LSB. Once this is done, the conversion is
complete and the N-bit digital word is available in the register.

For more information: www.google.com  and also you will have some sessions with your TAs
Requirements:

First:
Design the engine that performs the binary search operation described before. This is basically a
FSM. You should design this FSM.

Second:
Implement this FSM using discrete ICs and check its functionality using random inputs.

Third:
You replace the DAC either with a single IC or a to implement it also. However, in both cases,
you should examine its correct functionality by itself.

Fourth:
Implement the whole circuit. Check its functionality.

Best Regards…,

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