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Vlsi File Half Adder

The document describes an experiment to design and simulate a half adder circuit using Tanner Tool. It includes the circuit diagram, T-Spice code for the design with 16 MOSFETs, and indicates that the layout and output waveform will be shown to study the characteristics of the half adder circuit.

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avinash960
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© Attribution Non-Commercial (BY-NC)
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Download as DOCX, PDF, TXT or read online on Scribd
1K views

Vlsi File Half Adder

The document describes an experiment to design and simulate a half adder circuit using Tanner Tool. It includes the circuit diagram, T-Spice code for the design with 16 MOSFETs, and indicates that the layout and output waveform will be shown to study the characteristics of the half adder circuit.

Uploaded by

avinash960
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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EXPERIMENT -9

AIM:
TO DESIGN A HALF ADDER CIRCUIT AND STUDY ITS CHARACTERISTICS USING TANNER
TOOL

CIRCUIT DIAGRAM

T-SPICE CODE

M12 2 4 1 14 PMOS L=2u W=6u AD=18p PD=12u AS=18p PS=12u

* M12 DRAIN GATE SOURCE BULK (56 17 58 23)

M11 1 5 7 14 PMOS L=2u W=6u AD=18p PD=12u AS=36p PS=24u

* M11 DRAIN GATE SOURCE BULK (48 17 50 23)

M10 2 6 1 14 PMOS L=2u W=6u AD=36p PD=24u AS=18p PS=12u

* M10 DRAIN GATE SOURCE BULK (64 17 66 23)

M9 5 8 7 14 PMOS L=2u W=6u AD=36p PD=24u AS=36p PS=24u

* M9 DRAIN GATE SOURCE BULK (28 17 30 23)

M8 8 9 7 14 PMOS L=2u W=6u AD=36p PD=24u AS=18p PS=12u

* M8 DRAIN GATE SOURCE BULK (8 17 10 23)

M7 8 10 7 14 PMOS L=2u W=6u AD=18p PD=12u AS=36p PS=24u


* M7 DRAIN GATE SOURCE BULK (0 17 2 23)

M6 2 4 13 12 NMOS L=2u W=6u AD=18p PD=12u AS=18p PS=12u

* M6 DRAIN GATE SOURCE BULK (56 -2 58 4)

M5 2 5 3 12 NMOS L=2u W=6u AD=18p PD=12u AS=36p PS=24u

* M5 DRAIN GATE SOURCE BULK (48 -2 50 4)

M4 13 6 3 12 NMOS L=2u W=6u AD=36p PD=24u AS=18p PS=12u

* M4 DRAIN GATE SOURCE BULK (64 -2 66 4)

M3 5 8 3 12 NMOS L=2u W=6u AD=36p PD=24u AS=36p PS=24u

* M3 DRAIN GATE SOURCE BULK (28 -2 30 4)

M2 11 9 3 12 NMOS L=2u W=6u AD=36p PD=24u AS=18p PS=12u

* M2 DRAIN GATE SOURCE BULK (8 -2 10 4)

M1 8 10 11 12 NMOS L=2u W=6u AD=18p PD=12u AS=36p PS=24u

* M1 DRAIN GATE SOURCE BULK (0 -2 2 4)

VPP 14 0 5V

VDD 7 0 5V

VNN 12 0 0V

VGG 3 0 0V

VAA 10 0 BIT({0011})

VBB 9 0 BIT({0101})

VAO 4 0 BIT({1100})

VBO 6 0 BIT({1010})

.TRAN 100ns 200ns

.PRINT V(2) V(5) V(9) V(10)

.include "C:\Tanner\TSpice70\models\ml2_125.md"
LAYOUT OF HALF ADDER CIRCUIT:
OUTPUT WAVEFORM FOR TRANSIENT CHARACTERISTICS OF

HALF ADDER CIRCUIT

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