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Experiment No. 1: Aim of The Experiment

This experiment aims to investigate the logic behavior of NOT, OR, AND, NAND, NOR, and EX-OR gates. It also demonstrates how to realize different gates using universal NAND and NOR gates. The experiment involves using digital IC chips to build each logic gate and verifying their truth tables. Procedures are provided for testing each gate and realizing gates using NAND and NOR gates. The conclusion is that the experiment demonstrates the logic behavior of the gates and how to realize other gates with NAND and NOR gates.

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RabindraMaharana
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10K views

Experiment No. 1: Aim of The Experiment

This experiment aims to investigate the logic behavior of NOT, OR, AND, NAND, NOR, and EX-OR gates. It also demonstrates how to realize different gates using universal NAND and NOR gates. The experiment involves using digital IC chips to build each logic gate and verifying their truth tables. Procedures are provided for testing each gate and realizing gates using NAND and NOR gates. The conclusion is that the experiment demonstrates the logic behavior of the gates and how to realize other gates with NAND and NOR gates.

Uploaded by

RabindraMaharana
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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EXPERIMENT NO.

1
AIM OF THE EXPERIMENT:
TO INVESTIGATE LOGIC BEHAVIOUR OF NOT ,OR, AND, NAND, NOR & EX-OR, GATE AND REALISATION OF
DIFFERENT GATE BY USING THE UNIVERSAL GATE i.e NAND AND NOR GATE.

APPARATUS REQUIRED:
(i)DIGITAL IC TRAINER KIT(VBBT)

(ii)DIGITAL IC’S 7404(FOR NOT OPERATION)

7408(FOR AND OPERATION)

7432(FOR OR OPERATION)

7400(FOR NAND OPERATION)

7402(FOR NOR OPERATION)

7486(FOR EX-OR OPERATION)

(iii) CONNECTING WIRES

(iv)POWER SUPPLY

THEORY:
LOGIC GATES:
A DIGITAL CIRCUIT WITH ONE OR MORE I/P SIGNALS BUT ONLY ONE OUTPUT SIGNAL IS CALLED A LOGIC
GATES.

NOT GATE :(IC 7404)


IT IS KNOWN AS LOGIC INVERTER .IT’S OUTPUT IS AVAILABLE WHEN THERE IS NO INPUT SIGNAL.

SYMBOL:
BOOLEAN EXPRESSION:
X=A’

TRUTH TABLE:

A X
0 1
1 0

AND GATE: (IC 7486)


THE O/P IS AVAILABLE ONLY WHEN ALL THE I/P S ARE AVAILABLE i.e THE OUTPUT IS AT LOGICAL “1” WHEN
ALL I/P ARE AT LOGIC “1”.

SYMBOL:

BOOLEAN EXPRESSION:
X=A.B

TRUTH TABLE
A B X
0 0 0
0 1 0
1 0 0
1 1 1

OR GATE:(IC 7432)
IT’S OUTPUT IS AVIALABLE ,IF ANY ONE OR MORE INPUT S ARE AVAILABLE .

SYMBOL:
BOOLEAN EXPRESSION:
X=A+B

TRUTH TABLE:

A B X
0 0 0
0 1 1
1 0 1
1 1 1

NAND GATE: (IC 7400)


IT’S OUT PUT IS AVAILABLETO ALL INPUTS STATES EXCEPT WHEN ALL THE INPUTS ARE AVAILABLE

i.e(AT LOGIC “1”).

SYMBOL:

BOOLEAN EXPRESSION:
X=(A.B)’

TRUTH TABLE:
A B X
0 0 1
0 1 1
1 0 1
1 1 0

NOR GATE: (IC 7402)


IT’S OUTPUT IS AVAILBLE ONLY WHEN NO INPUT IS AVILABLE i.e ALL INPUT ARE AT LOGICAL ‘0’.
SYMBOL:

BOOLEAN EXPRESSION:
X=(A+B)’

TRUTH TABLE:
A B X
0 0 1
0 1 0
1 0 0
1 1 0

EX-OR GATE:(IC 7486)


IT’S OUTPUT IS AVAILABLE WHEN BOTH INPUT ARE UN EQUAL i.e OUT PUT IS ‘1’ WHEN I/P IS ‘0’ &’1’OR ‘1’
&’0’.

SYMBOL:

BOOLEAN EXPRESSION:
X=A B

A B X
0 0 0
0 1 1
1 0 1
1 1 0
REALISATION OF GATES BY USING NOR GATE :
NOT GATE USING NOR GATE:

OR GATE USING NOR GATE:

AND GATE USING NOR GATE:

EX-OR GATE USING NOR GATE:


REALISATION OF GATES BY USING NAND GATE:
NOT GATE USING NAND GATE:

OR GATE USING NAND GATE:

AND GATE USING NAND GATE:

EX-OR GATE USING NAND GATE:

OBSERVATION TABLE FOR LOGIC GATES:


TABLE FOR NOT GATE:
A X
0
1
TABLE FOR AND GATE:
A B X
0 0
0 1
1 0
1 1

TABLE FOR OR GATE:


A B X
0 0
0 1
1 0
1 1

TABLE FOR NAND GATE:


A B X
0 0
0 1
1 0
1 1

TABLE FOR NOR GATE:


A B X
0 0
0 1
1 0
1 1

TABLE FOR EX-OR GATE:


A B X
0 0
0 1
1 0
1 1 TABULATION FOR REALISATION OF GATES
USING NAND GATE:
TABLE FOR NOT GATE:
A X
TABLE FOR AND GATE:
A B X
0 0
0 1
1 0
1 1

TABLE FOR OR GATE:


A B X
0 0
0 1
1 0
1 1

TABLE FOR EX-OR GATE:


A B X
0 0
0 1
1 0
1 1

REALISATION OF GATES USING NOR GATE:


TABLE FOR NOT GATE:
A X

TABLE FOR AND GATE:


A B X
0 0
0 1
1 0
1 1
TABLE FOR OR GATE:
A B X
0 0
0 1
1 0
1 1

TABLE FOR EX-OR GATE:


A B X
0 0
0 1
1 0
1 1

PROCEDURE:
1. PLACE ALL THE GIVEN IC’S PROPERLY ON THE SOLDER LESS BREAD BOARD OF THE LOGIC TRINER(VBBT).

2. CONNECT THE PIN NO 7 TO GND AND PIN NO 14 TO +5V OF IC 7404 USING PATCH CHORD PROVIDED.

3. CONNECT THE LOGIC INPUTS TO THE INPUT PINS OF THE IC WITH PATCH CHORDS AS PERTHE GIVEN
CONFIGURATION DIAGRAM OF THE IC.

4.CONNECT THE O/P PINS OF THE IC TO O/P LED INDICATOR TO OBSERVE THE LOGIC O/P.(REMEMBER IF LED
GLOWS RED IT MEANS LOGIC ‘1’ IF IT GLOWS GREEN IT MEANS LOGIC ‘0’).

5. THEN SWITCH ON THE POWER SUPPLY OF THE VBBT AND THEN GIVE THE LOGIC I/P’S AND VERIFY THE
TRUTH TABLE .

6. THEN SWITCH OFF THE POWER SWITCH OF VBBT.

7. REPEAT THE ABOVE STEPS FROM ‘2’ TO ‘6’ FOR ALL IC ‘S TO VERIFY THE TRUTH TABLEAS PER AND FILL
THE TABLE GIVEN.

PROCEDURE:(FOR REALISATION OF DIFFERENT GATES USING NAND &NOR


GATE)
1.CONNECT THE IC’S PIN S OF NAND GATE AS PER THE CONNECTION DIAGRAM GIVENI N THEORY.
2.THEN SWITCH ON THE POWER SUPPLY OF VBBT.

3.VERIFY THE LOGIC O/P OF ALL THE GATES & FILL THE THE TABLE.

4. THEN SWITCH OFF THE POWER SUPPLY OF THE VBBT.

5.REPEAT THE ABOVE STEPS FROM ‘1’ TO ‘4’ FOR NOR GATE ALSO .

CONCLUSION:
FROM THE ABOVE EXPERIMENT , WE CAN ABLE TO OBSERVE THE LOGIC BEHAVIOUR OF NOT ,OR, AND
,NAND,NOR &EX-OR GATE AND ALSO REALISE THE DIFFERENT GATES BY USING NAND NOR GATE.

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