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01 Verification Panel Smith

System Verilog is a hardware description and verification language that provides extensions for writing testbenches, including: 1) Basic types for strings, associative arrays, and dynamic data structures to model complex testbench components. 2) Clocking domains that define synchronous interfaces between the testbench and design for cycle-accurate verification. 3) Program blocks containing the testbench verification code that can access the design through clocking domain interfaces. 4) Process control statements for thread synchronization and event-driven simulation that model concurrent activities in the testbench.

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Mohammed Shaik
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© Attribution Non-Commercial (BY-NC)
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Download as PPT, PDF, TXT or read online on Scribd
25 views

01 Verification Panel Smith

System Verilog is a hardware description and verification language that provides extensions for writing testbenches, including: 1) Basic types for strings, associative arrays, and dynamic data structures to model complex testbench components. 2) Clocking domains that define synchronous interfaces between the testbench and design for cycle-accurate verification. 3) Program blocks containing the testbench verification code that can access the design through clocking domain interfaces. 4) Process control statements for thread synchronization and event-driven simulation that model concurrent activities in the testbench.

Uploaded by

Mohammed Shaik
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as PPT, PDF, TXT or read online on Scribd
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System Verilog

Testbench Language

David W. Smith
Synopsys Scientist
Synopsys, Inc.
Sample SOC and Testbench

DUT
Testbench

10/100M AHB APB External


Ethernet Ethernet Memory Memory
MAC Controller
CPU
1Gb Ethernet Core Serial
Ethernet MAC RS232 model
Ports
Ethernet
10Gb Parallel 1284
MAC
Ethernet Ports model
Control
USB Bluetooth Bluetooth
USB model Logic
controller model

Proprietary Proprietary PCI Infrared IR device


model Bus Controller Controller controller model

Protocol Checkers
Synchronous for Interface
Interface Boundaries PCI Model

5 December 2003 David W. Smith


System with Multiple SOC’s

Packet Switched Bus

Cache AMBA Cache AMBA Cache AMBA


CPU CPU CPU
FPU FPU FPU
Mem Mem Mem

SOC 1 SOC 2 SOC 3


DUT

• At System Level Problem is Exacerbated


• Abstractions and Re-use are Necessary!

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Testbench Requirements
• Stimulus Generation
• Directed, Random, ATPG, ...
• Checkers
• Data
• Protocols
• Structured Connection to Multiple Independent Interfaces
• Interconnect
• Clocking Domain
• Protocol
• Abstract Modeling
• High-level data structures
• Dynamic Memory
> Memory Management
• Re-entrant Processes
> Inter-process Synchronization, Control, and Communication
• Re-usability
• Single language for design (HDL) and verification (HVL)  HDVL

5 December 2003 David W. Smith 4


Basic Types
• Strings
• arbitrary and dynamic length
• methods to manipulate and convert strings
• operators for comparison, concatenation and replication
• Associative arrays
• Indexed by integer, string, or class
• first(index), last(index), next(index), prev(index), delete(index), and
exist(index) methods
• Dynamic arrays
• integer mem[*];
• mem.size();
• Linked Lists
• doubly linked list of any data type
• iterator, modification, access methods
• Classes, Objects and Methods
• Object Oriented
> Encapsulation, Inheritance, and Polymorphism
• Objects referenced with handles (Safe Pointers)

5 December 2003 David W. Smith 5


Random Variables and Constraints

Test Scenarios
• Valid Inputs Specified as Constraints
Constraints
• Declarative
Constraints

Input Space
Design

Constraint Solver
• Find solutions
Valid

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Random Variables and Constraints
• rand, randc, and constraint added to class definition
class Bus;
rand bit[15:0] addr;
rand bit[31:0] data;
constraint word_align { addr[1:0] == 2’b0; }
endclass

• Generate 50 data and quad-aligned addresses

Bus bus = new;


repeat(50)
begin
integer result = bus.randomize();
end

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Basic Additions
• Wild card operators (=?= and !?=)
• Pass by reference
Declaration: task tk( var int[1000:1] ar );
Use: tk( my_array ); // no & needed
• Argument default values and pass by name
Declaration: task foo( int j = 5, int k = 8 );
Use: foo(); foo( 6 ); foo( ,9 ); foo( 6, 9 ); foo(.k(9));

• Alias for nets


• Short nets in a module
• Dynamic Memory
• Objects, threads, strings, dynamic and associative arrays
• Automatically Managed

5 December 2003 David W. Smith 8


Process Control/Synchronization
• Verilog thread support from fork…join with continuation
when all threads complete
• SV threads use fork…join with continuation control
• all
• any
• none
all any none 3.0 process
priority

• Threads execute until a blocking statement


• wait for event, mailbox, semaphore, variable change, ...
• Enhanced events (value and duration, passed as arguments)
• Threads are controlled by
• $terminate
• $wait_child
• $suspend_thread
• $exit

5 December 2003 David W. Smith 9


Clocking Domain

• A clocking domain defines a synchronous interface for testbench and properties


• Every clocking domain has only one clock event
• Sample and drive timing specified with respect to clock
• A signal may appear in multiple clocking domains
• Input - multiple samples
• Output – default bus resolution
• Clocking domain creates a scope

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Synchronous Interfaces: Clocking
Race-free cycle and transaction level abstraction
clk
enable
device bus full Synchronous
data[7:0] Interface
empty

clocking bus @(posedge clk); Clocking Event “clock”


default input #1ns output #2ns; Default I/O skew

input enable, full; Hierarchical signal


inout data;
output empty;
Testbench Uses:
output #6ns reset = top.u1.reset;
bus.enable
endclocking bus.data
...
Override Output skew
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Testbench Program Block

• Purpose: contains testbench verification code


• program is similar to a module
• Only one implicit initial block
• Special semantics
Execute in verification phase


design  clocking  verification  read_only

program name ( port_list );


declarations (class, type, function, clocking...)
statements
endprogram

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System Verilog Testbench

Testbench

Verification Extensions
Testbench Specific
Basic Types
Aliases
Random Constraints Clocking Domains

Program Block
Process Control/Synchronization

References

5 December 2003 David W. Smith 13

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