PIC18F47J53 Family

Data Sheet
28/44-Pin, High-Performance
USB Microcontrollers
with nanoWatt XLP Technology

 2010 Microchip Technology Inc. Preliminary DS39964B

Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device Trademarks

applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, dsPIC,
and may be superseded by updates. It is your responsibility to KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,
ensure that your application meets with your specifications.
PIC32 logo, rfPIC and UNI/O are registered trademarks of
MICROCHIP MAKES NO REPRESENTATIONS OR
Microchip Technology Incorporated in the U.S.A. and other
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
countries.
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION, FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
INCLUDING BUT NOT LIMITED TO ITS CONDITION, MXDEV, MXLAB, SEEVAL and The Embedded Control
QUALITY, PERFORMANCE, MERCHANTABILITY OR Solutions Company are registered trademarks of Microchip
FITNESS FOR PURPOSE. Microchip disclaims all liability Technology Incorporated in the U.S.A.
arising from this information and its use. Use of Microchip Analog-for-the-Digital Age, Application Maestro, CodeGuard,
devices in life support and/or safety applications is entirely at dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
the buyer’s risk, and the buyer agrees to defend, indemnify and ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
hold harmless Microchip from any and all damages, claims, Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified
suits, or expenses resulting from such use. No licenses are logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code
conveyed, implicitly or otherwise, under any Microchip Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
intellectual property rights. PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance,
TSHARC, UniWinDriver, WiperLock and ZENA are
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2010, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.

ISBN: 978-1-60932-306-6

Microchip received ISO/TS-16949:2002 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.

DS39964B-page 2 Preliminary  2010 Microchip Technology Inc.

 PIC18F47J53 FAMILY
28/44-Pin, High-Performance USB MCUs with nanoWatt XLP Technology

Universal Serial Bus Features: Peripheral Highlights:

• USB V2.0 Compliant • Peripheral Pin Select:
• Low Speed (1.5 Mbps) and Full Speed (12 Mbps) - Allows independent I/O mapping of many peripherals
• Supports Control, Interrupt, Isochronous and Bulk - Continuous hardware integrity checking and safety
Transfers interlocks prevent unintentional configuration changes
• Supports up to 32 Endpoints (16 bidirectional) • Hardware Real-Time Clock/Calendar (RTCC):
• USB module can use any RAM Location on the
- Provides clock, calendar and alarm functions
Device as USB Endpoint Buffers
• High-Current Sink/Source 25 mA/25mA
• On-Chip USB Transceiver with Crystal-Less Operation
(PORTB and PORTC)
Power Management with nanoWatt XLP • Four Programmable External Interrupts
• Deep Sleep mode: CPU off, Peripherals off, Currents • Four Input Change Interrupts
Down to 13 nA and 850 nA with RTCC • Three Enhanced Capture/Compare/PWM (ECCP) modules:
- Able to wake-up on external triggers, - One, two or four PWM outputs
programmable WDT or RTCC alarm - Selectable polarity
- Ultra Low-Power Wake-up (ULPWU) - Programmable dead time
• Sleep mode: CPU off, Peripherals off, SRAM on, - Auto-shutdown and auto-restart
Fast Wake-up, Currents Down to 105 nA Typical - Pulse steering control
• Idle: CPU off, Peripherals on, Currents Down to • Seven Capture/Compare/PWM (CCP) modules
2.3 A Typical • Two Master Synchronous Serial Port (MSSP)
• Run: CPU on, Peripherals on, Currents Down to modules Supporting Three-Wire SPI (all four modes)
6.2 A Typical and I2C™ Master and Slave modes
• Timer1 Oscillator w/RTCC: 1 μA, 32 kHz Typical • Eight-Bit Parallel Master Port/Enhanced Parallel
• Watchdog Timer: 0.8 μA, 2V Typical Slave Port
• Three Analog Comparators with Input Multiplexing
Special Microcontroller Features: • 10/12-Bit Analog-to-Digital (A/D) Converter
• 5.5V Tolerant Inputs (digital-only pins) module:
• Low-Power, High-Speed CMOS Flash Technology - Up to 13 input channels
• C Compiler Optimized Architecture for Re-Entrant Code - Auto-acquisition capability
• Priority Levels for Interrupts - Conversion available during Sleep
• Self-Programmable under Software Control • High/Low-Voltage Detect module
• 8 x 8 Single-Cycle Hardware Multiplier • Charge Time Measurement Unit (CTMU):
• Extended Watchdog Timer (WDT): - Supports capacitive touch sensing for touch
- Programmable period from 4 ms to 131s screens and capacitive switches
• Single-Supply In-Circuit Serial Programming™ - Provides precise resolution time measure-
(ICSP™) via Two Pins ment for flow measurement and simple tem-
• In-Circuit Debug with Three Breakpoints via Two Pins perature sensing
• Operating Voltage Range of 2.0V to 3.6V • Two Enhanced USART modules:
• On-Chip 2.5V Regulator - Supports RS-485, RS-232 and LIN/J2602
• Flash Program Memory of 10,000 Erase/Write - Auto-wake-up on Start bit
Cycles Minimum and 20-Year Data Retention - Auto-Baud Detect (ABD)
Flexible Oscillator Structure:
• High-Precision PLL for USB
• Two External Clock modes, up to 48 MHz (12 MIPS)
• Internal, 31-kHz Oscillator
• High-Precision, Internal Oscillator for USB, 31 kHz to
8 MHz or 48 MHz w/PLL, ±.15% Typical, ±1% Max
• Secondary Oscillator using Timer1 at 32 kHz
• Fail-Safe Clock Monitor (FSCM):
- Allows for safe shutdown if any clock stops
• Programmable Reference Clock Output Generator

 2010 Microchip Technology Inc. Preliminary DS39964B-page 3

PIC18F47J53 FAMILY

10/12-Bit A/D (Ch)

MSSP

Memory (bytes)

SRAM (bytes)

Comparators
ECCP/(PWM)
Remappable

Deep Sleep

PMP/PSP
EUSART
Program

8/16-Bit

SPI w/DMA
Timers

CTMU

RTCC
PIC18F

Pins

Pins

USB
I2C™
Device

PIC18F26J53 28 64K 3.8K* 16 4/4 3/7 2 2 Y Y 10 3 Y N Y Y Y

PIC18F27J53 28 128K 3.8K* 16 4/4 3/7 2 2 Y Y 10 3 Y N Y Y Y
PIC18F46J53 44 64K 3.8K* 22 4/4 3/7 2 2 Y Y 13 3 Y Y Y Y Y
PIC18F47J53 44 128K 3.8K* 22 4/4 3/7 2 2 Y Y 13 3 Y Y Y Y Y
PIC18LF26J53 28 64K 3.8K* 16 4/4 3/7 2 2 Y Y 10 3 N N Y Y Y
PIC18LF27J53 28 128K 3.8K* 16 4/4 3/7 2 2 Y Y 10 3 N N Y Y Y
PIC18LF46J53 44 64K 3.8K* 22 4/4 3/7 2 2 Y Y 13 3 N Y Y Y Y
PIC18LF47J53 44 128K 3.8K* 22 4/4 3/7 2 2 Y Y 13 3 N Y Y Y Y
* Dual access RAM for USB and/or general purpose use.

DS39964B-page 4 Preliminary  2010 Microchip Technology Inc.

 PIC18F47J53 FAMILY
Pin Diagrams

RB4/CCP4/KBI0/SCK1/SCL1/RP7
RB5/CCP5/KBI1/SDI1/SDA1/RP8
28-Pin QFN

RA0/AN0/C1INA/ULPWU/RP0

RB7/CCP7/KBI3/PGD/RP10
RB6/CCP6/KBI2/PGC/RP9
RA1/AN1/C2INA/VBG/RP1

MCLR
28 27 26 25 24 23 22
RA2/AN2/C2INB/C1IND/C3INB/VREF-/CVREF 1 21 RB3/AN9/C3INA/CTED2/VPO/RP6
RA3/AN3/C1INB/VREF+ 2 20 RB2/AN8/C2INC/CTED1/VMO/REFO/RP5
VDDCORE/VCAP 3 19 RB1/AN10/C3INC/RTCC/RP4
RA5/AN4/C1INC/SS1/HLVDIN/RCV/RP2 4 PIC18F2XJ53 18 RB0/AN12/C3IND/INT0/RP3
VSS1 5 17 VDD
OSC1/CLKI/RA7 6 16 VSS2
OSC2/CLKO/RA6 7 15 RC7/CCP10/RX1/DT1/SDO1/RP18
8 9 10 11 12 13 14
RC0/T1OSO/T1CKI/RP11
RC1/CCP8/T1OSI/UOE/RP12
RC2/AN11/C2IND/CTPLS/RP13

RC4/D-/VM

RC6/CCP9/TX1/CK1/RP17
VUSB

RC5/D+/VP

28-Pin SPDIP/SOIC/SSOP

MCLR 1 28 RB7/CCP7/KBI3/PGD/RP10
RA0/AN0/C1INA/ULPWU/RP0 2 27 RB6/CCP6/KBI2/PGC/RP9
RA1/AN1/C2INA/VBG/RP1 3 26 RB5/CCP5/KBI1/SDI1/SDA1/RP8
RA2/AN2/C2INB/C1IND/C3INB/VREF-/CVREF 4 25 RB4/CCP4/KBI0/SCK1/SCL1/RP7
PIC18F2XJ53

RA3/AN3/C1INB/VREF+ 5 24 RB3/AN9/C3INA/CTED2/VPO/RP6
VDDCORE/VCAP 6 23 RB2/AN8/C2INC/CTED1/VMO/REFO/RP5
RA5/AN4/C1INC/SS1/HLVDIN/RCV/RP2 7 22 RB1/AN10/C3INC/RTCC/RP4
VSS1 8 21 RB0/AN12/C3IND/INT0/RP3
OSC1/CLKI/RA7 9 20 VDD
OSC2/CLKO/RA6 10 19 VSS2
RC0/T1OSO/T1CKI/RP11 11 18 RC7/CCP10/RX1/DT1/SDO1/RP18
RC1/CCP8/T1OSI/UOE/RP12 12 17 RC6/CCP9/TX1/CK1/RP17
RC2/AN11/C2IND/CTPLS/RP13 13 16 RC5/D+/VP
VUSB 14 15 RC4/D-/VM

Legend: Shaded pins are 5.5V tolerant.

RPn represents remappable pins. Some input and output functions are routed through the Peripheral Pin
Select (PPS) module and can be dynamically assigned to any of the RPn pins. For a list of the input and
output functions, see Table 10-13 and Table 10-14, respectively. For details on configuring the PPS mod-
ule, see Section 10.7 “Peripheral Pin Select (PPS)”.
Note: For the QFN package, it is recommended that the bottom pad be connected to VSS.

 2010 Microchip Technology Inc. Preliminary DS39964B-page 5

PIC18F47J53 FAMILY
Pin Diagrams (Continued)

RC6/CCP9/PMA5/TX1/CK1/RP17

RC2/AN11/C2IND/CTPLS/RP13
44-Pin QFN

RC1/CCP8/T1OSI/UOE/RP12
RC0/T1OSO/T1CKI/RP11
RD1/PMD1/SDA2
RD3/PMD3/RP20
RD2/PMD2/RP19

RD0/PMD0/SCL2
RC5/D+/VP
RC4/D-/VM

VUSB
44
43
42
41
40
39
38
37
36
35
34
RC7/CCP10/PMA4/RX1/DT1/SDO1/RP18 1 33 OSC2/CLKO/RA6
RD4/PMD4/RP21 2 32 OSC1/CLKI/RA7
RD5/PMD5/RP22 3 31 VSS2
RD6/PMD6/RP23 4 30 AVSS1
RD7/PMD7/RP24 5 29 VDD2
VSS1 6 PIC18F4XJ53 28 AVDD2
AVDD1 7 27 RE2/AN7/PMCS
VDD1 8 26 RE1/AN6/PMWR
RB0/AN12/C3IND/INT0/RP3 9 25 RE0/AN5/PMRD
RB1/AN10/C3INC/PMBE/RTCC/RP4 10 24 RA5/AN4/C1INC/SS1/HLVDIN/RCV/RP2
RB2/AN8/C2INC/CTED1/PMA3/VMO/REFO/RP5 11 23 VDDCORE/VCAP
15
16
14

17
12
13

18
19
20
21
22
RB3/AN9/C3INA/CTED2/PMA2/VPO/RP6

RB6/CCP6/KBI2/PGC/RP9
RB7/CCP7/KBI3/PGD/RP10

RA2/AN2/C2INB/C1IND/C3INB/VREF-/CVREF
NC

MCLR

RA3/AN3/C1INB/VREF+
RA1/AN1/C2INA/VBG/PMA7/RP1
RB4/CCP4/PMA1/KBI0/SCK1/SCL1/RP7
RB5/CCP5/PMA0/KBI1/SDI1/SDA1/RP8

RA0/AN0/C1INA/ULPWU/PMA6/RP0

Legend: RPn represents remappable pins.

Shaded pins are 5.5V tolerant.
Note: For the QFN package, it is recommended that the bottom pad be connected to VSS.

DS39964B-page 6 Preliminary  2010 Microchip Technology Inc.

 PIC18F47J53 FAMILY
Pin Diagrams (Continued)

44-Pin TQFP(2)

RC6/CCP9/PMA5/TX1/CK1/RP17

RC2/AN11/C2IND/CTPLS/RP13
RC1/CCP8/T1OSI/UOE/RP12
RD1/PMD1/SDA2
RD3/PMD3/RP20
RD2/PMD2/RP19

RD0/PMD0/SCL2
RC5/D+/VP
RC4/D-/VM

VUSB

NC
44
43
42
41
40
39
38
37
36
35
34
RC7/CCP10/PMA4/RX1/DT1/SDO1/RP18 1 33 NC
RD4/PMD4/RP21 2 32 RC0/T1OSO/T1CKI/RP11
RD5/PMD5/RP22 3 31 OSC2/CLKO/RA6
RD6/PMD6/RP23 4 30 OSC1/CLKI/RA7
RD7/PMD7/RP24 5 29 VSS2
VSS1 6 PIC18F4XJ53 28 VDD2
VDD1 7 27 RE2/AN7/PMCS
RB0/AN12/C3IND/INT0/RP3 8 26 RE1/AN6/PMWR
RB1/AN10/C3INC/PMBE/RTCC/RP4 9 25 RE0/AN5/PMRD
RB2/AN8/C2INC/CTED1/PMA3/VMO/REFO/RP5 10 24 RA5/AN4/C1INC/SS1/HLVDIN/RCV/RP2
RB3/AN9/C3INA/CTED2/PMA2/VPO/RP6 11 23 VDDCORE/VCAP
12
13
14
15
16
17
18
19
20
21
22
RB6/CCP6/KBI2/PGC/RP9
RB7/CCP7/KBI3/PGD/RP10
NC
NC

MCLR

RA3/AN3/C1INB/VREF+
RA2/AN2/C2INB/C1IND/C3INB/VREF-/CVREF
RB4/CCP4/PMA1/KBI0/SCK1/SCL1/RP7
RB5/CCP5/PMA0/KBI1/SDI1/SDA1/RP8

RA0/AN0/C1INA/ULPWU/PMA6/RP0
RA1/AN1/C2INA/VBG/PMA7/RP1

Legend: RPn represents remappable pins.

Shaded pins are 5.5V tolerant.
Note: Dedicated AVDD/AVSS pins are available only on the 44-pin QFN package. Other packages internally tie
AVDD/AVSS to VDD/VSS.

 2010 Microchip Technology Inc. Preliminary DS39964B-page 7

PIC18F47J53 FAMILY
Table of Contents
1.0 Device Overview ........................................................................................................................................................................ 11
2.0 Guidelines for Getting Started with PIC18FJ Microcontrollers ................................................................................................... 31
3.0 Oscillator Configurations ............................................................................................................................................................ 35
4.0 Low-Power Modes...................................................................................................................................................................... 47
5.0 Reset .......................................................................................................................................................................................... 65
6.0 Memory Organization ................................................................................................................................................................. 81
7.0 Flash Program Memory ............................................................................................................................................................ 109
8.0 8 x 8 Hardware Multiplier.......................................................................................................................................................... 119
9.0 Interrupts .................................................................................................................................................................................. 121
10.0 I/O Ports ................................................................................................................................................................................... 141
11.0 Parallel Master Port (PMP)....................................................................................................................................................... 179
12.0 Timer0 Module ......................................................................................................................................................................... 205
13.0 Timer1 Module ......................................................................................................................................................................... 209
14.0 Timer2 Module ......................................................................................................................................................................... 219
15.0 Timer3/5 Module ...................................................................................................................................................................... 221
16.0 Timer4/6/8 Module ................................................................................................................................................................... 233
17.0 Real-Time Clock and Calendar (RTCC) ................................................................................................................................... 237
18.0 Capture/Compare/PWM (CCP) Modules ................................................................................................................................. 257
19.0 Enhanced Capture/Compare/PWM (ECCP) Module................................................................................................................ 269
20.0 Master Synchronous Serial Port (MSSP) Module .................................................................................................................... 291
21.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) ............................................................... 345
22.0 10/12-bit Analog-to-Digital Converter (A/D) Module ................................................................................................................. 367
23.0 Universal Serial Bus (USB) ...................................................................................................................................................... 379
24.0 Comparator Module.................................................................................................................................................................. 407
25.0 Comparator Voltage Reference Module ................................................................................................................................... 415
26.0 High/Low Voltage Detect (HLVD) ............................................................................................................................................. 419
27.0 Charge Time Measurement Unit (CTMU) ................................................................................................................................ 425
28.0 Special Features of the CPU .................................................................................................................................................... 441
29.0 Instruction Set Summary .......................................................................................................................................................... 459
30.0 Development Support............................................................................................................................................................... 509
31.0 Electrical Characteristics .......................................................................................................................................................... 513
32.0 Packaging Information.............................................................................................................................................................. 555
Appendix A: Revision History............................................................................................................................................................. 569
Appendix B: Migration From PIC18F46J50 to PIC18F47J53............................................................................................................. 569
The Microchip Web Site ..................................................................................................................................................................... 583
Customer Change Notification Service .............................................................................................................................................. 583
Customer Support .............................................................................................................................................................................. 583
Reader Response .............................................................................................................................................................................. 584
Product Identification System............................................................................................................................................................. 585

DS39964B-page 8 Preliminary  2010 Microchip Technology Inc.

 PIC18F47J53 FAMILY

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 2010 Microchip Technology Inc. Preliminary DS39964B-page 9

PIC18F47J53 FAMILY
NOTES:

DS39964B-page 10 Preliminary  2010 Microchip Technology Inc.

 PIC18F47J53 FAMILY
1.0 DEVICE OVERVIEW 1.1.3 OSCILLATOR OPTIONS AND
FEATURES
This document contains device-specific information for
the following devices: All of the devices in the PIC18F47J53 family offer five
different oscillator options, allowing users a range of
• PIC18F26J53 • PIC18LF26J53 choices in developing application hardware. These
• PIC18F27J53 • PIC18LF27J53 include:
• PIC18F46J53 • PIC18LF46J53 • Two Crystal modes, using crystals or ceramic
• PIC18F47J53 • PIC18LF47J53 resonators.
• Two External Clock modes, offering the option of
This family introduces a new line of low-voltage
a divide-by-4 clock output.
Universal Serial Bus (USB) microcontrollers with the
main traditional advantage of all PIC18 microcontrollers, • An internal oscillator block, which provides an
namely, high computational performance and a rich 8 MHz clock and an INTRC source (approxi-
feature set at an extremely competitive price point. mately 31 kHz, stable over temperature and VDD),
These features make the PIC18F47J53 family a logical as well as a range of six user-selectable clock
choice for many high-performance applications, where frequencies, between 125 kHz to 4 MHz, for a
cost is a primary consideration. total of eight clock frequencies. This option frees
an oscillator pin for use as an additional general
purpose I/O.
1.1 Core Features
• A Phase Lock Loop (PLL) frequency multiplier
1.1.1 nanoWatt XLP TECHNOLOGY available to the high-speed crystal, and external
and internal oscillators, providing a clock speed
All of the devices in the PIC18F47J53 family incorpo- up to 48 MHz.
rate a range of features that can significantly reduce
• Dual clock operation, allowing the USB module to
power consumption during operation. Key features are:
run from a high-frequency oscillator while the rest
• Alternate Run Modes: By clocking the controller of the microcontroller is clocked at a different
from the Timer1 source or the internal RC frequency.
oscillator, power consumption during code
The internal oscillator block provides a stable reference
execution can be reduced by as much as 90%.
source that gives the PIC18F47J53 family additional
• Multiple Idle Modes: The controller can also run features for robust operation:
with its CPU core disabled but the peripherals still
active. In these states, power consumption can be • Fail-Safe Clock Monitor: This option constantly
reduced even further, to as little as 4% of normal monitors the main clock source against a reference
operational requirements. signal provided by the internal oscillator. If a clock
failure occurs, the controller is switched to the
• On-the-Fly Mode Switching: The
internal oscillator, allowing for continued low-speed
power-managed modes are invoked by user code
operation or a safe application shutdown.
during operation, allowing the users to incorporate
power-saving ideas into their application’s • Two-Speed Start-up: This option allows the
software design. internal oscillator to serve as the clock source
from Power-on Reset (POR), or wake-up from
• Deep Sleep: The 2.5V internal core voltage regu-
Sleep mode, until the primary clock source is
lator on F parts can be shutdown to cut power
available.
consumption to as low as 15 nA (typical). Certain
features can remain operating during Deep Sleep, 1.1.4 EXPANDED MEMORY
such as the Real-Time Clock Calendar.
The PIC18F47J53 family provides ample room for
• Ultra Low Power Wake-Up: Waking from Sleep
application code, from 64 Kbytes to 128 Kbytes of code
or Deep Sleep modes after a period of time can
space. The Flash cells for program memory are rated
be done without an oscillator/clock source, saving
to last in excess of 10000 erase/write cycles. Data
power for applications requiring periodic activity.
retention without refresh is conservatively estimated to
1.1.2 UNIVERSAL SERIAL BUS (USB) be greater than 20 years.

Devices in the PIC18F47J53 family incorporate a The Flash program memory is readable and writable
fully-featured USB communications module with a during normal operation. The PIC18F47J53 family also
built-in transceiver that is compliant with the USB provides plenty of room for dynamic application data
Specification Revision 2.0. The module supports both with up to 3.8 Kbytes of data RAM.
low-speed and full-speed communication for all
supported data transfer types.

 2010 Microchip Technology Inc. Preliminary DS39964B-page 11

PIC18F47J53 FAMILY
1.1.5 EXTENDED INSTRUCTION SET • 10/12-Bit A/D Converter: This module incorpo-
rates programmable acquisition time, allowing for
The PIC18F47J53 family implements the optional
a channel to be selected and a conversion to be
extension to the PIC18 instruction set, adding eight
initiated without waiting for a sampling period, and
new instructions and an Indexed Addressing mode.
thus, reducing code overhead.
Enabled as a device configuration option, the extension
has been specifically designed to optimize re-entrant • Extended Watchdog Timer (WDT): This
application code originally developed in high-level enhanced version incorporates a 16-bit prescaler,
languages, such as C. allowing an extended time-out range that is stable
across operating voltage and temperature. See
1.1.6 EASY MIGRATION Section 31.0 “Electrical Characteristics” for
time-out periods.
Regardless of the memory size, all devices share the
same rich set of peripherals, allowing for a smooth
migration path as applications grow and evolve. 1.3 Details on Individual Family
Devices
The consistent pinout scheme used throughout the
entire family also aids in migrating to the next larger Devices in the PIC18F47J53 family are available in
device. 28-pin and 44-pin packages. Block diagrams for the
The PIC18F47J53 family is also pin compatible with two groups are shown in Figure 1-1 and Figure 1-2.
other PIC18 families, such as the PIC18F4550, The devices are differentiated from each other in two
PIC18F2450 and PIC18F46J50. This allows a new ways:
dimension to the evolution of applications, allowing • Flash program memory (two sizes: 64 Kbytes for
developers to select different price points within the PIC18FX6J53 and 128 Kbytes for
Microchip’s PIC18 portfolio, while maintaining the PIC18FX7J53)
same feature set. • I/O ports (three bidirectional ports on 28-pin
devices, five bidirectional ports on 44-pin devices)
1.2 Other Special Features All other features for devices in this family are identical.
• Communications: The PIC18F47J53 family These are summarized in Table 1-1 and Table 1-2.
incorporates a range of serial and parallel com- The pinouts for the PIC18F2XJ53 devices are listed in
munication peripherals, including a fully featured Table 1-3. The pinouts for the PIC18F4XJ53 devices
USB communications module that is compliant are shown in Table 1-4.
with the USB Specification Revision 2.0. This
The PIC18F47J53 family of devices provides an
device also includes two independent Enhanced
on-chip voltage regulator to supply the correct voltage
USARTs and two Master Synchronous Serial Port
levels to the core. Parts designated with an “F” part
(MSSP) modules, capable of both Serial
number (such as PIC18F47J53) have the voltage
Peripheral Interface (SPI) and I2C™ (Master and
regulator enabled.
Slave) modes of operation. The device also has a
parallel port and can be configured to serve as These parts can run from 2.15V-3.6V on VDD, but should
either a Parallel Master Port (PMP) or as a have the VDDCORE pin connected to VSS through a
Parallel Slave Port (PSP). low-ESR capacitor. Parts designated with an “LF” part
• CCP/ECCP Modules: All devices in the family number (such as PIC18LF47J53) do not enable the volt-
incorporate seven Capture/Compare/PWM (CCP) age regulator nor support Deep Sleep mode. For “LF”
modules and three Enhanced Capture/Com- parts, an external supply of 2.0V-2.7V has to be supplied
pare/PWM (ECCP) modules to maximize flexibility to the VDDCORE pin while 2.0V-3.6V can be supplied to
in control applications. ECCPs offer up to four VDD (VDDCORE should never exceed VDD).
PWM output signals each. The ECCPs also offer For more details about the internal voltage regulator,
many beneficial features, including polarity see Section 28.3 “On-Chip Voltage Regulator”.
selection, programmable dead time,
auto-shutdown and restart and Half-Bridge and
Full-Bridge Output modes.

DS39964B-page 12 Preliminary  2010 Microchip Technology Inc.

 PIC18F47J53 FAMILY
TABLE 1-1: DEVICE FEATURES FOR THE PIC18F2XJ53 (28-PIN DEVICES)
Features PIC18F26J53 PIC18F27J53
Operating Frequency DC – 48 MHz DC – 48 MHz
Program Memory (Kbytes) 64 128
Program Memory (Instructions) 32,768 65,536
Data Memory (Kbytes) 3.8 3.8
Interrupt Sources 30
I/O Ports Ports A, B, C
Timers 8
Enhanced Capture/Compare/PWM Modules 3 ECCP and 7 CCP
Serial Communications MSSP (2), Enhanced USART (2), USB
Parallel Communications (PMP/PSP) No
10/12-Bit Analog-to-Digital Module 10 Input Channels
Resets (and Delays) POR, BOR, RESET Instruction, Stack Full, Stack Underflow, MCLR, WDT
(PWRT, OST)
Instruction Set 75 Instructions, 83 with Extended Instruction Set Enabled
Packages 28-Pin QFN, SOIC, SSOP and SPDIP (300 mil)

TABLE 1-2: DEVICE FEATURES FOR THE PIC18F4XJ53 (44-PIN DEVICES)

Features PIC18F46J53 PIC18F47J53
Operating Frequency DC – 48 MHz DC – 48 MHz
Program Memory (Kbytes) 64 128
Program Memory (Instructions) 32,768 65,536
Data Memory (Kbytes) 3.8 3.8
Interrupt Sources 30
I/O Ports Ports A, B, C, D, E
Timers 8
Enhanced Capture/Compare/PWM Modules 3 ECCP and 7 CCP
Serial Communications MSSP (2), Enhanced USART (2), USB
Parallel Communications (PMP/PSP) Yes
10/12-Bit Analog-to-Digital Module 13 Input Channels
Resets (and Delays) POR, BOR, RESET Instruction, Stack Full, Stack Underflow, MCLR, WDT
(PWRT, OST)
Instruction Set 75 Instructions, 83 with Extended Instruction Set Enabled
Packages 44-Pin QFN and TQFP

 2010 Microchip Technology Inc. Preliminary DS39964B-page 13

PIC18F47J53 FAMILY
FIGURE 1-1: PIC18F2XJ53 (28-PIN) BLOCK DIAGRAM

Data Bus<8>
Table Pointer<21>
PORTA
Data Latch
inc/dec logic 8 8 RA0:RA7(1)
Data Memory
(3.8 Kbytes)
21 PCLATU PCLATH

20 Address Latch
PCU PCH PCL
Program Counter 12 PORTB
Data Address<12>
RB0:RB7(1)
31-Level Stack
Address Latch 4 12 4
BSR FSR0 Access
Program Memory STKPTR Bank
(16 Kbytes-64 Kbytes) FSR1
Data Latch FSR2 12
PORTC

inc/dec RC0:RC7(1)
8 logic
Table Latch

ROM Latch Address

Instruction Bus <16> Decode

IR

8
Instruction State Machine
Decode and Control Signals
Control
PRODH PRODL

8 x 8 Multiply
Timing 3
Power-up 8
OSC2/CLKO Generation
OSC1/CLKI Timer BITOP W
8 MHz 8
INTOSC 8 8
Oscillator
INTRC Start-up Timer
8 8
Oscillator
VUSB Power-on
USB ALU<8>
Module Reset
8
Precision Watchdog
Band Gap Timer
Reference
Brown-out
Voltage Reset(2)
Regulator

VDDCORE/VCAP VDD, VSS MCLR

RTCC HLVD ADC Timer0 Timer1 Timer2 Timer3 Timer4 Timer5 Timer6 Timer8 Comparators

CTMU ECCP1 ECCP2 ECCP3 CCP4 CCP5 CCP6 CCP7 CCP8 CCP9 CCP10 EUSART1 EUSART2 MSSP1 MSSP2 USB

Note 1: See Table 1-3 for I/O port pin descriptions.

2: BOR functionality is provided when the on-board voltage regulator is enabled.

DS39964B-page 14 Preliminary  2010 Microchip Technology Inc.

 PIC18F47J53 FAMILY
FIGURE 1-2: PIC18F4XJ53 (44-PIN) BLOCK DIAGRAM

Data Bus<8>

PORTA
Table Pointer<21> Data Latch
8 8 RA0:RA7(1)
Data Memory
inc/dec logic (3.8 Kbytes)
PCLATU PCLATH

21 20 Address Latch
PCU PCH PCL PORTB
Program Counter 12 RB0:RB7(1)
Data Address<12>
31-Level Stack
Address Latch 4 12 4
System Bus Interface

BSR Access PORTC

Program Memory STKPTR FSR0 Bank
(16 Kbytes-64 Kbytes) FSR1 RC0:RC7(1)
FSR2 12
Data Latch

8 inc/dec
logic PORTD
Table Latch
RD0:RD7(1)

ROM Latch Address

Decode
Instruction Bus <16>
PORTE
IR
AD<15:0>, A<19:16> RE0:RE2(1)
(Multiplexed with PORTD 8
and PORTE)

Instruction PRODH PRODL

State Machine
Decode and
Control Signals
Control 8 x 8 Multiply
3 8

BITOP W
Timing 8 8 8
OSC2/CLKO Generation Power-up
OSC1/CLKI Timer
8 MHz
INTOSC 8 8
Oscillator
INTRC Start-up Timer ALU<8>
Oscillator
VUSB 8
Power-on
USB
Module Reset

Precision Watchdog
Band Gap Timer
Reference
Brown-out
Voltage Reset(2)
Regulator

VDDCORE/VCAP VDD, VSS MCLR

RTCC HLVD ADC Timer0 Timer1 Timer2 Timer3 Timer4 Timer5 Timer6 Timer8 Comparators

CTMU ECCP1 ECCP2 ECCP3 CCP4 CCP5 CCP6 CCP7 CCP8 CCP9 CCP10 EUSART1 EUSART2 MSSP1 MSSP2 USB

Note 1: See Table 1-3 for I/O port pin descriptions.

2: The on-chip voltage regulator is always enabled by default.

 2010 Microchip Technology Inc. Preliminary DS39964B-page 15

PIC18F47J53 FAMILY

TABLE 1-3: PIC18F2XJ53 PINOUT I/O DESCRIPTIONS

Pin Number
28-SPDIP/ Pin Buffer
Pin Name Description
SSOP/ 28-QFN Type Type
SOIC

MCLR 1(2) 26(2) I ST Master Clear (Reset) input. This pin is an

active-low Reset to the device.
OSC1/CLKI/RA7 9 6 Oscillator crystal or external clock input.
OSC1 I ST Oscillator crystal input or external clock source
input. ST buffer when configured in RC mode;
CMOS otherwise. Main oscillator input
connection.
CLKI I CMOS External clock source input; always associated
with pin function OSC1 (see related OSC1/CLKI
pins).
RA7(1) I/O TTL/DIG Digital I/O.
OSC2/CLKO/RA6 10 7 Oscillator crystal or clock output.
OSC2 O — Oscillator crystal output. Connects to crystal or
resonator in Crystal Oscillator mode.
CLKO O DIG Main oscillator feedback output connection.
In RC mode, OSC2 pin outputs CLKO, which
has 1/4 the frequency of OSC1 and denotes
the instruction cycle rate.
RA6(1) I/O TTL/DIG Digital I/O.
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to VDD)
DIG = Digital output I2C™ = Open-Drain, I2C specific
Note 1: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function.
2: 5.5V tolerant.

DS39964B-page 16 Preliminary  2010 Microchip Technology Inc.

 PIC18F47J53 FAMILY
TABLE 1-3: PIC18F2XJ53 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number

28-SPDIP/ Pin Buffer

Pin Name Description
SSOP/ 28-QFN Type Type
SOIC
PORTA is a bidirectional I/O port.
RA0/AN0/C1INA/ULPWU/RP0 2 27
RA0 I/O TTL/DIG Digital I/O.
AN0 I Analog Analog Input 0.
C1INA I Analog Comparator 1 Input A.
ULPWU I Analog Ultra low-power wake-up input.
RP0 I/O ST/DIG Remappable Peripheral Pin 0 input/output.
RA1/AN1/C2INA/VBG/RP1 3 28
RA1 I/O TTL/DIG Digital I/O.
AN1 O Analog Analog Input 1.
C2INA I Analog Comparator 2 Input A.
VBG O Analog Band Gap Reference Voltage (VBG) output.
RP1 I/O ST/DIG Remappable Peripheral Pin 1 input/output.
RA2/AN2/C2INB/C1IND/ 4 1
C3INB/VREF-/CVREF
RA2 I/O TTL/DIG Digital I/O.
AN2 I Analog Analog Input 2.
C2INB I Analog Comparator 2 Input B.
C1IND I Analog Comparator 1 Input D.
C3INB I Analog Comparator 3 Input B.
VREF- O Analog A/D reference voltage (low) input.
CVREF I Analog Comparator reference voltage output.
RA3/AN3/C1INB/VREF+ 5 2
RA3 I/O TTL/DIG Digital I/O.
AN3 I Analog Analog Input 3.
C1INB I Analog Comparator 1 Input B.
VREF+ I Analog A/D reference voltage (high) input.
RA5/AN4/C1INC/SS1/ 7 4
HLVDIN/RCV/RP2
RA5 I/O TTL/DIG Digital I/O.
AN4 I Analog Analog Input 4.
C1INC I Analog Comparator 1 Input C.
SS1 I TTL SPI slave select input.
HLVDIN I Analog High/Low-Voltage Detect input.
RCV I Analog External USB transceiver RCV input.
RP2 I/O ST/DIG Remappable Peripheral Pin 2 input/output.
RA6(1) See the OSC2/CLKO/RA6 pin.
RA7(1) See the OSC1/CLKI/RA7 pin.
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to VDD)
DIG = Digital output I2C™ = Open-Drain, I2C specific
Note 1: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function.
2: 5.5V tolerant.

 2010 Microchip Technology Inc. Preliminary DS39964B-page 17

PIC18F47J53 FAMILY
TABLE 1-3: PIC18F2XJ53 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number

28-SPDIP/ Pin Buffer

Pin Name Description
SSOP/ 28-QFN Type Type
SOIC
PORTB is a bidirectional I/O port. PORTB can be
software programmed for internal weak pull-ups
on all inputs.
RB0/AN12/C3IND/INT0/RP3 21 18
RB0 I/O TTL/DIG Digital I/O.
AN12 I Analog Analog Input 12.
C3IND I Analog Comparator 3 Input D.
INT0 I ST External Interrupt 0.
RP3 I/O ST/DIG Remappable Peripheral Pin 3 input/output.
RB1/AN10/C3INC/RTCC/RP4 22 19
RB1 I/O TTL/DIG Digital I/O.
AN10 I Analog Analog Input 10.
C3INC I Analog Comparator 3 input.
RTCC O DIG Asynchronous serial transmit data output.
RP4 I/O ST/DIG Remappable Peripheral Pin 4 input/output.
RB2/AN8/C2INC/CTED1/ 23 20
VMO/REFO/RP5
RB2 I/O TTL/DIG Digital I/O.
AN8 I Analog Analog Input 8.
C2INC I Analog Comparator 2 Input C.
CTED1 I ST CTMU Edge 1 input.
VMO O DIG External USB Transceiver D- data output.
REFO O DIG Reference output clock.
RP5 I/O ST/DIG Remappable Peripheral Pin 5 input/output.
RB3/AN9/C3INA/CTED2/ 24 21
VPO/RP6
RB3 I/O TTL/DIG Digital I/O.
AN9 I Analog Analog Input 9.
C3INA I Analog Comparator 3 Input A.
CTED2 I ST CTMU edge 2 Input.
VPO O DIG External USB Transceiver D+ data output.
RP6 I ST/DIG Remappable Peripheral Pin 6 input/output.
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to VDD)
DIG = Digital output I2C™ = Open-Drain, I2C specific
Note 1: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function.
2: 5.5V tolerant.

DS39964B-page 18 Preliminary  2010 Microchip Technology Inc.

 PIC18F47J53 FAMILY
TABLE 1-3: PIC18F2XJ53 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number

28-SPDIP/ Pin Buffer

Pin Name Description
SSOP/ 28-QFN Type Type
SOIC
PORTB (continued)
RB4/CCP4/KBI0/SCK1/SCL1/ (2) (2)
25 22
RP7
RB4 I/O TTL/DIG Digital I/O.
CCP4 I/O ST/DIG Capture/Compare/PWM input/output.
KBI0 I TTL Interrupt-on-change pin.
SCK1 I/O ST/DIG Synchronous serial clock input/output.
SCL1 I/O I2C I2C clock input/output.
RP7 I/O ST/DIG Remappable Peripheral Pin 7 input/output.
RB5/CCP5/KBI1/SDI1/SDA1/ 26(2) 23(2)
RP8
RB5 I/O TTL/DIG Digital I/O.
CCP5 I/O ST/DIG Capture/Compare/PWM input/output.
KBI1 I TTL Interrupt-on-change pin.
SDI1 I ST SPI data input.
SDA1 I/O I2C I2C™ data input/output.
RP8 I/O ST/DIG Remappable Peripheral Pin 8 input/output.
RB6/CCP6/KBI2/PGC/RP9 27(2) 24(2)
RB6 I/O TTL/DIG Digital I/O.
CCP6 I/O ST/DIG Capture/Compare/PWM input/output.
KBI2 I TTL Interrupt-on-change pin.
PGC I ST ICSP™ clock input.
RP9 I/O ST/DIG Remappable Peripheral Pin 9 input/output.
RB7/CCP7/KBI3/PGD/RP10 28(2) 25(2)
RB7 I/O TTL/DIG Digital I/O.
CCP7 I/O ST/DIG Capture/Compare/PWM input/output.
KBI3 I TTL Interrupt-on-change pin.
PGD I/O ST/DIG In-Circuit Debugger and ICSP programming
data pin.
RP10 I/O ST/DIG Remappable Peripheral Pin 10 input/output.
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to VDD)
DIG = Digital output I2C™ = Open-Drain, I2C specific
Note 1: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function.
2: 5.5V tolerant.

 2010 Microchip Technology Inc. Preliminary DS39964B-page 19

PIC18F47J53 FAMILY
TABLE 1-3: PIC18F2XJ53 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number

28-SPDIP/ Pin Buffer

Pin Name Description
SSOP/ 28-QFN Type Type
SOIC
PORTC is a bidirectional I/O port.
RC0/T1OSO/T1CKI/RP11 11 8
RC0 I/O ST/DIG Digital I/O.
T1OSO O Analog Timer1 oscillator output.
T1CKI I ST Timer1 external digital clock input.
RP11 I/O ST/DIG Remappable Peripheral Pin 11 input/output.
RC1/CCP8/T1OSI/UOE/RP12 12 9
RC1 I/O ST/DIG Digital I/O.
CCP8 I/O ST/DIG Capture/Compare/PWM input/output.
T1OSI I Analog Timer1 oscillator input.
UOE O DIG External USB transceiver NOE output.
RP12 I/O ST/DIG Remappable Peripheral Pin 12 input/output.
RC2/AN11/C2IND/CTPLS/ 13 10
RP13
RC2 I/O ST/DIG Digital I/O.
AN11 I Analog Analog Input 11.
C2IND I Analog Comparator 2 Input D.
CTPLS O DIG CTMU pulse generator output.
RP13 I/O ST/DIG Remappable Peripheral Pin 13 input/output.
RC4/D-/VM 15 12
RC4 I ST Digital Input.
D- I/O — USB bus minus line input/output.
VM I ST External USB transceiver FM input.
RC5/D+/VP 16 13
RC5 I ST Digital Input.
D+ I/O — USB bus plus line input/output.
VP I ST External USB transceiver VP input.
RC6/CCP9/TX1/CK1/RP17 17(2) 14(2)
RC6 I/O ST/DIG Digital I/O.
CCP9 I/O ST/DIG Capture/Compare/PWM input/output.
TX1 O DIG EUSART1 asynchronous transmit.
CK1 I/O ST/DIG EUSART1 synchronous clock (see related
RX1/DT1).
RP17 I/O ST/DIG Remappable Peripheral Pin 17 input/output.
(2)
RC7/CCP10/RX1/DT1/SDO1/ 18 15(2)
RP18 Digital I/O.
RC7 I/O ST/DIG Asynchronous serial receive data input.
CCP10 I/O ST/DIG Capture/Compare/PWM input/output.
RX1 I ST Synchronous serial data output/input.
DT1 I/O ST/DIG SPI data output.
SDO1 O DIG Remappable Peripheral Pin 18 input/output.
RP18 I/O ST/DIG
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to VDD)
DIG = Digital output I2C™ = Open-Drain, I2C specific
Note 1: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function.
2: 5.5V tolerant.

DS39964B-page 20 Preliminary  2010 Microchip Technology Inc.

 PIC18F47J53 FAMILY
TABLE 1-3: PIC18F2XJ53 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number

28-SPDIP/ Pin Buffer

Pin Name Description
SSOP/ 28-QFN Type Type
SOIC
VSS1 8 5 P — Ground reference for logic and I/O pins.
VSS2 19 16 — —
VDD 20 17 P — Positive supply for peripheral digital logic and I/O
pins.
VDDCORE/VCAP 6 3 — — Core logic power or external filter capacitor
connection.
VDDCORE P — Positive supply for microcontroller core logic
(regulator disabled).
VCAP P — External filter capacitor connection (regulator
enabled).
VUSB 14 11 P — USB voltage input pin.
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to VDD)
DIG = Digital output I2C™ = Open-Drain, I2C specific
Note 1: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function.
2: 5.5V tolerant.

 2010 Microchip Technology Inc. Preliminary DS39964B-page 21

PIC18F47J53 FAMILY
TABLE 1-4: PIC18F4XJ53 PINOUT I/O DESCRIPTIONS
Pin Number
Pin Buffer
Pin Name 44- 44- Type Type Description
QFN TQFP

MCLR 18(3) 18 I ST Master Clear (Reset) input; this is an active-low

Reset to the device.
OSC1/CLKI/RA7 32 30 Oscillator crystal or external clock input.
OSC1 I ST Oscillator crystal input or external clock source
input. ST buffer when configured in RC mode;
otherwise CMOS. Main oscillator input
connection.
CLKI I CMOS External clock source input; always associated
with pin function OSC1 (see related OSC1/CLKI
pins).
RA7(1) I/O TTL/DIG Digital I/O.
OSC2/CLKO/RA6 33 31 Oscillator crystal or clock output.
OSC2 O — Oscillator crystal output. Connects to crystal or
resonator in Crystal Oscillator mode.
CLKO O — Main oscillator feedback output connection
in RC mode, OSC2 pin outputs CLKO, which
has 1/4 the frequency of OSC1 and denotes the
instruction cycle rate.
RA6(1) I/O TTL/DIG Digital I/O.
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to VDD)
DIG = Digital output I2C™ = Open-Drain, I2C specific
Note 1: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function.
2: Available only on 44-pin devices (PIC18F46J53, PIC18F47J53, PIC18LF46J53 and PIC18LF47J53).
3: 5.5V tolerant.

DS39964B-page 22 Preliminary  2010 Microchip Technology Inc.

 PIC18F47J53 FAMILY
TABLE 1-4: PIC18F4XJ53 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Buffer
Pin Name 44- 44- Type Type Description
QFN TQFP
PORTA is a bidirectional I/O port.
RA0/AN0/C1INA/ULPWU/PMA6/ 19 19
RP0
RA0 I/O TTL/DIG Digital I/O.
AN0 I Analog Analog Input 0.
C1INA I Analog Comparator 1 Input A.
ULPWU I Analog Ultra low-power wake-up input.
PMA6 I/O ST/TTL/ Parallel Master Port digital I/O.
DIG
RP0 I/O ST/DIG Remappable Peripheral Pin 0 input/output.
RA1/AN1/C2INA/VBG/PMA7/RP1 20 20
RA1 I/O TTL/DIG Digital I/O.
AN1 O Analog Analog Input 1.
C2INA I Analog Comparator 2 Input A.
VBG O Analog Band Gap Reference Voltage (VBG) output.
PMA7 I/O ST/TTL/ Parallel Master Port digital I/O.
DIG
RP1 I/O ST/DIG Remappable Peripheral Pin 1 input/output.
RA2/AN2/C2INB/C1IND/C3INB/ 21 21
VREF-/CVREF
RA2 I/O TTL/DIG Digital I/O.
AN2 I Analog Analog Input 2.
C2INB I Analog Comparator 2 Input B.
C1IND I Analog Comparator 1 Input D.
C3INB I Analog Comparator 3 Input B.
VREF- I Analog A/D reference voltage (low) input.
CVREF I Analog Comparator reference voltage output.
RA3/AN3/C1INB/VREF+ 22 22
RA3 I/O TTL/DIG Digital I/O.
AN3 I Analog Analog Input 3.
C1INB I Analog Comparator 1 Input B.
VREF+ I Analog A/D reference voltage (high) input.
RA5/AN4/C1INC/SS1/HLVDIN/ 24 24
RCV/RP2
RA5 I/O TTL/DIG Digital I/O.
AN4 I Analog Analog Input 4.
C1INC I Analog SPI slave select input.
SS1 I TTL Comparator 1 Input C.
HLVDIN I Analog High/Low-Voltage Detect input.
RCV I TTL External USB transceiver RCV input.
RP2 I/O ST/DIG Remappable Peripheral Pin 2 input/output.
RA6(1) See the OSC2/CLKO/RA6 pin.
RA7(1) See the OSC1/CLKI/RA7 pin.
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to VDD)
DIG = Digital output I2C™ = Open-Drain, I2C specific
Note 1: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function.
2: Available only on 44-pin devices (PIC18F46J53, PIC18F47J53, PIC18LF46J53 and PIC18LF47J53).
3: 5.5V tolerant.

 2010 Microchip Technology Inc. Preliminary DS39964B-page 23

PIC18F47J53 FAMILY
TABLE 1-4: PIC18F4XJ53 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Buffer
Pin Name 44- 44- Type Type Description
QFN TQFP
PORTB is a bidirectional I/O port. PORTB can be
software programmed for internal weak pull-ups on
all inputs.
RB0/AN12/C3IND/INT0/RP3 9 8
RB0 I/O TTL/DIG Digital I/O.
AN12 I Analog Analog Input 12.
C3IND I Analog Comparator 3 Input D.
INT0 I ST External Interrupt 0.
RP3 I/O ST/DIG Remappable Peripheral Pin 3 input/output.
RB1/AN10/C3INC/PMBE/RTCC/ 10 9
RP4
RB1 I/O TTL/DIG Digital I/O.
AN10 I Analog Analog Input 10.
C3INC I Analog Comparator 3 Input C.
PMBE(2) O DIG Parallel Master Port byte enable.
RTCC O DIG Asynchronous serial transmit data output.
RP4 I/O ST/DIG Remappable Peripheral Pin 4 input/output.
RB2/AN8/C2INC/CTED1/PMA3/ 11 10
VMO/REFO/RP5
RB2 I/O TTL/DIG Digital I/O.
AN8 I Analog Analog Input 8.
C2INC I Analog Comparator 2 Input C.
CTED1 I ST CTMU Edge 1 input.
PMA3(2) O DIG Parallel Master Port address.
VMO O DIG External USB Transceiver D- data output.
REFO O DIG Reference output clock.
RP5 I/O ST/DIG Remappable Peripheral Pin 5 input/output.
RB3/AN9/C3INA/CTED2/PMA2/ 12 11
VPO/RP6
RB3 I/O TTL/DIG Digital I/O.
AN9 I Analog Analog Input 9.
C3INA I Analog Comparator 3 Input A.
CTED2 I ST CTMU Edge 2 input.
PMA2(2) O DIG Parallel Master Port address.
VPO O DIG External USB Transceiver D+ data output.
RP6 I/O ST/DIG Remappable Peripheral Pin 6 input/output.
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to VDD)
DIG = Digital output I2C™ = Open-Drain, I2C specific
Note 1: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function.
2: Available only on 44-pin devices (PIC18F46J53, PIC18F47J53, PIC18LF46J53 and PIC18LF47J53).
3: 5.5V tolerant.

DS39964B-page 24 Preliminary  2010 Microchip Technology Inc.

 PIC18F47J53 FAMILY
TABLE 1-4: PIC18F4XJ53 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Buffer
Pin Name 44- 44- Type Type Description
QFN TQFP
PORTB (continued)
RB4/CCP4/PMA1/KBI0/SCK1/ (3) (3)
14 14
SCL1/RP7
RB4 I/O TTL/DIG Digital I/O.
CCP4(2) I/O ST/DIG Capture/Compare/PWM input/output.
PMA1(2) I/O ST/TTL/ Parallel Master Port address.
DIG
KBI0 I TTL Interrupt-on-change pin.
SCK1 I/O ST/DIG Synchronous serial clock input/output.
SCL1 I/O I2C I2C clock input/output.
RP7 I/O ST/DIG Remappable Peripheral Pin 7 input/output.
RB5/CCP5/PMA0/KBI1/SDI1/ 15(3) 15(3)
SDA1/RP8
RB5 I/O TTL/DIG Digital I/O.
CCP5 I/O ST/DIG Capture/Compare/PWM input/output.
PMA0(2) I/O ST/TTL/ Parallel Master Port address.
DIG
KBI1 I TTL Interrupt-on-change pin.
SDI1 I ST SPI data input.
SDA1 I/O I2C I2C™ data input/output.
RP8 I/O ST/DIG Remappable Peripheral Pin 8 input/output.
RB6/CCP6/KBI2/PGC/RP9 16(3) 16(3)
RB6 I/O TTL/DIG Digital I/O.
CCP6 I/O ST/DIG Capture/Compare/PWM input/output.
KBI2 I TTL Interrupt-on-change pin.
PGC I ST ICSP™ clock input.
RP9 I/O ST/DIG Remappable Peripheral Pin 9 input/output.
RB7/CCP7/KBI3/PGD/RP10 17(3) 17(3)
RB7 I/O TTL/DIG Digital I/O.
CCP7 I/O ST/DIG Capture/Compare/PWM input/output.
KBI3 I TTL Interrupt-on-change pin.
PGD I/O ST/DIG In-Circuit Debugger and ICSP programming
data pin.
RP10 I/O ST/DIG Remappable Peripheral Pin 10 input/output.
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to VDD)
DIG = Digital output I2C™ = Open-Drain, I2C specific
Note 1: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function.
2: Available only on 44-pin devices (PIC18F46J53, PIC18F47J53, PIC18LF46J53 and PIC18LF47J53).
3: 5.5V tolerant.

 2010 Microchip Technology Inc. Preliminary DS39964B-page 25

PIC18F47J53 FAMILY
TABLE 1-4: PIC18F4XJ53 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Buffer
Pin Name 44- 44- Type Type Description
QFN TQFP
PORTC is a bidirectional I/O port.
RC0/T1OSO/T1CKI/RP11 34 32
RC0 I/O STDIG Digital I/O.
T1OSO O Analog Timer1 oscillator output.
T1CKI I ST Timer1/Timer3 external clock input.
RP11 I/O ST/DIG Remappable Peripheral Pin 11 input/output.
RC1/CCP8/T1OSI/UOE/RP12 35 35
RC1 I/O ST/DIG Digital I/O.
CCP8 I/O ST/DIG Capture/Compare/PWM input/output.
T1OSI I Analog Timer1 oscillator input.
UOE O DIG External USB Transceiver NOE output.
RP12 I/O ST/DIG Remappable Peripheral Pin 12 input/output.
RC2/AN11/C2IND/CTPLS/RP13 36 36
RC2 I/O ST/DIG Digital I/O.
AN11 I Analog Analog Input 11.
C2IND I Analog Comparator 2 Input D.
CTPLS O DIG CTMU pulse generator output.
RP13 I/O ST/DIG Remappable Peripheral Pin 13 input/output.
RC4/D-/VM 42 42
RC4 I ST Digital Input.
D- I/O — USB bus minus line input/output.
VM I ST External USB Transceiver FM input.
RC5/D+/VP 43 43
RC5 I ST Digital Input.
D+ I/O — USB bus plus line input/output.
VP I ST External USB Transceiver VP input.
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to VDD)
DIG = Digital output I2C™ = Open-Drain, I2C specific
Note 1: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function.
2: Available only on 44-pin devices (PIC18F46J53, PIC18F47J53, PIC18LF46J53 and PIC18LF47J53).
3: 5.5V tolerant.

DS39964B-page 26 Preliminary  2010 Microchip Technology Inc.

 PIC18F47J53 FAMILY
TABLE 1-4: PIC18F4XJ53 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Buffer
Pin Name 44- 44- Type Type Description
QFN TQFP
RC6/CCP9/PMA5/TX1/CK1/RP17 44(3) 44(3)
RC6 I/O ST/DIG Digital I/O.
CCP9 I/O ST/DIG Capture/Compare/PWM input/output.
PMA5 I/O DIG Parallel Master Port address.
TX1 O ST/TTL/ EUSART1 asynchronous transmit.
DIG
CK1 I/O ST/DIG EUSART1 synchronous clock (see related
RX1/DT1).
RP17 I/O ST/DIG Remappable Peripheral Pin 17 input/output.
(3) (3)
RC7/CCP10/PMA4/RX1/DT1/ 1 1
SDO1/RP18
RC7 I/O ST/DIG EUSART1 asynchronous receive.
CCP10 I/O ST/DIG Capture/Compare/PWM input/output.
PMA4 I/O ST/TTL/ Parallel Master Port address.
RX1 DIG EUSART1 synchronous data (see related
TX1/CK1).
DT1 I ST Synchronous serial data output/input.
SDO1 SPI data output.
RP18 I/O ST/DIG Remappable Peripheral Pin 18 input/output.
O DIG
I/O ST/DIG
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to VDD)
DIG = Digital output I2C™ = Open-Drain, I2C specific
Note 1: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function.
2: Available only on 44-pin devices (PIC18F46J53, PIC18F47J53, PIC18LF46J53 and PIC18LF47J53).
3: 5.5V tolerant.

 2010 Microchip Technology Inc. Preliminary DS39964B-page 27

PIC18F47J53 FAMILY
TABLE 1-4: PIC18F4XJ53 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Buffer
Pin Name 44- 44- Type Type Description
QFN TQFP
PORTD is a bidirectional I/O port.
RD0/PMD0/SCL2 38(3) 38 (3)

RD0 I/O ST/DIG Digital I/O.

PMD0 I/O ST/TTL/ Parallel Master Port data.
DIG
SCL2 I/O I2C I2C™ data input/output.
RD1/PMD1/SDA2 39(3) 39(3)
RD1 I/O ST/DIG Digital I/O.
PMD1 I/O ST/TTL/ Parallel Master Port data.
DIG
SDA2 I/O I2C I2C data input/output.
RD2/PMD2/RP19 40(3) 40(3)
RD2 I/O ST/DIG Digital I/O.
PMD2 I/O ST/TTL/ Parallel Master Port data.
DIG
RP19 I/O ST/DIG Remappable Peripheral Pin 19 input/output.
RD3/PMD3/RP20 41(3) 41(3)
RD3 I/O ST/DIG Digital I/O.
PMD3 I/O ST/TTL/ Parallel Master Port data.
DIG
RP20 I/O ST/DIG Remappable Peripheral Pin 20 input/output.
RD4/PMD4/RP21 2(3) 2(3)
RD4 I/O ST/DIG Digital I/O.
PMD4 I/O ST/TTL/ Parallel Master Port data.
DIG
RP21 I/O ST/DIG Remappable Peripheral Pin 21 input/output.
RD5/PMD5/RP22 3(3) 3(3)
RD5 I/O ST/DIG Digital I/O.
PMD5 I/O ST/TTL/ Parallel Master Port data.
DIG
RP22 I/O ST/DIG Remappable Peripheral Pin 22 input/output.
RD6/PMD6/RP23 4(3) 4(3)
RD6 I/O ST/DIG Digital I/O.
PMD6 I/O ST/TTL/ Parallel Master Port data.
DIG
RP23 I/O ST/DIG Remappable Peripheral Pin 23 input/output.
RD7/PMD7/RP24 5(3) 5(3)
RD7 I/O ST/DIG Digital I/O.
PMD7 I/O ST/TTL/ Parallel Master Port data.
DIG
RP24 I/O ST/DIG Remappable Peripheral Pin 24 input/output.
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to VDD)
DIG = Digital output I2C™ = Open-Drain, I2C specific
Note 1: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function.
2: Available only on 44-pin devices (PIC18F46J53, PIC18F47J53, PIC18LF46J53 and PIC18LF47J53).
3: 5.5V tolerant.

DS39964B-page 28 Preliminary  2010 Microchip Technology Inc.

 PIC18F47J53 FAMILY
TABLE 1-4: PIC18F4XJ53 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Buffer
Pin Name 44- 44- Type Type Description
QFN TQFP
PORTE is a bidirectional I/O port.
RE0/AN5/PMRD 25 25
RE0 I/O ST/DIG Digital I/O.
AN5 I Analog Analog Input 5.
PMRD I/O ST/TTL/ Parallel Master Port input/output.
DIG
RE1/AN6/PMWR 26 26
RE1 I/O ST/DIG Digital I/O.
AN6 I Analog Analog Input 6.
PMWR I/O ST/TTL/ Parallel Master Port write strobe.
DIG
RE2/AN7/PMCS 27 27
RE2 I/O ST/DIG Digital I/O.
AN7 I Analog Analog Input 7.
PMCS O DIG Parallel Master Port byte enable.
VSS1 6 6 P — Ground reference for logic and I/O pins.
VSS2 31 29 — —
AVSS1 30 — P — Ground reference for analog modules.
VDD1 8 7 P — Positive supply for peripheral digital logic and
VDD2 29 28 P — I/O pins.
VDDCORE/VCAP 23 23 Core logic power or external filter capacitor
connection.
VDDCORE P — Positive supply for microcontroller core logic
(regulator disabled).
VCAP P — External filter capacitor connection (regulator
enabled).
AVDD1 7 — P — Positive supply for analog modules.
AVDD2 28 — — — Positive supply for analog modules.
VUSB 37 37 P — USB voltage input pin.
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to VDD)
DIG = Digital output I2C™ = Open-Drain, I2C specific
Note 1: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function.
2: Available only on 44-pin devices (PIC18F46J53, PIC18F47J53, PIC18LF46J53 and PIC18LF47J53).
3: 5.5V tolerant.

 2010 Microchip Technology Inc. Preliminary DS39964B-page 29

PIC18F47J53 FAMILY
NOTES:

DS39964B-page 30 Preliminary  2010 Microchip Technology Inc.

 PIC18F47J53 FAMILY
2.0 GUIDELINES FOR GETTING FIGURE 2-1: RECOMMENDED
STARTED WITH PIC18FJ MINIMUM CONNECTIONS
MICROCONTROLLERS
C2(2)
2.1 Basic Connection Requirements VDD

Getting started with the PIC18F47J53 family of 8-bit

VDD

VSS
R1 (1)
microcontrollers requires attention to a minimal set of R2
device pin connections before proceeding with MCLR
development. VCAP/VDDCORE
C1
The following pins must always be connected: C7
PIC18FXXJXX
• All VDD and VSS pins
VDD
(see Section 2.2 “Power Supply Pins”) VSS
C6(2) C3(2)
• All AVDD and AVSS pins, regardless of whether or VSS
VDD
not the analog device features are used

AVDD

AVSS

VDD

VSS
(see Section 2.2 “Power Supply Pins”)
• MCLR pin
(see Section 2.3 “Master Clear (MCLR) Pin”)
C5(2) C4(2)
• VCAP/VDDCORE pins (see Section 2.4 “Voltage
Regulator Pins (VCAP/VDDCORE)”)
These pins must also be connected if they are being Key (all values are recommendations):
used in the end application: C1 through C6: 0.1 F, 20V ceramic
• PGC/PGD pins used for In-Circuit Serial C7: 10 F, 6.3V or greater, tantalum or ceramic
Programming™ (ICSP™) and debugging purposes R1: 10 kΩ
(see Section 2.5 “ICSP Pins”)
R2: 100Ω to 470Ω
• OSCI and OSCO pins when an external oscillator
Note 1: See Section 2.4 “Voltage Regulator Pins
source is used (VCAP/VDDCORE)” for explanation of
(see Section 2.6 “External Oscillator Pins”) VCAP/VDDCORE connections.
Additionally, the following pins may be required: 2: The example shown is for a PIC18F device
with five VDD/VSS and AVDD/AVSS pairs.
• VREF+/VREF- pins are used when external voltage Other devices may have more or less pairs;
reference for analog modules is implemented adjust the number of decoupling capacitors
Note: On 44-pin QFN packages, the AVDD and appropriately.
AVSS pins must always be connected,
regardless of whether any of the analog
modules are being used. On other pack-
age types, the AVDD and AVSS pins are
internally connected to the VDD/VSS pins.
The minimum mandatory connections are shown in
Figure 2-1.

 2010 Microchip Technology Inc. Preliminary DS39964B-page 31

PIC18F47J53 FAMILY
2.2 Power Supply Pins 2.3 Master Clear (MCLR) Pin
2.2.1 DECOUPLING CAPACITORS The MCLR pin provides two specific device
functions: Device Reset, and Device Programming
The use of decoupling capacitors on every pair of and Debugging. If programming and debugging are
power supply pins, such as VDD, VSS, AVDD and not required in the end application, a direct
AVSS, is required. connection to VDD may be all that is required. The
Consider the following criteria when using decoupling addition of other components, to help increase the
capacitors: application’s resistance to spurious Resets from
voltage sags, may be beneficial. A typical
• Value and type of capacitor: A 0.1 F (100 nF),
configuration is shown in Figure 2-1. Other circuit
10-20V capacitor is recommended. The capacitor
designs may be implemented, depending on the
should be a low-ESR device, with a resonance
application’s requirements.
frequency in the range of 200 MHz and higher.
Ceramic capacitors are recommended. During programming and debugging, the resistance
• Placement on the printed circuit board: The and capacitance that can be added to the pin must
decoupling capacitors should be placed as close be considered. Device programmers and debuggers
to the pins as possible. It is recommended to drive the MCLR pin. Consequently, specific voltage
place the capacitors on the same side of the levels (VIH and VIL) and fast signal transitions must
board as the device. If space is constricted, the not be adversely affected. Therefore, specific values
capacitor can be placed on another layer on the of R1 and C1 will need to be adjusted based on the
PCB using a via; however, ensure that the trace application and PCB requirements. For example, it is
length from the pin to the capacitor is no greater recommended that the capacitor, C1, be isolated
than 0.25 inch (6 mm). from the MCLR pin during programming and
debugging operations by using a jumper (Figure 2-2).
• Handling high-frequency noise: If the board is
The jumper is replaced for normal run-time
experiencing high-frequency noise (upward of
operations.
tens of MHz), add a second ceramic type capaci-
tor in parallel to the above described decoupling Any components associated with the MCLR pin
capacitor. The value of the second capacitor can should be placed within 0.25 inch (6 mm) of the pin.
be in the range of 0.01 F to 0.001 F. Place this
second capacitor next to each primary decoupling FIGURE 2-2: EXAMPLE OF MCLR PIN
capacitor. In high-speed circuit designs, consider CONNECTIONS
implementing a decade pair of capacitances as
close to the power and ground pins as possible VDD
(e.g., 0.1 F in parallel with 0.001 F).
• Maximizing performance: On the board layout R1
from the power supply circuit, run the power and R2
return traces to the decoupling capacitors first, MCLR
and then to the device pins. This ensures that the PIC18FXXJXX
JP
decoupling capacitors are first in the power chain.
Equally important is to keep the trace length C1
between the capacitor and the power pins to a
minimum, thereby reducing PCB trace
inductance.
Note 1: R1  10 k is recommended. A suggested
2.2.2 TANK CAPACITORS starting value is 10 k. Ensure that the
On boards with power traces running longer than MCLR pin VIH and VIL specifications are met.
six inches in length, it is suggested to use a tank capac- 2: R2  470 will limit any current flowing into
itor for integrated circuits, including microcontrollers, to MCLR from the external capacitor, C, in the
supply a local power source. The value of the tank event of MCLR pin breakdown, due to
Electrostatic Discharge (ESD) or Electrical
capacitor should be determined based on the trace
Overstress (EOS). Ensure that the MCLR pin
resistance that connects the power supply source to
VIH and VIL specifications are met.
the device, and the maximum current drawn by the
device in the application. In other words, select the tank
capacitor so that it meets the acceptable voltage sag at
the device. Typical values range from 4.7 F to 47 F.

DS39964B-page 32 Preliminary  2010 Microchip Technology Inc.

 PIC18F47J53 FAMILY
2.4 Voltage Regulator Pins 2.5 ICSP Pins
(VCAP/VDDCORE) The PGC and PGD pins are used for In-Circuit Serial
On “F” devices, a low-ESR (< 5Ω) capacitor is required Programming™ (ICSP™) and debugging purposes. It
on the VCAP/VDDCORE pin to stabilize the voltage is recommended to keep the trace length between the
regulator output voltage. The VCAP/VDDCORE pin must ICSP connector and the ICSP pins on the device as
not be connected to VDD and must use a capacitor of 10 short as possible. If the ICSP connector is expected to
F connected to ground. The type can be ceramic or experience an ESD event, a series resistor is recom-
tantalum. A suitable example is the Murata mended, with the value in the range of a few tens of
GRM21BF50J106ZE01 (10 F, 6.3V) or equivalent. ohms, not to exceed 100Ω.
Designers may use Figure 2-3 to evaluate ESR Pull-up resistors, series diodes, and capacitors on the
equivalence of candidate devices. PGC and PGD pins are not recommended as they will
It is recommended that the trace length not exceed interfere with the programmer/debugger communica-
0.25 inch (6 mm). Refer to Section 31.0 “Electrical tions to the device. If such discrete components are an
Characteristics” for additional information. application requirement, they should be removed from
the circuit during programming and debugging. Alter-
On “LF” devices, the VCAP/VDDCORE pin must be tied to
natively, refer to the AC/DC characteristics and timing
a voltage supply at the VDDCORE level. Refer to
requirements information in the respective device
Section 31.0 “Electrical Characteristics” for
Flash programming specification for information on
information on VDD and VDDCORE.
capacitive loading limits, and pin input voltage high
Note that the “LF” versions of these devices are (VIH) and input low (VIL) requirements.
provided with the voltage regulator permanently
For device emulation, ensure that the “Communication
disabled; they must always be provided with a supply
Channel Select” (i.e., PGCx/PGDx pins) programmed
voltage on the VDDCORE pin.
into the device matches the physical connections for
the ICSP to the Microchip debugger/emulator tool.
FIGURE 2-3: FREQUENCY vs. ESR
For more information on available Microchip
PERFORMANCE FOR
development tools connection requirements, refer to
SUGGESTED VCAP
Section 30.0 “Development Support”.
10

1
ESR ()

0.1

0.01

0.001
0.01 0.1 1 10 100 1000 10,000
Frequency (MHz)
Note: Data for Murata GRM21BF50J106ZE01 shown.
Measurements at 25°C, 0V DC bias.

 2010 Microchip Technology Inc. Preliminary DS39964B-page 33

PIC18F47J53 FAMILY
2.6 External Oscillator Pins FIGURE 2-4: SUGGESTED PLACEMENT
OF THE OSCILLATOR
Many microcontrollers have options for at least two
CIRCUIT
oscillators: a high-frequency primary oscillator and a
low-frequency secondary oscillator (refer to Single-Sided and In-Line Layouts:
Section 3.0 “Oscillator Configurations” for details).
Copper Pour Primary Oscillator
The oscillator circuit should be placed on the same (tied to ground) Crystal
side of the board as the device. Place the oscillator
DEVICE PINS
circuit close to the respective oscillator pins with no
more than 0.5 inch (12 mm) between the circuit
components and the pins. The load capacitors should
be placed next to the oscillator itself, on the same side Primary OSC1
Oscillator
of the board.
C1 ` OSC2
Use a grounded copper pour around the oscillator cir-
cuit to isolate it from surrounding circuits. The C2 GND
grounded copper pour should be routed directly to the `
MCU ground. Do not run any signal traces or power T1OSO
traces inside the ground pour. Also, if using a two-sided
T1OS I
board, avoid any traces on the other side of the board Timer1 Oscillator
where the crystal is placed. Crystal
`
Layout suggestions are shown in Figure 2-4. In-line
packages may be handled with a single-sided layout
that completely encompasses the oscillator pins. With T1 Oscillator: C1 T1 Oscillator: C2
fine-pitch packages, it is not always possible to com-
pletely surround the pins and components. A suitable
solution is to tie the broken guard sections to a mirrored Fine-Pitch (Dual-Sided) Layouts:
ground layer. In all cases, the guard trace(s) must be
returned to ground. Top Layer Copper Pour
(tied to ground)
In planning the application’s routing and I/O assign-
ments, ensure that adjacent port pins and other signals Bottom Layer
in close proximity to the oscillator are benign (i.e., free Copper Pour
of high frequencies, short rise and fall times, and other (tied to ground)

similar noise).
OSCO
For additional information and design guidance on
oscillator circuits, please refer to these Microchip
C2
Application Notes, available at the corporate web site
Oscillator
(www.microchip.com): GND Crystal
• AN826, “Crystal Oscillator Basics and Crystal C1
Selection for rfPIC™ and PICmicro® Devices”
• AN849, “Basic PICmicro® Oscillator Design” OSCI
• AN943, “Practical PICmicro® Oscillator Analysis
and Design”
• AN949, “Making Your Oscillator Work”

2.7 Unused I/Os DEVICE PINS

Unused I/O pins should be configured as outputs and

driven to a logic low state. Alternatively, connect a 1 kΩ
to 10 kΩ resistor to VSS on unused pins and drive the
output to logic low.

DS39964B-page 34 Preliminary  2010 Microchip Technology Inc.

 PIC18F47J53 FAMILY
3.0 OSCILLATOR TABLE 3-1: OSCILLATOR MODES
CONFIGURATIONS Mode Description
ECPLL External Clock Input mode, the PLL can
3.1 Overview be enabled or disabled in software,
CLKO on RA6, apply external clock
Devices in the PIC18F47J53 family incorporate a
signal to RA7.
different oscillator and microcontroller clock system
than general purpose PIC18F devices. Besides the EC External Clock Input mode, the PLL is
always disabled, CLKO on RA6, apply
USB module, with its unique requirements for a stable
external clock signal to RA7.
clock source, make it is necessary to provide a
separate clock source that is compliant with both USB HSPLL High-Speed Crystal/Resonator mode,
low-speed and full-speed specifications. PLL can be enabled or disabled in
software, crystal/resonator connected
The PIC18F47J53 family has additional prescalers and between RA6 and RA7.
postscalers, which have been added to accommodate
HS High-Speed Crystal/Resonator mode,
a wide range of oscillator frequencies. Figure 3-1
PLL always disabled, crystal/resonator
provides an overview of the oscillator structure.
connected between RA6 and RA7.
Other oscillator features used in PIC18 enhanced INTOSCPLLO Internal Oscillator mode, PLL can be
microcontrollers, such as the internal oscillator block enabled or disabled in software, CLKO
and clock switching, remain the same. They are on RA6, port function on RA7, the
discussed later in this chapter. internal oscillator block is used to derive
both the primary clock source and the
3.1.1 OSCILLATOR CONTROL postscaled internal clock.
The operation of the oscillator in PIC18F47J53 family INTOSCPLL Internal Oscillator mode, PLL can be
devices is controlled through three Configuration regis- enabled or disabled in software, port
ters and two control registers. Configuration registers, function on RA6 and RA7, the internal
CONFIG1L, CONFIG1H and CONFIG2L, select the oscillator block is used to derive both the
oscillator mode, PLL prescaler and CPU divider primary clock source and the postscaled
options. As Configuration bits, these are set when the internal clock.
device is programmed and left in that configuration until INTOSCO Internal Oscillator mode, PLL is always
the device is reprogrammed. disabled, CLKO on RA6, port function on
RA7, the output of the INTOSC
The OSCCON register (Register 3-2) selects the Active
postscaler serves as both the postscaled
Clock mode; it is primarily used in controlling clock
internal clock and the primary clock
switching in power-managed modes. Its use is
source.
discussed in Section 3.5.1 “Oscillator Control
Register”. INTOSC Internal Oscillator mode, PLL is always
disabled, port function on RA6 and RA7,
The OSCTUNE register (Register 3-1) is used to trim the the output of the INTOSC postscaler
INTOSC frequency source and select the low-frequency serves as both the postscaled internal
clock source that drives several special features. The clock and the primary clock source.
OSCTUNE register is also used to activate or disable the
Phase Locked Loop (PLL). Its use is described in 3.2.1 OSCILLATOR MODES AND
Section 3.2.5.1 “OSCTUNE Register”. USB OPERATION
Because of the unique requirements of the USB module,
3.2 Oscillator Types a different approach to clock operation is necessary. In
order to use the USB module, a fixed 6 MHz or 48 MHz
PIC18F47J53 family devices can be operated in eight
clock must be internally provided to the USB module for
distinct oscillator modes. Users can program the
operation in either Low-Speed or Full-Speed mode,
FOSC<2:0> Configuration bits to select one of the
respectively. The microcontroller core need not be
modes listed in Table 3-1. For oscillator modes which
clocked at the same frequency as the USB module.
produce a clock output (CLKO) on pin RA6, the output
frequency will be one fourth of the peripheral clock A network of MUXes, clock dividers and a fixed 96 MHz
frequency. The clock output stops when in Sleep mode, output PLL have been provided, which can be used to
but will continue during Idle mode (see Figure 3-1). derive various microcontroller core and USB module
frequencies. Figure 3-1 helps in understanding the
oscillator structure of the PIC18F47J53 family of
devices.

 2010 Microchip Technology Inc. Preliminary DS39964B-page 35

PIC18F47J53 FAMILY
FIGURE 3-1: PIC18F47J53 FAMILY CLOCK DIAGRAM
PLLDIV<2:0>

 12 000
 10

PLL Prescaler
001
6 010
5 011 4 MHz 96 MHz 48 MHz
4 PLL(1) 2
100
3 101
2 110
Primary Oscillator 1 111 FSEN
OSC2
FOSC2 1
USB Module
Clock
1 1
OSC1 (Note 2) Needs 48 MHz for FS
8 1
0 0 Needs 6 MHz for LS
0
CPDIV<1:0>
4 0

6 00 LS48MHZ

CPU Divider
3
01
PLLEN
2
10
CFGPLLEN
1
11
FOSC<2:1>

Primary Clock

Other
Source(4) IDLE

00 CPU

Secondary Oscillator 00
Timer1 Clock(3) Peripherals
T1OSO 01
11 RA6
Postscaled
Internal Clock 4
OSCCON<6:4>
T1OSI
8 MHz OSCCON<1:0> CLKO
111 Enabled Modes
4 MHz
Internal 110
INTOSC Postscaler

Oscillator 2 MHz
Block 101
1 MHz
100
8 MHz 500 kHz
8 MHz 011
INTRC 250 kHz
010
31 kHz 125 kHz
001
1 31 kHz
000
0
WDT, PWRT, FSCM
OSCTUNE<7> and Two-Speed Start-up

Note 1: The PLL requires a 4 MHz input and it produces a 96 MHz output. The PLL will not be available until the PLLEN bit
in the OSCTUNE register is set. Once the PLLEN bit is set, the PLL requires up to trc to lock. During this time, the
device continues to be clocked at the PLL bypassed frequency.
2: In order to use the USB module in Full-Speed mode, this node must be run at 48 MHz. For Low-Speed mode, this
node may be run at either 48 MHz or 24 MHz, but the CPDIV bits must be set such that the USB module is clocked
at 6 MHz.
3: Selecting the Timer1 clock or postscaled internal clock will turn off the primary oscillator (unless required by the
reference clock of Section 3.6 “Reference Clock Output”) and PLL.
4: The USB module cannot be used to communicate unless the primary clock source is selected.

DS39964B-page 36 Preliminary  2010 Microchip Technology Inc.

 PIC18F47J53 FAMILY
3.2.2 CRYSTAL OSCILLATOR/CERAMIC TABLE 3-3: CAPACITOR SELECTION FOR
RESONATORS CRYSTAL OSCILLATOR
In HS and HSPLL Oscillator modes, a crystal or Typical Capacitor Values
ceramic resonator is connected to the OSC1 and Crystal Tested:
Osc Type
OSC2 pins to establish oscillation. Figure 3-2 displays Freq
the pin connections. C1 C2

The oscillator design requires the use of a parallel HS 4 MHz 27 pF 27 pF

resonant crystal. 8 MHz 22 pF 22 pF
Note: Use of a series resonant crystal may give 16 MHz 18 pF 18 pF
a frequency out of the crystal Capacitor values are for design guidance only.
manufacturer’s specifications.
These capacitors were tested with the crystals listed
below for basic start-up and operation. These values
FIGURE 3-2: CRYSTAL/CERAMIC are not optimized.
RESONATOR OPERATION Different capacitor values may be required to produce
(HS OR HSPLL acceptable oscillator operation. The user should test
CONFIGURATION) the performance of the oscillator over the expected
C1(1)
VDD and temperature range for the application.
OSC1
See the notes following this table for additional
To
Internal information.
XTAL Logic
Crystals Used:
Sleep 4 MHz
RS(2)
C2(1) PIC18F47J53 8 MHz
OSC2
16 MHz
Note 1: See Table 3-2 and Table 3-3 for initial values
of C1 and C2. Note 1: Higher capacitance not only increases
2: RS may be required to avoid overdriving the stability of oscillator, but also
crystals with low drive level specifications.
increases the start-up time.
2: Since each resonator/crystal has its own
TABLE 3-2: CAPACITOR SELECTION FOR characteristics, the user should consult
CERAMIC RESONATORS the resonator/crystal manufacturer for
appropriate values of external
Typical Capacitor Values Used: components.
Mode Freq OSC1 OSC2 3: Rs may be required to avoid overdriving
crystals with low drive level specification.
HS 8.0 MHz 27 pF 27 pF
16.0 MHz 22 pF 22 pF 4: Always verify oscillator performance over
Capacitor values are for design guidance only. the VDD and temperature range that is
expected for the application.
These capacitors were tested with the resonators
listed below for basic start-up and operation. These An internal postscaler allows users to select a clock
values are not optimized. frequency other than that of the crystal or resonator.
Frequency division is determined by the CPDIV
Different capacitor values may be required to produce
Configuration bits. Users may select a clock frequency
acceptable oscillator operation. The user should test
of the oscillator frequency, or 1/2, 1/3 or 1/6 of the
the performance of the oscillator over the expected
frequency.
VDD and temperature range for the application.
See the notes following Table 3-3 for additional
information.
Resonators Used:
4.0 MHz
8.0 MHz
16.0 MHz

 2010 Microchip Technology Inc. Preliminary DS39964B-page 37

PIC18F47J53 FAMILY
3.2.3 EXTERNAL CLOCK INPUT There is also a CPU divider, which can be used to derive
the microcontroller clock from the PLL. This allows the
The EC and ECPLL Oscillator modes require an
USB peripheral and microcontroller to use the same
external clock source to be connected to the OSC1 pin.
oscillator input and still operate at different clock speeds.
There is no oscillator start-up time required after a
The CPU divider can reduce the incoming frequency by
Power-on Reset (POR) or after an exit from Sleep
a factor of 1, 2, 3 or 6.
mode.
In the EC Oscillator mode, the oscillator frequency 3.2.5 INTERNAL OSCILLATOR BLOCK
divided by 4, is available on the OSC2 pin. In the
The PIC18F47J53 family devices include an internal
ECPLL Oscillator mode, the PLL output, divided by 4,
oscillator block which generates two different clock
is available on the OSC2 pin. This signal may be used
signals; either can be used as the microcontroller’s
for test purposes or to synchronize other logic.
clock source. The internal oscillator may eliminate the
Figure 3-3 displays the pin connections for the EC
need for external oscillator circuits on the OSC1 and/or
Oscillator mode.
OSC2 pins.
FIGURE 3-3: EXTERNAL CLOCK INPUT The main output (INTOSC) is an 8 MHz clock source
OPERATION (EC AND which can be used to directly drive the device clock. It
also drives the INTOSC postscaler which can provide a
ECPLL CONFIGURATION)
range of clock frequencies from 31 kHz to 8 MHz.
Additionally, the INTOSC may be used in conjunction
Clock from OSC1/CLKI
with the PLL to generate clock frequencies up to
Ext. System PIC18F47J53 48 MHz.
FOSC/4 OSC2/CLKO
The other clock source is the internal RC oscillator
(INTRC) which provides a nominal 31 kHz output.
INTRC is enabled if it is selected as the device clock
3.2.4 PLL FREQUENCY MULTIPLIER source. It is also enabled automatically when any of the
following are enabled:
PIC18F47J53 family devices include a PLL circuit. This
is provided specifically for USB applications with lower • Power-up Timer
speed oscillators and can also be used as a • Fail-Safe Clock Monitor
microcontroller clock source. • Watchdog Timer
The PLL can be enabled in HSPLL, ECPLL, • Two-Speed Start-up
INTOSCPLL and INTOSCPLLO Oscillator modes by
These features are discussed in larger detail in
setting the PLLEN bit (OSCTUNE<6>). It is designed
Section 28.0 “Special Features of the CPU”.
to produce a fixed 96 MHz reference clock from a
fixed 4 MHz input. The output can then be divided and The clock source frequency (INTOSC direct, INTRC
used for both the USB and the microcontroller core direct or INTOSC postscaler) is selected by configuring
clock. Because the PLL has a fixed frequency input the IRCF bits of the OSCCON register (page 43).
and output, there are eight prescaling options to
match the oscillator input frequency to the PLL. This
prescaler allows the PLL to be used with crystals, res-
onators and external clocks, which are integer multiple
frequencies of 4 MHz. For example, a 12 MHz crystal
could be used in a prescaler Divide-by-Three mode to
drive the PLL.

DS39964B-page 38 Preliminary  2010 Microchip Technology Inc.

 PIC18F47J53 FAMILY
3.2.5.1 OSCTUNE Register 3.2.5.3 Compensating for INTOSC Drift
The internal oscillator’s output has been calibrated at It is possible to adjust the INTOSC frequency by
the factory but can be adjusted in the user’s applica- modifying the value in the OSCTUNE register. This has
tion. This is done by writing to the OSCTUNE register no effect on the INTRC clock source frequency.
(Register 3-1). The tuning sensitivity is constant Tuning the INTOSC source requires knowing when to
throughout the tuning range. make the adjustment, in which direction it should be
When the OSCTUNE register is modified, the INTOSC made and in some cases, how large a change is
frequency will begin shifting to the new frequency. The needed. When using the EUSART, for example, an
INTOSC clock will stabilize typically within 1 s. Code adjustment may be required when it begins to generate
execution continues during this shift. There is no framing errors or receives data with errors while in
indication that the shift has occurred. Asynchronous mode. Framing errors indicate that the
The OSCTUNE register also contains the INTSRC bit. device clock frequency is too high; to adjust for this,
The INTSRC bit allows users to select which internal decrement the value in OSCTUNE to reduce the clock
oscillator provides the clock source when the 31 kHz frequency. On the other hand, errors in data may sug-
frequency option is selected. This is covered in larger gest that the clock speed is too low; to compensate,
detail in Section 3.5.1 “Oscillator Control Register”. increment OSCTUNE to increase the clock frequency.

The PLLEN bit, contained in the OSCTUNE register, It is also possible to verify device clock speed against
can be used to enable or disable the internal 96 MHz a reference clock. Two timers may be used: one timer
PLL when running in one of the PLL type oscillator is clocked by the peripheral clock, while the other is
modes (e.g., INTOSCPLL). Oscillator modes that do clocked by a fixed reference source, such as the
not contain “PLL” in their name cannot be used with Timer1 oscillator. Both timers are cleared, but the timer
the PLL. In these modes, the PLL is always disabled clocked by the reference generates interrupts. When
regardless of the setting of the PLLEN bit. an interrupt occurs, the internally clocked timer is read
and both timers are cleared. If the internally clocked
When configured for one of the PLL enabled modes, set- timer value is greater than expected, then the internal
ting the PLLEN bit does not immediately switch the oscillator block is running too fast. To adjust for this,
device clock to the PLL output. The PLL requires up to decrement the OSCTUNE register.
electrical parameter, trc, to start-up and lock, during
which time, the device continues to be clocked. Once the Finally, an ECCP module can use free-running Timer1
PLL output is ready, the microcontroller core will (or Timer3), clocked by the internal oscillator block and
automatically switch to the PLL derived frequency. an external event with a known period (i.e., AC power
frequency). The time of the first event is captured in the
3.2.5.2 Internal Oscillator Output Frequency CCPRxH:CCPRxL registers and is recorded for use
and Drift later. When the second event causes a capture, the
time of the first event is subtracted from the time of the
The internal oscillator block is calibrated at the factory second event. Since the period of the external event is
to produce an INTOSC output frequency of 8.0 MHz. known, the time difference between events can be
However, this frequency may drift as VDD or tempera- calculated.
ture changes, which can affect the controller operation
in a variety of ways. If the measured time is greater than the calculated time,
the internal oscillator block is running too fast; to
The low-frequency INTRC oscillator operates indepen- compensate, decrement the OSCTUNE register. If the
dently of the INTOSC source. Any changes in INTOSC measured time is less than the calculated time, the inter-
across voltage and temperature are not necessarily nal oscillator block is running too slow; to compensate,
reflected by changes in INTRC and vice versa. increment the OSCTUNE register.

 2010 Microchip Technology Inc. Preliminary DS39964B-page 39

PIC18F47J53 FAMILY
REGISTER 3-1: OSCTUNE: OSCILLATOR TUNING REGISTER (ACCESS F9Bh)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
INTSRC PLLEN(1) TUN5 TUN4 TUN3 TUN2 TUN1 TUN0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 INTSRC: Internal Oscillator Low-Frequency Source Select bit

1 = 31.25 kHz device clock derived from 8 MHz INTOSC source (divide-by-256 enabled)
0 = 31 kHz device clock derived directly from INTRC internal oscillator
bit 6 PLLEN: Frequency Multiplier Enable bit(1)
1 = 96 MHz PLL is enabled
0 = 96 MHz PLL is disabled
bit 5-0 TUN<5:0>: Frequency Tuning bits
011111 = Maximum frequency
011110
•
•
•
000001
000000 = Center frequency; oscillator module is running at the calibrated frequency
111111
•
•
•
100000 = Minimum frequency

Note 1: When the CFGPLLEN Configuration bit is used to enable the PLL, clearing OSCTUNE<6> will not disable
the PLL.

3.3 Oscillator Settings for USB 3.3.1 LOW-SPEED OPERATION

When the PIC18F47J53 family devices are used for The USB clock for Low-Speed mode is derived from the
USB connectivity, a 6 MHz or 48 MHz clock must be primary oscillator or from the 96 MHz PLL. In order to
provided to the USB module for operation in either operate the USB module in Low-Speed mode, a 6 MHz
Low-Speed or Full-Speed modes, respectively. This clock must be provided to the USB module.
may require some forethought in selecting an oscillator See Table 3-4 and Table 3-5 for possible combinations
frequency and programming the device. which can be used for low-speed USB operation.
The full range of possible oscillator configurations
compatible with USB operation is shown in Table 3-5.

TABLE 3-4: CLOCK FOR LOW-SPEED USB

System Clock CPDIV<1:0> Microcontroller Clock LS48MHZ USB Clock
48 11 48 MHz 1 48/8 = 6 MHz
48 10 48/2 = 24 MHz 1 48/8 = 6 MHz
48 01 48/3 = 16 MHz 1 48/8 = 6 MHz
48 00 48/6 = 8 MHz 1 48/8 = 6 MHz
24 11 24 MHz 0 24/4 = 6 MHz
24 10 24/2 = 12 MHz 0 24/4 = 6 MHz
24 01 24/3 = 8 MHz 0 24/4 = 6 MHz
24 00 24/6 = 4 MHz 0 24/4 = 6 MHz

DS39964B-page 40 Preliminary  2010 Microchip Technology Inc.

 PIC18F47J53 FAMILY

TABLE 3-5: OSCILLATOR CONFIGURATION OPTIONS FOR USB OPERATION

Input Oscillator PLL Division Clock Mode MCU Clock Division Microcontroller
Frequency (PLLDIV<2:0>) (FOSC<2:0>) (CPDIV<1:0>) Clock Frequency

None (11) 48 MHz

2 (10) 24 MHz
48 MHz N/A EC
3 (01) 16 MHz
6 (00) 8 MHz
None (11) 48 MHz
2 (10) 24 MHz
48 MHz 12 (000) ECPLL
3 (01) 16 MHz
6 (00) 8 MHz
None (11) 48 MHz
2 (10) 24 MHz
40 MHz 10 (001) ECPLL
3 (01) 16 MHz
6 (00) 8 MHz
None (11) 48 MHz
2 (10) 24 MHz
24 MHz 6 (010) ECPLL
3 (01) 16 MHz
6 (00) 8 MHz
None (11) 24 MHz
2 (10) 12 MHz
24 MHz N/A EC(1)
3 (01) 8 MHz
6 (00) 4 MHz
None (11) 48 MHz
2 (10) 24 MHz
20 MHz 5 (011) ECPLL
3 (01) 16 MHz
6 (00) 8 MHz
None (11) 48 MHz
2 (10) 24 MHz
16 MHz 4 (100) HSPLL, ECPLL
3 (01) 16 MHz
6 (00) 8 MHz
None (11) 48 MHz
2 (10) 24 MHz
12 MHz 3 (101) HSPLL, ECPLL
3 (01) 16 MHz
6 (00) 8 MHz
None (11) 48 MHz
HSPLL, ECPLL, 2 (10) 24 MHz
8 MHz 2 (110) INTOSCPLL/
INTOSCPLLO 3 (01) 16 MHz
6 (00) 8 MHz
None (11) 48 MHz
2 (10) 24 MHz
4 MHz 1 (111) HSPLL, ECPLL
3 (01) 16 MHz
6 (00) 8 MHz
Note 1: The 24 MHz EC mode (without PLL) is only compatible with low-speed USB. Full-speed USB requires a 48 MHz system
clock.

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PIC18F47J53 FAMILY
3.4 USB From INTOSC 3.5.1 OSCILLATOR CONTROL REGISTER
The 8 MHz INTOSC included in all PIC18F47J53 family The OSCCON register (Register 3-2) controls several
devices is extremely accurate. When the 8 MHz aspects of the device clock’s operation, both in
INTOSC is used with the 96 MHz PLL, it may be used full-power operation and in power-managed modes.
to derive the USB module clock. The high accuracy of The System Clock Select bits, SCS<1:0>, select the
the INTOSC will allow the application to meet clock source. The available clock sources are the
low-speed USB signal rate specifications. primary clock (defined by the FOSC<2:0> Configura-
tion bits), the secondary clock (Timer1 oscillator) and
3.5 Clock Sources and Oscillator the postscaled internal clock.The clock source changes
Switching immediately, after one or more of the bits is written to,
following a brief clock transition interval. The SCS bits
Like previous PIC18 enhanced devices, the are cleared on all forms of Reset.
PIC18F47J53 family includes a feature that allows the
The Internal Oscillator Frequency Select bits,
device clock source to be switched from the main
IRCF<2:0>, select the frequency output provided on
oscillator to an alternate, low-frequency clock source.
the postscaled internal clock line. The choices are the
PIC18F47J53 family devices offer two alternate clock
INTRC source, the INTOSC source (8 MHz) or one of
sources. When an alternate clock source is enabled,
the frequencies derived from the INTOSC postscaler
the various power-managed operating modes are
(31 kHz to 4 MHz). If the postscaled internal clock is
available.
supplying the device clock, changing the states of
Essentially, there are three clock sources for these these bits will have an immediate change on the inter-
devices: nal oscillator’s output. On device Resets, the default
• Primary Oscillators output frequency of the INTOSC postscaler is set at
4 MHz.
• Secondary Oscillators
• Internal Oscillator Block When an output frequency of 31 kHz is selected
(IRCF<2:0> = 000), users may choose the internal
The Primary Oscillators include the External Crystal oscillator, which acts as the source. This is done with
and Resonator modes, the External Clock modes and the INTSRC bit in the OSCTUNE register
the internal oscillator block. The particular mode is (OSCTUNE<7>). Setting this bit selects INTOSC as a
defined by the FOSC<2:0> Configuration bits. The 31.25 kHz clock source by enabling the divide-by-256
details of these modes are covered earlier in this output of the INTOSC postscaler. Clearing INTSRC
chapter. selects INTRC (nominally 31 kHz) as the clock source.
The Secondary Oscillators are external sources that This option allows users to select the tunable and more
are not connected to the OSC1 or OSC2 pins. These precise INTOSC as a clock source, while maintaining
sources may continue to operate even after the power savings with a very low clock speed. Regardless
controller is placed in a power-managed mode. of the setting of INTSRC, INTRC always remains the
PIC18F47J53 family devices offer the Timer1 oscillator clock source for features such as the WDT and the
as a secondary oscillator. This oscillator, in all FSCM.
power-managed modes, is often the time base for The OSTS and SOSCRUN bits indicate which clock
functions such as a Real-Time Clock (RTC). Most often, source is currently providing the device clock. The
a 32.768 kHz watch crystal is connected between the OSTS bit indicates that the Oscillator Start-up Timer
RC0/T1OSO/T1CKI/RP11 and RC1/CCP8/T1OSI/UOE/ (OST) has timed out and the primary clock is providing
RP12 pins. Like the HS Oscillator mode circuits, loading the device clock in primary clock modes. The
capacitors are also connected from each pin to ground. SOSCRUN bit (OSCCON2<6>) indicates when the
The Timer1 oscillator is discussed in larger detail in Timer1 oscillator is providing the device clock in sec-
Section 13.5 “Timer1 Oscillator”. ondary clock modes. In power-managed modes, only
In addition to being a primary clock source, the one of these bits will be set at any time. If none of these
postscaled internal clock is available as a bits are set, the INTRC is providing the clock or the
power-managed mode clock source. The INTRC internal oscillator block has just started and is not yet
source is also used as the clock source for several stable.
special features, such as the WDT and Fail-Safe Clock The IDLEN bit determines if the device goes into Sleep
Monitor (FSCM). mode, or one of the Idle modes, when the SLEEP
instruction is executed.

DS39964B-page 42 Preliminary  2010 Microchip Technology Inc.

 PIC18F47J53 FAMILY
The use of the flag and control bits in the OSCCON 3.5.2 OSCILLATOR TRANSITIONS
register is discussed in more detail in Section 4.0
PIC18F47J53 family devices contain circuitry to
“Low-Power Modes”.
prevent clock “glitches” when switching between clock
Note 1: The Timer1 crystal driver is enabled by sources. A short pause in the device clock occurs dur-
setting the T1OSCEN bit in the Timer1 ing the clock switch. The length of this pause is the sum
Control register (T1CON<3>). If the of two cycles of the old clock source and three to four
Timer1 oscillator is not enabled, then any cycles of the new clock source. This formula assumes
attempt to select the Timer1 clock source that the new clock source is stable.
will be ignored, unless the CONFIG2L Clock transitions are discussed in more detail in
register’s T1DIG bit is set. Section 4.1.2 “Entering Power-Managed Modes”.
2: If Timer1 is driving a crystal, it is recom-
mended that the Timer1 oscillator be
operating and stable prior to switching to
it as the clock source; otherwise, a very
long delay may occur while the Timer1
oscillator starts.

REGISTER 3-2: OSCCON: OSCILLATOR CONTROL REGISTER (ACCESS FD3h)

R/W-0 R/W-1 R/W-1 R/W-0 R-1(1) R-0 R/W-0 R/W-0
IDLEN IRCF2 IRCF1 IRCF0 OSTS FLTS SCS1 SCS0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 IDLEN: Idle Enable bit

1 = Device enters Idle mode on SLEEP instruction
0 = Device enters Sleep mode on SLEEP instruction
bit 6-4 IRCF<2:0>: Internal Oscillator Frequency Select bits
111 = 8 MHz (INTOSC drives clock directly)
110 = 4 MHz(2)
101 = 2 MHz
100 = 1 MHz
011 = 500 kHz
010 = 250 kHz
001 = 125 kHz
000 = 31 kHz (from either INTOSC/256 or INTRC directly)(3)
bit 3 OSTS: Oscillator Start-up Time-out Status bit(1)
1 = Oscillator Start-up Timer time-out has expired; primary oscillator is running
0 = Oscillator Start-up Timer time-out is running; primary oscillator is not ready
bit 2 FLTS: Frequency Lock Tuning Status bit
1 = INTOSC is stable
0 = INTOSC is not stable
bit 1-0 SCS<1:0>: System Clock Select bits
11 = Postscaled internal clock (INTRC/INTOSC derived)
10 = Reserved
01 = Timer1 oscillator
00 = Primary clock source (INTOSC postscaler output when FOSC<2:0> = 001 or 000)
00 = Primary clock source (CPU divider output for other values of FOSC<2:0>)

Note 1: Reset value is ‘0’ when Two-Speed Start-up is enabled and ‘1’ if disabled.
2: Default output frequency of INTOSC on Reset (4 MHz).
3: Source selected by the INTSRC bit (OSCTUNE<7>).

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PIC18F47J53 FAMILY
REGISTER 3-3: OSCCON2: OSCILLATOR CONTROL REGISTER 2 (ACCESS F87h)
U-0 R-0(2) U-0 R/W-1 R/W-0(2) R/W-1 U-0 U-0
(3)
— SOSCRUN — SOSCDRV SOSCGO PRISD — —
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 Unimplemented: Read as ‘0’

bit 6 SOSCRUN: SOSC Run Status bit
1 = System clock comes from secondary SOSC
0 = System clock comes from an oscillator other than SOSC
bit 5 Unimplemented: Read as ‘0’
bit 4 SOSCDRV: SOSC Drive Control bit
1 = T1OSC/SOSC oscillator drive circuit is selected by Configuration bits, CONFIG2L <4:3>
0 = Low-power T1OSC/SOSC circuit is selected
bit 3 SOSCGO: Oscillator Start Control bit(3)
1 = Turns on the oscillator, even if no peripherals are requesting it
0 = Oscillator is shut off unless peripherals are requesting it
bit 2 PRISD: Primary Oscillator Drive Circuit Shutdown bit
1 = Oscillator drive circuit is on
0 = Oscillator drive circuit is off (zero power)
bit 1-0 Unimplemented: Read as ‘0’

Note 1: Reset value is ‘0’ when Two-Speed Start-up is enabled and ‘1’ if disabled.
2: Default output frequency of INTOSC on Reset (4 MHz).
3: When the SOSC is selected to run from a digital clock input, rather than an external crystal, this bit has no
effect.

DS39964B-page 44 Preliminary  2010 Microchip Technology Inc.

 PIC18F47J53 FAMILY
3.6 Reference Clock Output The ROSSLP and ROSEL bits (REFOCON<5:4>)
control the availability of the reference output during
In addition to the peripheral clock/4 output in certain Sleep mode. The ROSEL bit determines if the oscillator
oscillator modes, the device clock in the PIC18F47J53 is on OSC1 and OSC2, or the current system clock
family can also be configured to provide a reference source is used for the reference clock output. The
clock output signal to a port pin. This feature is avail- ROSSLP bit determines if the reference source is
able in all oscillator configurations and allows the user available on RB2 when the device is in Sleep mode.
to select a greater range of clock submultiples to drive
external devices in the application. To use the reference clock output in Sleep mode, both
the ROSSLP and ROSEL bits must be set. The device
This reference clock output is controlled by the clock must also be configured for an EC or HS mode;
REFOCON register (Register 3-4). Setting the ROON otherwise, the oscillator on OSC1 and OSC2 will be
bit (REFOCON<7>) makes the clock signal available powered down when the device enters Sleep mode.
on the REFO (RB2) pin. The RODIV<3:0> bits enable Clearing the ROSEL bit allows the reference output
the selection of 16 different clock divider options. frequency to change as the system clock changes
during any clock switches.

REGISTER 3-4: REFOCON: REFERENCE OSCILLATOR CONTROL REGISTER (BANKED F3Dh)

R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
ROON — ROSSLP ROSEL RODIV3 RODIV2 RODIV1 RODIV0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 ROON: Reference Oscillator Output Enable bit

1 = Reference oscillator is enabled on REFO pin
0 = Reference oscillator is disabled
bit 6 Unimplemented: Read as ‘0’
bit 5 ROSSLP: Reference Oscillator Output Stop in Sleep bit
1 = Reference oscillator continues to run in Sleep
0 = Reference oscillator is disabled in Sleep
bit 4 ROSEL: Reference Oscillator Source Select bit
1 = Primary oscillator crystal/resonator is used as the base clock(1)
0 = System clock (FOSC) is used as the base clock; the base clock reflects any clock switching of the device
bit 3-0 RODIV<3:0>: Reference Oscillator Divisor Select bits
1111 = Base clock value divided by 32,768
1110 = Base clock value divided by 16,384
1101 = Base clock value divided by 8,192
1100 = Base clock value divided by 4,096
1011 = Base clock value divided by 2,048
1010 = Base clock value divided by 1,024
1001 = Base clock value divided by 512
1000 = Base clock value divided by 256
0111 = Base clock value divided by 128
0110 = Base clock value divided by 64
0101 = Base clock value divided by 32
0100 = Base clock value divided by 16
0011 = Base clock value divided by 8
0010 = Base clock value divided by 4
0001 = Base clock value divided by 2
0000 = Base clock value

Note 1: The crystal oscillator must be enabled using the FOSC<2:0> bits; the crystal maintains the operation in
Sleep mode.

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PIC18F47J53 FAMILY
3.7 Effects of Power-Managed Modes Sleep mode should not be invoked while the USB
on Various Clock Sources module is enabled and operating in Full-Power mode.
Before Sleep mode is selected, the USB module should
When the PRI_IDLE mode is selected, the designated be put in the suspend state. This is accomplished by
primary oscillator continues to run without interruption. setting the SUSPND bit in the UCON register.
For all other power-managed modes, the oscillator
Enabling any on-chip feature that will operate during
using the OSC1 pin is disabled. Unless the USB
Sleep mode increases the current consumed during
module is enabled, the OSC1 pin (and OSC2 pin if
Sleep mode. The INTRC is required to support WDT
used by the oscillator) will stop oscillating.
operation. The Timer1 oscillator may be operating to
In secondary clock modes (SEC_RUN and support an RTC. Other features may be operating that
SEC_IDLE), the Timer1 oscillator is operating and do not require a device clock source (i.e., MSSP slave,
providing the device clock. The Timer1 oscillator may PMP, INTx pins, etc.). Peripherals that may add
also run in all power-managed modes if required to significant current consumption are listed in
clock Timer1 or Timer3. Section 31.2 “DC Characteristics: Power-Down and
In internal oscillator modes (RC_RUN and RC_IDLE), Supply Current PIC18F47J53 Family (Industrial)”.
the internal oscillator block provides the device clock
source. The 31 kHz INTRC output can be used directly 3.8 Power-up Delays
to provide the clock and may be enabled to support
Power-up delays are controlled by two timers so that no
various special features regardless of the
external Reset circuitry is required for most applica-
power-managed mode (see Section 28.2 “Watchdog
tions. The delays ensure that the device is kept in
Timer (WDT)”, Section 28.4 “Two-Speed Start-up”
Reset until the device power supply is stable under
and Section 28.5 “Fail-Safe Clock Monitor” for more
normal circumstances and the primary clock is operat-
information on WDT, FSCM and Two-Speed Start-up).
ing and stable. For additional information on power-up
The INTOSC output at 8 MHz may be used directly to
delays, see Section 5.6 “Power-up Timer (PWRT)”.
clock the device or may be divided down by the post-
scaler. The INTOSC output is disabled if the clock is The first timer is the Power-up Timer (PWRT), which
provided directly from the INTRC output. provides a fixed delay on power-up (parameter 33,
Table 31-14).
If Sleep mode is selected, all clock sources which are
no longer required are stopped. Since all the transistor The second timer is the Oscillator Start-up Timer
switching currents have been stopped, Sleep mode (OST), intended to keep the chip in Reset until the
achieves the lowest current consumption of the device crystal oscillator is stable (HS mode). The OST does
(only leakage currents) outside of Deep Sleep. this by counting 1024 oscillator cycles before allowing
the oscillator to clock the device.
There is a delay of interval, TCSD (parameter 38,
Table 31-14), following POR, while the controller
becomes ready to execute instructions. This delay runs
concurrently with any other delays. This may be the only
delay that occurs when any of the internal oscillator or
EC modes are used as the primary clock source.

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 PIC18F47J53 FAMILY
4.0 LOW-POWER MODES The IDLEN bit (OSCCON<7>) controls CPU clocking
and the SCS<1:0> bits (OSCCON<1:0>) select the
The PIC18F47J53 family devices can manage power clock source. The individual modes, bit settings, clock
consumption through clocking to the CPU and the sources and affected modules are summarized in
peripherals. In general, reducing the clock frequency Table 4-1.
and number of circuits being clocked reduces power
consumption. 4.1.1 CLOCK SOURCES
For managing power in an application, the primary The SCS<1:0> bits allow the selection of one of three
modes of operation are: clock sources for power-managed modes. They are:
• Run Mode • Primary clock source – Defined by the
• Idle Mode FOSC<2:0> Configuration bits
• Sleep Mode • Timer1 clock – Provided by the secondary
• Deep Sleep Mode oscillator
• Postscaled internal clock – Derived from the
Additionally, there is an Ultra Low-Power Wake-up
internal oscillator block
(ULPWU) mode for generating an interrupt-on-change
on RA0.
4.1.2 ENTERING POWER-MANAGED
These modes define which portions of the device are MODES
clocked and at what speed.
Switching from one clock source to another begins by
• The Run and Idle modes can use any of the three loading the OSCCON register. The SCS<1:0> bits
available clock sources (primary, secondary or select the clock source.
internal oscillator blocks).
Changing these bits causes an immediate switch to the
• The Sleep mode does not use a clock source. new clock source, assuming that it is running. The
The ULPWU mode on RA0 allows a slow falling voltage switch also may be subject to clock transition delays.
to generate an interrupt-on-change on RA0 without These delays are discussed in Section 4.1.3 “Clock
excess current consumption. See Section 4.7 “Ultra Transitions and Status Indicators” and subsequent
Low-Power Wake-up”. sections.
The power-managed modes include several Entry to the power-managed Idle or Sleep modes is
power-saving features offered on previous PIC® triggered by the execution of a SLEEP instruction. The
devices, such as clock switching, ULPWU and Sleep actual mode that results depends on the status of the
mode. In addition, the PIC18F47J53 family devices add IDLEN bit.
a new power-managed Deep Sleep mode. Depending on the current mode and the mode being
switched to, a change to a power-managed mode does
4.1 Selecting Power-Managed Modes not always require setting all of these bits. Many transi-
tions may be done by changing the oscillator select
Selecting a power-managed mode requires these
bits, the IDLEN bit, or the DSEN bit prior to issuing a
decisions:
SLEEP instruction.
• Will the CPU be clocked?
If the IDLEN and DSEN bits are already configured
• If so, which clock source will be used? correctly, it may only be necessary to perform a SLEEP
instruction to switch to the desired mode.

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TABLE 4-1: LOW-POWER MODES
DSCONH<7> OSCCON<7,1:0> Module Clocking
Mode Available Clock and Oscillator Source
DSEN(1) IDLEN(1) SCS<1:0> CPU Peripherals
Sleep 0 0 N/A Off Off Timer1 oscillator and/or RTCC may optionally be
enabled
Deep 1 0 N/A Powered Powered off RTCC can run uninterrupted using the Timer1 or
Sleep(3) off(2) internal low-power RC oscillator
PRI_RUN 0 N/A 00 Clocked Clocked The normal, full-power execution mode; primary
clock source (defined by FOSC<2:0>)
SEC_RUN 0 N/A 01 Clocked Clocked Secondary – Timer1 oscillator
RC_RUN 0 N/A 11 Clocked Clocked Postscaled internal clock
PRI_IDLE 0 1 00 Off Clocked Primary clock source (defined by FOSC<2:0>)
SEC_IDLE 0 1 01 Off Clocked Secondary – Timer1 oscillator
RC_IDLE 0 1 11 Off Clocked Postscaled internal clock
Note 1: IDLEN and DSEN reflect their values when the SLEEP instruction is executed.
2: Deep Sleep turns off the internal core voltage regulator to power down core logic. See Section 4.6 “Deep Sleep
Mode” for more information.
3: Deep Sleep mode is only available on “F” devices, not “LF” devices.

4.1.3 CLOCK TRANSITIONS AND STATUS 4.1.4 MULTIPLE SLEEP COMMANDS

INDICATORS The power-managed mode that is invoked with the
The length of the transition between clock sources is SLEEP instruction is determined by the setting of the
the sum of two cycles of the old clock source and three IDLEN and DSEN bits at the time the instruction is exe-
to four cycles of the new clock source. This formula cuted. If another SLEEP instruction is executed, the
assumes that the new clock source is stable. device will enter the power-managed mode specified
by IDLEN and DSEN at that time. If IDLEN or DSEN
Two bits indicate the current clock source and its
have changed, the device will enter the new
status: OSTS (OSCCON<3>) and SOSCRUN
power-managed mode specified by the new setting.
(OSCCON2<6>). In general, only one of these bits will
be set in a given power-managed mode. When the
OSTS bit is set, the primary clock would be providing
the device clock. When the SOSCRUN bit is set, the
Timer1 oscillator would be providing the clock. If neither
of these bits is set, INTRC would be clocking the
device.
Note: Executing a SLEEP instruction does not
necessarily place the device into Sleep
mode. It acts as the trigger to place the
controller into either the Sleep or Deep
Sleep mode, or one of the Idle modes,
depending on the setting of the IDLEN bit.

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 PIC18F47J53 FAMILY
4.2 Run Modes Note: The Timer1 oscillator should already be
In the Run modes, clocks to both the core and running prior to entering SEC_RUN mode.
peripherals are active. The difference between these If the T1OSCEN bit is not set when the
modes is the clock source. SCS<1:0> bits are set to ‘01’, entry to
SEC_RUN mode will not occur. If the
4.2.1 PRI_RUN MODE Timer1 oscillator is enabled, but not yet
running, device clocks will be delayed until
The PRI_RUN mode is the normal, full-power execu-
the oscillator has started. In such situa-
tion mode of the microcontroller. This is also the default
tions, initial oscillator operation is far from
mode upon a device Reset unless Two-Speed Start-up
stable and unpredictable operation may
is enabled (see Section 28.4 “Two-Speed Start-up”
result.
for details). In this mode, the OSTS bit is set (see
Section 3.5.1 “Oscillator Control Register”). On transitions from SEC_RUN mode to PRI_RUN
mode, the peripherals and CPU continue to be clocked
4.2.2 SEC_RUN MODE from the Timer1 oscillator while the primary clock is
started. When the primary clock becomes ready, a
The SEC_RUN mode is the compatible mode to the
clock switch back to the primary clock occurs (see
“clock switching” feature offered in other PIC18
Figure 4-2). When the clock switch is complete, the
devices. In this mode, the CPU and peripherals are
SOSCRUN bit is cleared, the OSTS bit is set and the
clocked from the Timer1 oscillator. This gives users the
primary clock would be providing the clock. The IDLEN
option of low-power consumption while still using a
and SCS bits are not affected by the wake-up; the
high-accuracy clock source.
Timer1 oscillator continues to run.
SEC_RUN mode is entered by setting the SCS<1:0>
bits to ‘01’. The device clock source is switched to the
Timer1 oscillator (see Figure 4-1), the primary
oscillator is shut down, the SOSCRUN bit
(OSCCON2<6>) is set and the OSTS bit is cleared.

FIGURE 4-1: TRANSITION TIMING FOR ENTRY TO SEC_RUN MODE

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3

T1OSI 1 2 3 n-1 n

OSC1 Clock Transition

CPU
Clock
Peripheral
Clock
Program
Counter PC PC + 2 PC + 4

FIGURE 4-2: TRANSITION TIMING FROM SEC_RUN MODE TO PRI_RUN MODE (HSPLL)
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3

T1OSI
OSC1
TOST(1) TPLL(1)
1 2 n-1 n
PLL Clock
Output
Clock
Transition
CPU Clock

Peripheral
Clock
Program PC + 2 PC + 4
PC
Counter

SCS<1:0> Bits Changed OSTS Bit Set

Note 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.

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4.2.3 RC_RUN MODE On transitions from RC_RUN mode to PRI_RUN mode,
the device continues to be clocked from the INTOSC
In RC_RUN mode, the CPU and peripherals are
block while the primary clock is started. When the
clocked from the internal oscillator; the primary clock is
primary clock becomes ready, a clock switch to the
shut down. This mode provides the best power conser-
primary clock occurs (see Figure 4-4). When the clock
vation of all the Run modes while still executing code.
switch is complete, the OSTS bit is set and the primary
It works well for user applications, which are not highly
clock is providing the device clock. The IDLEN and
timing-sensitive or do not require high-speed clocks at
SCS bits are not affected by the switch. The INTRC
all times.
clock source will continue to run if either the WDT or the
This mode is entered by setting the SCS<1:0> bits FSCM is enabled.
(OSCCON<1:0>) to ‘11’. When the clock source is
switched to the internal oscillator block (see
Figure 4-3), the primary oscillator is shut down and the
OSTS bit is cleared.

FIGURE 4-3: TRANSITION TIMING TO RC_RUN MODE

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3

INTRC 1 2 3 n-1 n
Clock Transition
OSC1

CPU
Clock
Peripheral
Clock
Program
Counter PC PC + 2 PC + 4

FIGURE 4-4: TRANSITION TIMING FROM RC_RUN MODE TO PRI_RUN MODE

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3

INTRC

OSC1
TOST(1) TPLL(1)
1 2 n-1 n
PLL Clock
Output
Clock
Transition
CPU Clock

Peripheral
Clock

Program PC PC + 2 PC + 4
Counter

SCS<1:0> Bits Changed OSTS Bit Set

Note 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.

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4.3 Sleep Mode When a wake event occurs in Sleep mode (by interrupt,
Reset or WDT time-out), the device will not be clocked
The power-managed Sleep mode is identical to the until the clock source selected by the SCS<1:0> bits
legacy Sleep mode offered in all other PIC devices. It is becomes ready (see Figure 4-6), or it will be clocked
entered by clearing the IDLEN bit (the default state on from the internal oscillator if either the Two-Speed
device Reset) and executing the SLEEP instruction. Start-up or the FSCM is enabled (see Section 28.0
This shuts down the selected oscillator (Figure 4-5). All “Special Features of the CPU”). In either case, the
clock source status bits are cleared. OSTS bit is set when the primary clock is providing the
Entering the Sleep mode from any other mode does not device clocks. The IDLEN and SCS bits are not
require a clock switch. This is because no clocks are affected by the wake-up.
needed once the controller has entered Sleep mode. If
the WDT is selected, the INTRC source will continue to
operate. If the Timer1 oscillator is enabled, it will also
continue to run.

FIGURE 4-5: TRANSITION TIMING FOR ENTRY TO SLEEP MODE

Q1 Q2 Q3 Q4 Q1
OSC1

CPU
Clock
Peripheral
Clock

Sleep

Program
Counter PC PC + 2

FIGURE 4-6: TRANSITION TIMING FOR WAKE FROM SLEEP (HSPLL)

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

OSC1
TOST(1) TPLL(1)
PLL Clock
Output

CPU Clock
Peripheral
Clock
Program PC PC + 2 PC + 4 PC + 6
Counter

Wake Event OSTS Bit Set

Note 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.

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4.4 Idle Modes When a wake event occurs, the CPU is clocked from the
primary clock source. A delay of interval, TCSD, is
The Idle modes allow the controller’s CPU to be required between the wake event and when code
selectively shut down while the peripherals continue to execution starts. This is required to allow the CPU to
operate. Selecting a particular Idle mode allows users become ready to execute instructions. After the
to further manage power consumption. wake-up, the OSTS bit remains set. The IDLEN and
If the IDLEN bit is set to ‘1’ when a SLEEP instruction is SCS bits are not affected by the wake-up (see
executed, the peripherals will be clocked from the clock Figure 4-8).
source selected using the SCS<1:0> bits; however, the
CPU will not be clocked. The clock source status bits are 4.4.2 SEC_IDLE MODE
not affected. Setting IDLEN and executing a SLEEP In SEC_IDLE mode, the CPU is disabled but the
instruction provides a quick method of switching from a peripherals continue to be clocked from the Timer1
given Run mode to its corresponding Idle mode. oscillator. This mode is entered from SEC_RUN by set-
If the WDT is selected, the INTRC source will continue ting the IDLEN bit and executing a SLEEP instruction. If
to operate. If the Timer1 oscillator is enabled, it will also the device is in another Run mode, set IDLEN first, then
continue to run. set SCS<1:0> to ‘01’ and execute SLEEP. When the
clock source is switched to the Timer1 oscillator, the
Since the CPU is not executing instructions, the only
primary oscillator is shut down, the OSTS bit is cleared
exits from any of the Idle modes are by interrupt, WDT
and the SOSCRUN bit is set.
time-out or a Reset. When a wake event occurs, CPU
execution is delayed by an interval of TCSD When a wake event occurs, the peripherals continue to
(parameter 38, Table 31-14) while it becomes ready to be clocked from the Timer1 oscillator. After an interval
execute code. When the CPU begins executing code, of TCSD following the wake event, the CPU begins exe-
it resumes with the same clock source for the current cuting code being clocked by the Timer1 oscillator. The
Idle mode. For example, when waking from RC_IDLE IDLEN and SCS bits are not affected by the wake-up;
mode, the internal oscillator block will clock the CPU the Timer1 oscillator continues to run (see Figure 4-8).
and peripherals (in other words, RC_RUN mode). The Note: The Timer1 oscillator should already be
IDLEN and SCS bits are not affected by the wake-up. running prior to entering SEC_IDLE mode.
While in any Idle or Sleep mode, a WDT time-out will If the T1OSCEN bit is not set when the
result in a WDT wake-up to the Run mode currently SLEEP instruction is executed, the SLEEP
specified by the SCS<1:0> bits. instruction will be ignored and entry to
SEC_IDLE mode will not occur. If the
4.4.1 PRI_IDLE MODE Timer1 oscillator is enabled, but not yet
This mode is unique among the three low-power Idle running, peripheral clocks will be delayed
modes, in that it does not disable the primary device until the oscillator has started. In such
clock. For timing-sensitive applications, this allows for situations, initial oscillator operation is far
the fastest resumption of device operation with its more from stable and unpredictable operation
accurate primary clock source, since the clock source may result.
does not have to “warm up” or transition from another
oscillator.
PRI_IDLE mode is entered from PRI_RUN mode by
setting the IDLEN bit and executing a SLEEP instruc-
tion. If the device is in another Run mode, set IDLEN
first, then set the SCS bits to ‘00’ and execute SLEEP.
Although the CPU is disabled, the peripherals continue
to be clocked from the primary clock source specified
by the FOSC<1:0> Configuration bits. The OSTS bit
remains set (see Figure 4-7).

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FIGURE 4-7: TRANSITION TIMING FOR ENTRY TO IDLE MODE

Q1 Q2 Q3 Q4 Q1

OSC1

CPU Clock

Peripheral
Clock

Program
Counter PC PC + 2

FIGURE 4-8: TRANSITION TIMING FOR WAKE FROM IDLE TO RUN MODE

Q1 Q2 Q3 Q4

OSC1

TCSD
CPU Clock

Peripheral
Clock

Program PC
Counter

Wake Event

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4.4.3 RC_IDLE MODE On all exits from Idle or Sleep modes by interrupt, code
execution branches to the interrupt vector if the
In RC_IDLE mode, the CPU is disabled but the
GIE/GIEH bit (INTCON<7>) is set. Otherwise, code
peripherals continue to be clocked from the internal
execution continues or resumes without branching
oscillator block. This mode allows for controllable
(see Section 9.0 “Interrupts”).
power conservation during Idle periods.
A fixed delay of interval, TCSD, following the wake
From RC_RUN, this mode is entered by setting the
event, is required when leaving Sleep mode. This delay
IDLEN bit and executing a SLEEP instruction. If the
is required for the CPU to prepare for execution.
device is in another Run mode, first set IDLEN, then
Instruction execution resumes on the first clock cycle
clear the SCS bits and execute SLEEP. When the clock
following this delay.
source is switched to the INTOSC block, the primary
oscillator is shutdown and the OSTS bit is cleared.
4.5.2 EXIT BY WDT TIME-OUT
When a wake event occurs, the peripherals continue to
A WDT time-out will cause different actions depending
be clocked from the internal oscillator block. After a
on which power-managed mode the device is, when
delay of TCSD following the wake event, the CPU
the time-out occurs.
begins executing code being clocked by the INTRC.
The IDLEN and SCS bits are not affected by the If the device is not executing code (all Idle modes and
wake-up. The INTRC source will continue to run if Sleep mode), the time-out will result in an exit from the
either the WDT or the FSCM is enabled. power-managed mode (see Section 4.2 “Run
Modes” and Section 4.3 “Sleep Mode”). If the device
4.5 Exiting Idle and Sleep Modes is executing code (all Run modes), the time-out will
result in a WDT Reset (see Section 28.2 “Watchdog
An exit from Sleep mode, or any of the Idle modes, is Timer (WDT)”).
triggered by an interrupt, a Reset or a WDT time-out. The WDT and postscaler are cleared by one of the
This section discusses the triggers that cause exits following events:
from power-managed modes. The clocking subsystem
actions are discussed in each of the power-managed • Executing a SLEEP or CLRWDT instruction
modes sections (see Section 4.2 “Run Modes”, • The loss of a currently selected clock source (if
Section 4.3 “Sleep Mode” and Section 4.4 “Idle the FSCM is enabled)
Modes”).
4.5.3 EXIT BY RESET
4.5.1 EXIT BY INTERRUPT Exiting an Idle or Sleep mode by Reset automatically
Any of the available interrupt sources can cause the forces the device to run from the INTRC.
device to exit from an Idle mode, or the Sleep mode, to
a Run mode. To enable this functionality, an interrupt
source must be enabled by setting its enable bit in one
of the INTCON or PIE registers. The exit sequence is
initiated when the corresponding interrupt flag bit is set.

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4.5.4 EXIT WITHOUT AN OSCILLATOR In order to minimize the possibility of inadvertently enter-
START-UP DELAY ing Deep Sleep, the DSEN bit is cleared in hardware
two instruction cycles after having been set. Therefore,
Certain exits from power-managed modes do not
in order to enter Deep Sleep, the SLEEP instruction must
invoke the OST at all. There are two cases:
be executed in the immediate instruction cycle after set-
• PRI_IDLE mode (where the primary clock source ting DSEN. If DSEN is not set when Sleep is executed,
is not stopped) and the primary clock source is the device will enter conventional Sleep mode instead.
the EC mode
During Deep Sleep, the core logic circuitry of the
• PRI_IDLE mode and the primary clock source is microcontroller is powered down to reduce leakage
the ECPLL mode current. Therefore, most peripherals and functions of
In these instances, the primary clock source either the microcontroller become unavailable during Deep
does not require an oscillator start-up delay, since it is Sleep. However, a few specific peripherals and func-
already running (PRI_IDLE), or normally does not tions are powered directly from the VDD supply rail of
require an oscillator start-up delay (EC). However, a the microcontroller, and therefore, can continue to
fixed delay of interval, TCSD, following the wake event, function in Deep Sleep.
is still required when leaving Sleep and Idle modes to Entering Deep Sleep mode clears the DSWAKEL
allow the CPU to prepare for execution. Instruction register. However, if the Real-Time Clock and Calendar
execution resumes on the first clock cycle following this (RTCC) is enabled prior to entering Deep Sleep, it will
delay. continue to operate uninterrupted.
The device has a dedicated Brown-out Reset (DSBOR)
4.6 Deep Sleep Mode and Watchdog Timer Reset (DSWDT) for monitoring
Deep Sleep mode brings the device into its lowest voltage and time-out events in Deep Sleep. The
power consumption state without requiring the use of DSBOR and DSWDT are independent of the standard
external switches to remove power from the device. BOR and WDT used with other power-managed modes
During Deep Sleep, the on-chip VDDCORE voltage reg- (Run, Idle and Sleep).
ulator is powered down, effectively disconnecting When a wake event occurs in Deep Sleep mode (by
power to the core logic of the microcontroller. MCLR Reset, RTCC alarm, INT0 interrupt, ULPWU or
Note: Since Deep Sleep mode powers down the DSWDT), the device will exit Deep Sleep mode and
microcontroller by turning off the on-chip perform a Power-on Reset (POR). When the device is
VDDCORE voltage regulator, Deep Sleep released from Reset, code execution will resume at the
capability is available only on PIC18FXXJ device’s Reset vector.
members in the device family. The on-chip
4.6.1 PREPARING FOR DEEP SLEEP
voltage regulator is not available in
PIC18LFXXJ members of the device Because VDDCORE could fall below the SRAM retention
family, and therefore, they do not support voltage while in Deep Sleep mode, SRAM data could
Deep Sleep. be lost in Deep Sleep. Exiting Deep Sleep mode
causes a POR; as a result, most Special Function
On devices that support it, the Deep Sleep mode is
Registers will reset to their default POR values.
entered by:
Applications needing to save a small amount of data
• Setting the REGSLP (WDTCON<7>) bit
throughout a Deep Sleep cycle can save the data to the
• Clearing the IDLEN bit general purpose DSGPR0 and DSGPR1 registers. The
• Clearing the GIE bit contents of these registers are preserved while the
• Setting the DSEN bit (DSCONH<7>) device is in Deep Sleep, and will remain valid throughout
• Executing the SLEEP instruction immediately after an entire Deep Sleep entry and wake-up sequence.
setting DSEN (no delay or interrupts in between)

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4.6.2 I/O PINS DURING DEEP SLEEP 4.6.3 DEEP SLEEP WAKE-UP SOURCES
During Deep Sleep, the general purpose I/O pins will The device can be awakened from Deep Sleep mode by
retain their previous states. a MCLR, POR, RTCC, INT0 I/O pin interrupt, DSWDT or
Pins that are configured as inputs (TRIS bit set) prior to ULPWU event. After waking, the device performs a
entry into Deep Sleep will remain high-impedance POR. When the device is released from Reset, code
during Deep Sleep. execution will begin at the device’s Reset vector.

Pins that are configured as outputs (TRIS bit clear) The software can determine if the wake-up was caused
prior to entry into Deep Sleep will remain as output pins from an exit from Deep Sleep mode by reading the DS
during Deep Sleep. While in this mode, they will drive bit (WDTCON<3>). If this bit is set, the POR was
the output level determined by their corresponding LAT caused by a Deep Sleep exit. The DS bit must be
bit at the time of entry into Deep Sleep. manually cleared by the software.

When the device wakes back up, the I/O pin behavior The software can determine the wake event source by
depends on the type of wake up source. reading the DSWAKEH and DSWAKEL registers.
When the application firmware is done using the
If the device wakes back up by an RTCC alarm, INT0 DSWAKEH and DSWAKEL status registers, individual
interrupt, DSWDT or ULPWU event, all I/O pins will bits do not need to be manually cleared before entering
continue to maintain their previous states, even after the Deep Sleep again. When entering Deep Sleep mode,
device has finished the POR sequence and is executing these registers are automatically cleared.
application code again. Pins configured as inputs during
Deep Sleep will remain high-impedance, and pins 4.6.3.1 Wake-up Event Considerations
configured as outputs will continue to drive their previous
Deep Sleep wake-up events are only monitored while
value.
the processor is fully in Deep Sleep mode. If a wake-up
After waking up, the TRIS and LAT registers will be event occurs before Deep Sleep mode is entered, the
reset, but the I/O pins will still maintain their previous event status will not be reflected in the DSWAKE
states. If firmware modifies the TRIS and LAT values registers. If the wake-up source asserts prior to entering
for the I/O pins, they will not immediately go to the Deep Sleep, the CPU will either go to the interrupt vector
newly configured states. Once the firmware clears the (if the wake source has an interrupt bit and the interrupt
RELEASE bit (DSCONL<0>), the I/O pins will be is fully enabled) or will abort the Deep Sleep entry
“released”. This causes the I/O pins to take the states sequence by executing past the SLEEP instruction if the
configured by their respective TRIS and LAT bit values. interrupt was not enabled. In this case, a wake-up event
If the Deep Sleep BOR (DSBOR) circuit is enabled, and handler should be placed after the SLEEP instruction to
VDD drops below the DSBOR and VDD rail POR thresh- process the event and re-attempt entry into Deep Sleep
olds, the I/O pins will be immediately released similar to if desired.
clearing the RELEASE bit. All previous state informa- When the device is in Deep Sleep with more than one
tion will be lost, including the general purpose DSGPR0 wake-up source simultaneously enabled, only the first
and DSGPR1 contents. See Section 4.6.5 “Deep wake-up source to assert will be detected and logged
Sleep Brown-Out Reset (DSBOR)” for additional in the DSWAKEH/DSWAKEL status registers.
details regarding this scenario
If a MCLR Reset event occurs during Deep Sleep, the 4.6.4 DEEP SLEEP WATCHDOG TIMER
I/O pins will also be released automatically, but in this (DSWDT)
case, the DSGPR0 and DSGPR1 contents will remain Deep Sleep has its own dedicated WDT (DSWDT) with
valid. a postscaler for time-outs of 2.1 ms to 25.7 days,
In all other Deep Sleep wake-up cases, application configurable through the bits, DSWDTPS<3:0>.
firmware needs to clear the RELEASE bit in order to The DSWDT can be clocked from either the INTRC or
reconfigure the I/O pins. the T1OSC/T1CKI input. If the T1OSC/T1CKI source
will be used with a crystal, the T1OSCEN bit in the
T1CON register needs to be set prior to entering Deep
Sleep. The reference clock source is configured through
the DSWDTOSC bit.
DSWDT is enabled through the DSWDTEN bit. Entering
Deep Sleep mode automatically clears the DSWDT. See
Section 28.0 “Special Features of the CPU” for more
information.

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4.6.5 DEEP SLEEP BROWN-OUT RESET 14. Clear the Deep Sleep bit, DS (WDTCON<3>).
(DSBOR) 15. Determine the wake-up source by reading the
The Deep Sleep module contains a dedicated Deep Sleep DSWAKEH and DSWAKEL registers.
BOR (DSBOR) circuit. This circuit may be optionally 16. Determine if a DSBOR event occurred during
enabled through the DSBOREN Configuration bit. Deep Sleep mode by reading the DSBOR bit
(DSCONL<1>).
The DSBOR circuit monitors the VDD supply rail
voltage. The behavior of the DSBOR circuit is 17. Read the DSGPR0 and DSGPR1 context save
described in Section 5.4 “Brown-out Reset (BOR)”. registers (optional).
18. Clear the RELEASE bit (DSCONL<0>).
4.6.6 RTCC PERIPHERAL AND DEEP Note 1: DSWDT and DSBOR are enabled
SLEEP through the devices’ Configuration bits.
The RTCC can operate uninterrupted during Deep For more information, see Section 28.1
Sleep mode. It can wake the device from Deep Sleep “Configuration Bits”.
by configuring an alarm. 2: The DSWDT and RTCC clock sources
The RTCC clock source is configured with the are selected through the devices’ Con-
RTCOSC bit (CONFIG3L<1>). The available reference figuration bits. For more information, see
clock sources are the INTRC and T1OSC/T1CKI. If the Section 28.1 “Configuration Bits”.
INTRC is used, the RTCC accuracy will directly depend 3: For more information, see Section 17.0
on the INTRC tolerance.For more information on “Real-Time Clock and Calendar
configuring the RTCC peripheral, see Section 17.0 (RTCC)”.
“Real-Time Clock and Calendar (RTCC)”. 4: For more information on configuring this
peripheral, see Section 4.7 “Ultra
4.6.7 TYPICAL DEEP SLEEP SEQUENCE Low-Power Wake-up”.
This section gives the typical sequence for using the Deep
Sleep mode. Optional steps are indicated and additional 4.6.8 DEEP SLEEP FAULT DETECTION
information is given in notes at the end of the procedure. If during Deep Sleep, the device is subjected to
1. Enable DSWDT (optional). (1) unusual operating conditions, such as an Electrostatic
Discharge (ESD) event, it is possible that internal cir-
2. Configure the DSWDT clock source (optional).(2)
cuit states used by the Deep Sleep module could
3. Enable DSBOR (optional).(1) become corrupted. If this were to happen, the device
4. Enable RTCC (optional).(3) may exhibit unexpected behavior, such as a failure to
5. Configure the RTCC peripheral (optional).(3) wake back up.
6. Configure the ULPWU peripheral (optional).(4) In order to prevent this type of scenario from occurring,
7. Enable the INT0 Interrupt (optional). the Deep Sleep module includes automatic
8. Context save SRAM data by writing to the self-monitoring capability. During Deep Sleep, critical
DSGPR0 and DSGPR1 registers (optional). internal nodes are continuously monitored in order to
9. Set the REGSLP bit (WDTCON<7>) and clear detect possible Fault conditions (which would not
the IDLEN bit (OSCCON<7>). ordinarily occur). If a Fault condition is detected, the
circuitry will set the DSFLT status bit (DSWAKEL<7>)
10. If using an RTCC alarm for wake-up, wait until
and automatically wake the microcontroller from Deep
the RTCSYNC bit (RTCCFG<4>) is clear.
Sleep, causing a POR Reset.
11. Enter Deep Sleep mode by setting the DSEN bit
(DSCONH<7>) and issuing a SLEEP instruction. During Deep Sleep, the Fault detection circuitry is
These two instructions must be executed back always enabled and does not require any specific
to back. configuration prior to entering Deep Sleep.
12. Once a wake-up event occurs, the device will
perform a POR Reset sequence. Code execution
resumes at the device’s Reset vector.
13. Determine if the device exited Deep Sleep by
reading the Deep Sleep bit, DS (WDTCON<3>).
This bit will be set if there was an exit from Deep
Sleep mode.

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4.6.9 DEEP SLEEP MODE REGISTERS
Deep Sleep mode registers are provided in
Register 4-1 through Register 4-6.

REGISTER 4-1: DSCONH: DEEP SLEEP CONTROL HIGH BYTE REGISTER (BANKED F4Dh)
R/W-0 U-0 U-0 U-0 U-0 r-0 R/W-0 R/W-0
(1)
DSEN — — — — r DSULPEN RTCWDIS
bit 7 bit 0

Legend: r = Reserved bit

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 DSEN: Deep Sleep Enable bit(1)

1 = Deep Sleep mode is entered on a SLEEP command
0 = Sleep mode is entered on a SLEEP command
bit 6-3 Unimplemented: Read as ‘0’
bit 2 (Reserved): Always write ‘0’ to this bit
bit 1 DSULPEN: Ultra Low-Power Wake-up Module Enable bit
1 = ULPWU module is enabled in Deep Sleep
0 = ULPWU module is disabled in Deep Sleep
bit 0 RTCWDIS: RTCC Wake-up Disable bit
1 = Wake-up from RTCC is disabled
0 = Wake-up from RTCC is enabled

Note 1: In order to enter Deep Sleep, Sleep must be executed immediately after setting DSEN.

REGISTER 4-2: DSCONL: DEEP SLEEP LOW BYTE CONTROL REGISTER (BANKED F4Ch)
U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0(1) R/W-0(1)
— — — — — ULPWDIS DSBOR RELEASE
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-3 Unimplemented: Read as ‘0’

bit 2 ULPWDIS: Ultra Low-Power Wake-up Disable bit
1 = ULPWU wake-up source is disabled
0 = ULPWU wake-up source is enabled (must also set DSULPEN = 1)
bit 1 DSBOR: Deep Sleep BOR Event Status bit
1 = DSBOREN was enabled and VDD dropped below the DSBOR arming voltage during Deep Sleep,
but did not fall below VDSBOR
0 = DSBOREN was disabled or VDD did not drop below the DSBOR arming voltage during Deep
Sleep
bit 0 RELEASE: I/O Pin State Release bit
Upon waking from Deep Sleep, the I/O pins maintain their previous states. Clearing this bit will
release the I/O pins and allow their respective TRIS and LAT bits to control their states.

Note 1: This is the value when VDD is initially applied.

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REGISTER 4-3: DSGPR0: DEEP SLEEP PERSISTENT GENERAL PURPOSE REGISTER 0
(BANKED F4Eh)
R/W-xxxx(1)
Deep Sleep Persistent General Purpose bits
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-0 Deep Sleep Persistent General Purpose bits

Contents are retained even in Deep Sleep mode.

Note 1: All register bits are maintained unless: VDDCORE drops below the normal BOR threshold outside of Deep
Sleep or the device is in Deep Sleep and the dedicated DSBOR is enabled and VDD drops below the
DSBOR threshold, or DSBOR is enabled or disabled, but VDD is hard cycled to near VSS.

REGISTER 4-4: DSGPR1: DEEP SLEEP PERSISTENT GENERAL PURPOSE REGISTER 1

(BANKED F4Fh)
R/W-xxxx(1)
Deep Sleep Persistent General Purpose bits
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-0 Deep Sleep Persistent General Purpose bits

Contents are retained even in Deep Sleep mode.

Note 1: All register bits are maintained unless: VDDCORE drops below the normal BOR threshold outside of Deep
Sleep or the device is in Deep Sleep and the dedicated DSBOR is enabled and VDD drops below the
DSBOR threshold, or DSBOR is enabled or disabled, but VDD is hard cycled to near VSS.

REGISTER 4-5: DSWAKEH: DEEP SLEEP WAKE HIGH BYTE REGISTER (BANKED F4Bh)
U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0
— — — — — — — DSINT0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-1 Unimplemented: Read as ‘0’

bit 0 DSINT0: Interrupt-on-Change bit
1 = Interrupt-on-change was asserted during Deep Sleep
0 = Interrupt-on-change was not asserted during Deep Sleep

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REGISTER 4-6: DSWAKEL: DEEP SLEEP WAKE LOW BYTE REGISTER (BANKED F4Ah)
R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-1
DSFLT — DSULP DSWDT DSRTC DSMCLR — DSPOR
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 DSFLT: Deep Sleep Fault Detected bit

1 = A Deep Sleep Fault was detected during Deep Sleep
0 = A Deep Sleep Fault was not detected during Deep Sleep
bit 6 Unimplemented: Read as ‘0’
bit 5 DSULP: Ultra Low-Power Wake-up Status bit
1 = An ultra low-power wake-up event occurred during Deep Sleep
0 = An ultra low-power wake-up event did not occur during Deep Sleep
bit 4 DSWDT: Deep Sleep Watchdog Timer Time-out bit
1 = The Deep Sleep Watchdog Timer timed out during Deep Sleep
0 = The Deep Sleep Watchdog Timer did not time out during Deep Sleep
bit 3 DSRTC: Real-Time Clock and Calendar Alarm bit
1 = The Real-Time Clock/Calendar triggered an alarm during Deep Sleep
0 = The Real-Time Clock /Calendar did not trigger an alarm during Deep Sleep
bit 2 DSMCLR: MCLR Event bit
1 = The MCLR pin was asserted during Deep Sleep
0 = The MCLR pin was not asserted during Deep Sleep
bit 1 Unimplemented: Read as ‘0’
bit 0 DSPOR: Power-on Reset Event bit
1 = The VDD supply POR circuit was active and a POR event was detected(1)
0 = The VDD supply POR circuit was not active, or was active, but did not detect a POR event

Note 1: Unlike the other bits in this register, this bit can be set outside of Deep Sleep.

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4.7 Ultra Low-Power Wake-up When the voltage on RA0 drops below VIL, an interrupt
will be generated, which will cause the device to
The Ultra Low-Power Wake-up (ULPWU) on RA0 allows wake-up and execute the next instruction.
a slow falling voltage to generate an interrupt-on-change
without excess current consumption. This feature provides a low-power technique for
periodically waking up the device from Sleep mode.
Follow these steps to use this feature: The time-out is dependent on the discharge time of the
1. Configure a remappable output pin to output the RC circuit on RA0.
ULPOUT signal. When the ULPWU module causes the device to
2. Map an INTx interrupt-on-change input function to wake-up from Sleep mode, the ULPLVL (WDTCON<5>)
the same pin as used for the ULPOUT output func- bit is set. When the ULPWU module causes the device
tion. Alternatively, in step 1, configure ULPOUT to to wake-up from Deep Sleep, the DSULP
output onto a PORTB interrupt-on-change pin. (DSWAKEL<5>) bit is set. Software can check these bits
3. Charge the capacitor on RA0 by configuring the upon wake-up to determine the wake-up source. Also in
RA0 pin to an output and setting it to ‘1’. Sleep mode, only the remappable output function,
4. Enable interrupt-on-change (PIE bit) for the ULPWU, will output this bit value to an RPn pin for
corresponding pin selected in step 2. externally detecting wake-up events.
5. Stop charging the capacitor by configuring RA0 See Example 4-1 for initializing the ULPWU module.
as an input.
Note: For module related bit definitions, see the
6. Discharge the capacitor by setting the ULPEN WDTCON register in Section 28.2
and ULPSINK bits in the WDTCON register. “Watchdog Timer (WDT)” and the
7. Configure Sleep mode. DSWAKEL register (Register 4-6).
8. Enter Sleep mode.

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EXAMPLE 4-1: ULTRA LOW-POWER WAKE-UP INITIALIZATION
//*********************************************************************************
//Configure a remappable output pin with interrupt capability
//for ULPWU function (RP21 => RD4/INT1 in this example)
//*********************************************************************************
RPOR21 = 13;// ULPWU function mapped to RP21/RD4
RPINR1 = 21;// INT1 mapped to RP21 (RD4)

//***************************
//Charge the capacitor on RA0
//***************************
TRISAbits.TRISA0 = 0;
PORTAbits.RA0 = 1;
for(i = 0; i < 10000; i++) Nop();

//**********************************
//Stop Charging the capacitor on RA0
//**********************************
TRISAbits.TRISA0 = 1;

//*****************************************
//Enable the Ultra Low Power Wakeup module
//and allow capacitor discharge
//*****************************************
WDTCONbits.ULPEN = 1;
WDTCONbits.ULPSINK = 1;

//******************************************
//Enable Interrupt for ULPW
//******************************************
//For Sleep
//(assign the ULPOUT signal in the PPS module to a pin
//which has also been assigned an interrupt capability,
//such as INT1)
INTCON3bits.INT1IF = 0;
INTCON3bits.INT1IE = 1;

//********************
//Configure Sleep Mode
//********************
//For Sleep
OSCCONbits.IDLEN = 0;

//For Deep Sleep

OSCCONbits.IDLEN = 0; // enable deep sleep
DSCONHbits.DSEN = 1; // Note: must be set just before executing Sleep();
//****************
//Enter Sleep Mode
//****************
Sleep();
// for sleep, execution will resume here
// for deep sleep, execution will restart at reset vector (use WDTCONbits.DS to detect)

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A series resistor between RA0 and the external 4.8 Peripheral Module Disable
capacitor provides overcurrent protection for the
RA0/AN0/C1INA/ULPWU/RP0 pin and can allow for All peripheral modules (except for I/O ports) also have
software calibration of the time-out (see Figure 4-9). a second control bit that can disable their functionality.
These bits, known as the Peripheral Module Disable
(PMDISx) bits, are generically named “xxxMD” (using
FIGURE 4-9: SERIAL RESISTOR
“xxx” as the mnemonic version of the module’s name).
R1 These bits are located in the PMDISx special function
RA0 registers. In contrast to the module enable bits (gener-
ically named “xxxEN” and located in bit position seven
of the control registers), the PMDISx bits must be set
C1
(= 1) to disable the modules.
While the PMD and module enable bits both disable a
peripheral’s functionality, the PMD bit completely shuts
down the peripheral, effectively powering down all
circuits and removing all clock sources. This has the
A timer can be used to measure the charge time and additional effect of making any of the module’s control
discharge time of the capacitor. The charge time can and buffer registers, mapped in the SFR space,
then be adjusted to provide the desired interrupt delay. unavailable for operations. Essentially, the peripheral
This technique will compensate for the affects of ceases to exist until the PMD bit is cleared.
temperature, voltage and component accuracy. The
ULPWU peripheral can also be configured as a simple This differs from using the module enable bit, which
Programmable Low-Voltage Detect (LVD) or allows the peripheral to be reconfigured and buffer reg-
temperature sensor. isters preloaded, even when the peripheral’s
operations are disabled.
Note: For more information, refer to AN879,
The PMDISx bits are most useful in highly
“Using the Microchip Ultra Low-Power
power-sensitive applications. In these cases, the bits
Wake-up Module” application note
can be set before the main body of the application to
(DS00879).
remove peripherals that will not be needed at all.

TABLE 4-2: LOW-POWER MODE REGISTERS

Value on
Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
POR, BOR

PMDIS3 CCP10MD CCP9MD CCP8MD CCP7MD CCP6MD CCP5MD CCP4MD — 0000 000–
PMDIS2 — TMR8MD — TMR6MD TMR5MD CMP3MD CMP2MD CMP1MD –0–0 0000
PMDIS1 PSPMD(1) CTMUMD RTCCMD TMR4MD TMR3MD TMR2MD TMR1MD — 0000 000–
PMDIS0 ECCP3MD ECCP2MD ECCP1MD UART2MD UART1MD SPI2MD SPI1MD ADCMD 0000 0000
Note 1: Not implemented on 28-pin devices (PIC18F26J53, PIC18F27J53, PIC18LF26J53 and PIC18LF27J53).

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NOTES:

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5.0 RESET For information on WDT Resets, see Section 28.2
“Watchdog Timer (WDT)”. For Stack Reset events,
The PIC18F47J53 family of devices differentiates
see Section 6.1.4.4 “Stack Full and Underflow
among various kinds of Reset:
Resets” and for Deep Sleep mode, see Section 4.6
a) Power-on Reset (POR) “Deep Sleep Mode”.
b) MCLR Reset during normal operation Figure 5-1 provides a simplified block diagram of the
c) MCLR Reset during power-managed modes on-chip Reset circuit.
d) Watchdog Timer (WDT) Reset (during
execution) 5.1 RCON Register
e) Configuration Mismatch (CM)
Device Reset events are tracked through the RCON
f) Brown-out Reset (BOR) register (Register 5-1). The lower five bits of the register
g) RESET Instruction indicate that a specific Reset event has occurred. In
h) Stack Full Reset most cases, these bits can only be set by the event and
i) Stack Underflow Reset must be cleared by the application after the event. The
j) Deep Sleep Reset state of these flag bits, taken together, can be read to
indicate the type of Reset that just occurred. This is
This section discusses Resets generated by MCLR, described in more detail in Section 5.7 “Reset State of
POR and BOR, and covers the operation of the various Registers”.
start-up timers.
The RCON register also has a control bit for setting
interrupt priority (IPEN). Interrupt priority is discussed
in Section 9.0 “Interrupts”.

FIGURE 5-1: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT

RESET Instruction

Configuration Word Mismatch

Stack Stack Full/Underflow Reset

Pointer

External Reset

MCLR ( )_IDLE
Deep Sleep Reset
Sleep

WDT
Time-out

VDD Rise POR Pulse

Detect
VDD
Brown-out
Reset(1) S
Brown-out
Reset(2)

VDDCORE PWRT

32 ms PWRT 66 ms Chip_Reset
R Q
INTRC
11-Bit Ripple Counter

Note 1: The VDD monitoring BOR circuit can be enabled or disabled on “LF” devices based on the CONFIG3L<DSBOREN>
Configuration bit. On “F” devices, the VDD monitoring BOR circuit is only enabled during Deep Sleep mode by
CONFIG3L<DSBOREN>.
2: The VDDCORE monitoring BOR circuit is only implemented on “F” devices. It is always used, except while in Deep
Sleep mode. The VDDCORE monitoring BOR circuit has a trip point threshold of VBOR (parameter D005).

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REGISTER 5-1: RCON: RESET CONTROL REGISTER (ACCESS FD0h)
R/W-0 U-0 R/W-1 R/W-1 R-1 R-1 R/W-0 R/W-0
IPEN — CM RI TO PD POR BOR
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 IPEN: Interrupt Priority Enable bit

1 = Enable priority levels on interrupts
0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode)
bit 6 Unimplemented: Read as ‘0’
bit 5 CM: Configuration Mismatch Flag bit
1 = A Configuration Mismatch Reset has not occurred
0 = A Configuration Mismatch Reset has occurred (must be set in software after a Configuration
Mismatch Reset occurs)
bit 4 RI: RESET Instruction Flag bit
1 = The RESET instruction was not executed (set by firmware only)
0 = The RESET instruction was executed causing a device Reset (must be set in software after a
Brown-out Reset occurs)
bit 3 TO: Watchdog Time-out Flag bit
1 = Set by power-up, CLRWDT instruction or SLEEP instruction
0 = A WDT time-out occurred
bit 2 PD: Power-Down Detection Flag bit
1 = Set by power-up or by the CLRWDT instruction
0 = Set by execution of the SLEEP instruction
bit 1 POR: Power-on Reset Status bit
1 = A Power-on Reset has not occurred (set by firmware only)
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
bit 0 BOR: Brown-out Reset Status bit
1 = A Brown-out Reset has not occurred (set by firmware only)
0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)

Note 1: It is recommended that the POR bit be set after a Power-on Reset has been detected, so that subsequent
Power-on Resets may be detected.
2: If the on-chip voltage regulator is disabled, BOR remains ‘0’ at all times. See Section 5.4.1 “Detecting
BOR” for more information.
3: Brown-out Reset is said to have occurred when BOR is ‘0’ and POR is ‘1’ (assuming that POR was set to
‘1’ by software immediately after a Power-on Reset).

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5.2 Master Clear (MCLR) Deep Sleep. Once the VDD voltage recovers back
above the VDSBOR threshold, and once the core
The Master Clear Reset (MCLR) pin provides a method voltage regulator achieves a VDDCORE voltage above
for triggering a hard external Reset of the device. A VBOR, the device will begin executing code again
Reset is generated by holding the pin low. PIC18 normally, but the DS bit in the WDTCON register will
extended microcontroller devices have a noise filter in not be set. The device behavior will be similar to hard
the MCLR Reset path, which detects and ignores small cycling all power to the device.
pulses.
On “LF” devices (ex: PIC18LF47J53), the VDDCORE
The MCLR pin is not driven low by any internal Resets, BOR circuit is always disabled because the internal
including the WDT. core voltage regulator is disabled. Instead of monitor-
ing VDDCORE, PIC18LF devices in this family can still
5.3 Power-on Reset (POR) use the VDD BOR circuit to monitor VDD excursions
below the VDSBOR threshold. The VDD BOR circuit can
A POR condition is generated on-chip whenever VDD
be disabled by setting the DSBOREN bit = 0.
rises above a certain threshold. This allows the device
to start in the initialized state when VDD is adequate for The VDD BOR circuit is enabled when DSBOREN = 1
operation. on “LF” devices, or on “F” devices while in Deep Sleep
with DSBOREN = 1. When enabled, the VDD BOR cir-
To take advantage of the POR circuitry, tie the MCLR
cuit is extremely low power (typ. 200nA) during normal
pin through a resistor (1 k to 10 k) to VDD. This will
operation above ~2.3V on VDD. If VDD drops below this
eliminate external RC components usually needed to
DSBOR arming level when the VDD BOR circuit is
create a POR delay.
enabled, the device may begin to consume additional
When the device starts normal operation (i.e., exits the current (typ. 50 A) as internal features of the circuit
Reset condition), device operating parameters power-up. The higher current is necessary to achieve
(voltage, frequency, temperature, etc.) must be met to more accurate sensing of the VDD level. However, the
ensure operation. If these conditions are not met, the device will not enter Reset until VDD falls below the
device must be held in Reset until the operating VDSBOR threshold.
conditions are met.
POR events are captured by the POR bit (RCON<1>). 5.4.1 DETECTING BOR
The state of the bit is set to ‘0’ whenever a Power-on The BOR bit always resets to ‘0’ on any VDDCORE
Reset occurs; it does not change for any other Reset Brown-out Reset or Power-on Reset event. This makes
event. POR is not reset to ‘1’ by any hardware event. it difficult to determine if a Brown-out Reset event has
To capture multiple events, the user manually resets occurred just by reading the state of BOR alone. A
the bit to ‘1’ in software following any POR. more reliable method is to simultaneously check the
state of both POR and BOR. This assumes that the
5.4 Brown-out Reset (BOR) POR bit is reset to ‘1’ in software immediately after any
Power-on Reset event. If BOR is ‘0’ while POR is ‘1’, it
The “F” devices in the PIC18F47J53 family incorporate can be reliably assumed that a Brown-out Reset event
two types of BOR circuits: one which monitors has occurred.
VDDCORE and one which monitors VDD. Only one BOR
If the voltage regulator is disabled (LF device), the
circuit can be active at a time. When in normal Run
VDDCORE BOR functionality is disabled. In this case,
mode, Idle or normal Sleep modes, the BOR circuit that
the BOR bit cannot be used to determine a Brown-out
monitors VDDCORE is active and will cause the device
Reset event. The BOR bit is still cleared by a Power-on
to be held in BOR if VDDCORE drops below VBOR
Reset event.
(parameter D005). Once VDDCORE rises back above
VBOR, the device will be held in Reset until the
expiration of the Power-up Timer, with period, TPWRT
(parameter 33).
During Deep Sleep operation, the on-chip core voltage
regulator is disabled and VDDCORE is allowed to drop to
VSS. If the Deep Sleep BOR circuit is enabled by the
DSBOREN bit (CONFIG3L<2> = 1), it will monitor VDD.
If VDD drops below the VDSBOR threshold, the device
will be held in a Reset state similar to POR. All registers
will be set back to their POR Reset values and the con-
tents of the DSGPR0 and DSGPR1 holding registers
will be lost. Additionally, if any I/O pins had been
configured as outputs during Deep Sleep, these pins
will be tri-stated and the device will no longer be held in

 2010 Microchip Technology Inc. Preliminary DS39964B-page 67

PIC18F47J53 FAMILY
5.5 Configuration Mismatch (CM) 5.6 Power-up Timer (PWRT)
The Configuration Mismatch (CM) Reset is designed to PIC18F47J53 family devices incorporate an on-chip
detect, and attempt to recover from, random memory PWRT to help regulate the POR process. The PWRT is
corrupting events. These include Electrostatic always enabled. The main function is to ensure that the
Discharge (ESD) events, which can cause widespread device voltage is stable before code is executed.
single bit changes throughout the device and result in The Power-up Timer (PWRT) of the PIC18F47J53 family
catastrophic failure. devices is a 5-bit counter which uses the INTRC source
In PIC18FXXJ Flash devices, the device Configuration as the clock input. This yields an approximate time
registers (located in the configuration memory space) interval of 32 x 32 s = 1 ms. While the PWRT is
are continuously monitored during operation by com- counting, the device is held in Reset.
paring their values to complimentary shadow registers. The power-up time delay depends on the INTRC clock
If a mismatch is detected between the two sets of and will vary from chip-to-chip due to temperature and
registers, a CM Reset automatically occurs. These process variation. See DC parameter 33 (TPWRT) for
events are captured by the CM bit (RCON<5>). The details.
state of the bit is set to ‘0’ whenever a CM event occurs;
it does not change for any other Reset event. 5.6.1 TIME-OUT SEQUENCE
A CM Reset behaves similarly to a MCLR, RESET The PWRT time-out is invoked after the POR pulse has
instruction, WDT time-out or Stack Event Resets. As cleared. The total time-out will vary based on the status
with all hard and power Reset events, the device of the PWRT. Figure 5-2, Figure 5-3, Figure 5-4 and
Configuration Words are reloaded from the Flash Figure 5-5 all depict time-out sequences on power-up
Configuration Words in program memory as the device with the PWRT.
restarts.
Since the time-outs occur from the POR pulse, if MCLR
is kept low long enough, the PWRT will expire. Bringing
MCLR high will begin execution immediately if a clock
source is available (Figure 5-4). This is useful for
testing purposes or to synchronize more than one
PIC18F device operating in parallel.

FIGURE 5-2: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD, VDD RISE < TPWRT)

VDD

MCLR

INTERNAL POR

TPWRT

PWRT TIME-OUT

INTERNAL RESET

DS39964B-page 68 Preliminary  2010 Microchip Technology Inc.

 PIC18F47J53 FAMILY
FIGURE 5-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1

VDD

MCLR

INTERNAL POR
TPWRT

PWRT TIME-OUT

INTERNAL RESET

FIGURE 5-4: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2

VDD

MCLR

INTERNAL POR
TPWRT

PWRT TIME-OUT

INTERNAL RESET

FIGURE 5-5: SLOW RISE TIME (MCLR TIED TO VDD, VDD RISE > TPWRT)

3.3V
VDD 0V 1V

MCLR

INTERNAL POR

TPWRT
PWRT TIME-OUT

INTERNAL RESET

 2010 Microchip Technology Inc. Preliminary DS39964B-page 69

PIC18F47J53 FAMILY
5.7 Reset State of Registers TO, PD, POR and BOR) are set or cleared differently in
different Reset situations, as indicated in Table 5-1.
Most registers are unaffected by a Reset. Their status These bits are used in software to determine the nature
is unknown on POR and unchanged by all other of the Reset.
Resets. The other registers are forced to a “Reset
state” depending on the type of Reset that occurred. Table 5-2 describes the Reset states for all of the
Special Function Registers. These are categorized by
Most registers are not affected by a WDT wake-up, POR and BOR, MCLR and WDT Resets and WDT
since this is viewed as the resumption of normal wake-ups.
operation. Status bits from the RCON register (CM, RI,

TABLE 5-1: STATUS BITS, THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION FOR
RCON REGISTER

Program RCON Register STKPTR Register

Condition
Counter(1)
CM RI TO PD POR BOR STKFUL STKUNF
Power-on Reset 0000h 1 1 1 1 0 0 0 0
RESET instruction 0000h u 0 u u u u u u
Brown-out Reset 0000h 1 1 1 1 u 0 u u
Configuration Mismatch Reset 0000h 0 u u u u u u u
MCLR Reset during 0000h u u 1 u u u u u
power-managed Run modes
MCLR Reset during 0000h u u 1 0 u u u u
power-managed Idle modes and
Sleep mode
MCLR Reset during full-power 0000h u u u u u u u u
execution
Stack Full Reset (STVREN = 1) 0000h u u u u u u 1 u
Stack Underflow Reset 0000h u u u u u u u 1
(STVREN = 1)
Stack Underflow Error (not an 0000h u u u u u u u 1
actual Reset, STVREN = 0)
WDT time-out during full-power 0000h u u 0 u u u u u
or power-managed Run modes
WDT time-out during PC + 2 u u 0 0 u u u u
power-managed Idle or Sleep
modes
Interrupt exit from PC + 2 u u u 0 u u u u
power-managed modes
Legend: u = unchanged
Note 1: When the wake-up is due to an interrupt and the GIEH or GIEL bit is set, the PC is loaded with the
interrupt vector (0008h or 0018h).

DS39964B-page 70 Preliminary  2010 Microchip Technology Inc.

 PIC18F47J53 FAMILY

TABLE 5-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS

MCLR Resets
Power-on Reset,
WDT Reset
Brown-out Reset, Wake-up via WDT
Register Applicable Devices RESET Instruction
Wake From Deep or Interrupt
Stack Resets
Sleep
CM Resets
TOSU PIC18F2XJ53 PIC18F4XJ53 ---0 0000 ---0 0000 ---u uuuu(1)
TOSH PIC18F2XJ53 PIC18F4XJ53 0000 0000 0000 0000 uuuu uuuu(1)
TOSL PIC18F2XJ53 PIC18F4XJ53 0000 0000 0000 0000 uuuu uuuu(1)
STKPTR PIC18F2XJ53 PIC18F4XJ53 00-0 0000 uu-0 0000 uu-u uuuu(1)
PCLATU PIC18F2XJ53 PIC18F4XJ53 ---0 0000 ---0 0000 ---u uuuu
PCLATH PIC18F2XJ53 PIC18F4XJ53 0000 0000 0000 0000 uuuu uuuu
PCL PIC18F2XJ53 PIC18F4XJ53 0000 0000 0000 0000 PC + 2(2)
TBLPTRU PIC18F2XJ53 PIC18F4XJ53 --00 0000 --00 0000 --uu uuuu
TBLPTRH PIC18F2XJ53 PIC18F4XJ53 0000 0000 0000 0000 uuuu uuuu
TBLPTRL PIC18F2XJ53 PIC18F4XJ53 0000 0000 0000 0000 uuuu uuuu
TABLAT PIC18F2XJ53 PIC18F4XJ53 0000 0000 0000 0000 uuuu uuuu
PRODH PIC18F2XJ53 PIC18F4XJ53 xxxx xxxx uuuu uuuu uuuu uuuu
PRODL PIC18F2XJ53 PIC18F4XJ53 xxxx xxxx uuuu uuuu uuuu uuuu
INTCON PIC18F2XJ53 PIC18F4XJ53 0000 000x 0000 000u uuuu uuuu(3)
INTCON2 PIC18F2XJ53 PIC18F4XJ53 1111 1111 1111 1111 uuuu uuuu(3)
INTCON3 PIC18F2XJ53 PIC18F4XJ53 1100 0000 1100 0000 uuuu uuuu(3)
INDF0 PIC18F2XJ53 PIC18F4XJ53 N/A N/A N/A
POSTINC0 PIC18F2XJ53 PIC18F4XJ53 N/A N/A N/A
POSTDEC0 PIC18F2XJ53 PIC18F4XJ53 N/A N/A N/A
PREINC0 PIC18F2XJ53 PIC18F4XJ53 N/A N/A N/A
PLUSW0 PIC18F2XJ53 PIC18F4XJ53 N/A N/A N/A
FSR0H PIC18F2XJ53 PIC18F4XJ53 ---- 0000 ---- 0000 ---- uuuu
FSR0L PIC18F2XJ53 PIC18F4XJ53 xxxx xxxx uuuu uuuu uuuu uuuu
WREG PIC18F2XJ53 PIC18F4XJ53 xxxx xxxx uuuu uuuu uuuu uuuu
INDF1 PIC18F2XJ53 PIC18F4XJ53 N/A N/A N/A
POSTINC1 PIC18F2XJ53 PIC18F4XJ53 N/A N/A N/A
POSTDEC1 PIC18F2XJ53 PIC18F4XJ53 N/A N/A N/A
PREINC1 PIC18F2XJ53 PIC18F4XJ53 N/A N/A N/A
PLUSW1 PIC18F2XJ53 PIC18F4XJ53 N/A N/A N/A
FSR1H PIC18F2XJ53 PIC18F4XJ53 ---- 0000 ---- 0000 ---- uuuu
FSR1L PIC18F2XJ53 PIC18F4XJ53 xxxx xxxx uuuu uuuu uuuu uuuu
BSR PIC18F2XJ53 PIC18F4XJ53 ---- 0000 ---- 0000 ---- uuuu
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
4: See Table 5-1 for Reset value for specific condition.
5: Not implemented for PIC18F2XJ53 devices.
6: Not implemented for “LF” devices.

 2010 Microchip Technology Inc. Preliminary DS39964B-page 71

PIC18F47J53 FAMILY
TABLE 5-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
MCLR Resets
Power-on Reset,
WDT Reset
Brown-out Reset, Wake-up via WDT
Register Applicable Devices RESET Instruction
Wake From Deep or Interrupt
Stack Resets
Sleep
CM Resets
INDF2 PIC18F2XJ53 PIC18F4XJ53 N/A N/A N/A
POSTINC2 PIC18F2XJ53 PIC18F4XJ53 N/A N/A N/A
POSTDEC2 PIC18F2XJ53 PIC18F4XJ53 N/A N/A N/A
PREINC2 PIC18F2XJ53 PIC18F4XJ53 N/A N/A N/A
PLUSW2 PIC18F2XJ53 PIC18F4XJ53 N/A N/A N/A
FSR2H PIC18F2XJ53 PIC18F4XJ53 ---- 0000 ---- 0000 ---- uuuu
FSR2L PIC18F2XJ53 PIC18F4XJ53 xxxx xxxx uuuu uuuu uuuu uuuu
STATUS PIC18F2XJ53 PIC18F4XJ53 ---x xxxx ---u uuuu ---u uuuu
TMR0H PIC18F2XJ53 PIC18F4XJ53 0000 0000 0000 0000 uuuu uuuu
TMR0L PIC18F2XJ53 PIC18F4XJ53 xxxx xxxx uuuu uuuu uuuu uuuu
T0CON PIC18F2XJ53 PIC18F4XJ53 1111 1111 1111 1111 uuuu uuuu
OSCCON PIC18F2XJ53 PIC18F4XJ53 0110 qq00 0110 qq00 0110 qq0u
CM1CON PIC18F2XJ53 PIC18F4XJ53 0001 1111 uuuu uuuu uuuu uuuu
CM2CON PIC18F2XJ53 PIC18F4XJ53 0001 1111 uuuu uuuu uuuu uuuu
RCON(4) PIC18F2XJ53 PIC18F4XJ53 0-11 11qq 0-qq qquu u-qq qquu
TMR1H PIC18F2XJ53 PIC18F4XJ53 xxxx xxxx uuuu uuuu uuuu uuuu
TMR1L PIC18F2XJ53 PIC18F4XJ53 xxxx xxxx uuuu uuuu uuuu uuuu
T1CON PIC18F2XJ53 PIC18F4XJ53 0000 0000 u0uu uuuu uuuu uuuu
TMR2 PIC18F2XJ53 PIC18F4XJ53 0000 0000 0000 0000 uuuu uuuu
PR2 PIC18F2XJ53 PIC18F4XJ53 1111 1111 1111 1111 uuuu uuuu
T2CON PIC18F2XJ53 PIC18F4XJ53 -000 0000 -000 0000 -uuu uuuu
SSP1BUF PIC18F2XJ53 PIC18F4XJ53 xxxx xxxx uuuu uuuu uuuu uuuu
SSP1ADD PIC18F2XJ53 PIC18F4XJ53 0000 0000 0000 0000 uuuu uuuu
SSP1MSK PIC18F2XJ53 PIC18F4XJ53 ---- ---- uuuu uuuu uuuu uuuu
SSP1STAT PIC18F2XJ53 PIC18F4XJ53 0000 0000 0000 0000 uuuu uuuu
SSP1CON1 PIC18F2XJ53 PIC18F4XJ53 0000 0000 0000 0000 uuuu uuuu
SSP1CON2 PIC18F2XJ53 PIC18F4XJ53 0000 0000 0000 0000 uuuu uuuu
ADRESH PIC18F2XJ53 PIC18F4XJ53 xxxx xxxx uuuu uuuu uuuu uuuu
ADRESL PIC18F2XJ53 PIC18F4XJ53 xxxx xxxx uuuu uuuu uuuu uuuu
ADCON0 PIC18F2XJ53 PIC18F4XJ53 0000 0000 0000 0000 uuuu uuuu
ADCON1 PIC18F2XJ53 PIC18F4XJ53 0000 0000 0000 0000 uuuu uuuu
WDTCON PIC18F2XJ53 PIC18F4XJ53 1qq0 0000 0qq0 0000 uqqu uuuu
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
4: See Table 5-1 for Reset value for specific condition.
5: Not implemented for PIC18F2XJ53 devices.
6: Not implemented for “LF” devices.

DS39964B-page 72 Preliminary  2010 Microchip Technology Inc.

 PIC18F47J53 FAMILY
TABLE 5-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
MCLR Resets
Power-on Reset,
WDT Reset
Brown-out Reset, Wake-up via WDT
Register Applicable Devices RESET Instruction
Wake From Deep or Interrupt
Stack Resets
Sleep
CM Resets
PSTR1CON PIC18F2XJ53 PIC18F4XJ53 00-0 0001 00-0 0001 uu-u uuuu
ECCP1AS PIC18F2XJ53 PIC18F4XJ53 0000 0000 0000 0000 uuuu uuuu
ECCP1DEL PIC18F2XJ53 PIC18F4XJ53 0000 0000 0000 0000 uuuu uuuu
CCPR1H PIC18F2XJ53 PIC18F4XJ53 xxxx xxxx uuuu uuuu uuuu uuuu
CCPR1L PIC18F2XJ53 PIC18F4XJ53 xxxx xxxx uuuu uuuu uuuu uuuu
CCP1CON PIC18F2XJ53 PIC18F4XJ53 0000 0000 0000 0000 uuuu uuuu
PSTR2CON PIC18F2XJ53 PIC18F4XJ53 00-0 0001 00-0 0001 uu-u uuuu
ECCP2AS PIC18F2XJ53 PIC18F4XJ53 0000 0000 0000 0000 uuuu uuuu
ECCP2DEL PIC18F2XJ53 PIC18F4XJ53 0000 0000 0000 0000 uuuu uuuu
CCPR2H PIC18F2XJ53 PIC18F4XJ53 xxxx xxxx uuuu uuuu uuuu uuuu
CCPR2L PIC18F2XJ53 PIC18F4XJ53 xxxx xxxx uuuu uuuu uuuu uuuu
CCP2CON PIC18F2XJ53 PIC18F4XJ53 0000 0000 0000 0000 uuuu uuuu
CTMUCONH PIC18F2XJ53 PIC18F4XJ53 0-00 000- 0-00 000- u-uu uuu-
CTMUCONL PIC18F2XJ53 PIC18F4XJ53 0000 00xx 0000 00xx uuuu uuuu
CTMUICON PIC18F2XJ53 PIC18F4XJ53 0000 0000 0000 0000 uuuu uuuu
SPBRG1 PIC18F2XJ53 PIC18F4XJ53 0000 0000 0000 0000 uuuu uuuu
RCREG1 PIC18F2XJ53 PIC18F4XJ53 0000 0000 0000 0000 uuuu uuuu
TXREG1 PIC18F2XJ53 PIC18F4XJ53 xxxx xxxx uuuu uuuu uuuu uuuu
TXSTA1 PIC18F2XJ53 PIC18F4XJ53 0000 0010 0000 0010 uuuu uuuu
RCSTA1 PIC18F2XJ53 PIC18F4XJ53 0000 000x 0000 000x uuuu uuuu
SPBRG2 PIC18F2XJ53 PIC18F4XJ53 0000 0000 0000 0000 uuuu uuuu
RCREG2 PIC18F2XJ53 PIC18F4XJ53 0000 0000 0000 0000 uuuu uuuu
TXREG2 PIC18F2XJ53 PIC18F4XJ53 0000 0000 0000 0000 uuuu uuuu
TXSTA2 PIC18F2XJ53 PIC18F4XJ53 0000 0010 0000 0010 uuuu uuuu
EECON2 PIC18F2XJ53 PIC18F4XJ53 ---- ---- ---- ---- ---- ----
EECON1 PIC18F2XJ53 PIC18F4XJ53 --00 x00- --00 u00- --00 u00-
IPR3 PIC18F2XJ53 PIC18F4XJ53 1111 1111 1111 1111 uuuu uuuu
PIR3 PIC18F2XJ53 PIC18F4XJ53 0000 0000 0000 0000 uuuu uuuu(3)
PIE3 PIC18F2XJ53 PIC18F4XJ53 0000 0000 0000 0000 uuuu uuuu
IPR2 PIC18F2XJ53 PIC18F4XJ53 1111 1111 1111 1111 uuuu uuuu
PIR2 PIC18F2XJ53 PIC18F4XJ53 0000 0000 0000 0000 uuuu uuuu(3)
PIE2 PIC18F2XJ53 PIC18F4XJ53 0000 0000 0000 0000 uuuu uuuu
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
4: See Table 5-1 for Reset value for specific condition.
5: Not implemented for PIC18F2XJ53 devices.
6: Not implemented for “LF” devices.

 2010 Microchip Technology Inc. Preliminary DS39964B-page 73

PIC18F47J53 FAMILY
TABLE 5-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
MCLR Resets
Power-on Reset,
WDT Reset
Brown-out Reset, Wake-up via WDT
Register Applicable Devices RESET Instruction
Wake From Deep or Interrupt
Stack Resets
Sleep
CM Resets
IPR1 PIC18F2XJ53 PIC18F4XJ53 1111 1111 1111 1111 uuuu uuuu
PIR1 PIC18F2XJ53 PIC18F4XJ53 0000 0000 0000 0000 uuuu uuuu(3)
PIE1 PIC18F2XJ53 PIC18F4XJ53 0000 0000 0000 0000 uuuu uuuu
RCSTA2 PIC18F2XJ53 PIC18F4XJ53 0000 000x 0000 000x uuuu uuuu
OSCTUNE PIC18F2XJ53 PIC18F4XJ53 0000 0000 0000 0000 uuuu uuuu
T1GCON PIC18F2XJ53 PIC18F4XJ53 0000 0x00 0000 0x00 uuuu uuuu
T3GCON PIC18F2XJ53 PIC18F4XJ53 0000 0x00 uuuu uxuu uuuu uxuu
(5)
TRISE PIC18F2XJ53 PIC18F4XJ53 00-- -111 uu-- -111 uu-- -uuu
TRISD(5) PIC18F2XJ53 PIC18F4XJ53 1111 1111 1111 1111 uuuu uuuu
TRISC PIC18F2XJ53 PIC18F4XJ53 11-- -111 11-- -111 uu-- -uuu
TRISB PIC18F2XJ53 PIC18F4XJ53 1111 1111 1111 1111 uuuu uuuu
TRISA PIC18F2XJ53 PIC18F4XJ53 111- 1111 111- 1111 uuu- uuuu
LATE(5) PIC18F2XJ53 PIC18F4XJ53 ---- -xxx ---- -uuu ---- -uuu
(5)
LATD PIC18F2XJ53 PIC18F4XJ53 xxxx xxxx uuuu uuuu uuuu uuuu
LATC PIC18F2XJ53 PIC18F4XJ53 xx-- -xxx uu-- -uuu uu-- -uuu
LATB PIC18F2XJ53 PIC18F4XJ53 xxxx xxxx uuuu uuuu uuuu uuuu
LATA PIC18F2XJ53 PIC18F4XJ53 xxx- xxxx uuu- uuuu uuu- uuuu
DMACON1 PIC18F2XJ53 PIC18F4XJ53 0000 0000 0000 0000 uuuu uuuu
OSCCON2 PIC18F2XJ53 PIC18F4XJ53 -0-1 01-- — —
DMACON2 PIC18F2XJ53 PIC18F4XJ53 0000 0000 0000 0000 uuuu uuuu
HLVDCON PIC18F2XJ53 PIC18F4XJ53 0000 0000 0000 0000 uuuu uuuu
PORTE(5) PIC18F2XJ53 PIC18F4XJ53 ---- -xxx ---- -uuu ---- -uuu
PORTD(5) PIC18F2XJ53 PIC18F4XJ53 xxxx xxxx uuuu uuuu uuuu uuuu
PORTC PIC18F2XJ53 PIC18F4XJ53 xxxx -xxx uuuu -uuu uuuu -uuu
PORTB PIC18F2XJ53 PIC18F4XJ53 xxxx xxxx uuuu uuuu uuuu uuuu
PORTA PIC18F2XJ53 PIC18F4XJ53 xxx- xxxx uuu- uuuu uuu- uuuu
SPBRGH1 PIC18F2XJ53 PIC18F4XJ53 0000 0000 0000 0000 uuuu uuuu
BAUDCON1 PIC18F2XJ53 PIC18F4XJ53 0100 0-00 0100 0-00 uuuu u-uu
SPBRGH2 PIC18F2XJ53 PIC18F4XJ53 0000 0000 0000 0000 uuuu uuuu
BAUDCON2 PIC18F2XJ53 PIC18F4XJ53 0100 0-00 0100 0-00 uuuu u-uu
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
4: See Table 5-1 for Reset value for specific condition.
5: Not implemented for PIC18F2XJ53 devices.
6: Not implemented for “LF” devices.

DS39964B-page 74 Preliminary  2010 Microchip Technology Inc.

 PIC18F47J53 FAMILY
TABLE 5-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
MCLR Resets
Power-on Reset,
WDT Reset
Brown-out Reset, Wake-up via WDT
Register Applicable Devices RESET Instruction
Wake From Deep or Interrupt
Stack Resets
Sleep
CM Resets
TMR3H PIC18F2XJ53 PIC18F4XJ53 xxxx xxxx uuuu uuuu uuuu uuuu
TMR3L PIC18F2XJ53 PIC18F4XJ53 xxxx xxxx uuuu uuuu uuuu uuuu
T3CON PIC18F2XJ53 PIC18F4XJ53 0000 0000 uuuu uuuu uuuu uuuu
TMR4 PIC18F2XJ53 PIC18F4XJ53 0000 0000 uuuu uuuu uuuu uuuu
PR4 PIC18F2XJ53 PIC18F4XJ53 1111 1111 1111 1111 uuuu uuuu
T4CON PIC18F2XJ53 PIC18F4XJ53 -000 0000 -000 0000 -uuu uuuu
SSP2BUF PIC18F2XJ53 PIC18F4XJ53 xxxx xxxx uuuu uuuu uuuu uuuu
SSP2ADD PIC18F2XJ53 PIC18F4XJ53 0000 0000 0000 0000 uuuu uuuu
SSP2MSK PIC18F2XJ53 PIC18F4XJ53 ---- ---- 0000 0000 uuuu uuuu
SSP2STAT PIC18F2XJ53 PIC18F4XJ53 1111 1111 1111 1111 uuuu uuuu
SSP2CON1 PIC18F2XJ53 PIC18F4XJ53 0000 0000 0000 0000 uuuu uuuu
SSP2CON2 PIC18F2XJ53 PIC18F4XJ53 0000 0000 0000 0000 uuuu uuuu
CMSTAT PIC18F2XJ53 PIC18F4XJ53 ---- --11 ---- --11 ---- --uu
(5)
PMADDRH PIC18F2XJ53 PIC18F4XJ53 -000 0000 -000 0000 -uuu uuuu
PMDOUT1H(5) PIC18F2XJ53 PIC18F4XJ53 0000 0000 0000 0000 uuuu uuuu
PMADDRL PIC18F2XJ53 PIC18F4XJ53 0000 0000 0000 0000 uuuu uuuu
PMDOUT1L PIC18F2XJ53 PIC18F4XJ53 0000 0000 0000 0000 uuuu uuuu
PMDIN1H PIC18F2XJ53 PIC18F4XJ53 0000 0000 0000 0000 uuuu uuuu
PMDIN1L PIC18F2XJ53 PIC18F4XJ53 0000 0000 0000 0000 uuuu uuuu
TXADDRL PIC18F2XJ53 PIC18F4XJ53 0000 0000 0000 0000 uuuu uuuu
TXADDRH PIC18F2XJ53 PIC18F4XJ53 ---- 0000 ---- 0000 ---- uuuu
RXADDRL PIC18F2XJ53 PIC18F4XJ53 0000 0000 0000 0000 uuuu uuuu
RXADDRH PIC18F2XJ53 PIC18F4XJ53 ---- 0000 ---- 0000 ---- uuuu
DMABCL PIC18F2XJ53 PIC18F4XJ53 0000 0000 0000 0000 uuuu uuuu
DMABCH PIC18F2XJ53 PIC18F4XJ53 ---- --00 ---- --00 ---- --uu
UCON PIC18F2XJ53 PIC18F4XJ53 -0x0 000- -0x0 000- -uuu uuu-
USTAT PIC18F2XJ53 PIC18F4XJ53 -xxx xxx- -xxx xxx- -uuu uuu-
UEIR PIC18F2XJ53 PIC18F4XJ53 0--0 0000 0--0 0000 u--u uuuu
UIR PIC18F2XJ53 PIC18F4XJ53 -000 0000 -000 0000 -uuu uuuu
UFRMH PIC18F2XJ53 PIC18F4XJ53 ---- -xxx ---- -xxx ---- -uuu
UFRML PIC18F2XJ53 PIC18F4XJ53 xxxx xxxx xxxxx xxxx uuuu uuuu
PMCONH PIC18F2XJ53 PIC18F4XJ53 0-00 0000 0-00 0000 u-uu uuuu
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
4: See Table 5-1 for Reset value for specific condition.
5: Not implemented for PIC18F2XJ53 devices.
6: Not implemented for “LF” devices.

 2010 Microchip Technology Inc. Preliminary DS39964B-page 75

PIC18F47J53 FAMILY
TABLE 5-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
MCLR Resets
Power-on Reset,
WDT Reset
Brown-out Reset, Wake-up via WDT
Register Applicable Devices RESET Instruction
Wake From Deep or Interrupt
Stack Resets
Sleep
CM Resets
PMCONL PIC18F2XJ53 PIC18F4XJ53 000- 0000 000- 0000 uuu- uuuu
PMMODEH PIC18F2XJ53 PIC18F4XJ53 0000 0000 0000 0000 uuuu uuuu
PMMODEL PIC18F2XJ53 PIC18F4XJ53 0000 0000 0000 0000 uuuu uuuu
PMDOUT2H PIC18F2XJ53 PIC18F4XJ53 0000 0000 0000 0000 uuuu uuuu
PMDOUT2L PIC18F2XJ53 PIC18F4XJ53 0000 0000 0000 0000 uuuu uuuu
PMDIN2H PIC18F2XJ53 PIC18F4XJ53 0000 0000 0000 0000 uuuu uuuu
PMDIN2L PIC18F2XJ53 PIC18F4XJ53 0000 0000 0000 0000 uuuu uuuu
PMEH PIC18F2XJ53 PIC18F4XJ53 0000 0000 0000 0000 uuuu uuuu
PMEL PIC18F2XJ53 PIC18F4XJ53 0000 0000 0000 0000 uuuu uuuu
PMSTATH PIC18F2XJ53 PIC18F4XJ53 00-- 0000 00-- 0000 uu-- uuuu
PMSTATL PIC18F2XJ53 PIC18F4XJ53 10-- 1111 10-- 1111 uu-- uuuu
CVRCON PIC18F2XJ53 PIC18F4XJ53 0000 0000 0000 0000 uuuu uuuu
CCPTMRS0 PIC18F2XJ53 PIC18F4XJ53 0000 0000 0000 0000 uuuu uuuu
CCPTMRS1 PIC18F2XJ53 PIC18F4XJ53 0000 0000 0000 0000 uuuu uuuu
CCPTMRS2 PIC18F2XJ53 PIC18F4XJ53 0000 0000 0000 0000 uuuu uuuu
(6)
DSGPR1 PIC18F2XJ53 PIC18F4XJ53 uuuu uuuu uuuu uuuu uuuu uuuu
DSGPR0(6) PIC18F2XJ53 PIC18F4XJ53 uuuu uuuu uuuu uuuu uuuu uuuu
DSCONH(6) PIC18F2XJ53 PIC18F4XJ53 0--- --00 0--- --00 u--- --uu
DSCONL(6) PIC18F2XJ53 PIC18F4XJ53 ---- -000 ---- -000 ---- -uuu
(6)
DSWAKEH PIC18F2XJ53 PIC18F4XJ53 ---- ---q ---- ---0 ---- ---u
DSWAKEL(6) PIC18F2XJ53 PIC18F4XJ53 q-qq qq-q 0-00 00-0 u-uu uu-u
ANCON1 PIC18F2XJ53 PIC18F4XJ53 00-0 0000 uu-u uuuu uu-u uuuu
ANCON0 PIC18F2XJ53 PIC18F4XJ53 0000 0000 uuuu uuuu uuuu uuuu
ALRMCFG PIC18F2XJ53 PIC18F4XJ53 0000 0000 uuuu uuuu uuuu uuuu
ALRMRPT PIC18F2XJ53 PIC18F4XJ53 0000 0000 uuuu uuuu uuuu uuuu
ALRMVALH PIC18F2XJ53 PIC18F4XJ53 xxxx xxxx uuuu uuuu uuuu uuuu
ALRMVALL PIC18F2XJ53 PIC18F4XJ53 xxxx xxxx uuuu uuuu uuuu uuuu
ODCON1 PIC18F2XJ53 PIC18F4XJ53 ---- 0000 ---- uuuu ---- uuuu
ODCON2 PIC18F2XJ53 PIC18F4XJ53 ---- --00 ---- --uu ---- --uu
ODCON3 PIC18F2XJ53 PIC18F4XJ53 ---- --00 ---- --uu ---- --uu
RTCCFG PIC18F2XJ53 PIC18F4XJ53 0-00 0000 u-uu uuuu u-uu uuuu
RTCCAL PIC18F2XJ53 PIC18F4XJ53 0000 0000 uuuu uuuu uuuu uuuu
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
4: See Table 5-1 for Reset value for specific condition.
5: Not implemented for PIC18F2XJ53 devices.
6: Not implemented for “LF” devices.

DS39964B-page 76 Preliminary  2010 Microchip Technology Inc.

 PIC18F47J53 FAMILY
TABLE 5-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
MCLR Resets
Power-on Reset,
WDT Reset
Brown-out Reset, Wake-up via WDT
Register Applicable Devices RESET Instruction
Wake From Deep or Interrupt
Stack Resets
Sleep
CM Resets
REFOCON PIC18F2XJ53 PIC18F4XJ53 0-00 0000 u-uu uuuu u-uu uuuu
PADCFG1 PIC18F2XJ53 PIC18F4XJ53 ---- -000 ---- -uuu ---- -uuu
RTCVALH PIC18F2XJ53 PIC18F4XJ53 0xxx xxxx 0uuu uuuu 0uuu uuuu
RTCVALL PIC18F2XJ53 PIC18F4XJ53 0xxx xxxx 0uuu uuuu 0uuu uuuu
UCFG PIC18F2XJ53 PIC18F4XJ53 00-0 0000 00-0 0000 uu-u uuuu
UADDR PIC18F2XJ53 PIC18F4XJ53 -000 0000 -uuu uuuu -uuu uuuu
UEIE PIC18F2XJ53 PIC18F4XJ53 0--0 0000 0--0 0000 u--u uuuu
UIE PIC18F2XJ53 PIC18F4XJ53 -000 0000 -000 0000 -uuu uuuu
UEP15 PIC18F2XJ53 PIC18F4XJ53 ---0 0000 ---0 0000 ---u uuuu
UEP14 PIC18F2XJ53 PIC18F4XJ53 ---0 0000 ---0 0000 ---u uuuu
UEP13 PIC18F2XJ53 PIC18F4XJ53 ---0 0000 ---0 0000 ---u uuuu
UEP12 PIC18F2XJ53 PIC18F4XJ53 ---0 0000 ---0 0000 ---u uuuu
UEP11 PIC18F2XJ53 PIC18F4XJ53 ---0 0000 ---0 0000 ---u uuuu
UEP10 PIC18F2XJ53 PIC18F4XJ53 ---0 0000 ---0 0000 ---u uuuu
UEP9 PIC18F2XJ53 PIC18F4XJ53 ---0 0000 ---0 0000 ---u uuuu
UEP8 PIC18F2XJ53 PIC18F4XJ53 ---0 0000 ---0 0000 ---u uuuu
UEP7 PIC18F2XJ53 PIC18F4XJ53 ---0 0000 ---0 0000 ---u uuuu
UEP6 PIC18F2XJ53 PIC18F4XJ53 ---0 0000 ---0 0000 ---u uuuu
UEP5 PIC18F2XJ53 PIC18F4XJ53 ---0 0000 ---0 0000 ---u uuuu
UEP4 PIC18F2XJ53 PIC18F4XJ53 ---0 0000 ---0 0000 ---u uuuu
UEP3 PIC18F2XJ53 PIC18F4XJ53 ---0 0000 ---0 0000 ---u uuuu
UEP2 PIC18F2XJ53 PIC18F4XJ53 ---0 0000 ---0 0000 ---u uuuu
UEP1 PIC18F2XJ53 PIC18F4XJ53 ---0 0000 ---0 0000 ---u uuuu
UEP0 PIC18F2XJ53 PIC18F4XJ53 ---0 0000 ---0 0000 ---u uuuu
CM3CON PIC18F2XJ53 PIC18F4XJ53 0001 1111 uuuu uuuu uuuu uuuu
TMR5H PIC18F2XJ53 PIC18F4XJ53 xxxx xxxx — —
TMR5L PIC18F2XJ53 PIC18F4XJ53 xxxx xxxx — —
T5CON PIC18F2XJ53 PIC18F4XJ53 0000 0000 — —
T5GCON PIC18F2XJ53 PIC18F4XJ53 0000 0x00 — —
TMR6 PIC18F2XJ53 PIC18F4XJ53 0000 0000 — —
PR6 PIC18F2XJ53 PIC18F4XJ53 1111 1111 — —
T6CON PIC18F2XJ53 PIC18F4XJ53 -000 0000 — —
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
4: See Table 5-1 for Reset value for specific condition.
5: Not implemented for PIC18F2XJ53 devices.
6: Not implemented for “LF” devices.

 2010 Microchip Technology Inc. Preliminary DS39964B-page 77

PIC18F47J53 FAMILY
TABLE 5-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
MCLR Resets
Power-on Reset,
WDT Reset
Brown-out Reset, Wake-up via WDT
Register Applicable Devices RESET Instruction
Wake From Deep or Interrupt
Stack Resets
Sleep
CM Resets
TMR8 PIC18F2XJ53 PIC18F4XJ53 0000 0000 — —
PR8 PIC18F2XJ53 PIC18F4XJ53 1111 1111 — —
T8CON PIC18F2XJ53 PIC18F4XJ53 -000 0000 — —
PSTR3CON PIC18F2XJ53 PIC18F4XJ53 00-0 0001 — —
ECCP3AS PIC18F2XJ53 PIC18F4XJ53 0000 0000 — —
ECCP3DEL PIC18F2XJ53 PIC18F4XJ53 0000 0000 — —
CCPR3H PIC18F2XJ53 PIC18F4XJ53 xxxx xxxx — —
CCPR3L PIC18F2XJ53 PIC18F4XJ53 xxxx xxxx — —
CCP3CON PIC18F2XJ53 PIC18F4XJ53 0000 0000 — —
CCPR4H PIC18F2XJ53 PIC18F4XJ53 xxxx xxxx — —
CCPR4L PIC18F2XJ53 PIC18F4XJ53 xxxx xxxx — —
CCP4CON PIC18F2XJ53 PIC18F4XJ53 --00 0000 — —
CCPR5H PIC18F2XJ53 PIC18F4XJ53 xxxx xxxx — —
CCPR5L PIC18F2XJ53 PIC18F4XJ53 xxxx xxxx — —
CCP5CON PIC18F2XJ53 PIC18F4XJ53 --00 0000 — —
CCPR6H PIC18F2XJ53 PIC18F4XJ53 xxxx xxxx — —
CCPR6L PIC18F2XJ53 PIC18F4XJ53 xxxx xxxx — —
CCP6CON PIC18F2XJ53 PIC18F4XJ53 --00 0000 — —
CCPR7H PIC18F2XJ53 PIC18F4XJ53 xxxx xxxx — —
CCPR7L PIC18F2XJ53 PIC18F4XJ53 xxxx xxxx — —
CCP7CON PIC18F2XJ53 PIC18F4XJ53 --00 0000 — —
CCPR8H PIC18F2XJ53 PIC18F4XJ53 xxxx xxxx — —
CCPR8L PIC18F2XJ53 PIC18F4XJ53 xxxx xxxx — —
CCP8CON PIC18F2XJ53 PIC18F4XJ53 --00 0000 — —
CCPR9H PIC18F2XJ53 PIC18F4XJ53 xxxx xxxx — —
CCPR9L PIC18F2XJ53 PIC18F4XJ53 xxxx xxxx — —
CCP9CON PIC18F2XJ53 PIC18F4XJ53 --00 0000 — —
CCPR10H PIC18F2XJ53 PIC18F4XJ53 xxxx xxxx — —
CCPR10L PIC18F2XJ53 PIC18F4XJ53 xxxx xxxx — —
CCP10CON PIC18F2XJ53 PIC18F4XJ53 --00 0000 — —
RPINR24 PIC18F2XJ53 PIC18F4XJ53 ---1 1111 ---1 1111 ---u uuuu
RPINR23 PIC18F2XJ53 PIC18F4XJ53 ---1 1111 ---1 1111 ---u uuuu
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
4: See Table 5-1 for Reset value for specific condition.
5: Not implemented for PIC18F2XJ53 devices.
6: Not implemented for “LF” devices.

DS39964B-page 78 Preliminary  2010 Microchip Technology Inc.

 PIC18F47J53 FAMILY
TABLE 5-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
MCLR Resets
Power-on Reset,
WDT Reset
Brown-out Reset, Wake-up via WDT
Register Applicable Devices RESET Instruction
Wake From Deep or Interrupt
Stack Resets
Sleep
CM Resets
RPINR22 PIC18F2XJ53 PIC18F4XJ53 ---1 1111 ---1 1111 ---u uuuu
RPINR21 PIC18F2XJ53 PIC18F4XJ53 ---1 1111 ---1 1111 ---u uuuu
RPINR17 PIC18F2XJ53 PIC18F4XJ53 ---1 1111 ---1 1111 ---u uuuu
RPINR16 PIC18F2XJ53 PIC18F4XJ53 ---1 1111 ---1 1111 ---u uuuu
RPINR14 PIC18F2XJ53 PIC18F4XJ53 ---1 1111 ---1 1111 ---u uuuu
RPINR13 PIC18F2XJ53 PIC18F4XJ53 ---1 1111 ---1 1111 ---u uuuu
RPINR12 PIC18F2XJ53 PIC18F4XJ53 ---1 1111 ---1 1111 ---u uuuu
RPINR9 PIC18F2XJ53 PIC18F4XJ53 ---1 1111 ---1 1111 ---u uuuu
RPINR8 PIC18F2XJ53 PIC18F4XJ53 ---1 1111 ---1 1111 ---u uuuu
RPINR7 PIC18F2XJ53 PIC18F4XJ53 ---1 1111 ---1 1111 ---u uuuu
RPINR15 PIC18F2XJ53 PIC18F4XJ53 ---1 1111 ---1 1111 ---u uuuu
RPINR6 PIC18F2XJ53 PIC18F4XJ53 ---1 1111 ---1 1111 ---u uuuu
RPINR4 PIC18F2XJ53 PIC18F4XJ53 ---1 1111 ---1 1111 ---u uuuu
RPINR3 PIC18F2XJ53 PIC18F4XJ53 ---1 1111 ---1 1111 ---u uuuu
RPINR2 PIC18F2XJ53 PIC18F4XJ53 ---1 1111 ---1 1111 ---u uuuu
RPINR1 PIC18F2XJ53 PIC18F4XJ53 ---1 1111 ---1 1111 ---u uuuu
RPOR24 PIC18F2XJ53 PIC18F4XJ53 ---0 0000 ---0 0000 ---u uuuu
RPOR23 PIC18F2XJ53 PIC18F4XJ53 ---0 0000 ---0 0000 ---u uuuu
RPOR22 PIC18F2XJ53 PIC18F4XJ53 ---0 0000 ---0 0000 ---u uuuu
RPOR21 PIC18F2XJ53 PIC18F4XJ53 ---0 0000 ---0 0000 ---u uuuu
RPOR20 PIC18F2XJ53 PIC18F4XJ53 ---0 0000 ---0 0000 ---u uuuu
RPOR19 PIC18F2XJ53 PIC18F4XJ53 ---0 0000 ---0 0000 ---u uuuu
RPOR18 PIC18F2XJ53 PIC18F4XJ53 ---0 0000 ---0 0000 ---u uuuu
RPOR17 PIC18F2XJ53 PIC18F4XJ53 ---0 0000 ---0 0000 ---u uuuu
RPOR13 PIC18F2XJ53 PIC18F4XJ53 ---0 0000 ---0 0000 ---u uuuu
RPOR12 PIC18F2XJ53 PIC18F4XJ53 ---0 0000 ---0 0000 ---u uuuu
RPOR11 PIC18F2XJ53 PIC18F4XJ53 ---0 0000 ---0 0000 ---u uuuu
RPOR10 PIC18F2XJ53 PIC18F4XJ53 ---0 0000 ---0 0000 ---u uuuu
RPOR9 PIC18F2XJ53 PIC18F4XJ53 ---0 0000 ---0 0000 ---u uuuu
RPOR8 PIC18F2XJ53 PIC18F4XJ53 ---0 0000 ---0 0000 ---u uuuu
RPOR7 PIC18F2XJ53 PIC18F4XJ53 ---0 0000 ---0 0000 ---u uuuu
RPOR6 PIC18F2XJ53 PIC18F4XJ53 ---0 0000 ---0 0000 ---u uuuu
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
4: See Table 5-1 for Reset value for specific condition.
5: Not implemented for PIC18F2XJ53 devices.
6: Not implemented for “LF” devices.

 2010 Microchip Technology Inc. Preliminary DS39964B-page 79

PIC18F47J53 FAMILY
TABLE 5-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
MCLR Resets
Power-on Reset,
WDT Reset
Brown-out Reset, Wake-up via WDT
Register Applicable Devices RESET Instruction
Wake From Deep or Interrupt
Stack Resets
Sleep
CM Resets
RPOR5 PIC18F2XJ53 PIC18F4XJ53 ---0 0000 ---0 0000 ---u uuuu
RPOR4 PIC18F2XJ53 PIC18F4XJ53 ---0 0000 ---0 0000 ---u uuuu
RPOR3 PIC18F2XJ53 PIC18F4XJ53 ---0 0000 ---0 0000 ---u uuuu
RPOR2 PIC18F2XJ53 PIC18F4XJ53 ---0 0000 ---0 0000 ---u uuuu
RPOR1 PIC18F2XJ53 PIC18F4XJ53 ---0 0000 ---0 0000 ---u uuuu
RPOR0 PIC18F2XJ53 PIC18F4XJ53 ---0 0000 ---0 0000 ---u uuuu
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
4: See Table 5-1 for Reset value for specific condition.
5: Not implemented for PIC18F2XJ53 devices.
6: Not implemented for “LF” devices.

DS39964B-page 80 Preliminary  2010 Microchip Technology Inc.

 PIC18F47J53 FAMILY
6.0 MEMORY ORGANIZATION 6.1 Program Memory Organization
There are two types of memory in PIC18 Flash PIC18 microcontrollers implement a 21-bit program
microcontrollers: counter, which is capable of addressing a 2-Mbyte
program memory space. Accessing a location between
• Program Memory
the upper boundary of the physically implemented
• Data RAM memory and the 2-Mbyte address returns all ‘0’s (a
As Harvard architecture devices, the data and program NOP instruction).
memories use separate busses; this allows for The PIC18F47J53 family offers a range of on-chip
concurrent access of the two memory spaces. Flash program memory sizes, from 64 Kbytes (up to
Section 7.0 “Flash Program Memory” provides 32,768 single-word instructions) to 128 Kbytes
additional information on the operation of the Flash (65,536 single-word instructions).
program memory. Figure 6-1 provides the program memory maps for
individual family devices.

FIGURE 6-1: MEMORY MAPS FOR PIC18F47J53 FAMILY DEVICES

PC<20:0>
CALL, CALLW, RCALL, 21
RETURN, RETFIE, RETLW,
ADDULNK, SUBULNK
Stack Level 1

Stack Level 31

PIC18FX6J53 PIC18FX7J53
000000h
On-Chip On-Chip
Memory Memory

Config. Words
00FFFFh

Config. Words
User Memory Space

01FFFFh

Unimplemented Unimplemented
Read as ‘0’ Read as ‘0’

1FFFFFF

Note: Sizes of memory areas are not to scale. Sizes of program memory areas are enhanced to show detail.

 2010 Microchip Technology Inc. Preliminary DS39964B-page 81

PIC18F47J53 FAMILY
6.1.1 HARD MEMORY VECTORS 6.1.2 FLASH CONFIGURATION WORDS
All PIC18 devices have a total of three hard-coded Because PIC18F47J53 family devices do not have
return vectors in their program memory space. The persistent configuration memory, the top four words of
Reset vector address is the default value to which the on-chip program memory are reserved for configuration
program counter returns on all device Resets; it is information. On Reset, the configuration information is
located at 0000h. copied into the Configuration registers.
PIC18 devices also have two interrupt vector The Configuration Words are stored in their program
addresses for handling high-priority and low-priority memory location in numerical order, starting with the
interrupts. The high-priority interrupt vector is located at lower byte of CONFIG1 at the lowest address and
0008h and the low-priority interrupt vector at 0018h. ending with the upper byte of CONFIG4.
Figure 6-2 provides their locations in relation to the Table 6-1 provides the actual addresses of the Flash
program memory map. Configuration Word for devices in the PIC18F47J53
family. Figure 6-2 displays their location in the memory
FIGURE 6-2: HARD VECTOR AND map with other memory vectors.
CONFIGURATION WORD
Additional details on the device Configuration Words
LOCATIONS FOR are provided in Section 28.1 “Configuration Bits”.
PIC18F47J53 FAMILY
DEVICES TABLE 6-1: FLASH CONFIGURATION
WORD FOR PIC18F47J53
Reset Vector 0000h FAMILY DEVICES
High-Priority Interrupt Vector 0008h Program
Configuration
Low-Priority Interrupt Vector 0018h Device Memory
Word Addresses
(Kbytes)
PIC18F26J53
64 FFF8h to FFFFh
PIC18F46J53
On-Chip PIC18F27J53
Program Memory 128 1FFF8h to 1FFFFh
PIC18F47J53

Flash Configuration Words (Top of Memory-7)

(Top of Memory)

Read as ‘0’

1FFFFFh

Legend: (Top of Memory) represents upper boundary

of on-chip program memory space (see
Figure 6-1 for device-specific values).
Shaded area represents unimplemented
memory. Areas are not shown to scale.

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 PIC18F47J53 FAMILY
6.1.3 PROGRAM COUNTER The stack operates as a 31-word by 21-bit RAM and a
5-bit Stack Pointer (SP), STKPTR. The stack space is
The Program Counter (PC) specifies the address of the
not part of either program or data space. The Stack
instruction to fetch for execution. The PC is 21 bits wide
Pointer is readable and writable and the address on the
and is contained in three separate 8-bit registers. The
top of the stack is readable and writable through the
low byte, known as the PCL register, is both readable
Top-of-Stack Special Function Registers (SFRs). Data
and writable. The high byte, or PCH register, contains
can also be pushed to, or popped from, the stack using
the PC<15:8> bits; it is not directly readable or writable.
these registers.
Updates to the PCH register are performed through the
PCLATH register. The upper byte is called PCU. This A CALL type instruction causes a push onto the stack.
register contains the PC<20:16> bits; it is also not The Stack Pointer is first incremented and the location
directly readable or writable. Updates to the PCU pointed to by the Stack Pointer is written with the
register are performed through the PCLATU register. contents of the PC (already pointing to the instruction
following the CALL). A RETURN type instruction causes
The contents of PCLATH and PCLATU are transferred
a pop from the stack. The contents of the location
to the program counter by any operation that writes to
pointed to by the STKPTR are transferred to the PC
PCL. Similarly, the upper 2 bytes of the program
and then the Stack Pointer is decremented.
counter are transferred to PCLATH and PCLATU by an
operation that reads PCL. This is useful for computed The Stack Pointer is initialized to ‘00000’ after all
offsets to the PC (see Section 6.1.6.1 “Computed Resets. There is no RAM associated with the location
GOTO”). corresponding to a Stack Pointer value of ‘00000’; this
is only a Reset value. Status bits indicate if the stack is
The PC addresses bytes in the program memory. To
full, has overflowed or has underflowed.
prevent the PC from becoming misaligned with word
instructions, the Least Significant bit (LSb) of PCL is
6.1.4.1 Top-of-Stack Access
fixed to a value of ‘0’. The PC increments by two to
address sequential instructions in the program Only the top of the return address stack (TOS) is read-
memory. able and writable. A set of three registers,
TOSU:TOSH:TOSL, holds the contents of the stack
The CALL, RCALL, GOTO and program branch
location pointed to by the STKPTR register
instructions write to the program counter directly. For
(Figure 6-3). This allows users to implement a software
these instructions, the contents of PCLATH and
stack if necessary. After a CALL, RCALL or interrupt
PCLATU are not transferred to the program counter.
(and ADDULNK and SUBULNK instructions if the
extended instruction set is enabled), the software can
6.1.4 RETURN ADDRESS STACK
read the pushed value by reading the
The return address stack allows any combination of up TOSU:TOSH:TOSL registers. These values can be
to 31 program calls and interrupts to occur. The PC is placed on a user-defined software stack. At return time,
pushed onto the stack when a CALL or RCALL instruc- the software can return these values to
tion is executed, or an interrupt is Acknowledged. The TOSU:TOSH:TOSL and do a return.
PC value is pulled off the stack on a RETURN, RETLW
The user must disable the global interrupt enable bits
or a RETFIE instruction (and on ADDULNK and
while accessing the stack to prevent inadvertent stack
SUBULNK instructions if the extended instruction set is
corruption.
enabled). PCLATU and PCLATH are not affected by
any of the RETURN or CALL instructions.

FIGURE 6-3: RETURN ADDRESS STACK AND ASSOCIATED REGISTERS

Return Address Stack <20:0>

Top-of-Stack Registers Stack Pointer
11111
TOSU TOSH TOSL 11110 STKPTR<4:0>
00h 1Ah 34h 11101 00010

00011
Top-of-Stack 001A34h 00010
000D58h 00001
00000

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PIC18F47J53 FAMILY
6.1.4.2 Return Stack Pointer (STKPTR) When the stack has been popped enough times to
unload the stack, the next pop will return zero to the PC
The STKPTR register (Register 6-1) contains the Stack
and set the STKUNF bit, while the Stack Pointer
Pointer value, the STKFUL (Stack Full) and the STKUNF
remains at zero. The STKUNF bit will remain set until
(Stack Underflow) status bits. The value of the Stack
cleared by software or until a POR occurs.
Pointer can be 0 through 31. The Stack Pointer
increments before values are pushed onto the stack and Note: Returning a value of zero to the PC on an
decrements after values are popped off of the stack. On underflow has the effect of vectoring the
Reset, the Stack Pointer value will be zero. The user program to the Reset vector, where the
may read and write the Stack Pointer value. This feature stack conditions can be verified and
can be used by a Real-Time Operating System (RTOS) appropriate actions can be taken. This is
for return stack maintenance. not the same as a Reset, as the contents
After the PC is pushed onto the stack 31 times (without of the SFRs are not affected.
popping any values off the stack), the STKFUL bit is
set. The STKFUL bit is cleared by software or by a 6.1.4.3 PUSH and POP Instructions
Power-on Reset (POR). Since the Top-of-Stack (TOS) is readable and writable,
The action that takes place when the stack becomes the ability to push values onto the stack and pull values
full depends on the state of the Stack Overflow Reset off of the stack, without disturbing normal program exe-
Enable (STVREN) Configuration bit. cution, is necessary. The PIC18 instruction set includes
two instructions, PUSH and POP, that permit the TOS to
Refer to Section 28.1 “Configuration Bits” for device
be manipulated under software control. TOSU, TOSH
Configuration bits’ description.
and TOSL can be modified to place data or a return
If STVREN is set (default), the 31st push will push the address on the stack.
(PC + 2) value onto the stack, set the STKFUL bit and
The PUSH instruction places the current PC value onto
reset the device. The STKFUL bit will remain set and
the stack. This increments the Stack Pointer and loads
the Stack Pointer will be set to zero.
the current PC value onto the stack.
If STVREN is cleared, the STKFUL bit will be set on the
The POP instruction discards the current TOS by
31st push and the Stack Pointer will increment to 31.
decrementing the Stack Pointer. The previous value
Any additional pushes will not overwrite the 31st push
pushed onto the stack then becomes the TOS value.
and the STKPTR will remain at 31.

REGISTER 6-1: STKPTR: STACK POINTER REGISTER (ACCESS FFCh)

R/C-0 R/C-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
STKFUL(1) STKUNF(1) — SP4 SP3 SP2 SP1 SP0
bit 7 bit 0

Legend: C = Clearable bit

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 STKFUL: Stack Full Flag bit(1)

1 = Stack became full or overflowed
0 = Stack has not become full or overflowed
bit 6 STKUNF: Stack Underflow Flag bit(1)
1 = Stack underflow occurred
0 = Stack underflow did not occur
bit 5 Unimplemented: Read as ‘0’
bit 4-0 SP<4:0>: Stack Pointer Location bits

Note 1: Bits 7 and 6 are cleared by user software or by a POR.

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 PIC18F47J53 FAMILY
6.1.4.4 Stack Full and Underflow Resets 6.1.6 LOOK-UP TABLES IN PROGRAM
Device Resets on stack overflow and stack underflow MEMORY
conditions are enabled by setting the STVREN bit in There may be programming situations that require the
Configuration register 1L. When STVREN is set, a full creation of data structures or look-up tables in program
or underflow condition sets the appropriate STKFUL or memory. For PIC18 devices, look-up tables can be
STKUNF bit and then causes a device Reset. When implemented in two ways:
STVREN is cleared, a full or underflow condition sets
• Computed GOTO
the appropriate STKFUL or STKUNF bit, but does not
cause a device Reset. The STKFUL or STKUNF bits • Table Reads
are cleared by the user software or a POR.
6.1.6.1 Computed GOTO
6.1.5 FAST REGISTER STACK (FRS) A computed GOTO is accomplished by adding an offset
A Fast Register Stack (FRS) is provided for the to the PC. An example is shown in Example 6-2.
STATUS, WREG and BSR registers to provide a “fast A look-up table can be formed with an ADDWF PCL
return” option for interrupts. This stack is only one level instruction and a group of RETLW nn instructions. The
deep and is neither readable nor writable. It is loaded W register is loaded with an offset into the table before
with the current value of the corresponding register executing a call to that table. The first instruction of the
when the processor vectors for an interrupt. All inter- called routine is the ADDWF PCL instruction. The next
rupt sources push values into the Stack registers. The executed instruction will be one of the RETLW nn
values in the registers are then loaded back into the instructions that returns the value, ‘nn’, to the calling
working registers if the RETFIE, FAST instruction is function.
used to return from the interrupt. The offset value (in WREG) specifies the number of
If both low-priority and high-priority interrupts are bytes that the PC should advance and should be
enabled, the Stack registers cannot be used reliably to multiples of 2 (LSb = 0).
return from low-priority interrupts. If a high-priority In this method, only one byte may be stored in each
interrupt occurs while servicing a low-priority interrupt, instruction location, but room on the return address
the Stack register values stored by the low-priority stack is required.
interrupt will be overwritten. In these cases, users must
save the key registers in software during a low-priority
EXAMPLE 6-2: COMPUTED GOTO USING
interrupt.
AN OFFSET VALUE
If interrupt priority is not used, all interrupts may use the MOVF OFFSET, W
FRS for returns from interrupt. If no interrupts are used, CALL TABLE
the FRS can be used to restore the STATUS, WREG ORG nn00h
and BSR registers at the end of a subroutine call. To TABLE ADDWF PCL
use the Fast Register Stack for a subroutine call, a RETLW nnh
CALL label, FAST instruction must be executed to RETLW nnh
save the STATUS, WREG and BSR registers to the RETLW nnh
Fast Register Stack. A RETURN, FAST instruction is .
then executed to restore these registers from the FRS. .
.
Example 6-1 provides a source code example that
uses the FRS during a subroutine call and return.
6.1.6.2 Table Reads
EXAMPLE 6-1: FAST REGISTER STACK A better method of storing data in program memory
CODE EXAMPLE allows two bytes to be stored in each instruction
location.
CALL SUB1, FAST ;STATUS, WREG, BSR
;SAVED IN FAST REGISTER Look-up table data may be stored two bytes per
;STACK program word while programming. The Table Pointer
 (TBLPTR) specifies the byte address, and the Table
 Latch (TABLAT) contains the data that is read from the
program memory. Data is transferred from program
SUB1 
memory, one byte at a time.

RETURN FAST ;RESTORE VALUES SAVED Table read operation is discussed further in
;IN FAST REGISTER STACK Section 7.1 “Table Reads and Table Writes”.

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PIC18F47J53 FAMILY
6.2 PIC18 Instruction Cycle 6.2.2 INSTRUCTION FLOW/PIPELINING
An “Instruction Cycle” consists of four Q cycles, Q1
6.2.1 CLOCKING SCHEME through Q4. The instruction fetch and execute are pipe-
The microcontroller clock input, whether from an lined in such a manner that a fetch takes one instruction
internal or external source, is internally divided by ‘4’ to cycle, while the decode and execute take another
generate four non-overlapping quadrature clocks (Q1, instruction cycle. However, due to the pipelining, each
Q2, Q3 and Q4). Internally, the PC is incremented on instruction effectively executes in one cycle. If an
every Q1; the instruction is fetched from the program instruction causes the PC to change (e.g., GOTO), then
memory and latched into the Instruction Register (IR) two cycles are required to complete the instruction
during Q4. The instruction is decoded and executed (Example 6-3).
during the following Q1 through Q4. Figure 6-4 A fetch cycle begins with the PC incrementing in Q1.
illustrates the clocks and instruction execution flow.
In the execution cycle, the fetched instruction is latched
into the IR in cycle, Q1. This instruction is then decoded
and executed during the Q2, Q3 and Q4 cycles. Data
memory is read during Q2 (operand read) and written
during Q4 (destination write).

FIGURE 6-4: CLOCK/INSTRUCTION CYCLE

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
Q1
Q2 Internal
Phase
Q3 Clock
Q4
PC PC PC + 2 PC + 4
OSC2/CLKO
(RC mode)
Execute INST (PC – 2)
Fetch INST (PC) Execute INST (PC)
Fetch INST (PC + 2) Execute INST (PC + 2)
Fetch INST (PC + 4)

EXAMPLE 6-3: INSTRUCTION PIPELINE FLOW

TCY0 TCY1 TCY2 TCY3 TCY4 TCY5

1. MOVLW 55h Fetch 1 Execute 1
2. MOVWF PORTB Fetch 2 Execute 2
3. BRA SUB_1 Fetch 3 Execute 3
4. BSF PORTA, BIT3 (Forced NOP) Fetch 4 Flush (NOP)
5. Instruction @ address SUB_1 Fetch SUB_1 Execute SUB_1

Note: All instructions are single-cycle, except for any program branches. These take two cycles since the
fetch instruction is “flushed” from the pipeline while the new instruction is being fetched and then
executed.

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 PIC18F47J53 FAMILY
6.2.3 INSTRUCTIONS IN PROGRAM The CALL and GOTO instructions have the absolute
MEMORY program memory address embedded into the instruc-
tion. Since instructions are always stored on word
The program memory is addressed in bytes. Instruc-
boundaries, the data contained in the instruction is a
tions are stored as 2 bytes or 4 bytes in program
word address. The word address is written to PC<20:1>,
memory. The Least Significant Byte (LSB) of an
which accesses the desired byte address in program
instruction word is always stored in a program memory
memory. Instruction #2 in Figure 6-5 displays how the
location with an even address (LSB = 0). To maintain
instruction, GOTO 0006h, is encoded in the program
alignment with instruction boundaries, the PC
memory. Program branch instructions, which encode a
increments in steps of 2 and the LSB will always read
relative address offset, operate in the same manner. The
‘0’ (see Section 6.1.3 “Program Counter”).
offset value stored in a branch instruction represents the
Figure 6-5 provides an example of how instruction number of single-word instructions that the PC will be
words are stored in the program memory. offset by. Section 29.0 “Instruction Set Summary”
provides further details of the instruction set.

FIGURE 6-5: INSTRUCTIONS IN PROGRAM MEMORY

Word Address
LSB = 1 LSB = 0 
Program Memory 000000h
Byte Locations  000002h
000004h
000006h
Instruction 1: MOVLW 055h 0Fh 55h 000008h
Instruction 2: GOTO 0006h EFh 03h 00000Ah
F0h 00h 00000Ch
Instruction 3: MOVFF 123h, 456h C1h 23h 00000Eh
F4h 56h 000010h
000012h
000014h

6.2.4 TWO-WORD INSTRUCTIONS used by the instruction sequence. If the first word is
skipped for some reason and the second word is
The standard PIC18 instruction set has four two-word
executed by itself, a NOP is executed instead. This is
instructions: CALL, MOVFF, GOTO and LSFR. In all
necessary for cases when the two-word instruction is
cases, the second word of the instructions always has
preceded by a conditional instruction that changes the
‘1111’ as its four Most Significant bits (MSbs); the other
PC. Example 6-4 illustrates how this works.
12 bits are literal data, usually a data memory address.
The use of ‘1111’ in the 4 MSbs of an instruction Note: See Section 6.5 “Program Memory and
specifies a special form of NOP. If the instruction is the Extended Instruction Set” for infor-
executed in proper sequence immediately after the first mation on two-word instructions in the
word, the data in the second word is accessed and extended instruction set.

EXAMPLE 6-4: TWO-WORD INSTRUCTIONS

CASE 1:
Object Code Source Code
0110 0110 0000 0000 TSTFSZ REG1 ; is RAM location 0?
1100 0001 0010 0011 MOVFF REG1, REG2 ; No, skip this word
1111 0100 0101 0110 ; Execute this word as a NOP
0010 0100 0000 0000 ADDWF REG3 ; continue code
CASE 2:
Object Code Source Code
0110 0110 0000 0000 TSTFSZ REG1 ; is RAM location 0?
1100 0001 0010 0011 MOVFF REG1, REG2 ; Yes, execute this word
1111 0100 0101 0110 ; 2nd word of instruction
0010 0100 0000 0000 ADDWF REG3 ; continue code

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PIC18F47J53 FAMILY
6.3 Data Memory Organization 6.3.1 USB RAM
All 3.8 Kbytes of the GPRs implemented on the
Note: The operation of some aspects of data
PIC18F47J53 family devices can be accessed simulta-
memory are changed when the PIC18
neously by both the microcontroller core and the Serial
extended instruction set is enabled. See
Interface Engine (SIE) of the USB module. The SIE
Section 6.6 “Data Memory and the
uses a dedicated USB DMA engine to store any
Extended Instruction Set” for more
incoming data packets (OUT/SETUP) directly into the
information.
main system data memory.
The data memory in PIC18 devices is implemented as For IN data packets, the SIE can directly read the
static RAM. Each register in the data memory has a contents of general purpose SRAM and uses it to
12-bit address, allowing up to 4096 bytes of data create USB data packets that are sent to the host.
memory. The memory space is divided into as many as
16 banks that contain 256 bytes each. The Note: IN and OUT are always from the USB
PIC18F47J53 family implements all available banks host's perspective.
and provides 3.8 Kbytes of data memory available to
SRAM Bank 13 (D00h-DFFh) is unique. In addition to
the user. Figure 6-6 provides the data memory
being accessible by both the microcontroller core and
organization for the devices.
the USB module, the SIE uses a portion of Bank 13 as
The data memory contains Special Function Registers Special Function Registers (SFRs). These SFRs
(SFRs) and General Purpose Registers (GPRs). The compose the Buffer Descriptor Table (BDT).
SFRs are used for control and status of the controller
When the USB module is enabled, the BDT registers
and peripheral functions, while GPRs are used for data
are used to control the behavior of the USB DMA oper-
storage and scratchpad operations in the user’s
ation for each of the enabled endpoints. The exact
application. Any read of an unimplemented location will
number of SRAM locations that are used for the BDT
read as ‘0’s.
depends on how many endpoints are enabled and what
The instruction set and architecture allow operations USB Ping-Pong mode is used. For more details, see
across all banks. The entire data memory may be Section 23.3 “USB RAM”.
accessed by Direct, Indirect or Indexed Addressing
When the USB module is disabled, these SRAM loca-
modes. Addressing modes are discussed later in this
tions behave like any other GPR location. When the
section.
USB module is disabled, these locations may be used
To ensure that commonly used registers (select SFRs for any general purpose.
and select GPRs) can be accessed in a single cycle,
PIC18 devices implement an Access Bank. This is a
256-byte memory space that provides fast access to
select SFRs and the lower portion of GPR Bank 0 with-
out using the BSR. Section 6.3.3 “Access Bank”
provides a detailed description of the Access RAM.

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 PIC18F47J53 FAMILY
6.3.2 BANK SELECT REGISTER Because up to 16 registers can share the same
low-order address, the user must always be careful to
Large areas of data memory require an efficient
ensure that the proper bank is selected before perform-
addressing scheme to make rapid access to any
ing a data read or write. For example, writing what
address possible. Ideally, this means that an entire
should be program data to an 8-bit address of F9h
address does not need to be provided for each read or
while the BSR is 0Fh, will end up resetting the PC.
write operation. For PIC18 devices, this is accom-
plished with a RAM banking scheme. This divides the While any bank can be selected, only those banks that
memory space into 16 contiguous banks of 256 bytes. are actually implemented can be read or written to.
Depending on the instruction, each location can be Writes to unimplemented banks are ignored, while
addressed directly by its full 12-bit address, or an 8-bit reads from unimplemented banks will return ‘0’s. Even
low-order address and a 4-bit Bank Pointer. so, the STATUS register will still be affected as if the
operation was successful. The data memory map in
Most instructions in the PIC18 instruction set make use
Figure 6-6 indicates which banks are implemented.
of the Bank Pointer, known as the Bank Select Register
(BSR). This SFR holds the 4 MSbs of a location’s In the core PIC18 instruction set, only the MOVFF
address; the instruction itself includes the 8 LSbs. Only instruction fully specifies the 12-bit address of the
the four lower bits of the BSR are implemented source and target registers. This instruction ignores the
(BSR<3:0>). The upper four bits are unused; they will BSR completely when it executes. All other instructions
always read ‘0’ and cannot be written to. The BSR can include only the low-order address as an operand and
be loaded directly by using the MOVLB instruction. must use either the BSR or the Access Bank to locate
their target registers.
The value of the BSR indicates the bank in data
memory. The 8 bits in the instruction show the location
in the bank and can be thought of as an offset from the
bank’s lower boundary. The relationship between the
BSR’s value and the bank division in data memory is
illustrated in Figure 6-7.

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PIC18F47J53 FAMILY
FIGURE 6-6: DATA MEMORY MAP FOR PIC18F47J53 FAMILY DEVICES
BSR3:BSR0 When a = 0:
Data Memory Map
The BSR is ignored and the
00h 000h Access Bank is used.
(1)
= 0000 Access RAM The first 96 bytes are general
Bank 0 05Fh
(1) 060h purpose RAM (from Bank 0).
GPR
FFh 0FFh The remaining 160 bytes are
= 0001 00h 100h
(1) Special Function Registers
Bank 1 GPR (from Bank 15).
FFh 1FFh
00h 200h
= 0010 When a = 1:
Bank 2 GPR(1)
FFh 2FFh The BSR specifies the bank
00h 300h used by the instruction.
= 0011
Bank 3 GPR(1)
FFh 3FFh
00h 400h
= 0100
Bank 4 GPR(1)
FFh 4FFh
00h 500h
= 0101
Bank 5 GPR(1)
FFh 5FFh
00h 600h
= 0110
Bank 6 GPR(1)
FFh 6FFh Access Bank
00h 700h 00h
= 0111
Bank 7 GPR(1) Access RAM Low
5Fh
FFh 7FFh Access RAM High 60h
00h 800h
= 1000 (SFRs)
Bank 8 GPR(1) FFh
FFh 8FFh
= 1001 00h 900h
Bank 9 GPR(1)
FFh 9FFh
00h A00h
= 1010
Bank 10 GPR(1)
FFh AFFh
00h B00h
= 1011
Bank 11 GPR(1)
FFh BFFh
00h C00h
= 1100 GPR (1)
Bank 12
FFh CFFh
00h D00h
= 1101 GPR, BDT(1)
Bank 13
FFh DFFh
00h E00h
= 1110 GPR(1)
Bank 14 EBFh
C0h EC0h
Non-Access SFR(2)
FFh EFFh
= 1111 00h F00h
Bank 15 Non-Access SFR(2)
60h F5Fh
Access SFRs
FFh FFFh
Note 1: These banks also serve as RAM buffers for USB operation. See Section 6.3.1 “USB RAM” for more information.
2: Addresses, EC0h through F5Fh, are not part of the Access Bank. Either the BANKED or the MOVFF instruction should
be used to access these SFRs.

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 PIC18F47J53 FAMILY
FIGURE 6-7: USE OF THE BANK SELECT REGISTER (DIRECT ADDRESSING)

BSR(1)
Data Memory From Opcode(2)
7 0 000h 00h 7 0
0 0 0 0 0 0 1 0 Bank 0 11 11 11 11 11 1 1 1
FFh
100h 00h
Bank 1
Bank Select(2) 200h FFh
00h
Bank 2
300h FFh
00h

Bank 3
through
Bank 13

FFh
E00h
00h
Bank 14
F00h FFh
00h
Bank 15
FFFh FFh

Note 1: The Access RAM bit of the instruction can be used to force an override of the selected bank (BSR<3:0>) to
the registers of the Access Bank.
2: The MOVFF instruction embeds the entire 12-bit address in the instruction.

6.3.3 ACCESS BANK Using this “forced” addressing allows the instruction to
operate on a data address in a single cycle without
While the use of the BSR with an embedded 8-bit
updating the BSR first. For 8-bit addresses of 60h and
address allows users to address the entire range of
above, this means that users can evaluate and operate
data memory, it also means that the user must always
on SFRs more efficiently. The Access RAM below 60h
ensure that the correct bank is selected. Otherwise,
is a good place for data values that the user might need
data may be read from or written to the wrong location.
to access rapidly, such as immediate computational
This can be disastrous if a GPR is the intended target
results or common program variables. Access RAM
of an operation, but an SFR is written to instead.
also allows for faster and more code efficient context
Verifying and/or changing the BSR for each read or
saving and switching of variables.
write to data memory can become very inefficient.
The mapping of the Access Bank is slightly different
To streamline access for the most commonly used data
when the extended instruction set is enabled (XINST
memory locations, the data memory is configured with
Configuration bit = 1). This is discussed in more detail
an Access Bank, which allows users to access a
in Section 6.6.3 “Mapping the Access Bank in
mapped block of memory without specifying a BSR.
Indexed Literal Offset Mode”.
The Access Bank consists of the first 96 bytes of
memory (00h-5Fh) in Bank 0 and the last 160 bytes of
6.3.4 GENERAL PURPOSE
memory (60h-FFh) in Bank 15. The lower half is known
REGISTER FILE
as the Access RAM and is composed of GPRs. The
upper half is where the device’s SFRs are mapped. PIC18 devices may have banked memory in the GPR
These two areas are mapped contiguously in the area. This is data RAM, which is available for use by all
Access Bank and can be addressed in a linear fashion instructions. GPRs start at the bottom of Bank 0
by an 8-bit address (Figure 6-6). (address 000h) and grow upward toward the bottom of
the SFR area. GPRs are not initialized by a POR and
The Access Bank is used by core PIC18 instructions
are unchanged on all other Resets.
that include the Access RAM bit (the ‘a’ parameter in
the instruction). When ‘a’ is equal to ‘1’, the instruction
uses the BSR and the 8-bit address included in the
opcode for the data memory address. When ‘a’ is ‘0’,
however, the instruction is forced to use the Access
Bank address map; the current value of the BSR is
ignored entirely.

 2010 Microchip Technology Inc. Preliminary DS39964B-page 91

PIC18F47J53 FAMILY
6.3.5 SPECIAL FUNCTION REGISTERS ALU’s STATUS register is described later in this section.
The SFRs are registers used by the CPU and periph- Registers related to the operation of the peripheral
eral modules for controlling the desired operation of the features are described in the chapter for that peripheral.
device. These registers are implemented as static The SFRs are typically distributed among the
RAM. SFRs start at the top of data memory (FFFh) and peripherals whose functions they control. Unused SFR
extend downward to occupy more than the top half of locations are unimplemented and read as ‘0’s
Bank 15 (F40h to FFFh). Table 6-2, Table 6-3 and
Note: The SFRs located between EB0h and
Table 6-4 provide a list of these registers.
F5Fh are not part of the Access Bank.
The SFRs can be classified into two sets: those Either BANKED instructions (using BSR) or
associated with the “core” device functionality (ALU, the MOVFF instruction should be used to
Resets and interrupts) and those related to the access these locations. When program-
peripheral functions. The Reset and Interrupt registers ming in MPLAB® C18, the compiler will
are described in their corresponding chapters, while the automatically use the appropriate
addressing mode.

TABLE 6-2: ACCESS BANK SPECIAL FUNCTION REGISTER MAP

Address Name Address Name Address Name Address Name Address Name
(1)
FFFh TOSU FDFh INDF2 FBFh PSTR1CON F9Fh IPR1 F7Fh SPBRGH1
FFEh TOSH FDEh POSTINC2(1) FBEh ECCP1AS F9Eh PIR1 F7Eh BAUDCON1
FFDh TOSL FDDh POSTDEC2(1) FBDh ECCP1DEL F9Dh PIE1 F7Dh SPBRGH2
FFCh STKPTR FDCh PREINC2(1) FBCh CCPR1H F9Ch RCSTA2 F7Ch BAUDCON2
FFBh PCLATU FDBh PLUSW2(1) FBBh CCPR1L F9Bh OSCTUNE F7Bh TMR3H
FFAh PCLATH FDAh FSR2H FBAh CCP1CON F9Ah T1GCON F7Ah TMR3L
FF9h PCL FD9h FSR2L FB9h PSTR2CON F99h IPR5 F79h T3CON
FF8h TBLPTRU FD8h STATUS FB8h ECCP2AS F98h PIR5 F78h TMR4
FF7h TBLPTRH FD7h TMR0H FB7h ECCP2DEL F97h T3GCON F77h PR4
FF6h TBLPTRL FD6h TMR0L FB6h CCPR2H F96h TRISE F76h T4CON
FF5h TABLAT FD5h T0CON FB5h CCPR2L F95h TRISD F75h SSP2BUF
FF4h PRODH FD4h —(5) FB4h CCP2CON F94h TRISC F74h SSP2ADD(3)
FF3h PRODL FD3h OSCCON FB3h CTMUCONH F93h TRISB F73h SSP2STAT
FF2h INTCON FD2h CM1CON FB2h CTMUCONL F92h TRISA F72h SSP2CON1
FF1h INTCON2 FD1h CM2CON FB1h CTMUICON F91h PIE5 F71h SSP2CON2
FF0h INTCON3 FD0h RCON FB0h SPBRG1 F90h IPR4 F70h CMSTAT
FEFh INDF0(1) FCFh TMR1H FAFh RCREG1 F8Fh PIR4 F6Fh PMADDRH(2,4)
FEEh POSTINC0(1) FCEh TMR1L FAEh TXREG1 F8Eh PIE4 F6Eh PMADDRL(2,4)
(1) (2)
FEDh POSTDEC0 FCDh T1CON FADh TXSTA1 F8Dh LATE F6Dh PMDIN1H(2)
(1) (2)
FECh PREINC0 FCCh TMR2 FACh RCSTA1 F8Ch LATD F6Ch PMDIN1L(2)
(1)
FEBh PLUSW0 FCBh PR2 FABh SPBRG2 F8Bh LATC F6Bh TXADDRL
FEAh FSR0H FCAh T2CON FAAh RCREG2 F8Ah LATB F6Ah TXADDRH
FE9h FSR0L FC9h SSP1BUF FA9h TXREG2 F89h LATA F69h RXADDRL
FE8h WREG FC8h SSP1ADD(3) FA8h TXSTA2 F88h DMACON1 F68h RXADDRH
FE7h INDF1(1) FC7h SSP1STAT FA7h EECON2 F87h OSCCON2(5) F67h DMABCL
(1)
FE6h POSTINC1 FC6h SSP1CON1 FA6h EECON1 F86h DMACON2 F66h DMABCH
FE5h POSTDEC1(1) FC5h SSP1CON2 FA5h IPR3 F85h HLVDCON F65h UCON
FE4h PREINC1(1) FC4h ADRESH FA4h PIR3 F84h PORTE(2) F64h USTAT
FE3h PLUSW1(1) FC3h ADRESL FA3h PIE3 F83h PORTD(2) F63h UEIR
FE2h FSR1H FC2h ADCON0 FA2h IPR2 F82h PORTC F62h UIR
FE1h FSR1L FC1h ADCON1 FA1h PIR2 F81h PORTB F61h UFRMH
FE0h BSR FC0h WDTCON FA0h PIE2 F80h PORTA F60h UFRML
Note 1: This is not a physical register.
2: This register is not available on 28-pin devices.
3: SSPxADD and SSPxMSK share the same address.
4: PMADDRH and PMDOUTH share the same address and PMADDRL and PMDOUTL share the same address.
PMADDRx is used in Master modes and PMDOUTx is used in Slave modes.
5: Reserved: Do not write to this location.

DS39964B-page 92 Preliminary  2010 Microchip Technology Inc.

 PIC18F47J53 FAMILY

TABLE 6-3: NON-ACCESS BANK SPECIAL FUNCTION REGISTER MAP

Address Name Address Name Address Name Address Name Address Name Address Name

F5Fh PMCONH F3Fh RTCCFG F1Fh PR6 EFFh RPINR24 EDFh — EBFh PPSCON
F5Eh PMCONL F3Eh RTCCAL F1Eh T6CON EFEh RPINR23 EDEh — EBEh —
F5Dh PMMODEH F3Dh REFOCON F1Dh TMR8 EFDh RPINR22 EDDh — EBDh —
F5Ch PMMODEL F3Ch PADCFG1 F1Ch PR8 EFCh RPINR21 EDCh — EBCh PMDIS3
F5Bh PMDOUT2H F3Bh RTCVALH F1Bh T8CON EFBh — EDBh — EBBh PMDIS2
F5Ah PMDOUT2L F3Ah RTCVALL F1Ah PSTR3CON EFAh — EDAh — EBAh PMDIS1
F59h PMDIN2H F39h UCFG F19h ECCP3AS EF9h — ED9h — EB9h PMDIS0
F58h PMDIN2L F38h UADDR F18h ECCP3DEL EF8h RPINR17 ED8h RPOR24 EB8h ADCTRIG
F57h PMEH F37h UEIE F17h CCPR3H EF7h RPINR16 ED7h RPOR23 EB7h —
F56h PMEL F36h UIE F16h CCPR3L EF6h — ED6h RPOR22 EB6h —
F55h PMSTATH F35h UEP15 F15h CCP3CON EF5h — ED5h RPOR21 EB5h —
F54h PMSTATL F34h UEP14 F14h CCPR4H EF4h RPINR14 ED4h RPOR20 EB4h —
F53h CVRCON F33h UEP13 F13h CCPR4L EF3h RPINR13 ED3h RPOR19 EB3h —
F52h CCPTMRS0 F32h UEP12 F12h CCP4CON EF2h RPINR12 ED2h RPOR18 EB2h —
F51h CCPTMRS1 F31h UEP11 F11h CCPR5H EF1h — ED1h RPOR17 EB1h —
F50h CCPTMRS2 F30h UEP10 F10h CCPR5L EF0h — ED0h — EB0h —
F4Fh DSGPR1 F2Fh UEP9 F0Fh CCP5CON EEFh — ECFh —
F4Eh DSGPR0 F2Eh UEP8 F0Eh CCPR6H EEEh — ECEh —
F4Dh DSCONH F2Dh UEP7 F0Dh CCPR6L EEDh — ECDh RPOR13
F4Ch DSCONL F2Ch UEP6 F0Ch CCP6CON EECh — ECCh RPOR12
F4Bh DSWAKEH F2Bh UEP5 F0Bh CCPR7H EEBh — ECBh RPOR11
F4Ah DSWAKEL F2Ah UEP4 F0Ah CCPR7L EEAh RPINR9 ECAh RPOR10
F49h ANCON1 F29h UEP3 F09h CCP7CON EE9h RPINR8 EC9h RPOR9
F48h ANCON0 F28h UEP2 F08h CCPR8H EE8h RPINR7 EC8h RPOR8
F47h ALRMCFG F27h UEP1 F07h CCPR8L EE7h RPINR15 EC7h RPOR7
F46h ALRMRPT F26h UEP0 F06h CCP8CON EE6h RPINR6 EC6h RPOR6
F45h ALRMVALH F25h CM3CON F05h CCPR9H EE5h — EC5h RPOR5
F44h ALRMVALL F24h TMR5H F04h CCPR9L EE4h RPINR4 EC4h RPOR4
F43h — F23h TMR5L F03h CCP9CON EE3h RPINR3 EC3h RPOR3
F42h ODCON1 F22h T5CON F02h CCPR10H EE2h RPINR2 EC2h RPOR2
F41h ODCON2 F21h T5GCON F01h CCPR10L EE1h RPINR1 EC1h RPOR1
F40h ODCON3 F20h TMR6 F00h CCP10CON EE0h — EC0h RPOR0

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PIC18F47J53 FAMILY
6.3.5.1 Context Defined SFRs • PMADDRH/L and PMDOUT2H/L: In this case,
these named buffer pairs are actually the same
There are several registers that share the same
physical registers. The Parallel Master Port (PMP)
address in the SFR space. The register's definition and
module’s operating mode determines what func-
usage depends on the operating mode of its associated
tion the registers take on. See Section 11.1.2
peripheral. These registers are:
“Data Registers” for additional details.
• SSPxADD and SSPxMSK: These are two
separate hardware registers, accessed through a
single SFR address. The operating mode of the
MSSP modules determines which register is
being accessed. See Section 20.5.3.4 “7-Bit
Address Masking Mode” for additional details.

TABLE 6-4: REGISTER FILE SUMMARY (PIC18F47J53 FAMILY)

Value on
Addr. File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
POR, BOR

FFFh TOSU — — — Top-of-Stack Upper Byte (TOS<20:16>) ---0 0000

FFEh TOSH Top-of-Stack High Byte (TOS<15:8>) 0000 0000
FFDh TOSL Top-of-Stack Low Byte (TOS<7:0>) 0000 0000
FFCh STKPTR STKFUL STKUNF — SP4 SP3 SP2 SP1 SP0 00-0 0000
FFBh PCLATU — — bit 21 Holding Register for PC<20:16> ---0 0000
FFAh PCLATH Holding Register for PC<15:8> 0000 0000
FF9h PCL PC Low Byte (PC<7:0>) 0000 0000
FF8h TBLPTRU — — bit 21 Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) --00 0000
FF7h TBLPTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>) 0000 0000
FF6h TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>) 0000 0000
FF5h TABLAT Program Memory Table Latch 0000 0000
FF4h PRODH Product Register High Byte xxxx xxxx
FF3h PRODL Product Register Low Byte xxxx xxxx
FF2h INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x
FF1h INTCON2 RBPU INTEDG0 INTEDG1 INTEDG2 INTEDG3 TMR0IP INT3IP RBIP 1111 1111
FF0h INTCON3 INT2IP INT1IP INT3IE INT2IE INT1IE INT3IF INT2IF INT1IF 1100 0000
FEFh INDF0 Uses contents of FSR0 to address data memory – value of FSR0 not changed (not a physical register) N/A
FEEh POSTINC0 Uses contents of FSR0 to address data memory – value of FSR0 post-incremented (not a physical register) N/A
FEDh POSTDEC0 Uses contents of FSR0 to address data memory – value of FSR0 post-decremented (not a physical register) N/A
FECh PREINC0 Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) N/A
FEBh PLUSW0 Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) – N/A
value of FSR0 offset by W
FEAh FSR0H — — — — Indirect Data Memory Address Pointer 0 High Byte ---- xxxx
FE9h FSR0L Indirect Data Memory Address Pointer 0 Low Byte xxxx xxxx
FE8h WREG Working Register xxxx xxxx
FE7h INDF1 Uses contents of FSR1 to address data memory – value of FSR1 not changed (not a physical register) N/A
FE6h POSTINC1 Uses contents of FSR1 to address data memory – value of FSR1 post-incremented (not a physical register) N/A
FE5h POSTDEC1 Uses contents of FSR1 to address data memory – value of FSR1 post-decremented (not a physical register) N/A
FE4h PREINC1 Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register) N/A
FE3h PLUSW1 Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register) – N/A
value of FSR1 offset by W
FE2h FSR1H — — — — Indirect Data Memory Address Pointer 1 High Byte ---- xxxx
FE1h FSR1L Indirect Data Memory Address Pointer 1 Low Byte xxxx xxxx
FE0h BSR — — — — Bank Select Register ---- 0000
FDFh INDF2 Uses contents of FSR2 to address data memory – value of FSR2 not changed (not a physical register) N/A
FDEh POSTINC2 Uses contents of FSR2 to address data memory – value of FSR2 post-incremented (not a physical register) N/A
FDDh POSTDEC2 Uses contents of FSR2 to address data memory – value of FSR2 post-decremented (not a physical register) N/A
Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition, r = reserved, do not modify
Note 1: Implemented only for 44-pin devices (PIC18F46J53, PIC18F47J53, PIC18LF46J53 and PIC18LF47J53).
2: Implemented only for 28-pin devices (PIC18F26J53, PIC18F27J53, PIC18LF26J53 and PIC18LF27J53).
3: Implemented only for devices with 128 Kbyte of program memory (PIC18F27J53, PIC18F47J53, PIC18LF27J53 and PIC18LF47J53).

DS39964B-page 94 Preliminary  2010 Microchip Technology Inc.

 PIC18F47J53 FAMILY
TABLE 6-4: REGISTER FILE SUMMARY (PIC18F47J53 FAMILY) (CONTINUED)
Value on
Addr. File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
POR, BOR

FDCh PREINC2 Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) N/A
FDBh PLUSW2 Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) – N/A
value of FSR2 offset by W
FDAh FSR2H — — — — Indirect Data Memory Address Pointer 2 High Byte ---- xxxx
FD9h FSR2L Indirect Data Memory Address Pointer 2 Low Byte xxxx xxxx
FD8h STATUS — — — N OV Z DC C ---x xxxx
FD7h TMR0H Timer0 Register High Byte 0000 0000
FD6h TMR0L Timer0 Register Low Byte xxxx xxxx
FD5h T0CON TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 1111 1111
FD3h OSCCON IDLEN IRCF2 IRCF1 IRCF0 OSTS FLTS SCS1 SCS0 0110 q000
FD2h CM1CON CON COE CPOL EVPOL1 EVPOL0 CREF CCH1 CCH0 0001 1111
FD1h CM2CON CON COE CPOL EVPOL1 EVPOL0 CREF CCH1 CCH0 0001 1111
FD0h RCON IPEN — CM RI TO PD POR BOR 0-11 11qq
FCFh TMR1H Timer1 Register High Byte xxxx xxxx
FCEh TMR1L Timer1 Register Low Bytes xxxx xxxx
FCDh T1CON TMR1CS1 TMR1CS0 T1CKPS1 T1CKPS0 T1OSCEN T1SYNC RD16 TMR1ON 0000 0000
FCCh TMR2 Timer2 Register 0000 0000
FCBh PR2 Timer2 Period Register 1111 1111
FCAh T2CON — T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000
FC9h SSP1BUF MSSP1 Receive Buffer/Transmit Register xxxx xxxx
FC8h SSP1ADD MSSP1 Address Register (I2C™ Slave Mode). MSSP1 Baud Rate Reload Register (I2C Master Mode). 0000 0000
FC8h SSP1MSK MSK7 MSK6 MSK5 MSK4 MSK3 MSK2 MSK1 MSK0 ---- ----
FC7h SSP1STAT SMP CKE D/A P S R/W UA BF 1111 1111
FC6h SSP1CON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000
FC5h SSP1CON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000
FC5h SSP1CON2 GCEN ACKSTAT ADMSK5 ADMSK4 ADMSK3 ADMSK2 ADMSK1 SEN 0000 0000
FC4h ADRESH A/D Result Register High Byte xxxx xxxx
FC3h ADRESL A/D Result Register Low Byte xxxx xxxx
FC2h ADCON0 VCFG1 VCFG0 CHS3 CHS2 CHS1 CHS0 GO/DONE ADON 0000 0000
FC1h ADCON1 ADFM ADCAL ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 0000 0000
FC0h WDTCON REGSLP LVDSTAT ULPLVL VBGOE DS ULPEN ULPSINK SWDTEN 1xx0 0000
FBFh PSTR1CON CMPL1 CMPL0 — STRSYNC STRD STRC STRB STRA 00-0 0001
FBEh ECCP1AS ECCP1ASE ECCP1AS2 ECCP1AS1 ECCP1AS0 PSS1AC1 PSS1AC0 PSS1BD1 PSS1BD0 0000 0000
FBDh ECCP1DEL P1RSEN P1DC6 P1DC5 P1DC4 P1DC3 P1DC2 P1DC1 P1DC0 0000 0000
FBCh CCPR1H Capture/Compare/PWM Register 1 High Byte xxxx xxxx
FBBh CCPR1L Capture/Compare/PWM Register 1 Low Byte xxxx xxxx
FBAh CCP1CON P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000
FB9h PSTR2CON CMPL1 CMPL0 — STRSYNC STRD STRC STRB STRA 00-0 0001
FB8h ECCP2AS ECCP2ASE ECCP2AS2 ECCP2AS1 ECCP2AS0 PSS2AC1 PSS2AC0 PSS2BD1 PSS2BD0 0000 0000
FB7h ECCP2DEL P2RSEN P2DC6 P2DC5 P2DC4 P2DC3 P2DC2 P2DC1 P2DC0 0000 0000
FB6h CCPR2H Capture/Compare/PWM Register 2 High Byte xxxx xxxx
FB5h CCPR2L Capture/Compare/PWM Register 2 Low Byte xxxx xxxx
FB4h CCP2CON P2M1 P2M0 DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 0000 0000
FB3h CTMUCONH CTMUEN — CTMUSIDL TGEN EDGEN EDGSEQEN IDISSEN CTTRIG 0-00 0000
FB2h CTMUCONL EDG2POL EDG2SEL1 EDG2SEL0 EDG1POL EDG1SEL1 EDG1SEL0 EDG2STAT EDG1STAT 0000 00xx
FB1h CTMUICON ITRIM5 ITRIM4 ITRIM3 ITRIM2 ITRIM1 ITRIM0 IRNG1 IRNG0 0000 0000
FB0h SPBRG1 EUSART1 Baud Rate Generator Register Low Byte 0000 0000
FAFh RCREG1 EUSART1 Receive Register 0000 0000
Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition, r = reserved, do not modify
Note 1: Implemented only for 44-pin devices (PIC18F46J53, PIC18F47J53, PIC18LF46J53 and PIC18LF47J53).
2: Implemented only for 28-pin devices (PIC18F26J53, PIC18F27J53, PIC18LF26J53 and PIC18LF27J53).
3: Implemented only for devices with 128 Kbyte of program memory (PIC18F27J53, PIC18F47J53, PIC18LF27J53 and PIC18LF47J53).

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PIC18F47J53 FAMILY
TABLE 6-4: REGISTER FILE SUMMARY (PIC18F47J53 FAMILY) (CONTINUED)
Value on
Addr. File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
POR, BOR

FAEh TXREG1 EUSART1 Transmit Register xxxx xxxx

FADh TXSTA1 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010
FACh RCSTA1 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x
FABh SPBRG2 EUSART2 Baud Rate Generator Register Low Byte 0000 0000
FAAh RCREG2 EUSART2 Receive Register 0000 0000
FA9h TXREG2 EUSART2 Transmit Register 0000 0000
FA8h TXSTA2 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010
FA7h EECON2 Flash Self-Program Control Register (not a physical register) ---- ----
FA6h EECON1 — — WPROG FREE WRERR WREN WR — --00 x00-
FA5h IPR3 SSP2IP BCL2IP RC2IP TX2IP TMR4IP CTMUIP TMR3GIP RTCCIP 1111 1111
FA4h PIR3 SSP2IF BCL2IF RC2IF TX2IF TMR4IF CTMUIF TMR3GIF RTCCIF 0000 0000
FA3h PIE3 SSP2IE BCL2IE RC2IE TX2IE TMR4IE CTMUIE TMR3GIE RTCCIE 0000 0000
FA2h IPR2 OSCFIP CM2IP CM1IP USBIP BCL1IP HLVDIP TMR3IP CCP2IP 1111 1111
FA1h PIR2 OSCFIF CM2IF CM1IF USBIF BCL1IF HLVDIF TMR3IF CCP2IF 0000 0000
FA0h PIE2 OSCFIE CM2IE CM1IE USBIE BCL1IE HLVDIE TMR3IE CCP2IE 0000 0000
F9Fh IPR1 PMPIP(1) ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 1111 1111
F9Eh PIR1 PMPIF(1) ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 0000 0000
F9Dh PIE1 PMPIE(1) ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 0000 0000
F9Ch RCSTA2 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x
F9Bh OSCTUNE INTSRC PLLEN TUN5 TUN4 TUN3 TUN2 TUN1 TUN0 0000 0000
F9Ah T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO/ T1GVAL T1GSS1 T1GSS0 0000 0x00
T1DONE
F99h IPR5 — — CM3IP TMR8IP TMR6IP TMR5IP TMR5GIP TMR1GIP --11 1111
F98h PIR5 — — CM3IF TMR8IF TMR6IF TMR5IF TMR5GIF TMR1GIF --00 0000
F97h T3GCON TMR3GE T3GPOL T3GTM T3GSPM T3GGO/ T3GVAL T3GSS1 T3GSS0 0000 0x00
T3DONE
F96h TRISE(1) RDPU REPU — — — TRISE2 TRISE1 TRISE0 00-- -111
F95h TRISD(1) TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 1111 1111
F94h TRISC TRISC7 TRISC6 — — — TRISC2 TRISC1 TRISC0 1111 1111
F93h TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111
F92h TRISA TRISA7 TRISA6 TRISA5 — TRISA3 TRISA2 TRISA1 TRISA0 111- 1111
F91h PIE5 — — CM3IE TMR8IE TMR6IE TMR5IE TMR5GIE TMR1GIE --00 0000
F90h IPR4 CCP10IP CCP9IP CCP8IP CCP7IP CCP6IP CCP5IP CCP4IP CCP3IP 1111 1111
F8Fh PIR4 CCP10IF CCP9IF CCP8IF CCP7IF CCP6IF CCP5IF CCP4IF CCP3IF 0000 0000
F8Eh PIE4 CCP10IE CCP9IE CCP8IE CCP7IE CCP6IE CCP5IE CCP4IE CCP3IE 0000 0000
F8Dh LATE(1) — — — — — LATE2 LATE1 LATE0 ---- -xxx
F8Ch LATD(1) LATD7 LATD6 LATD5 LATD4 LATD3 LATD2 LATD1 LATD0 xxxx xxxx
F8Bh LATC LATC7 LATC6 — — — LATC2 LATC1 LATC0 xxxx xxxx
F8Ah LATB LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 xxxx xxxx
F89h LATA LATA7 LATA6 LATA5 — LATA3 LATA2 LATA1 LATA0 xxx- xxxx
F88h DMACON1 SSCON1 SSCON0 TXINC RXINC DUPLEX1 DUPLEX0 DLYINTEN DMAEN 0000 0000
F87h OSCCON2 — SOSCRUN — SOSCDRV SOSCGO PRISD — — -0-1 01--
F86h DMACON2 DLYCYC3 DLYCYC2 DLYCYC1 DLYCYC0 INTLVL3 INTLVL2 INTLVL1 INTLVL0 0000 0000
F85h HLVDCON VDIRMAG BGVST IRVST HLVDEN HLVDL3 HLVDL2 HLVDL1 HLVDL0 0000 0000
F84h PORTE(1) — — — — — RE2 RE1 RE0 ---- -xxx
F83h PORTD(1) RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 xxxx xxxx
F82h PORTC RC7 RC6 RC5 RC4 — RC2 RC1 RC0 xxxx xxxx
F81h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx
F80h PORTA RA7 RA6 RA5 — RA3 RA2 RA1 RA0 xxx- xxxx
Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition, r = reserved, do not modify
Note 1: Implemented only for 44-pin devices (PIC18F46J53, PIC18F47J53, PIC18LF46J53 and PIC18LF47J53).
2: Implemented only for 28-pin devices (PIC18F26J53, PIC18F27J53, PIC18LF26J53 and PIC18LF27J53).
3: Implemented only for devices with 128 Kbyte of program memory (PIC18F27J53, PIC18F47J53, PIC18LF27J53 and PIC18LF47J53).

DS39964B-page 96 Preliminary  2010 Microchip Technology Inc.

 PIC18F47J53 FAMILY
TABLE 6-4: REGISTER FILE SUMMARY (PIC18F47J53 FAMILY) (CONTINUED)
Value on
Addr. File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
POR, BOR

F7Fh SPBRGH1 EUSART1 Baud Rate Generator High Byte 0000 0000
F7Eh BAUDCON1 ABDOVF RCIDL RXDTP TXCKP BRG16 — WUE ABDEN 0100 0-00
F7Dh SPBRGH2 EUSART2 Baud Rate Generator High Byte 0000 0000
F7Ch BAUDCON2 ABDOVF RCIDL RXDTP TXCKP BRG16 — WUE ABDEN 0100 0-00
F7Bh TMR3H Timer3 Register High Byte xxxx xxxx
F7Ah TMR3L Timer3 Register Low Byte xxxx xxxx
F79h T3CON TMR3CS1 TMR3CS0 T3CKPS1 T3CKPS0 T3OSCEN T3SYNC RD16 TMR3ON 0000 0000
F78h TMR4 Timer4 Register 0000 0000
F77h PR4 Timer4 Period Register 1111 1111
F76h T4CON — T4OUTPS3 T4OUTPS2 T4OUTPS1 T4OUTPS0 TMR4ON T4CKPS1 T4CKPS0 -000 0000
F75h SSP2BUF MSSP2 Receive Buffer/Transmit Register xxxx xxxx
F74h SSP2ADD MSSP2 Address Register (I2C™ Slave Mode). MSSP2 Baud Rate Reload Register (I2C Master Mode). ---- ----
F74h SSP2MSK MSK7 MSK6 MSK5 MSK4 MSK3 MSK2 MSK1 MSK0 0000 0000
F73h SSP2STAT SMP CKE D/A P S R/W UA BF 1111 1111
F72h SSP2CON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000
F71h SSP2CON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000
ADMSK5 ADMSK4 ADMSK3 ADMSK2 ADMSK1
F70h CMSTAT — — — — — COUT3 COUT2 COUT1 ---- -111
F6Fh PMADDRH/ — CS1 Parallel Master Port Address High Byte -000 0000
PMDOUT1H(1)
Parallel Port Out Data High Byte (Buffer 1) 0000 0000
F6Eh PMADDRL/ Parallel Master Port Address Low Byte/ 0000 0000
PMDOUT1L(1) Parallel Port Out Data Low Byte (Buffer 1)
F6Dh PMDIN1H(1) Parallel Port In Data High Byte (Buffer 1) 0000 0000
F6Ch PMDIN1L(1) Parallel Port In Data Low Byte (Buffer 1) 0000 0000
F6Bh TXADDRL SPI DMA Transmit Data Pointer Low Byte xxxx xxxx
F6Ah TXADDRH — — — — SPI DMA Transmit Data Pointer High Byte ---- xxxx
F69h RXADDRL SPI DMA Receive Data Pointer Low Byte xxxx xxxx
F68h RXADDRH — — — — SPI DMA Receive Data Pointer High Byte ---- xxxx
F67h DMABCL SPI DMA Byte Count Low Byte xxxx xxxx
F66h DMABCH — — — — — — SPI DMA Byte Count High ---- --xx
Byte
F65h UCON(1) — PPBRST SE0 PKTDIS USBEN RESUME SUSPND — -0x0 000-
F64h USTAT — ENDP3 ENDP2 ENDP1 ENDP0 DIR PPBI — -xxx xxx-
F63h UEIR BTSEF — — BTOEF DFN8EF CRC16EF CRC5EF PIDEF 0--0 0000
F62h UIR — SOFIF STALLIF IDLEIF TRNIF ACTVIF UERRIF URSTIF -000 0000
F61h UFRMH — — — — — FRM10 FRM9 FRM8 ---- -xxx
F60h UFRML FRM7 FRM6 FRM5 FRM4 FRM3 FRM2 FRM1 FRM0 xxxx xxxx
F5Fh PMCONH(1) PMPEN — PSIDL ADRMUX1 ADRMUX0 PTBEEN PTWREN PTRDEN 0-00 0000
F5Eh PMCONL(1) CSF1 CSF0 ALP — CS1P BEP WRSP RDSP 000- 0000
F5Dh PMMODEH(1) BUSY IRQM1 IRQM0 INCM1 INCM0 MODE16 MODE1 MODE0 0000 0000
F5Ch PMMODEL(1) WAITB1 WAITB0 WAITM3 WAITM2 WAITM1 WAITM0 WAITE1 WAITE0 0000 0000
F5Bh PMDOUT2H(1) Parallel Port Out Data High Byte (Buffer 2) 0000 0000
F5Ah PMDOUT2L(1) Parallel Port Out Data Low Byte (Buffer 2) 0000 0000
F59h PMDIN2H(1) Parallel Port In Data High Byte (Buffer 2) 0000 0000
F58h PMDIN2L(1) Parallel Port In Data Low Byte (Buffer 2) 0000 0000
F57h PMEH(1) PTEN15 PTEN14 PTEN13 PTEN12 PTEN11 PTEN10 PTEN9 PTEN8 0000 0000
F56h PMEL(1) PTEN7 PTEN6 PTEN5 PTEN4 PTEN3 PTEN2 PTEN1 PTEN0 0000 0000
F55h PMSTATH(1) IBF IBOV — — IB3F IB2F IB1F IB0F 00-- 0000
F54h PMSTATL(1) OBE OBUF — — OB3E OB2E OB1E OB0E 10-- 1111
Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition, r = reserved, do not modify
Note 1: Implemented only for 44-pin devices (PIC18F46J53, PIC18F47J53, PIC18LF46J53 and PIC18LF47J53).
2: Implemented only for 28-pin devices (PIC18F26J53, PIC18F27J53, PIC18LF26J53 and PIC18LF27J53).
3: Implemented only for devices with 128 Kbyte of program memory (PIC18F27J53, PIC18F47J53, PIC18LF27J53 and PIC18LF47J53).

 2010 Microchip Technology Inc. Preliminary DS39964B-page 97

PIC18F47J53 FAMILY
TABLE 6-4: REGISTER FILE SUMMARY (PIC18F47J53 FAMILY) (CONTINUED)
Value on
Addr. File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
POR, BOR

F53h CVRCON CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 0000 0000
F52h CCPTMRS0 C3TSEL1 C3TSEL0 C2TSEL2 C2TSEL1 C2TSEL0 C1TSEL2 C1TSEL1 C1TSEL0 0000 0000
F51h CCPTMRS1 C7TSEL1 C7TSEL0 — C6TSEL0 — C5TSEL0 C4TSEL1 C4TSEL0 00-0 -000
F50h CCPTMRS2 — — — C10TSEL0(3) — C9TSEL0(3) C8TSEL1 C8TSEL0 ---0 -000
F4Fh DSGPR1 Deep Sleep Persistent General Purpose Register (contents retained even in deep sleep) xxxx xxxx
F4Eh DSGPR0 Deep Sleep Persistent General Purpose Register (contents retained even in deep sleep) xxxx xxxx
F4Dh DSCONH DSEN — — — — r DSULPEN RTCWDIS 0--- -000
F4Ch DSCONL — — — — — ULPWDIS DSBOR RELEASE ---- -000
F4Bh DSWAKEH — — — — — — — DSINT0 ---- ---0
F4Ah DSWAKEL DSFLT — DSULP DSWDT DSRTC DSMCLR — DSPOR 0-00 00-1
F49h ANCON1 VBGEN — — PCFG12 PCFG11 PCFG10 PCFG9 PCFG8 0--0 0000
F48h ANCON0 PCFG7(1) PCFG6(1) PCFG5(1) PCFG4 PCFG3 PCFG2 PCFG1 PCFG0 0000 0000
F47h OEDCON ALRMEN CHIME AMASK3 AMASK2 AMASK1 AMASK0 ALRMPTR1 ALRMPTR0 0000 0000
F46h ALRMRPT ARPT7 ARPT6 ARPT5 ARPT4 ARPT3 ARPT2 ARPT1 ARPT0 0000 0000
F45h ALRMVALH Alarm Value High Register Window based on ALRMPTR<1:0> xxxx xxxx
F44h ALRMVALL Alarm Value Low Register Window based on ALRMPTR<1:0> xxxx xxxx
F43h — — — — — — — — — ---- ----
F42h ODCON1 CCP8OD CCP7OD CCP6OD CCP5OD CCP4OD ECCP3OD ECCP2OD ECCP1OD 0000 0000
F41h ODCON2 — — — — CCP10OD CCP9OD U2OD U1OD ---- 0000
F40h ODCON3 — — — — — — SPI2OD SPI1OD ---- --00
F3Fh RTCCFG RTCEN — RTCWREN RTCSYNC HALFSEC RTCOE RTCPTR1 RTCPTR0 0-00 0000
F3Eh RTCCAL CAL7 CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 0000 0000
F3Dh REFOCON ROON — ROSSLP ROSEL RODIV3 RODIV2 RODIV1 RODIV0 0-00 0000
F3Ch PADCFG1 — — — — — RTSECSEL1 RTSECSEL0 PMPTTL(1) ---- -000
F3Bh RTCVALH RTCC Value High Register Window Based on RTCPTR<1:0> 0xxx xxxx
F3Ah RTCVALL RTCC Value Low Register Window Based on RTCPTR<1:0> 0xxx xxxx
F39h UCFG UTEYE UOEMON — UPUEN UTRDIS FSEN PPB1 PPB0 00-0 0000
F38h UADDR — ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0 -000 0000
F37h UEIE BTSEE — — BTOEE DFN8EE CRC16EE CRC5EE PIDEE 0--0 0000
F36h UIE — SOFIE STALLIE IDLEIE TRNIE ACTVIE UERRIE URSTIE -000 0000
F35h UEP15 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000
F34h UEP14 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000
F33h UEP13 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000
F32h UEP12 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000
F31h UEP11 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000
F30h UEP10 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000
F2Fh UEP9 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000
F2Eh UEP8 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000
F2Dh UEP7 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000
F2Ch UEP6 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000
F2Bh UEP5 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000
F2Ah UEP4 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000
F29h UEP3 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000
F28h UEP2 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000
F27h UEP1 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000
F26h UEP0 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000
F25h CM3CON CON COE CPOL EVPOL1 EVPOL0 CREF CCH1 CCH0 0001 1111
F24h TMR5H Timer5 Register High Byte xxxx xxxx
Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition, r = reserved, do not modify
Note 1: Implemented only for 44-pin devices (PIC18F46J53, PIC18F47J53, PIC18LF46J53 and PIC18LF47J53).
2: Implemented only for 28-pin devices (PIC18F26J53, PIC18F27J53, PIC18LF26J53 and PIC18LF27J53).
3: Implemented only for devices with 128 Kbyte of program memory (PIC18F27J53, PIC18F47J53, PIC18LF27J53 and PIC18LF47J53).

DS39964B-page 98 Preliminary  2010 Microchip Technology Inc.

 PIC18F47J53 FAMILY
TABLE 6-4: REGISTER FILE SUMMARY (PIC18F47J53 FAMILY) (CONTINUED)
Value on
Addr. File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
POR, BOR

F23h TMR5L Timer5 Register Low Bytes xxxx xxxx

F22h T5CON TMR5CS1 TMR5CS0 T5CKPS1 T5CKPS0 T5OSCEN T5SYNC RD16 TMR5ON 0000 0000
F21h T5GCON TMR5GE T5GPOL T5GTM T5GSPM T5GGO/ T5GVAL T5GSS1 T5GSS0 0000 0x00
T5DONE
F20h TMR6 Timer6 Register 0000 0000
F1Fh PR6 Timer6 Period Register 1111 1111
F1Eh T6CON — T6OUTPS3 T6OUTPS2 T6OUTPS1 T6OUTPS0 TMR6ON T6CKPS1 T6CKPS0 -000 0000
F1Dh TMR8 Timer8 Register 0000 0000
F1Ch PR8 Timer8 Period Register 1111 1111
F1Bh T8CON — T8OUTPS3 T8OUTPS2 T8OUTPS1 T8OUTPS0 TMR8ON T8CKPS1 T8CKPS0 -000 0000
F1Ah PSTR3CON CMPL1 CMPL0 — STRSYNC STRD STRC STRB STRA 00-0 0001
F19h ECCP3AS ECCP3ASE ECCP3AS2 ECCP3AS1 ECCP3AS0 PSS3AC1 PSS3AC0 PSS3BD1 PSS3BD0 0000 0000
F18h ECCP3DEL P3RSEN P3DC6 P3DC5 P3DC4 P3DC3 P3DC2 P3DC1 P3DC0 0000 0000
F17h CCPR3H Capture/Compare/PWM Register 3 High Byte xxxx xxxx
F16h CCPR3L Capture/Compare/PWM Register 3 Low Byte xxxx xxxx
F15h CCP3CON P3M1 P3M0 DC3B1 DC3B0 CCP3M3 CCP3M2 CCP3M1 CCP3M0 0000 0000
F14h CCPR4H Capture/Compare/PWM Register 4 High Byte xxxx xxxx
F13h CCPR4L Capture/Compare/PWM Register 4 Low Byte xxxx xxxx
F12h CCP4CON — — DC4B1 DC4B0 CCP4M3 CCP4M2 CCP4M1 CCP4M0 --00 0000
F11h CCPR5H Capture/Compare/PWM Register 5 High Byte xxxx xxxx
F10h CCPR5L Capture/Compare/PWM Register 5 Low Byte xxxx xxxx
F0Fh CCP5CON — — DC5B1 DC5B0 CCP5M3 CCP5M2 CCP5M1 CCP5M0 --00 0000
F0Eh CCPR6H Capture/Compare/PWM Register 6 High Byte xxxx xxxx
F0Dh CCPR6L Capture/Compare/PWM Register 6 Low Byte xxxx xxxx
F0Ch CCP6CON — — DC6B1 DC6B0 CCP6M3 CCP6M2 CCP6M1 CCP6M0 --00 0000
F0Bh CCPR7H Capture/Compare/PWM Register 7 High Byte xxxx xxxx
F0Ah CCPR7L Capture/Compare/PWM Register 7 Low Byte xxxx xxxx
F09h CCP7CON — — DC7B1 DC7B0 CCP7M3 CCP7M2 CCP7M1 CCP7M0 --00 0000
F08h CCPR8H Capture/Compare/PWM Register 8 High Byte xxxx xxxx
F07h CCPR8L Capture/Compare/PWM Register 8 Low Byte xxxx xxxx
F06h CCP8CON — — DC8B1 DC8B0 CCP8M3 CCP8M2 CCP8M1 CCP8M0 --00 0000
F05h CCPR9H Capture/Compare/PWM Register 9 High Byte xxxx xxxx
F04h CCPR9L Capture/Compare/PWM Register 9 Low Byte xxxx xxxx
F03h CCP9CON — — DC9B1 DC9B0 CCP9M3 CCP9M2 CCP9M1 CCP9M0 --00 0000
F02h CCPR10H Capture/Compare/PWM Register 10 High Byte xxxx xxxx
F01h CCPR10L Capture/Compare/PWM Register 10 Low Byte xxxx xxxx
F00h CCP10CON — — DC10B1 DC10B0 CCP10M3 CCP10M2 CCP10M1 CCP10M0 --00 0000
EFFh RPINR24 — — — PWM Fault Input (FLT0) to Input Pin Mapping bits ---1 1111
EFEh RPINR23 — — — SPI2 Slave Select Input (SS2) to Input Pin Mapping bits ---1 1111
EFDh RPINR22 — — — SPI2 Clock Input (SCK2) to Input Pin Mapping bits ---1 1111
EFCh RPINR21 — — — SPI2 Data Input (SDI2) to Input Pin Mapping bits ---1 1111
EFBh — — — — — — — — —
EFAh — — — — — — — — —
EF9h — — — — — — — — —
EF8h RPINR17 — — — EUSART2 Clock Input (CK2) to Input Pin Mapping bits ---1 1111
EF7h RPINR16 — — — EUSART2 RX2DT2 to Input Pin Mapping bits ---1 1111
EF6h — — — — — — — — —
EF5h — — — — — — — — —
Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition, r = reserved, do not modify
Note 1: Implemented only for 44-pin devices (PIC18F46J53, PIC18F47J53, PIC18LF46J53 and PIC18LF47J53).
2: Implemented only for 28-pin devices (PIC18F26J53, PIC18F27J53, PIC18LF26J53 and PIC18LF27J53).
3: Implemented only for devices with 128 Kbyte of program memory (PIC18F27J53, PIC18F47J53, PIC18LF27J53 and PIC18LF47J53).

 2010 Microchip Technology Inc. Preliminary DS39964B-page 99

PIC18F47J53 FAMILY
TABLE 6-4: REGISTER FILE SUMMARY (PIC18F47J53 FAMILY) (CONTINUED)
Value on
Addr. File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
POR, BOR

EF4h RPINR14 — — — Timer5 Gate Input (T5G) to Input Pin Mapping bits ---1 1111
EF3h RPINR13 — — — Timer3 Gate Input (T3G) to Input Pin Mapping bits ---1 1111
EF2h RPINR12 — — — Timer1 Gate Input (T1G) to Input Pin Mapping bits ---1 1111
EF1h — — — — — — — — —
EF0h — — — — — — — — —
EEFh — — — — — — — — —
EEEh — — — — — — — — —
EEDh — — — — — — — — —
EECh — — — — — — — — —
EEBh — — — — — — — — —
EEAh RPINR9 — — — ECCP3 Input Capture (IC3) to Input Pin Mapping bits ---1 1111
EE9h RPINR8 — — — ECCP2 Input Capture (IC2) to Input Pin Mapping bits ---1 1111
EE8h RPINR7 — — — ECCP1 Input Capture (IC1) to Input Pin Mapping bits ---1 1111
EE7h RPINR15 — — — Timer5 External Clock Input (T5CKI) to Input Pin Mapping bits ---1 1111
EE6h RPINR6 — — — Timer3 External Clock Input (T3CKI) to Input Pin Mapping bits ---1 1111
EE5h — — — — — — — — —
EE4h RPINR4 — — — Timer0 External Clock Input (T0CKI) to Input Pin Mapping bits ---1 1111
EE3h RPINR3 — — — External Interrupt (INT3) to Input Pin Mapping bits ---1 1111
EE2h RPINR2 — — — External Interrupt (INT2) to Input Pin Mapping bits ---1 1111
EE1h RPINR1 — — — External Interrupt (INT1) to Input Pin Mapping bits ---1 1111
EE0h — — — — — — — — —
EDFh — — — — — — — — —
EDEh — — — — — — — — —
EDDh — — — — — — — — —
EDCh — — — — — — — — —
EDBh — — — — — — — — —
EDAh — — — — — — — — —
ED9h — — — — — — — — —
ED8h(1) RPOR24 — — — Remappable Pin RP24 Output Signal Select bits ---0 0000
ED7h(1) RPOR23 — — — Remappable Pin RP23 Output Signal Select bits ---0 0000
ED6h(1) RPOR22 — — — Remappable Pin RP22 Output Signal Select bits ---0 0000
ED5h(1) RPOR21 — — — Remappable Pin RP21 Output Signal Select bits ---0 0000
ED4h(1) RPOR20 — — — Remappable Pin RP20 Output Signal Select bits ---0 0000
ED3h(1) RPOR19 — — — Remappable Pin RP19 Output Signal Select bits ---0 0000
ED2h RPOR18 — — — Remappable Pin RP18 Output Signal Select bits ---0 0000
ED1h RPOR17 — — — Remappable Pin RP17 Output Signal Select bits ---0 0000
ED0h) — — — — — — — — — ---0 0000
ECFh — — — — — — — — — ---0 0000
ECEh — — — — — — — — — ---0 0000
ECDh RPOR13 — — — Remappable Pin RP13 Output Signal Select bits ---0 0000
ECCh RPOR12 — — — Remappable Pin RP12 Output Signal Select bits ---0 0000
ECBh RPOR11 — — — Remappable Pin RP11 Output Signal Select bits ---0 0000
ECAh RPOR10 — — — Remappable Pin RP10 Output Signal Select bits ---0 0000
EC9h RPOR9 — — — Remappable Pin RP9 Output Signal Select bits ---0 0000
EC8h RPOR8 — — — Remappable Pin RP8 Output Signal Select bits ---0 0000
EC7h RPOR7 — — — Remappable Pin RP7 Output Signal Select bits ---0 0000
EC6h RPOR6 — — — Remappable Pin RP6 Output Signal Select bits ---0 0000
EC5h RPOR5 — — — Remappable Pin RP5 Output Signal Select bits ---0 0000
Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition, r = reserved, do not modify
Note 1: Implemented only for 44-pin devices (PIC18F46J53, PIC18F47J53, PIC18LF46J53 and PIC18LF47J53).
2: Implemented only for 28-pin devices (PIC18F26J53, PIC18F27J53, PIC18LF26J53 and PIC18LF27J53).
3: Implemented only for devices with 128 Kbyte of program memory (PIC18F27J53, PIC18F47J53, PIC18LF27J53 and PIC18LF47J53).

DS39964B-page 100 Preliminary  2010 Microchip Technology Inc.

 PIC18F47J53 FAMILY
TABLE 6-4: REGISTER FILE SUMMARY (PIC18F47J53 FAMILY) (CONTINUED)
Value on
Addr. File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
POR, BOR

EC4h RPOR4 — — — Remappable Pin RP4 Output Signal Select bits ---0 0000
EC3h RPOR3 — — — Remappable Pin RP3 Output Signal Select bits ---0 0000
EC2h RPOR2 — — — Remappable Pin RP2 Output Signal Select bits ---0 0000
EC1h RPOR1 — — — Remappable Pin RP1 Output Signal Select bits ---0 0000
EC0h RPOR0 — — — Remappable Pin RP0 Output Signal Select bits ---0 0000
EBFh PPSCON — — — — — — — IOLOCK ---- ---0
EBEh — — — — — — — — —
EBDh — — — — — — — — —
EBCh PMDIS3 CCP10MD CCP9MD CCP8MD CCP7MD CCP6MD CCP5MD CCP4MD — 0000 000-
EBBh PMDIS2 — TMR8MD — TMR6MD TMR5MD CMP3MD CMP2MD CMP1MD -0-0 0000
EBAh PMDIS1 PSPMD(1) CTMUMD RTCCMD TMR4MD TMR3MD TMR2MD TMR1MD — 0000 000-
EB9h PMDIS0 CCP3MD CCP2MD CCP1MD UART2MD UART1MD SPI2MD SPI1MD ADCMD 0000 0000
EB8h ADCTRIG — — — — — — TRIGSEL1 TRIGSEL0 ---- --00
EB7h — — — — — — — — —
EB6h — — — — — — — — —
EB5h — — — — — — — — —
EB4h — — — — — — — — —
EB3h — — — — — — — — —
EB2h — — — — — — — — —
EB1h — — — — — — — — —
EB0h — — — — — — — — —
300000h CONFIG1L DEBUG XINST STVREN CFGPLLEN PLLDIV2 PLLDIV1 PLLDIV0 WDTEN 1111 1111
300001h CONFIG1H — — — — — CP0 CPDIV1 CPDIV0 ---- -111
300002h CONFIG2L IESO FCMEN CLKOEC SOSCSEL1 SOSCSEL0 FOSC2 FOSC1 FOSC0 1111 1111
300003h CONFIG2H — — — — WDTPS3 WDTPS2 WDTPS1 WDTPS0 ---- 1111
300004h CONFIG3L DSWDTPS3 DSWDTPS2 DSWDTPS1 DSWDTPS0 DSWDTEN DSBOREN RTCOSC DSWDTOSC 1111 1111
300005h CONFIG3H — — — — MSSPMSK — ADCSEL IOL1WAY ---- 1-11
300006h CONFIG4L WPCFG WPFP6 WPFP5 WPFP4 WPFP3 WPFP2 WPFP1 WPFP0 1111 1111
300007h CONFIG4H — — — — LS48MHZ — WPEND WPDIS ---- 1-11
Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition, r = reserved, do not modify
Note 1: Implemented only for 44-pin devices (PIC18F46J53, PIC18F47J53, PIC18LF46J53 and PIC18LF47J53).
2: Implemented only for 28-pin devices (PIC18F26J53, PIC18F27J53, PIC18LF26J53 and PIC18LF27J53).
3: Implemented only for devices with 128 Kbyte of program memory (PIC18F27J53, PIC18F47J53, PIC18LF27J53 and PIC18LF47J53).

 2010 Microchip Technology Inc. Preliminary DS39964B-page 101

PIC18F47J53 FAMILY
6.3.6 STATUS REGISTER register then reads back as ‘000u u1uu’. It is recom-
mended, therefore, that only BCF, BSF, SWAPF, MOVFF
The STATUS register, shown in Register 6-2, contains
and MOVWF instructions are used to alter the STATUS
the arithmetic status of the ALU. The STATUS register
register because these instructions do not affect the Z,
can be the operand for any instruction, as with any
C, DC, OV or N bits in the STATUS register.
other register. If the STATUS register is the destination
for an instruction that affects the Z, DC, C, OV or N bits, For other instructions not affecting any Status bits, see
then the write to these five bits is disabled. the instruction set summary in Table 29-2 and
Table 29-3.
These bits are set or cleared according to the device
logic. Therefore, the result of an instruction with the Note: The C and DC bits operate as Borrow and
STATUS register as destination may be different than Digit Borrow bits, respectively in
intended. For example, CLRF STATUS will set the Z bit subtraction.
but leave the other bits unchanged. The STATUS

REGISTER 6-2: STATUS REGISTER (ACCESS FDBh)

U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x
— — — N OV Z DC(1) C(2)
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-5 Unimplemented: Read as ‘0’

bit 4 N: Negative bit
This bit is used for signed arithmetic (2’s complement). It indicates whether the result was negative
(ALU MSB = 1).
1 = Result was negative
0 = Result was positive
bit 3 OV: Overflow bit
This bit is used for signed arithmetic (2’s complement). It indicates an overflow of the 7-bit magnitude,
which causes the sign bit (bit 7) to change state.
1 = Overflow occurred for signed arithmetic (in this arithmetic operation)
0 = No overflow occurred
bit 2 Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1 DC: Digit Carry/Digit Borrow bit(1)
For ADDWF, ADDLW, SUBLW and SUBWF instructions:
1 = A carry out from the 4th low-order bit of the result occurred
0 = No carry out from the 4th low-order bit of the result
bit 0 C: Carry/Borrow bit(2)
For ADDWF, ADDLW, SUBLW and SUBWF instructions:
1 = A carry out from the MSb of the result occurred
0 = No carry out from the MSb of the result occurred

Note 1: For Digit Borrow, the polarity is reversed. A subtraction is executed by adding the 2’s complement of the
second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either bit 4 or bit 3 of the source
register.
2: For Borrow, the polarity is reversed. A subtraction is executed by adding the 2’s complement of the sec-
ond operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low-order bit of
the source register.

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6.4 Data Addressing Modes Register File”) or a location in the Access Bank
(Section 6.3.3 “Access Bank”) as the data source for
Note: The execution of some instructions in the the instruction.
core PIC18 instruction set are changed
The Access RAM bit, ‘a’, determines how the address
when the PIC18 extended instruction set is
is interpreted. When ‘a’ is ‘1’, the contents of the BSR
enabled. See Section 6.6 “Data Memory
(Section 6.3.2 “Bank Select Register”) are used with
and the Extended Instruction Set” for
the address to determine the complete 12-bit address
more information.
of the register. When ‘a’ is ‘0’, the address is interpreted
While the program memory can be addressed in only as being a register in the Access Bank. Addressing that
one way through the PC, information in the data mem- uses the Access RAM is sometimes also known as
ory space can be addressed in several ways. For most Direct Forced Addressing mode.
instructions, the addressing mode is fixed. Other A few instructions, such as MOVFF, include the entire
instructions may use up to three modes, depending on 12-bit address (either source or destination) in their
which operands are used and whether or not the opcodes. In these cases, the BSR is ignored entirely.
extended instruction set is enabled.
The destination of the operation’s results is determined
The addressing modes are: by the destination bit, ‘d’. When ‘d’ is ‘1’, the results are
• Inherent stored back in the source register, overwriting its
• Literal original contents. When ‘d’ is ‘0’, the results are stored
in the W register. Instructions without the ‘d’ argument
• Direct
have a destination that is implicit in the instruction; their
• Indirect destination is either the target register being operated
An additional addressing mode, Indexed Literal Offset, on or the W register.
is available when the extended instruction set is
enabled (XINST Configuration bit = 1). Its operation is 6.4.3 INDIRECT ADDRESSING
discussed in more detail in Section 6.6.1 “Indexed Indirect Addressing allows the user to access a location
Addressing with Literal Offset”. in data memory without giving a fixed address in the
instruction. This is done by using File Select Registers
6.4.1 INHERENT AND LITERAL (FSRs) as pointers to the locations to be read or written
ADDRESSING to. Since the FSRs are themselves located in RAM as
Many PIC18 control instructions do not need any SFRs, they can also be directly manipulated under
argument at all; they either perform an operation that program control. This makes FSRs very useful in
globally affects the device, or they operate implicitly on implementing data structures such as tables and arrays
one register. This addressing mode is known as in data memory.
Inherent Addressing. Examples include SLEEP, RESET The registers for Indirect Addressing are also
and DAW. implemented with Indirect File Operands (INDFs) that
Other instructions work in a similar way, but require an permit automatic manipulation of the pointer value with
additional explicit argument in the opcode. This is auto-incrementing, auto-decrementing or offsetting
known as Literal Addressing mode, because they with another value. This allows for efficient code using
require some literal value as an argument. Examples loops, such as the example of clearing an entire RAM
include ADDLW and MOVLW, which respectively, add or bank in Example 6-5. It also enables users to perform
move a literal value to the W register. Other examples Indexed Addressing and other Stack Pointer
include CALL and GOTO, which include a 20-bit operations for program memory in data memory.
program memory address.
EXAMPLE 6-5: HOW TO CLEAR RAM
6.4.2 DIRECT ADDRESSING (BANK 1) USING INDIRECT
Direct Addressing specifies all or part of the source ADDRESSING
and/or destination address of the operation within the LFSR FSR0, 100h ;
opcode itself. The options are specified by the NEXT CLRF POSTINC0 ; Clear INDF
arguments accompanying the instruction. ; register then
; inc pointer
In the core PIC18 instruction set, bit-oriented and BTFSS FSR0H, 1 ; All done with
byte-oriented instructions use some version of Direct ; Bank1?
Addressing by default. All of these instructions include BRA NEXT ; NO, clear next
some 8-bit literal address as their LSB. This address CONTINUE ; YES, continue
specifies either a register address in one of the banks
of data RAM (Section 6.3.4 “General Purpose

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6.4.3.1 FSR Registers and the INDF SFR space but are not physically implemented. Read-
Operand (INDF) ing or writing to a particular INDF register actually
accesses its corresponding FSR register pair. A read
At the core of Indirect Addressing are three sets of
from INDF1, for example, reads the data at the address
registers: FSR0, FSR1 and FSR2. Each represents a
indicated by FSR1H:FSR1L. Instructions that use the
pair of 8-bit registers, FSRnH and FSRnL. The four
INDF registers as operands actually use the contents
upper bits of the FSRnH register are not used, so each
of their corresponding FSR as a pointer to the instruc-
FSR pair holds a 12-bit value. This represents a value
tion’s target. The INDF operand is just a convenient
that can address the entire range of the data memory
way of using the pointer.
in a linear fashion. The FSR register pairs, then, serve
as pointers to data memory locations. Because Indirect Addressing uses a full 12-bit address,
data RAM banking is not necessary. Thus, the current
Indirect Addressing is accomplished with a set of INDF
contents of the BSR and the Access RAM bit have no
operands, INDF0 through INDF2. These can be pre-
effect on determining the target address.
sumed as “virtual” registers; they are mapped in the

FIGURE 6-8: INDIRECT ADDRESSING

000h
Using an instruction with one of the ADDWF, INDF1, 1 Bank 0
Indirect Addressing registers as the 100h
operand.... Bank 1
200h
Bank 2
300h
...uses the 12-bit address stored in FSR1H:FSR1L
the FSR pair associated with that
7 0 7 0
register.... Bank 3
x x x x 1 1 1 1 1 1 0 0 1 1 0 0 through
Bank 13

...to determine the data memory

location to be used in that operation.
In this case, the FSR1 pair contains E00h
FCCh. This means the contents of Bank 14
location, FCCh, will be added to that F00h
of the W register and stored back in Bank 15
FCCh. FFFh
Data Memory

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6.4.3.2 FSR Registers and POSTINC, 6.4.3.3 Operations by FSRs on FSRs
POSTDEC, PREINC and PLUSW Indirect Addressing operations that target other FSRs
In addition to the INDF operand, each FSR register pair or virtual registers represent special cases. For
also has four additional indirect operands. Like INDF, example, using an FSR to point to one of the virtual
these are “virtual” registers that cannot be indirectly registers will not result in successful operations. As a
read or written to. Accessing these registers actually specific case, assume that FSR0H:FSR0L contains
accesses the associated FSR register pair, but also FE7h, the address of INDF1. Attempts to read the
performs a specific action on its stored value. They are: value of the INDF1, using INDF0 as an operand, will
return 00h. Attempts to write to INDF1, using INDF0 as
• POSTDEC: accesses the FSR value, then
the operand, will result in a NOP.
automatically decrements it by ‘1’ thereafter
• POSTINC: accesses the FSR value, then On the other hand, using the virtual registers to write to
automatically increments it by ‘1’ thereafter an FSR pair may not occur as planned. In these cases,
the value will be written to the FSR pair but without any
• PREINC: increments the FSR value by ‘1’, then
incrementing or decrementing. Thus, writing to INDF2
uses it in the operation
or POSTDEC2 will write the same value to the
• PLUSW: adds the signed value of the W register FSR2H:FSR2L.
(range of 127 to 128) to that of the FSR and uses
the new value in the operation Since the FSRs are physical registers mapped in the
SFR space, they can be manipulated through all direct
In this context, accessing an INDF register uses the operations. Users should proceed cautiously when
value in the FSR registers without changing them. working on these registers, particularly if their code
Similarly, accessing a PLUSW register gives the FSR uses Indirect Addressing.
value offset by the value in the W register; neither value
is actually changed in the operation. Accessing the Similarly, operations by Indirect Addressing are gener-
other virtual registers changes the value of the FSR ally permitted on all other SFRs. Users should exercise
registers. appropriate caution that they do not inadvertently
change settings that might affect the operation of the
Operations on the FSRs with POSTDEC, POSTINC device.
and PREINC affect the entire register pair; that is, roll-
overs of the FSRnL register from FFh to 00h carry over
to the FSRnH register. On the other hand, results of
6.5 Program Memory and the
these operations do not change the value of any flags Extended Instruction Set
in the STATUS register (e.g., Z, N, OV, etc.). The operation of program memory is unaffected by the
The PLUSW register can be used to implement a form use of the extended instruction set.
of Indexed Addressing in the data memory space. By Enabling the extended instruction set adds five
manipulating the value in the W register, users can additional two-word commands to the existing PIC18
reach addresses that are fixed offsets from pointer instruction set: ADDFSR, CALLW, MOVSF, MOVSS and
addresses. In some applications, this can be used to SUBFSR. These instructions are executed as described
implement some powerful program control structure, in Section 6.2.4 “Two-Word Instructions”.
such as software stacks, inside of data memory.

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6.6 Data Memory and the Extended Under these conditions, the file address of the
Instruction Set instruction is not interpreted as the lower byte of an
address (used with the BSR in Direct Addressing) or as
Enabling the PIC18 extended instruction set (XINST an 8-bit address in the Access Bank. Instead, the value
Configuration bit = 1) significantly changes certain is interpreted as an offset value to an Address Pointer
aspects of data memory and its addressing. Specifically, specified by FSR2. The offset and the contents of
the use of the Access Bank for many of the core PIC18 FSR2 are added to obtain the target address of the
instructions is different. This is due to the introduction of operation.
a new addressing mode for the data memory space.
This mode also alters the behavior of Indirect 6.6.2 INSTRUCTIONS AFFECTED BY
Addressing using FSR2 and its associated operands. INDEXED LITERAL OFFSET MODE
What does not change is just as important. The size of Any of the core PIC18 instructions that can use Direct
the data memory space is unchanged, as well as its Addressing are potentially affected by the Indexed
linear addressing. The SFR map remains the same. Literal Offset Addressing mode. This includes all byte
Core PIC18 instructions can still operate in both Direct and bit-oriented instructions, or almost one-half of the
and Indirect Addressing mode; inherent and literal standard PIC18 instruction set. Instructions that only
instructions do not change at all. Indirect Addressing use Inherent or Literal Addressing modes are
with FSR0 and FSR1 also remains unchanged. unaffected.
Additionally, byte and bit-oriented instructions are not
6.6.1 INDEXED ADDRESSING WITH
affected if they use the Access Bank (Access RAM bit is
LITERAL OFFSET
‘1’) or include a file address of 60h or above. Instructions
Enabling the PIC18 extended instruction set changes meeting these criteria will continue to execute as before.
the behavior of Indirect Addressing using the FSR2 A comparison of the different possible addressing
register pair and its associated file operands. Under modes when the extended instruction set is enabled is
proper conditions, instructions that use the Access provided in Figure 6-9.
Bank, that is, most bit and byte-oriented instructions,
Those who desire to use byte or bit-oriented instruc-
can invoke a form of Indexed Addressing using an
tions in the Indexed Literal Offset mode should note the
offset specified in the instruction. This special address-
changes to assembler syntax for this mode. This is
ing mode is known as Indexed Addressing with Literal
described in more detail in Section 29.2.1 “Extended
Offset or Indexed Literal Offset mode.
Instruction Syntax”.
When using the extended instruction set, this
addressing mode requires the following:
• The use of the Access Bank is forced (‘a’ = 0);
and
• The file address argument is less than or equal to
5Fh.

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FIGURE 6-9: COMPARING ADDRESSING OPTIONS FOR BIT-ORIENTED AND BYTE-ORIENTED
INSTRUCTIONS (EXTENDED INSTRUCTION SET ENABLED)

EXAMPLE INSTRUCTION: ADDWF, f, d, a (Opcode: 0010 01da ffff ffff)

000h
When a = 0 and f  60h:
The instruction executes in 060h
Direct Forced mode. ‘f’ is Bank 0
interpreted as a location in the 100h
Access RAM between 060h 00h
Bank 1
and FFFh. This is the same as through 60h
locations, F60h to FFFh Bank 14
Valid range
(Bank 15), of data memory. for ‘f’
Locations below 060h are not FFh
F00h Access RAM
available in this addressing
Bank 15
mode.
F60h
SFRs
FFFh
Data Memory

When a = 0 and f5Fh: 000h

The instruction executes in Bank 0
Indexed Literal Offset mode. ‘f’ 060h

is interpreted as an offset to the

100h 001001da ffffffff
address value in FSR2. The
two are added together to Bank 1
obtain the address of the target through
Bank 14
register for the instruction. The
address can be anywhere in FSR2H FSR2L
the data memory space.
F00h
Note that in this mode, the Bank 15
correct syntax is: F60h
ADDWF [k], d SFRs
where ‘k’ is the same as ‘f’. FFFh
Data Memory

BSR
When a = 1 (all values of f): 000h 00000000
Bank 0
The instruction executes in
060h
Direct mode (also known as
Direct Long mode). ‘f’ is 100h
interpreted as a location in
one of the 16 banks of the data Bank 1 001001da ffffffff
memory space. The bank is through
Bank 14
designated by the Bank Select
Register (BSR). The address
can be in any implemented F00h
bank in the data memory Bank 15
space. F60h
SFRs
FFFh
Data Memory

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6.6.3 MAPPING THE ACCESS BANK IN Remapping of the Access Bank applies only to opera-
INDEXED LITERAL OFFSET MODE tions using the Indexed Literal Offset mode. Operations
that use the BSR (Access RAM bit is ‘1’) will continue
The use of Indexed Literal Offset Addressing mode
to use Direct Addressing as before. Any Indirect or
effectively changes how the lower part of Access RAM
Indexed Addressing operation that explicitly uses any
(00h to 5Fh) is mapped. Rather than containing just the
of the indirect file operands (including FSR2) will con-
contents of the bottom part of Bank 0, this mode maps
tinue to operate as standard Indirect Addressing. Any
the contents from Bank 0 and a user-defined “window”
instruction that uses the Access Bank, but includes a
that can be located anywhere in the data memory
register address of greater than 05Fh, will use Direct
space. The value of FSR2 establishes the lower
Addressing and the normal Access Bank map.
boundary of the addresses mapped to the window,
while the upper boundary is defined by FSR2 plus 95 6.6.4 BSR IN INDEXED LITERAL OFFSET
(5Fh). Addresses in the Access RAM above 5Fh are
MODE
mapped as previously described (see Section 6.3.3
“Access Bank”). Figure 6-10 provides an example of Although the Access Bank is remapped when the
Access Bank remapping in this addressing mode. extended instruction set is enabled, the operation of the
BSR remains unchanged. Direct Addressing, using the
BSR to select the data memory bank, operates in the
same manner as previously described.

FIGURE 6-10: REMAPPING THE ACCESS BANK WITH INDEXED LITERAL OFFSET ADDRESSING
Example Situation:
ADDWF f, d, a 000h
Not Accessible
FSR2H:FSR2L = 120h 05Fh

Locations in the region Bank 0

from the FSR2 Pointer 100h
(120h) to the pointer plus 120h
05Fh (17Fh) are mapped Window
17Fh 00h
to the bottom of the Bank 1 Bank 1 “Window”
Access RAM (000h-05Fh). 200h
Special Function Registers 5Fh
60h
at F60h through FFFh are
mapped to 60h through Bank 2
FFh, as usual. through SFRs
Bank 0 addresses below Bank 14
5Fh are not available in FFh
this mode. They can still Access Bank
be addressed by using the F00h
BSR.
Bank 15
F60h
SFRs
FFFh
Data Memory

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7.0 FLASH PROGRAM MEMORY 7.1 Table Reads and Table Writes
The Flash program memory is readable, writable and In order to read and write program memory, there are
erasable during normal operation over the entire VDD two operations that allow the processor to move bytes
range. between the program memory space and the data RAM:
A read from program memory is executed on 1 byte at • Table Read (TBLRD)
a time. A write to program memory is executed on • Table Write (TBLWT)
blocks of 64 bytes at a time or 2 bytes at a time.
The program memory space is 16 bits wide, while the
Program memory is erased in blocks of 1024 bytes at
data RAM space is 8 bits wide. Table reads and table
a time. A bulk erase operation may not be issued from
writes move data between these two memory spaces
user code.
through an 8-bit register (TABLAT).
Writing or erasing program memory will cease
Table read operations retrieve data from program
instruction fetches until the operation is complete. The
memory and place it into the data RAM space.
program memory cannot be accessed during the write
Figure 7-1 illustrates the operation of a table read with
or erase, therefore, code cannot execute. An internal
program memory and data RAM.
programming timer terminates program memory writes
and erases. Table write operations store data from the data memory
space into holding registers in program memory. The
A value written to program memory does not need to be
procedure to write the contents of the holding registers
a valid instruction. Executing a program memory
into program memory is detailed in Section 7.5 “Writing
location that forms an invalid instruction results in a
to Flash Program Memory”. Figure 7-2 illustrates the
NOP.
operation of a table write with program memory and data
RAM.
Table operations work with byte entities. A table block
containing data, rather than program instructions, is not
required to be word-aligned. Therefore, a table block can
start and end at any byte address. If a table write is being
used to write executable code into program memory,
program instructions will need to be word-aligned.

FIGURE 7-1: TABLE READ OPERATION

Instruction: TBLRD*

Program Memory
Table Pointer(1)
Table Latch (8-bit)
TBLPTRU TBLPTRH TBLPTRL
TABLAT

Program Memory
(TBLPTR)

Note 1: The Table Pointer register points to a byte in program memory.

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FIGURE 7-2: TABLE WRITE OPERATION

Instruction: TBLWT*

Program Memory
Holding Registers
Table Pointer(1) Table Latch (8-bit)

TBLPTRU TBLPTRH TBLPTRL TABLAT

Program Memory
(TBLPTR)

Note 1: The Table Pointer actually points to one of 64 holding registers, the address of which is determined by
TBLPTRL<5:0>. The process for physically writing data to the program memory array is discussed in
Section 7.5 “Writing to Flash Program Memory”.

7.2 Control Registers The FREE bit, when set, will allow a program memory
erase operation. When FREE is set, the erase
Several control registers are used in conjunction with operation is initiated on the next WR command. When
the TBLRD and TBLWT instructions. Those are: FREE is clear, only writes are enabled.
• EECON1 register The WREN bit, when set, will allow a write operation.
• EECON2 register On power-up, the WREN bit is clear. The WRERR bit is
• TABLAT register set in hardware when the WR bit is set, and cleared
• TBLPTR registers when the internal programming timer expires and the
write operation is complete.
7.2.1 EECON1 AND EECON2 REGISTERS Note: During normal operation, the WRERR is
The EECON1 register (Register 7-1) is the control read as ‘1’. This can indicate that a write
register for memory accesses. The EECON2 register is operation was prematurely terminated by
not a physical register; it is used exclusively in the a Reset or a write operation was
memory write and erase sequences. Reading attempted improperly.
EECON2 will read all ‘0’s.
The WR control bit initiates write operations. The bit
The WPROG bit, when set, will allow programming cannot be cleared, only set, in software. It is cleared in
two bytes per word on the execution of the WR hardware at the completion of the write operation.
command. If this bit is cleared, the WR command will
result in programming on a block of 64 bytes.

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REGISTER 7-1: EECON1: EEPROM CONTROL REGISTER 1 (ACCESS FA6h)
U-0 U-0 R/W-0 R/W-0 R/W-x R/W-0 R/S-0 U-0
— — WPROG FREE WRERR WREN WR —
bit 7 bit 0

Legend: S = Settable bit (cannot be cleared in software)

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-6 Unimplemented: Read as ‘0’

bit 5 WPROG: One Word-Wide Program bit
1 = Program 2 bytes on the next WR command
0 = Program 64 bytes on the next WR command
bit 4 FREE: Flash Erase Enable bit
1 = Perform an erase operation on the next WR command (cleared by hardware after completion of erase)
0 = Perform write-only
bit 3 WRERR: Flash Program Error Flag bit
1 = A write operation is prematurely terminated (any Reset during self-timed programming in normal
operation or an improper write attempt)
0 = The write operation completed
bit 2 WREN: Flash Program Write Enable bit
1 = Allows write cycles to Flash program memory
0 = Inhibits write cycles to Flash program memory
bit 1 WR: Write-Control bit
1 = Initiates a program memory erase cycle or write cycle
(The operation is self-timed and the bit is cleared by hardware once the write is complete. The WR
bit can only be set (not cleared) in software.)
0 = Write cycle is complete
bit 0 Unimplemented: Read as ‘0’

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7.2.2 TABLE LATCH REGISTER (TABLAT) 7.2.4 TABLE POINTER BOUNDARIES
The Table Latch (TABLAT) is an 8-bit register mapped TBLPTR is used in reads, writes and erases of the
into the Special Function Register (SFR) space. The Flash program memory.
Table Latch register is used to hold 8-bit data during When a TBLRD is executed, all 22 bits of the TBLPTR
data transfers between program memory and data determine which byte is read from program memory
RAM. into TABLAT.
7.2.3 TABLE POINTER REGISTER When a TBLWT is executed, the seven Least Significant
(TBLPTR) bits (LSbs) of the Table Pointer register (TBLPTR<6:0>)
determine which of the 64 program memory holding
The Table Pointer (TBLPTR) register addresses a byte registers is written to. When the timed write to program
within the program memory. The TBLPTR comprises memory begins (via the WR bit), the 12 Most Significant
three SFR registers: Table Pointer Upper Byte, Table bits (MSbs) of the TBLPTR (TBLPTR<21:10>)
Pointer High Byte and Table Pointer Low Byte determine which program memory block of 1024 bytes
(TBLPTRU:TBLPTRH:TBLPTRL). These three registers is written to. For more information, see Section 7.5
join to form a 22-bit wide pointer. The low-order 21 bits “Writing to Flash Program Memory”.
allow the device to address up to 2 Mbytes of program
memory space. The 22nd bit allows access to the device When an erase of program memory is executed, the
ID, the user ID and the Configuration bits. 12 MSbs of the Table Pointer register point to the
1024-byte block that will be erased. The LSbs are
The Table Pointer register, TBLPTR, is used by the ignored.
TBLRD and TBLWT instructions. These instructions can
update the TBLPTR in one of four ways based on the Figure 7-3 illustrates the relevant boundaries of the
table operation. TBLPTR based on Flash program memory operations.
Table 7-1 provides these operations. These operations
on the TBLPTR only affect the low-order 21 bits.

TABLE 7-1: TABLE POINTER OPERATIONS WITH TBLRD AND TBLWT INSTRUCTIONS
Example Operation on Table Pointer
TBLRD*
TBLPTR is not modified
TBLWT*
TBLRD*+
TBLPTR is incremented after the read/write
TBLWT*+
TBLRD*-
TBLPTR is decremented after the read/write
TBLWT*-
TBLRD+*
TBLPTR is incremented before the read/write
TBLWT+*

FIGURE 7-3: TABLE POINTER BOUNDARIES BASED ON OPERATION

21 TBLPTRU 16 15 TBLPTRH 8 7 TBLPTRL 0

ERASE: TBLPTR<20:10>

TABLE WRITE: TBLPTR<20:6>

TABLE READ: TBLPTR<21:0>

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7.3 Reading the Flash Program The TBLPTR points to a byte address in program
Memory space. Executing TBLRD places the byte pointed to into
TABLAT. In addition, the TBLPTR can be modified
The TBLRD instruction is used to retrieve data from automatically for the next table read operation.
program memory and places it into data RAM. Table
The internal program memory is typically organized by
reads from program memory are performed one byte at
words. The LSb of the address selects between the high
a time.
and low bytes of the word.
Figure 7-4 illustrates the interface between the internal
program memory and the TABLAT.

FIGURE 7-4: READS FROM FLASH PROGRAM MEMORY

Program Memory

(Even Byte Address) (Odd Byte Address)

TBLPTR = xxxxx1 TBLPTR = xxxxx0

Instruction Register TABLAT

FETCH TBLRD
(IR) Read Register

EXAMPLE 7-1: READING A FLASH PROGRAM MEMORY WORD

MOVLW CODE_ADDR_UPPER ; Load TBLPTR with the base
MOVWF TBLPTRU ; address of the word
MOVLW CODE_ADDR_HIGH
MOVWF TBLPTRH
MOVLW CODE_ADDR_LOW
MOVWF TBLPTRL
READ_WORD
TBLRD*+ ; read into TABLAT and increment
MOVF TABLAT, W ; get data
MOVWF WORD_EVEN
TBLRD*+ ; read into TABLAT and increment
MOVF TABLAT, W ; get data
MOVWF WORD_ODD

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7.4 Erasing Flash Program Memory 7.4.1 FLASH PROGRAM MEMORY
ERASE SEQUENCE
The minimum erase block is 512 words or 1024 bytes.
Only through the use of an external programmer, or The sequence of events for erasing a block of internal
through ICSP control, can larger blocks of program program memory location is:
memory be bulk erased. Word erase in the Flash array 1. Load Table Pointer register with address of row
is not supported. being erased.
When initiating an erase sequence from the micro- 2. Set the WREN and FREE bits (EECON1<2,4>)
controller itself, a block of 1024 bytes of program to enable the erase operation.
memory is erased. The Most Significant 12 bits of the 3. Disable interrupts.
TBLPTR<21:10> point to the block being erased; 4. Write 55h to EECON2.
TBLPTR<9:0> are ignored.
5. Write 0AAh to EECON2.
The EECON1 register commands the erase operation. 6. Set the WR bit; this will begin the erase cycle.
The WREN bit must be set to enable write operations.
7. The CPU will stall for the duration of the erase
The FREE bit is set to select an erase operation. For
for TIE (see parameter D133B).
protection, the write initiate sequence for EECON2
must be used. 8. Re-enable interrupts.

A long write is necessary for erasing the internal Flash.

Instruction execution is halted while in a long write
cycle. The long write will be terminated by the internal
programming timer.

EXAMPLE 7-2: ERASING FLASH PROGRAM MEMORY

MOVLW CODE_ADDR_UPPER ; load TBLPTR with the base
MOVWF TBLPTRU ; address of the memory block
MOVLW CODE_ADDR_HIGH
MOVWF TBLPTRH
MOVLW CODE_ADDR_LOW
MOVWF TBLPTRL
ERASE_ROW
BSF EECON1, WREN ; enable write to memory
BSF EECON1, FREE ; enable Erase operation
BCF INTCON, GIE ; disable interrupts
Required MOVLW 55h
Sequence MOVWF EECON2 ; write 55h
MOVLW 0AAh
MOVWF EECON2 ; write 0AAh
BSF EECON1, WR ; start erase (CPU stall)
BSF INTCON, GIE ; re-enable interrupts

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 PIC18F47J53 FAMILY
7.5 Writing to Flash Program Memory The on-chip timer controls the write time. The
write/erase voltages are generated by an on-chip
The programming block is 32 words or 64 bytes. charge pump, rated to operate over the voltage range
Programming one word or 2 bytes at a time is also of the device.
supported.
Note 1: Unlike previous PIC® devices, devices of
Table writes are used internally to load the holding
the PIC18F47J53 family do not reset the
registers needed to program the Flash memory. There
holding registers after a write occurs. The
are 64 holding registers used by the table writes for
holding registers must be cleared or
programming.
overwritten before a programming
Since the Table Latch (TABLAT) is only a single byte, the sequence.
TBLWT instruction may need to be executed 64 times for
2: To maintain the endurance of the program
each programming operation (if WPROG = 0). All of the
memory cells, each Flash byte should not
table write operations will essentially be short writes
be programmed more than once between
because only the holding registers are written. At the
erase operations. Before attempting to
end of updating the 64 holding registers, the EECON1
modify the contents of the target cell a
register must be written to in order to start the
second time, an erase of the target page,
programming operation with a long write.
or a bulk erase of the entire memory, must
The long write is necessary for programming the be performed.
internal Flash. Instruction execution is halted while in a
long write cycle. The long write will be terminated by
the internal programming timer.

FIGURE 7-5: TABLE WRITES TO FLASH PROGRAM MEMORY

TABLAT
Write Register

8 8 8 8

TBLPTR = xxxxx0 TBLPTR = xxxxx1 TBLPTR = xxxxx2 TBLPTR = xxxx3F

Holding Register Holding Register Holding Register Holding Register

Program Memory

7.5.1 FLASH PROGRAM MEMORY WRITE 8. Disable interrupts.

SEQUENCE 9. Write 55h to EECON2.
The sequence of events for programming an internal 10. Write 0AAh to EECON2.
program memory location should be: 11. Set the WR bit; this will begin the write cycle.
1. Read 1024 bytes into RAM. 12. The CPU will stall for the duration of the write for
2. Update data values in RAM as necessary. TIW (see parameter D133A).
13. Re-enable interrupts.
3. Load the Table Pointer register with address
being erased. 14. Repeat steps 6 through 13 until all 1024 bytes
4. Execute the erase procedure. are written to program memory.
5. Load the Table Pointer register with the address 15. Verify the memory (table read).
of the first byte being written, minus 1. An example of the required code is provided in
6. Write the 64 bytes into the holding registers with Example 7-3 on the following page.
auto-increment. Note: Before setting the WR bit, the Table
7. Set the WREN bit (EECON1<2>) to enable byte Pointer address needs to be within the
writes. intended address range of the 64 bytes in
the holding register.

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EXAMPLE 7-3: WRITING TO FLASH PROGRAM MEMORY
MOVLW CODE_ADDR_UPPER ; Load TBLPTR with the base address
MOVWF TBLPTRU ; of the memory block, minus 1
MOVLW CODE_ADDR_HIGH
MOVWF TBLPTRH
MOVLW CODE_ADDR_LOW
MOVWF TBLPTRL
ERASE_BLOCK
BSF EECON1, WREN ; enable write to memory
BSF EECON1, FREE ; enable Erase operation
BCF INTCON, GIE ; disable interrupts
MOVLW 55h
MOVWF EECON2 ; write 55h
MOVLW 0AAh
MOVWF EECON2 ; write 0AAh
BSF EECON1, WR ; start erase (CPU stall)
BSF INTCON, GIE ; re-enable interrupts
MOVLW D'16'
MOVWF WRITE_COUNTER ; Need to write 16 blocks of 64 to write
; one erase block of 1024
RESTART_BUFFER
MOVLW D'64'
MOVWF COUNTER
MOVLW BUFFER_ADDR_HIGH ; point to buffer
MOVWF FSR0H
MOVLW BUFFER_ADDR_LOW
MOVWF FSR0L
FILL_BUFFER
... ; read the new data from I2C, SPI,
; PSP, USART, etc.
WRITE_BUFFER
MOVLW D’64 ; number of bytes in holding register
MOVWF COUNTER
WRITE_BYTE_TO_HREGS
MOVFF POSTINC0, WREG ; get low byte of buffer data
MOVWF TABLAT ; present data to table latch
TBLWT+* ; write data, perform a short write
; to internal TBLWT holding register.
DECFSZ COUNTER ; loop until buffers are full
BRA WRITE_BYTE_TO_HREGS
PROGRAM_MEMORY
BSF EECON1, WREN ; enable write to memory
BCF INTCON, GIE ; disable interrupts
MOVLW 55h
Required MOVWF EECON2 ; write 55h
Sequence MOVLW 0AAh
MOVWF EECON2 ; write 0AAh
BSF EECON1, WR ; start program (CPU stall)
BSF INTCON, GIE ; re-enable interrupts
BCF EECON1, WREN ; disable write to memory

DECFSZ WRITE_COUNTER ; done with one write cycle

BRA RESTART_BUFFER ; if not done replacing the erase block

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7.5.2 FLASH PROGRAM MEMORY WRITE 3. Set the WREN bit (EECON1<2>) to enable
SEQUENCE (WORD PRORAMMING). writes and the WPROG bit (EECON1<5>) to
select Word Write mode.
The PIC18F47J53 family of devices has a feature that
allows programming a single word (two bytes). This 4. Disable interrupts.
feature is enabled when the WPROG bit is set. If the 5. Write 55h to EECON2.
memory location is already erased, the following 6. Write 0AAh to EECON2.
sequence is required to enable this feature: 7. Set the WR bit; this will begin the write cycle.
1. Load the Table Pointer register with the address 8. The CPU will stall for the duration of the write for
of the data to be written. (It must be an even TIW (see parameter D133A).
address.) 9. Re-enable interrupts.
2. Write the 2 bytes into the holding registers by
performing table writes. (Do not post-increment
on the second table write.)

EXAMPLE 7-4: SINGLE-WORD WRITE TO FLASH PROGRAM MEMORY

MOVLW CODE_ADDR_UPPER ; Load TBLPTR with the base address
MOVWF TBLPTRU
MOVLW CODE_ADDR_HIGH
MOVWF TBLPTRH
MOVLW CODE_ADDR_LOW ; The table pointer must be loaded with an even
address
MOVWF TBLPTRL

MOVLW DATA0 ; LSB of word to be written

MOVWF TABLAT
TBLWT*+
MOVLW DATA1 ; MSB of word to be written
MOVWF TABLAT
TBLWT* ; The last table write must not increment the table
pointer! The table pointer needs to point to the
MSB before starting the write operation.

PROGRAM_MEMORY
BSF EECON1, WPROG ; enable single word write
BSF EECON1, WREN ; enable write to memory
BCF INTCON, GIE ; disable interrupts
MOVLW 55h
Required MOVWF EECON2 ; write 55h
Sequence MOVLW 0AAh
MOVWF EECON2 ; write AAh
BSF EECON1, WR ; start program (CPU stall)
BSF INTCON, GIE ; re-enable interrupts
BCF EECON1, WPROG ; disable single word write
BCF EECON1, WREN ; disable write to memory

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PIC18F47J53 FAMILY
7.5.3 WRITE VERIFY reprogrammed if needed. If the write operation is
interrupted by a MCLR Reset, or a WDT time-out Reset
Depending on the application, good programming
during normal operation, the user can check the
practice may dictate that the value written to the
WRERR bit and rewrite the location(s) as needed.
memory should be verified against the original value.
This should be used in applications where excessive
writes can stress bits near the specification limit. 7.6 Flash Program Operation During
Code Protection
7.5.4 UNEXPECTED TERMINATION OF
See Section 28.6 “Program Verification and Code
WRITE OPERATION
Protection” for details on code protection of Flash
If a write is terminated by an unplanned event, such as program memory.
loss of power or an unexpected Reset, the memory
location just programmed should be verified and

TABLE 7-2: REGISTERS ASSOCIATED WITH PROGRAM FLASH MEMORY

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
TBLPTRU — — bit 21 Program Memory Table Pointer Upper Byte (TBLPTR<20:16>)
TBPLTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>)
TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>)
TABLAT Program Memory Table Latch
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF
EECON2 Program Memory Control Register 2 (not a physical register)
EECON1 — — WPROG FREE WRERR WREN WR —
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during Flash program memory access.

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 PIC18F47J53 FAMILY
8.0 8 x 8 HARDWARE MULTIPLIER EXAMPLE 8-1: 8 x 8 UNSIGNED MULTIPLY
ROUTINE
8.1 Introduction MOVF ARG1, W ;
MULWF ARG2 ; ARG1 * ARG2 ->
All PIC18 devices include an 8 x 8 hardware multiplier ; PRODH:PRODL
as part of the ALU. The multiplier performs an unsigned
operation and yields a 16-bit result that is stored in the
product register pair, PRODH:PRODL. The multiplier’s EXAMPLE 8-2: 8 x 8 SIGNED MULTIPLY
operation does not affect any flags in the STATUS ROUTINE
register.
MOVF ARG1, W
Making multiplication a hardware operation allows it to MULWF ARG2 ; ARG1 * ARG2 ->
be completed in a single instruction cycle. This has the ; PRODH:PRODL
advantages of higher computational throughput and BTFSC ARG2, SB ; Test Sign Bit
reduced code size for multiplication algorithms and SUBWF PRODH, F ; PRODH = PRODH
allows the PIC18 devices to be used in many applica- ; - ARG1
MOVF ARG2, W
tions previously reserved for digital signal processors.
BTFSC ARG1, SB ; Test Sign Bit
Table 8-1 provides a comparison of various hardware
SUBWF PRODH, F ; PRODH = PRODH
and software multiply operations, along with the ; - ARG2
savings in memory and execution time.

8.2 Operation
Example 8-1 provides the instruction sequence for an
8 x 8 unsigned multiplication. Only one instruction is
required when one of the arguments is already loaded
in the WREG register.
Example 8-2 provides the instruction sequence for an
8 x 8 signed multiplication. To account for the sign bits
of the arguments, each argument’s Most Significant bit
(MSb) is tested and the appropriate subtractions are
done.

TABLE 8-1: PERFORMANCE COMPARISON FOR VARIOUS MULTIPLY OPERATIONS

Program Time
Cycles
Routine Multiply Method Memory
(Max) @ 48 MHz @ 10 MHz @ 4 MHz
(Words)
Without hardware multiply 13 69 5.7 s 27.6 s 69 s
8 x 8 unsigned
Hardware multiply 1 1 83.3 ns 400 ns 1 s
Without hardware multiply 33 91 7.5 s 36.4 s 91 s
8 x 8 signed
Hardware multiply 6 6 500 ns 2.4 s 6 s
Without hardware multiply 21 242 20.1 s 96.8 s 242 s
16 x 16 unsigned
Hardware multiply 28 28 2.3 s 11.2 s 28 s
Without hardware multiply 52 254 21.6 s 102.6 s 254 s
16 x 16 signed
Hardware multiply 35 40 3.3 s 16.0 s 40 s

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Example 8-3 provides the instruction sequence for a EQUATION 8-2: 16 x 16 SIGNED
16 x 16 unsigned multiplication. Equation 8-1 provides MULTIPLICATION
the algorithm that is used. The 32-bit result is stored in ALGORITHM
four registers (RES3:RES0). RES3:RES0 = ARG1H:ARG1L · ARG2H:ARG2L
= (ARG1H · ARG2H · 216) +
EQUATION 8-1: 16 x 16 UNSIGNED (ARG1H · ARG2L · 28) +
MULTIPLICATION (ARG1L · ARG2H · 28) +
(ARG1L · ARG2L) +
ALGORITHM
(-1 · ARG2H<7> · ARG1H:ARG1L · 216) +
RES3:RES0 = ARG1H:ARG1L · ARG2H:ARG2L
(-1 · ARG1H<7> · ARG2H:ARG2L · 216)
= (ARG1H · ARG2H · 216) +
(ARG1H · ARG2L · 28) +
(ARG1L · ARG2H · 28) +
(ARG1L · ARG2L) EXAMPLE 8-4: 16 x 16 SIGNED MULTIPLY
ROUTINE
EXAMPLE 8-3: 16 x 16 UNSIGNED MOVF ARG1L, W
MULWF ARG2L ; ARG1L * ARG2L ->
MULTIPLY ROUTINE
; PRODH:PRODL
MOVF ARG1L, W MOVFF PRODH, RES1 ;
MULWF ARG2L ; ARG1L * ARG2L-> MOVFF PRODL, RES0 ;
; PRODH:PRODL
MOVFF PRODH, RES1 ; MOVF ARG1H, W
MOVFF PRODL, RES0 ; MULWF ARG2H ; ARG1H * ARG2H ->
; PRODH:PRODL
MOVF ARG1H, W MOVFF PRODH, RES3 ;
MULWF ARG2H ; ARG1H * ARG2H-> MOVFF PRODL, RES2 ;
; PRODH:PRODL
MOVFF PRODH, RES3 ; MOVF ARG1L, W
MOVFF PRODL, RES2 ; MULWF ARG2H ; ARG1L * ARG2H ->
; PRODH:PRODL
MOVF ARG1L, W MOVF PRODL, W ;
MULWF ARG2H ; ARG1L * ARG2H-> ADDWF RES1, F ; Add cross
; PRODH:PRODL MOVF PRODH, W ; products
MOVF PRODL, W ; ADDWFC RES2, F ;
ADDWF RES1, F ; Add cross CLRF WREG ;
MOVF PRODH, W ; products ADDWFC RES3, F ;
ADDWFC RES2, F ;
CLRF WREG ; MOVF ARG1H, W ;
ADDWFC RES3, F ; MULWF ARG2L ; ARG1H * ARG2L ->
; PRODH:PRODL
MOVF ARG1H, W ; MOVF PRODL, W ;
MULWF ARG2L ; ARG1H * ARG2L-> ADDWF RES1, F ; Add cross
; PRODH:PRODL MOVF PRODH, W ; products
MOVF PRODL, W ; ADDWFC RES2, F ;
ADDWF RES1, F ; Add cross CLRF WREG ;
MOVF PRODH, W ; products ADDWFC RES3, F ;
ADDWFC RES2, F ;
CLRF WREG ; BTFSS ARG2H, 7 ; ARG2H:ARG2L neg?
ADDWFC RES3, F ; BRA SIGN_ARG1 ; no, check ARG1
MOVF ARG1L, W ;
Example 8-4 provides the sequence to do a 16 x 16 SUBWF RES2 ;
signed multiply. Equation 8-2 provides the algorithm MOVF ARG1H, W ;
used. The 32-bit result is stored in four registers SUBWFB RES3
(RES3:RES0). To account for the sign bits of the
SIGN_ARG1
arguments, the MSb for each argument pair is tested
BTFSS ARG1H, 7 ; ARG1H:ARG1L neg?
and the appropriate subtractions are done.
BRA CONT_CODE ; no, done
MOVF ARG2L, W ;
SUBWF RES2 ;
MOVF ARG2H, W ;
SUBWFB RES3

CONT_CODE
:

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 PIC18F47J53 FAMILY
9.0 INTERRUPTS When the IPEN bit is cleared (default state), the
interrupt priority feature is disabled and interrupts are
Devices of the PIC18F47J53 family have multiple inter- compatible with PIC® mid-range devices. In
rupt sources and an interrupt priority feature that allows Compatibility mode, the interrupt priority bits for each
most interrupt sources to be assigned a high-priority source have no effect. INTCON<6> is the PEIE bit,
level or a low-priority level. The high-priority interrupt which enables/disables all peripheral interrupt sources.
vector is at 0008h and the low-priority interrupt vector INTCON<7> is the GIE bit, which enables/disables all
is at 0018h. High-priority interrupt events will interrupt interrupt sources. All interrupts branch to address
any low-priority interrupts that may be in progress. 0008h in Compatibility mode.
There are 19 registers, which are used to control When an interrupt is responded to, the global interrupt
interrupt operation. These registers are: enable bit is cleared to disable further interrupts. If the
• RCON IPEN bit is cleared, this is the GIE bit. If interrupt priority
• INTCON levels are used, this will be either the GIEH or GIEL bit.
High-priority interrupt sources can interrupt a
• INTCON2
low-priority interrupt. Low-priority interrupts are not
• INTCON3 processed while high-priority interrupts are in progress.
• PIR1, PIR2, PIR3, PIR4, PIR5
The return address is pushed onto the stack and the
• PIE1, PIE2, PIE3, PIE4, PIE5 PC is loaded with the interrupt vector address (0008h
• IPR1, IPR2, IPR3, IPR4, IPR5 or 0018h). Once in the Interrupt Service Routine (ISR),
It is recommended that the Microchip header files the source(s) of the interrupt can be determined by poll-
supplied with MPLAB® IDE be used for the symbolic bit ing the interrupt flag bits. The interrupt flag bits must be
names in these registers. This allows the cleared in software before re-enabling interrupts to
assembler/compiler to automatically take care of the avoid recursive interrupts.
placement of these bits within the specified register. The “return from interrupt” instruction, RETFIE, exits
In general, interrupt sources have three bits to control the interrupt routine and sets the GIE bit (GIEH or GIEL
their operation. They are: if priority levels are used), which re-enables interrupts.
• Flag bit to indicate that an interrupt event For external interrupt events, such as the INTx pins or
occurred the PORTB input change interrupt, the interrupt latency
will be three to four instruction cycles. The exact
• Enable bit that allows program execution to
latency is the same for one or two-cycle instructions.
branch to the interrupt vector address when the
Individual interrupt flag bits are set regardless of the
flag bit is set
status of their corresponding enable bit or the GIE bit.
• Priority bit to select high priority or low priority
Note: Do not use the MOVFF instruction to modify
The interrupt priority feature is enabled by setting the
any of the Interrupt Control registers while
IPEN bit (RCON<7>). When interrupt priority is
any interrupt is enabled. Doing so may
enabled, there are two bits which enable interrupts
cause erratic microcontroller behavior.
globally. Setting the GIEH bit (INTCON<7>) enables all
interrupts that have the priority bit set (high priority).
Setting the GIEL bit (INTCON<6>) enables all
interrupts that have the priority bit cleared (low priority).
When the interrupt flag, enable bit and appropriate
global interrupt enable bit are set, the interrupt will
vector immediately to address, 0008h or 0018h,
depending on the priority bit setting. Individual
interrupts can be disabled through their corresponding
enable bits.

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PIC18F47J53 FAMILY
FIGURE 9-1: PIC18F47J53 FAMILY INTERRUPT LOGIC

TMR0IF Wake-up if in
TMR0IE Idle or Sleep modes
TMR0IP
RBIF
RBIE
RBIP
INT0IF
INT0IE
INT1IF
INT1IE Interrupt to CPU
INT1IP Vector to Location
INT2IF
INT2IE 0008h
PIR1<7:0>
PIE1<7:0> INT2IP
IPR1<7:0> INT3IF
INT3IE
INT3IP
PIR2<7:0> GIE/GIEH
PIE2<7:0>
IPR2<7:0> IPEN

PIR3<7:0> IPEN
PIE3<7:0>
IPR3<7:0> PEIE/GIEL
IPEN

High-Priority Interrupt Generation

Low-Priority Interrupt Generation

PIR1<7:0>
PIE1<7:0>
IPR1<7:0>

PIR2<7:0>
PIE2<7:0>
IPR2<7:0> Interrupt to CPU
TMR0IF Vector to Location
TMR0IE IPEN
PIR3<7:0> 0018h
PIE3<7:0> TMR0IP
IPR3<7:0>
RBIF
RBIE
RBIP GIE/GIEH
PEIE/GIEL
INT1IF
INT1IE
INT1IP
INT2IF
INT2IE
INT2IP
INT3IF
INT3IE
INT3IP

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 PIC18F47J53 FAMILY
9.1 INTCON Registers Note: Interrupt flag bits are set when an interrupt
The INTCON registers are readable and writable condition occurs, regardless of the state of
registers, which contain various enable, priority and its corresponding enable bit or the global
flag bits. interrupt enable bit. User software should
ensure the appropriate interrupt flag bits
are clear prior to enabling an interrupt.
This feature allows for software polling.

REGISTER 9-1: INTCON: INTERRUPT CONTROL REGISTER (ACCESS FF2h)

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x
GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF(1)
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 GIE/GIEH: Global Interrupt Enable bit

When IPEN = 0:
1 = Enables all unmasked interrupts
0 = Disables all interrupts
When IPEN = 1:
1 = Enables all high-priority interrupts
0 = Disables all interrupts
bit 6 PEIE/GIEL: Peripheral Interrupt Enable bit
When IPEN = 0:
1 = Enables all unmasked peripheral interrupts
0 = Disables all peripheral interrupts
When IPEN = 1:
1 = Enables all low-priority peripheral interrupts
0 = Disables all low-priority peripheral interrupts
bit 5 TMR0IE: TMR0 Overflow Interrupt Enable bit
1 = Enables the TMR0 overflow interrupt
0 = Disables the TMR0 overflow interrupt
bit 4 INT0IE: INT0 External Interrupt Enable bit
1 = Enables the INT0 external interrupt
0 = Disables the INT0 external interrupt
bit 3 RBIE: RB Port Change Interrupt Enable bit
1 = Enables the RB port change interrupt
0 = Disables the RB port change interrupt
bit 2 TMR0IF: TMR0 Overflow Interrupt Flag bit
1 = The TMR0 register has overflowed (must be cleared in software)
0 = The TMR0 register did not overflow
bit 1 INT0IF: INT0 External Interrupt Flag bit
1 = The INT0 external interrupt occurred (must be cleared in software)
0 = The INT0 external interrupt did not occur
bit 0 RBIF: RB Port Change Interrupt Flag bit(1)
1 = At least one of the RB<7:4> pins changed state (must be cleared in software)
0 = None of the RB<7:4> pins have changed state

Note 1: A mismatch condition will continue to set this bit. Reading PORTB and waiting 1 TCY will end the mismatch
condition and allow the bit to be cleared.

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REGISTER 9-2: INTCON2: INTERRUPT CONTROL REGISTER 2 (ACCESS FF1h)
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
RBPU INTEDG0 INTEDG1 INTEDG2 INTEDG3 TMR0IP INT3IP RBIP
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 RBPU: PORTB Pull-up Enable bit

1 = All PORTB pull-ups are disabled
0 = PORTB pull-ups are enabled by individual port latch values
bit 6 INTEDG0: External Interrupt 0 Edge Select bit
1 = Interrupt on rising edge
0 = Interrupt on falling edge
bit 5 INTEDG1: External Interrupt 1 Edge Select bit
1 = Interrupt on rising edge
0 = Interrupt on falling edge
bit 4 INTEDG2: External Interrupt 2 Edge Select bit
1 = Interrupt on rising edge
0 = Interrupt on falling edge
bit 3 INTEDG3: External Interrupt 3 Edge Select bit
1 = Interrupt on rising edge
0 = Interrupt on falling edge
bit 2 TMR0IP: TMR0 Overflow Interrupt Priority bit
1 = High priority
0 = Low priority
bit 1 INT3IP: INT3 External Interrupt Priority bit
1 = High priority
0 = Low priority
bit 0 RBIP: RB Port Change Interrupt Priority bit
1 = High priority
0 = Low priority

Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding
enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits
are clear prior to enabling an interrupt. This feature allows for software polling.

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 PIC18F47J53 FAMILY
REGISTER 9-3: INTCON3: INTERRUPT CONTROL REGISTER 3 (ACCESS FF0h)
R/W-1 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
INT2IP INT1IP INT3IE INT2IE INT1IE INT3IF INT2IF INT1IF
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 INT2IP: INT2 External Interrupt Priority bit

1 = High priority
0 = Low priority
bit 6 INT1IP: INT1 External Interrupt Priority bit
1 = High priority
0 = Low priority
bit 5 INT3IE: INT3 External Interrupt Enable bit
1 = Enables the INT3 external interrupt
0 = Disables the INT3 external interrupt
bit 4 INT2IE: INT2 External Interrupt Enable bit
1 = Enables the INT2 external interrupt
0 = Disables the INT2 external interrupt
bit 3 INT1IE: INT1 External Interrupt Enable bit
1 = Enables the INT1 external interrupt
0 = Disables the INT1 external interrupt
bit 2 INT3IF: INT3 External Interrupt Flag bit
1 = The INT3 external interrupt occurred (must be cleared in software)
0 = The INT3 external interrupt did not occur
bit 1 INT2IF: INT2 External Interrupt Flag bit
1 = The INT2 external interrupt occurred (must be cleared in software)
0 = The INT2 external interrupt did not occur
bit 0 INT1IF: INT1 External Interrupt Flag bit
1 = The INT1 external interrupt occurred (must be cleared in software)
0 = The INT1 external interrupt did not occur

Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding
enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits
are clear prior to enabling an interrupt. This feature allows for software polling.

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9.2 PIR Registers Note 1: Interrupt flag bits are set when an interrupt
The PIR registers contain the individual flag bits for the condition occurs, regardless of the state of
peripheral interrupts. Due to the number of peripheral its corresponding enable bit or the Global
interrupt sources, there are three Peripheral Interrupt Interrupt Enable bit, GIE (INTCON<7>).
Request (Flag) registers (PIR1, PIR2, PIR3). 2: User software should ensure the
appropriate interrupt flag bits are cleared
prior to enabling an interrupt and after
servicing that interrupt.

REGISTER 9-4: PIR1: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1 (ACCESS F9Eh)
R/W-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0
PMPIF(1) ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 PMPIF: Parallel Master Port Read/Write Interrupt Flag bit(1)

1 = A read or a write operation has taken place (must be cleared in software)
0 = No read or write has occurred
bit 6 ADIF: A/D Converter Interrupt Flag bit
1 = An A/D conversion completed (must be cleared in software)
0 = The A/D conversion is not complete
bit 5 RC1IF: EUSART1 Receive Interrupt Flag bit
1 = The EUSART1 receive buffer, RCREG1, is full (cleared when RCREG1 is read)
0 = The EUSART1 receive buffer is empty
bit 4 TX1IF: EUSART1 Transmit Interrupt Flag bit
1 = The EUSART1 transmit buffer, TXREG1, is empty (cleared when TXREG1 is written)
0 = The EUSART1 transmit buffer is full
bit 3 SSP1IF: Master Synchronous Serial Port 1 Interrupt Flag bit
1 = The transmission/reception is complete (must be cleared in software)
0 = Waiting to transmit/receive
bit 2 CCP1IF: ECCP1 Interrupt Flag bit
Capture mode:
1 = A TMR1/TMR3 register capture occurred (must be cleared in software)
0 = No TMR1/TMR3 register capture occurred
Compare mode:
1 = A TMR1/TMR3 register compare match occurred (must be cleared in software)
0 = No TMR1/TMR3 register compare match occurred
PWM mode:
Unused in this mode.
bit 1 TMR2IF: TMR2 to PR2 Match Interrupt Flag bit
1 = TMR2 to PR2 match occurred (must be cleared in software)
0 = No TMR2 to PR2 match occurred
bit 0 TMR1IF: TMR1 Overflow Interrupt Flag bit
1 = TMR1 register overflowed (must be cleared in software)
0 = TMR1 register did not overflow

Note 1: These bits are unimplemented on 28-pin devices.

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REGISTER 9-5: PIR2: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 2 (ACCESS FA1h)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
OSCFIF CM2IF CM1IF USBIF BCL1IF HLVDIF TMR3IF CCP2IF
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 OSCFIF: Oscillator Fail Interrupt Flag bit

1 = The device oscillator failed, clock input has changed to INTOSC (must be cleared in software)
0 = The device clock operating
bit 6 CM2IF: Comparator 2 Interrupt Flag bit
1 = The comparator input has changed (must be cleared in software)
0 = The comparator input has not changed
bit 5 CM1IF: Comparator 1 Interrupt Flag bit
1 = The comparator input has changed (must be cleared in software)
0 = The comparator input has not changed
bit 4 USBIF: USB Interrupt Flag bit
1 = USB has requested an interrupt (must be cleared in software)
0 = No USB interrupt request
bit 3 BCL1IF: Bus Collision Interrupt Flag bit (MSSP1 module)
1 = A bus collision occurred (must be cleared in software)
0 = No bus collision occurred
bit 2 HLVDIF: High/Low-Voltage Detect (HLVD) Interrupt Flag bit
1 = A High/Low-Voltage condition occurred (must be cleared in software)
0 = An HLVD event has not occurred
bit 1 TMR3IF: TMR3 Overflow Interrupt Flag bit
1 = The TMR3 register overflowed (must be cleared in software)
0 = The TMR3 register did not overflow
bit 0 CCP2IF: ECCP2 Interrupt Flag bit
Capture mode:
1 = A TMR1/TMR3 register capture occurred (must be cleared in software)
0 = No TMR1/TMR3 register capture occurred
Compare mode:
1 = A TMR1/TMR3 register compare match occurred (must be cleared in software)
0 = No TMR1/TMR3 register compare match occurred
PWM mode:
Unused in this mode.

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REGISTER 9-6: PIR3: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 3 (ACCESS FA4h)
R/W-0 R/W-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
SSP2IF BCL2IF RC2IF TX2IF TMR4IF CTMUIF TMR3GIF RTCCIF
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 SSP2IF: Master Synchronous Serial Port 2 Interrupt Flag bit

1 = The transmission/reception is complete (must be cleared in software)
0 = Waiting to transmit/receive
bit 6 BCL2IF: Bus Collision Interrupt Flag bit (MSSP2 module)
1 = A bus collision occurred (must be cleared in software)
0 = No bus collision occurred
bit 5 RC2IF: EUSART2 Receive Interrupt Flag bit
1 = The EUSART2 receive buffer, RCREG2, is full (cleared when RCREG2 is read)
0 = The EUSART2 receive buffer is empty
bit 4 TX2IF: EUSART2 Transmit Interrupt Flag bit
1 = The EUSART2 transmit buffer, TXREG2, is empty (cleared when TXREG2 is written)
0 = The EUSART2 transmit buffer is full
bit 3 TMR4IF: TMR4 to PR4 Match Interrupt Flag bit
1 = A TMR4 to PR4 match occurred (must be cleared in software)
0 = No TMR4 to PR4 match occurred
bit 2 CTMUIF: Charge Time Measurement Unit Interrupt Flag bit
1 = A CTMU event has occurred (must be cleared in software)
0 = A CTMU event has not occurred
bit 1 TMR3GIF: Timer3 Gate Event Interrupt Flag bit
1 = A Timer3 gate event completed (must be cleared in software)
0 = No Timer3 gate event completed
bit 0 RTCCIF: RTCC Interrupt Flag bit
1 = An RTCC interrupt occurred (must be cleared in software)
0 = No RTCC interrupt occurred

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REGISTER 9-7: PIR4: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 4 (ACCESS F8Fh)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CCP10IF CCP9IF CCP8IF CCP7IF CCP6IF CCP5IF CCP4IF CCP3IF
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-1 CCP10IF:CCP4IF: CCP<10:4> Interrupt Flag bits

Capture Mode
1 = A TMR register capture occurred (must be cleared in software)
0 = No TMR register capture occurred
Compare Mode
1 = A TMR register compare match occurred (must be cleared in software)
0 = No TMR register compare match occurred
PWM Mode
Unused in this mode.
bit 0 CCP3IF: ECCP3 Interrupt Flag bit
Capture Mode
1 = A TMR register capture occurred (must be cleared in software)
0 = No TMR register capture occurred
Compare Mode
1 = A TMR register compare match occurred (must be cleared in software)
0 = No TMR register compare match occurred
PWM Mode
Unused in this mode.

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REGISTER 9-8: PIR5: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 5 (ACCESS F98h)
U-0 U-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — CM3IF TMR8IF TMR6IF TMR5IF TMR5GIF TMR1GIF
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-6 Unimplemented: Read as ‘0’

bit 5 CM3IF: Comparator Interrupt Flag bit
1 = Comparator3 input has changed (must be cleared in software)
0 = Comparator3 input has not changed
bit 4 TMR8IF: TMR8 to PR8 Match Interrupt Flag bit
1 = TMR8 to PR8 match occurred (must be cleared in software)
0 = No TMR8 to PR8 match occurred
bit 3 TMR6IF: TMR6 to PR6 Match Interrupt Flag bit
1 = TMR6 to PR6 match occurred (must be cleared in software)
0 = No TMR6 to PR6 match occurred
bit 2 TMR5IF: TMR3 Overflow Interrupt Flag bit
1 = TMR3 register overflowed (must be cleared in software)
0 = TMR3 register did not overflow
bit 1 TMR5GIF: TMR5 Gate Interrupt Flag bits
1 = TMR gate interrupt occurred (must be cleared in software)
0 = No TMR gate interrupt occurred
bit 0 TMR1GIF: TMR5 Gate Interrupt Flag bits
1 = TMR gate interrupt occurred (must be cleared in software)
0 = No TMR gate interrupt occurred

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9.3 PIE Registers
The PIE registers contain the individual enable bits for
the peripheral interrupts. Due to the number of
peripheral interrupt sources, there are three Peripheral
Interrupt Enable registers (PIE1, PIE2, PIE3). When
IPEN = 0, the PEIE bit must be set to enable any of
these peripheral interrupts.

REGISTER 9-9: PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1 (ACCESS F9Dh)

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
(1)
PMPIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 PMPIE: Parallel Master Port Read/Write Interrupt Enable bit(1)

1 = Enables the PMP read/write interrupt
0 = Disables the PMP read/write interrupt
bit 6 ADIE: A/D Converter Interrupt Enable bit
1 = Enables the A/D interrupt
0 = Disables the A/D interrupt
bit 5 RC1IE: EUSART1 Receive Interrupt Enable bit
1 = Enables the EUSART1 receive interrupt
0 = Disables the EUSART1 receive interrupt
bit 4 TX1IE: EUSART1 Transmit Interrupt Enable bit
1 = Enables the EUSART1 transmit interrupt
0 = Disables the EUSART1 transmit interrupt
bit 3 SSP1IE: Master Synchronous Serial Port 1 Interrupt Enable bit
1 = Enables the MSSP1 interrupt
0 = Disables the MSSP1 interrupt
bit 2 CCP1IE: ECCP1 Interrupt Enable bit
1 = Enables the ECCP1 interrupt
0 = Disables the ECCP1 interrupt
bit 1 TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1 = Enables the TMR2 to PR2 match interrupt
0 = Disables the TMR2 to PR2 match interrupt
bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit
1 = Enables the TMR1 overflow interrupt
0 = Disables the TMR1 overflow interrupt

Note 1: These bits are unimplemented on 28-pin devices.

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REGISTER 9-10: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2 (ACCESS FA0h)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
OSCFIE CM2IE CM1IE USBIE BCL1IE HLVDIE TMR3IE CCP2IE
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 OSCFIE: Oscillator Fail Interrupt Enable bit

1 = Enabled
0 = Disabled
bit 6 CM2IE: Comparator 2 Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 5 CM1IE: Comparator 1 Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 4 USBIE: USB Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 3 BCL1IE: Bus Collision Interrupt Enable bit (MSSP1 module)
1 = Enabled
0 = Disabled
bit 2 HLVDIE: High/Low-Voltage Detect Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 1 TMR3IE: TMR3 Overflow Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 0 CCP2IE: ECCP2 Interrupt Enable bit
1 = Enabled
0 = Disabled

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REGISTER 9-11: PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER 3 (ACCESS FA3h)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
SSP2IE BCL2IE RC2IE TX2IE TMR4IE CTMUIE TMR3GIE RTCCIE
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 SSP2IE: Master Synchronous Serial Port 2 Interrupt Enable bit

1 = Enabled
0 = Disabled
bit 6 BCL2IE: Bus Collision Interrupt Enable bit (MSSP2 module)
1 = Enabled
0 = Disabled
bit 5 RC2IE: EUSART2 Receive Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 4 TX2IE: EUSART2 Transmit Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 3 TMR4IE: TMR4 to PR4 Match Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 2 CTMUIE: Charge Time Measurement Unit (CTMU) Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 1 TMR3GIE: Timer3 Gate Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 0 RTCCIE: RTCC Interrupt Enable bit
1 = Enabled
0 = Disabled

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REGISTER 9-12: PIE4: PERIPHERAL INTERRUPT ENABLE REGISTER 4 (ACCESS F8Eh)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CCP10IE CCP9IE CCP8IE CCP7IE CCP6IE CCP5IE CCP4IE CCP3IE
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-1 CCP10IE:CCP4IE: CCP<10:4> Interrupt Enable bits

1 = Enabled
0 = Disabled
bit 0 CCP3IE: ECCP3 Interrupt Enable bit
1 = Enabled
0 = Disabled

REGISTER 9-13: PIE5: PERIPHERAL INTERRUPT ENABLE REGISTER 5 (ACCESS F91h)

U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — CM3IE TMR8IE TMR6IE TMR5IE TMR5GIE TMR1GIE
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-6 Unimplemented: Read as ‘0’

bit 5 CM3IE: Comparator3 Receive Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 4 TMR8IE: TMR8 to PR8 Match Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 3 TMR6IE: TMR6 to PR6 Match Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 2 TMR5IE: TMR5 Overflow Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 1 TMR5GIE: TMR5 Gate Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 0 TMR1GIE: TMR1 Gate Interrupt Enable bit
1 = Enabled
0 = Disabled

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 PIC18F47J53 FAMILY
9.4 IPR Registers
The IPR registers contain the individual priority bits for
the peripheral interrupts. Due to the number of
peripheral interrupt sources, there are three Peripheral
Interrupt Priority registers (IPR1, IPR2, IPR3). Using
the priority bits requires that the Interrupt Priority
Enable (IPEN) bit be set.

REGISTER 9-14: IPR1: PERIPHERAL INTERRUPT PRIORITY REGISTER 1 (ACCESS F9Fh)

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
PMPIP(1) ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 PMPIP: Parallel Master Port Read/Write Interrupt Priority bit(1)

1 = High priority
0 = Low priority
bit 6 ADIP: A/D Converter Interrupt Priority bit
1 = High priority
0 = Low priority
bit 5 RC1IP: EUSART1 Receive Interrupt Priority bit
1 = High priority
0 = Low priority
bit 4 TX1IP: EUSART1 Transmit Interrupt Priority bit
1 = High priority
0 = Low priority
bit 3 SSP1IP: Master Synchronous Serial Port Interrupt Priority bit (MSSP1 module)
1 = High priority
0 = Low priority
bit 2 CCP1IP: ECCP1 Interrupt Priority bit
1 = High priority
0 = Low priority
bit 1 TMR2IP: TMR2 to PR2 Match Interrupt Priority bit
1 = High priority
0 = Low priority
bit 0 TMR1IP: TMR1 Overflow Interrupt Priority bit
1 = High priority
0 = Low priority

Note 1: These bits are unimplemented on 28-pin devices.

 2010 Microchip Technology Inc. Preliminary DS39964B-page 135

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REGISTER 9-15: IPR2: PERIPHERAL INTERRUPT PRIORITY REGISTER 2 (ACCESS FA2h)
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
OSCFIP CM2IP CM1IP USBIP BCL1IP HLVDIP TMR3IP CCP2IP
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 OSCFIP: Oscillator Fail Interrupt Priority bit

1 = High priority
0 = Low priority
bit 6 CM2IP: Comparator 2 Interrupt Priority bit
1 = High priority
0 = Low priority
bit 5 C12IP: Comparator 1 Interrupt Priority bit
1 = High priority
0 = Low priority
bit 4 USBIP: USB Interrupt Priority bit
1 = High priority
0 = Low priority
bit 3 BCL1IP: Bus Collision Interrupt Priority bit (MSSP1 module)
1 = High priority
0 = Low priority
bit 2 HLVDIP: High/Low-Voltage Detect Interrupt Priority bit
1 = High priority
0 = Low priority
bit 1 TMR3IP: TMR3 Overflow Interrupt Priority bit
1 = High priority
0 = Low priority
bit 0 CCP2IP: ECCP2 Interrupt Priority bit
1 = High priority
0 = Low priority

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 PIC18F47J53 FAMILY
REGISTER 9-16: IPR3: PERIPHERAL INTERRUPT PRIORITY REGISTER 3 (ACCESS FA5h)
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
SSP2IP BCL2IP RC2IP TX2IP TMR4IP CTMUIP TMR3GIP RTCCIP
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 SSP2IP: Master Synchronous Serial Port 2 Interrupt Priority bit

1 = High priority
0 = Low priority
bit 6 BCL2IP: Bus Collision Interrupt Priority bit (MSSP2 module)
1 = High priority
0 = Low priority
bit 5 RC2IP: EUSART2 Receive Interrupt Priority bit
1 = High priority
0 = Low priority
bit 4 TX2IP: EUSART2 Transmit Interrupt Priority bit
1 = High priority
0 = Low priority
bit 3 TMR4IE: TMR4 to PR4 Interrupt Priority bit
1 = High priority
0 = Low priority
bit 2 CTMUIP: Charge Time Measurement Unit (CTMU) Interrupt Priority bit
1 = High priority
0 = Low priority
bit 1 TMR3GIP: Timer3 Gate Interrupt Priority bit
1 = High priority
0 = Low priority
bit 0 RTCCIP: RTCC Interrupt Priority bit
1 = High priority
0 = Low priority

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REGISTER 9-17: IPR4: PERIPHERAL INTERRUPT PRIORITY REGISTER 4 (ACCESS F90h)
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
CCP10IP CCP9IP CCP8IP CCP7IP CCP6IP CCP5IP CCP4IP CCP3IP
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-1 CCP10IP:CCP4IP: CCP<10:4> Interrupt Priority bits

1 = High priority
0 = Low priority
bit 0 CCP3IP: ECCP3 Interrupt Priority bit
1 = High priority
0 = Low priority

REGISTER 9-18: IPR5: PERIPHERAL INTERRUPT PRIORITY REGISTER 5 (ACCESS F99h)

U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
— — CM3IP TMR8IP TMR6IP TMR5IP TMR5GIP TMR1GIP
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-6 Unimplemented: Read as ‘0’

bit 5 CM3IP: Comparator3 Interrupt Priority bit
1 = High priority
0 = Low priority
bit 4 TMR8IP: TMR8 to PR8 Match Interrupt Priority bit
1 = High priority
0 = Low priority
bit 3 TMR6IP: TMR6 to PR6 Match Interrupt Priority bit
1 = High priority
0 = Low priority
bit 2 TMR5IP: TMR5 Overflow Interrupt Priority bit
1 = High priority
0 = Low priority
bit 1 TMR5GIP: TMR5 Gate Interrupt Priority bit
1 = High priority
0 = Low priority
bit 0 TMR1GIP: TMR1 Gate Interrupt Priority bit
1 = High priority
0 = Low priority

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 PIC18F47J53 FAMILY
9.5 RCON Register
The RCON register contains bits used to determine the
cause of the last Reset or wake-up from Idle or Sleep
mode. RCON also contains the bit that enables
interrupt priorities (IPEN).

REGISTER 9-19: RCON: RESET CONTROL REGISTER (ACCESS FD0h)

R/W-0 U-0 R/W-1 R/W-1 R-1 R-1 R/W-0 R/W-0
IPEN — CM RI TO PD POR BOR
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 IPEN: Interrupt Priority Enable bit

1 = Enable priority levels on interrupts
0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode)
bit 6 Unimplemented: Read as ‘0’
bit 5 CM: Configuration Mismatch Flag bit
For details on bit operation, see Register 5-1.
bit 4 RI: RESET Instruction Flag bit
For details on bit operation, see Register 5-1.
bit 3 TO: Watchdog Timer Time-out Flag bit
For details on bit operation, see Register 5-1.
bit 2 PD: Power-Down Detection Flag bit
For details on bit operation, see Register 5-1.
bit 1 POR: Power-on Reset Status bit
For details on bit operation, see Register 5-1.
bit 0 BOR: Brown-out Reset Status bit
For details on bit operation, see Register 5-1.

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9.6 INTx Pin Interrupts pair (FFFFh  0000h) will set TMR0IF. The interrupt
can be enabled/disabled by setting/clearing enable bit,
External interrupts on the INT0, INT1, INT2 and INT3 TMR0IE (INTCON<5>). Interrupt priority for Timer0 is
pins are edge-triggered. If the corresponding INTEDGx determined by the value contained in the interrupt prior-
bit in the INTCON2 register is set (= 1), the interrupt is ity bit, TMR0IP (INTCON2<2>). See Section 12.0
triggered by a rising edge; if the bit is clear, the trigger “Timer0 Module” for further details on the Timer0
is on the falling edge. When a valid edge appears on module.
the INTx pin, the corresponding flag bit and INTxIF are
set. This interrupt can be disabled by clearing the
9.8 PORTB Interrupt-on-Change
corresponding enable bit, INTxIE. Flag bit, INTxIF,
must be cleared in software in the Interrupt Service An input change on PORTB<7:4> sets flag bit, RBIF
Routine before re-enabling the interrupt. (INTCON<0>). The interrupt can be enabled/disabled
All external interrupts (INT0, INT1, INT2 and INT3) can by setting/clearing enable bit, RBIE (INTCON<3>).
wake up the processor from the Sleep and Idle modes Interrupt priority for PORTB interrupt-on-change is
if bit, INTxIE, was set prior to going into the power-man- determined by the value contained in the interrupt
aged modes. Deep Sleep mode can wake up from priority bit, RBIP (INTCON2<0>).
INT0, but the processor will start execution from the
power-on reset vector rather than branch to the 9.9 Context Saving During Interrupts
interrupt vector.
During interrupts, the return PC address is saved on
Interrupt priority for INT1, INT2 and INT3 is determined the stack. Additionally, the WREG, STATUS and BSR
by the value contained in the Interrupt Priority bits, registers are saved on the Fast Return Stack. If a fast
INT1IP (INTCON3<6>), INT2IP (INTCON3<7>) and return from interrupt is not used (see Section 6.3
INT3IP (INTCON2<1>). There is no priority bit “Data Memory Organization”), the user may need to
associated with INT0; It is always a high-priority save the WREG, STATUS and BSR registers on entry
interrupt source. to the Interrupt Service Routine. Depending on the
user’s application, other registers may also need to be
9.7 TMR0 Interrupt saved. Example 9-1 saves and restores the WREG,
STATUS and BSR registers during an Interrupt Service
In 8-bit mode (which is the default), an overflow in the Routine.
TMR0 register (FFh  00h) will set flag bit, TMR0IF. In
16-bit mode, an overflow in the TMR0H:TMR0L register

EXAMPLE 9-1: SAVING STATUS, WREG AND BSR REGISTERS IN RAM

MOVWF W_TEMP ; W_TEMP is in virtual bank
MOVFF STATUS, STATUS_TEMP ; STATUS_TEMP located anywhere
MOVFF BSR, BSR_TEMP ; BSR_TMEP located anywhere
;
; USER ISR CODE
;
MOVFF BSR_TEMP, BSR ; Restore BSR
MOVF W_TEMP, W ; Restore WREG
MOVFF STATUS_TEMP, STATUS ; Restore STATUS

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10.0 I/O PORTS 10.1 I/O Port Pin Capabilities
Depending on the device selected and features When developing an application, the capabilities of the
enabled, there are up to five ports available. Some pins port pins must be considered. Outputs on some pins
of the I/O ports are multiplexed with an alternate have higher output drive strength than others. Similarly,
function from the peripheral features on the device. In some pins can tolerate higher than VDD input levels.
general, when a peripheral is enabled, that pin may not
be used as a general purpose I/O pin. 10.1.1 PIN OUTPUT DRIVE
Each port has three registers for its operation. These The output pin drive strengths vary for groups of pins
registers are: intended to meet the needs for a variety of applications.
PORTB and PORTC are designed to drive higher
• TRIS register (Data Direction register)
loads, such as LEDs. All other ports are designed for
• PORT register (reads the levels on the pins of the small loads, typically indication only. Table 10-1 sum-
device) marizes the output capabilities. Refer to Section 31.0
• LAT register (Data Latch) “Electrical Characteristics” for more details.
The Data Latch (LAT register) is useful for read-modify-
write operations on the value that the I/O pins are TABLE 10-1: OUTPUT DRIVE LEVELS
driving. Port Drive Description
Figure 10-1 displays a simplified model of a generic I/O
PORTA
port, without the interfaces to other peripherals.
PORTD Minimum Intended for indication.
FIGURE 10-1: GENERIC I/O PORT PORTE
OPERATION PORTB Suitable for direct LED drive
High
PORTC levels.

RD LAT
10.1.2 INPUT PINS AND VOLTAGE
Data
Bus CONSIDERATIONS
D Q
WR LAT I/O pin(1)
The voltage tolerance of pins used as device inputs is
or PORT
CK
dependent on the pin’s input function. Pins that are used
as digital only inputs are able to handle DC voltages up
Data Latch
to 5.5V; a level typical for digital logic circuits. In contrast,
D Q pins that also have analog input functions of any kind
can only tolerate voltages up to VDD. Voltage excur-
WR TRIS
CK sions beyond VDD on these pins should be avoided.
TRIS Latch
Table 10-2 summarizes the input capabilities. Refer to
Input
Buffer Section 31.0 “Electrical Characteristics” for more
details.
RD TRIS

TABLE 10-2: INPUT VOLTAGE LEVELS

Q D
Tolerated
Port or Pin Description
Input
ENEN
PORTA<7:0>
RD PORT
PORTB<3:0> Only VDD input levels
VDD
PORTC<2:0> tolerated.
Note 1: I/O pins have diode protection to VDD and
VSS. PORTE<2:0>
PORTB<7:4> Tolerates input levels
PORTC<7:6> 5.5V above VDD, useful for
PORTD<7:0> most standard logic.
PORTC<5:4> (USB) Designed for USB
specifications.

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PIC18F47J53 FAMILY
10.1.3 INTERFACING TO A 5V SYSTEM the ECCP modules. It is selectively enabled by setting
the open-drain control bit for the corresponding module
Though the VDDMAX of the PIC18F47J53 family is 3.6V,
in the ODCON registers (Register 10-1, Register 10-2
these devices are still capable of interfacing with 5V
and Register 10-3). Their configuration is discussed in
systems, even if the VIH of the target system is above
more detail with the individual port where these
3.6V. This is accomplished by adding a pull-up resistor
peripherals are multiplexed. Output functions that are
to the port pin (Figure 10-2), clearing the LAT bit for that
routed through the PPS module may also use the
pin and manipulating the corresponding TRIS bit
open-drain option. The open-drain functionality will
(Figure 10-1) to either allow the line to be pulled high or
follow the I/O pin assignment in the PPS module.
to drive the pin low. Only port pins that are tolerant of
voltages up to 5.5V can be used for this type of When the open-drain option is required, the output pin
interface (refer to Section 10.1.2 “Input Pins and must also be tied through an external pull-up resistor
Voltage Considerations”). provided by the user to a higher voltage level, up to
5.5V (Figure 10-3). When a digital logic high signal is
FIGURE 10-2: +5V SYSTEM HARDWARE output, it is pulled up to the higher voltage level.
INTERFACE
FIGURE 10-3: USING THE OPEN-DRAIN
+5V OUTPUT (USART SHOWN
PIC18F47J53 +5V Device
AS EXAMPLE)

3.3V +5V
PIC18F47J53
RD7

VDD TXX 5V
(at logic ‘1’)

EXAMPLE 10-1: COMMUNICATING WITH

THE +5V SYSTEM
BCF LATD, 7 ; set up LAT register so
; changing TRIS bit will
; drive line low 10.1.5 TTL INPUT BUFFER OPTION
BCF TRISD, 7 ; send a 0 to the 5V system
Many of the digital I/O ports use Schmitt Trigger (ST)
BCF TRISD, 7 ; send a 1 to the 5V system
input buffers. While this form of buffering works well
with many types of input, some applications may
require TTL level signals to interface with external logic
10.1.4 OPEN-DRAIN OUTPUTS
devices. This is particularly true for the Parallel Master
The output pins for several peripherals are also Port (PMP), which is likely to be interfaced to TTL level
equipped with a configurable open-drain output option. logic or memory devices.
This allows the peripherals to communicate with The inputs for the PMP can be optionally configured for
external digital logic operating at a higher voltage level, TTL buffers with the PMPTTL bit in the PADCFG1 reg-
without the use of level translators. ister (Register 10-4). Setting this bit configures all data
The open-drain option is implemented on port pins and control input pins for the PMP to use TTL buffers.
specifically associated with the data and clock outputs By default, these PMP inputs use the port’s ST buffers.
of the EUSARTs, the MSSP modules (in SPI mode) and

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REGISTER 10-1: ODCON1: PERIPHERAL OPEN-DRAIN CONTROL REGISTER 1 (BANKED F42h)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CCP8OD CCP7OD CCP6OD CCP5OD CCP4OD ECCP3OD ECCP2OD ECCP1OD
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 CCP8OD: CCP8 Open-Drain Output Enable bit

1 = Open-drain capability is enabled
0 = Open-drain capability is disabled
bit 6 CCP7OD: CCP7 Open-Drain Output Enable bit
1 = Open-drain capability is enabled
0 = Open-drain capability is disabled
bit 5 CCP6OD: CCP6 Open-Drain Output Enable bit
1 = Open-drain capability is enabled
0 = Open-drain capability is disabled
bit 4 CCP5OD: CCP5 Open-Drain Output Enable bit
1 = Open-drain capability is enabled
0 = Open-drain capability is disabled
bit 3 CCP4OD: CCP4 Open-Drain Output Enable bit
1 = Open-drain capability is enabled
0 = Open-drain capability is disabled
bit 2 ECCP3OD: ECCP3 Open-Drain Output Enable bit
1 = Open-drain capability is enabled
0 = Open-drain capability is disabled
bit 1 ECCP2OD: ECCP2 Open-Drain Output Enable bit
1 = Open-drain capability is enabled
0 = Open-drain capability is disabled
bit 0 ECCP1OD: ECCP1 Open-Drain Output Enable bit
1 = Open-drain capability is enabled
0 = Open-drain capability is disabled

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REGISTER 10-2: ODCON2: PERIPHERAL OPEN-DRAIN CONTROL REGISTER 2 (BANKED F41h)
U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — — CCP10OD CCP9OD U2OD U1OD
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-4 Unimplemented: Read as ‘0’

bit 3 CCP10OD: CCP10 Open-Drain Output Enable bit
1 = Open-drain capability is enabled
0 = Open-drain capability is disabled
bit 2 CCP9OD: CCP9 Open-Drain Output Enable bit
1 = Open-drain capability is enabled
0 = Open-drain capability is disabled
bit 1 U2OD: USART2 Open-Drain Output Enable bit
1 = Open-drain capability is enabled
0 = Open-drain capability is disabled
bit 0 U1OD: USART1 Open-Drain Output Enable bit
1 = Open-drain capability is enabled
0 = Open-drain capability is disabled

REGISTER 10-3: ODCON3: PERIPHERAL OPEN-DRAIN CONTROL REGISTER 3 (BANKED F40h)

U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0
— — — — — — SPI2OD SPI1OD
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-2 Unimplemented: Read as ‘0’

bit 1 SPI2OD: SPI2 Open-Drain Output Enable bit
1 = Open-drain capability is enabled
0 = Open-drain capability is disabled
bit 0 SPI1OD: SPI1 Open-Drain Output Enable bit
1 = Open-drain capability is enabled
0 = Open-drain capability is disabled

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REGISTER 10-4: PADCFG1: PAD CONFIGURATION CONTROL REGISTER 1 (BANKED F3Ch)
U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0
— — — — — RTSECSEL1(1) RTSECSEL0(1) PMPTTL
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-3 Unimplemented: Read as ‘0’

bit 2-1 RTSECSEL<1:0>: RTCC Seconds Clock Output Select bits(1)
11 = Reserved; do not use
10 = RTCC source clock is selected for the RTCC pin (can be INTRC, T1OSC or T1CKI depending
upon the RTCOSC (CONFIG3L<1>) and T1OSCEN (T1CON<3>) bit settings)
01 = RTCC seconds clock is selected for the RTCC pin
00 = RTCC alarm pulse is selected for the RTCC pin
bit 0 PMPTTL: PMP Module TTL Input Buffer Select bit
1 = PMP module uses TTL input buffers
0 = PMP module uses Schmitt Trigger input buffers

Note 1: To enable the actual RTCC output, the RTCOE (RTCCFG<2>) bit needs to be set.

10.2 PORTA, TRISA and LATA Registers All PORTA pins have TTL input levels and full CMOS
output drivers.
PORTA is a 7-bit wide, bidirectional port. It may
function as a 5-bit port, depending on the oscillator The TRISA register controls the direction of the PORTA
mode selected. Setting a TRISA bit (= 1) will make the pins, even when they are being used as analog inputs.
corresponding PORTA pin an input (i.e., put the The user must ensure the bits in the TRISA register are
corresponding output driver in a High-impedance maintained set when using them as analog inputs.
mode). Clearing a TRISA bit (= 0) will make the
corresponding PORTA pin an output (i.e., put the EXAMPLE 10-2: INITIALIZING PORTA
contents of the output latch on the selected pin). CLRF PORTA ; Initialize PORTA by
; clearing output
Reading the PORTA register reads the status of the ; data latches
pins, whereas writing to it, will write to the port latch. CLRF LATA ; Alternate method
The Data Latch (LATA) register is also memory mapped. ; to clear output
Read-modify-write operations on the LATA register read ; data latches
and write the latched output value for PORTA. MOVLW 07h ; Configure A/D
MOVWF ADCON0 ; for digital inputs
The other PORTA pins are multiplexed with analog MOVWF 07h ; Configure comparators
inputs, the analog VREF+ and VREF- inputs and the com- MOVWF CMCON ; for digital input
parator voltage reference output. The operation of pins, MOVLW 0CFh ; Value used to
RA<3:0> and RA5, as A/D Converter inputs is selected ; initialize data
by clearing or setting the control bits in the ADCON0 ; direction
register (A/D Port Configuration Register 0). MOVWF TRISA ; Set RA<3:0> as inputs
; RA<5:4> as outputs
Pins, RA0, RA2, and RA3, may also be used as com-
parator inputs and by setting the appropriate bits in the
CMCON register. To use RA<3:0> as digital inputs, it is
also necessary to turn off the comparators.
Note: On a Power-on Reset (POR), RA5 and
RA<3:0> are configured as analog inputs
and read as ‘0’.

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TABLE 10-3: PORTA I/O SUMMARY
TRIS I/O
Pin Function I/O Description
Setting Type
RA0/AN0/C1INA/ RA0 1 I TTL PORTA<0> data input; disabled when analog input is enabled.
ULPWU/PMA6/ 0 O DIG LATA<0> data output; not affected by analog input.
RP0
AN0 1 I ANA A/D Input Channel 0 and Comparator C1- input. Default
input configuration on POR; does not affect digital output.
C1INA 1 I ANA Comparator 1 Input A.
ULPWU 1 I ANA Ultra low-power wake-up input.
(1)
PMA6 x I/O ST/TTL/ Parallel Master Port digital I/O.
DIG
RP0 1 I ST Remappable Peripheral Pin 0 input.
0 O DIG Remappable Peripheral Pin 0 output.
RA1/AN1/C2INA/ RA1 1 I TTL PORTA<1> data input; disabled when analog input is enabled.
VBG/PMA7/RP1 0 O DIG LATA<1> data output; not affected by analog input.
AN1 1 I ANA A/D Input Channel 1 and Comparator C2- input. Default
input configuration on POR; does not affect digital output.
C2INA 1 I ANA Comparator 1 Input A.
VBG x O ANA Band Gap Voltage Reference output. (Enabled by setting
the VBGOE bit (WDTCON<4>.)
PMA7(1) 1 I ST/TTL Parallel Master Port (io_addr_in[7]).
0 O DIG Parallel Master Port address.
RP1 1 I ST Remappable Peripheral Pin 1 input.
0 O DIG Remappable Peripheral Pin 1 output
RA2/AN2/C2INB/ RA2 0 O DIG LATA<2> data output; not affected by analog input. Disabled
C1IND/C3INB/ when CVREF output enabled.
VREF-/CVREF 1 I TTL PORTA<2> data input. Disabled when analog functions are
enabled; disabled when CVREF output is enabled.
AN2 1 I ANA A/D Input Channel 2 and Comparator C2+ input. Default
input configuration on POR; not affected by analog output.
C2INB 1 I ANA Comparator 2 Input B.
0 O ANA CTMU pulse generator charger for the C2INB comparator
input.
C1IND 1 I ANA Comparator 1 Input D.
C3INB 1 I ANA Comparator 3 Input B.
VREF- 1 I ANA A/D and comparator voltage reference low input.
CVREF x O ANA Comparator voltage reference output. Enabling this feature
disables digital I/O.
RA3/AN3/C1INB/ RA3 0 O DIG LATA<3> data output; not affected by analog input.
VREF+ 1 I TTL PORTA<3> data input; disabled when analog input is enabled.
AN3 1 I ANA A/D Input Channel 3 and Comparator C1+ input. Default
input configuration on POR.
C1INB 1 I ANA Comparator 1 Input B
VREF+ 1 I ANA A/D and comparator voltage reference high input.
Legend: DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level
input/output; x = Don’t care (TRIS bit does not affect port direction or is overridden for this option)
Note 1: This bit is only available on 44-pin devices (PIC18F46J53, PIC18F47J53, PIC18LF46J53 and
PIC18LF47J53).

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TABLE 10-3: PORTA I/O SUMMARY (CONTINUED)
TRIS I/O
Pin Function I/O Description
Setting Type

RA5/AN4/C1INC/ RA5 0 O DIG LATA<5> data output; not affected by analog input.
SS1/HLVDIN/ 1 I TTL PORTA<5> data input; disabled when analog input is enabled.
RCV/RP2
AN4 1 I ANA A/D Input Channel 4. Default configuration on POR.
C1INC 0 O DIG Comparator 1 Input C.
SS1 1 I TTL Slave select input for MSSP1.
HLVDIN 1 I ANA High/Low-Voltage Detect external trip point reference input.
RCV 1 I TTL External USB transceiver RCV input.
RP2 1 I ST Remappable Peripheral Pin 2 input.
0 O DIG Remappable Peripheral Pin 2 output.
OSC2/CLKO/ OSC2 x O ANA Main oscillator feedback output connection (HS mode).
RA6 CLKO x O DIG System cycle clock output (FOSC/4) in RC and EC Oscillator
modes.
RA6 1 I TTL PORTA<6> data input.
0 O DIG LATA<6> data output.
OSC1/CLKI/RA7 OSC1 1 I ANA Main oscillator input connection.
CLKI 1 I ANA Main clock input connection.
RA7 1 I TTL PORTA<6> data input.
0 O DIG LATA<6> data output.
Legend: DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level
input/output; x = Don’t care (TRIS bit does not affect port direction or is overridden for this option)
Note 1: This bit is only available on 44-pin devices (PIC18F46J53, PIC18F47J53, PIC18LF46J53 and
PIC18LF47J53).

TABLE 10-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PORTA RA7 RA6 RA5 — RA3 RA2 RA1 RA0
LATA LAT7 LAT6 LAT5 — LAT3 LAT2 LAT1 LAT0
TRISA TRIS7 TRIS6 TRISA5 — TRISA3 TRISA2 TRISA1 TRISA0
ANCON0 PCFG7(1) PCFG6(1) PCFG5(1) PCFG4 PCFG3 PCFG2 PCFG1 PCFG0
CMxCON CON COE CPOL EVPOL1 EVPOL0 CREF CCH1 CCH0
CVRCON CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0
WDTCON REGSLP LVDSTAT ULPLVL VBGOE DS ULPEN ULPSINK SWDTEN
HLVDCON VDIRMAG BGVST IRVST HLVDEN HLVDL3 HLVDL2 HLVDL1 HLVDL0
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTA.
Note 1: These bits are only available in 44-pin devices (PIC18F46J53, PIC18F47J53, PIC18LF46J53 and
PIC18LF47J53).

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10.3 PORTB, TRISB and LATB Four of the PORTB pins (RB<7:4>) have an interrupt-
Registers on-change feature. Only pins configured as inputs can
cause this interrupt to occur (i.e., any RB<7:4> pin
PORTB is an 8-bit wide, bidirectional port. The corre- configured as an output is excluded from the interrupt-
sponding Data Direction register is TRISB. Setting a on-change comparison). The input pins (of RB<7:4>)
TRISB bit (= 1) will make the corresponding PORTB are compared with the old value latched on the last
pin an input (i.e., put the corresponding output driver in read of PORTB. The “mismatch” outputs of RB<7:4>
a High-Impedance mode). Clearing a TRISB bit (= 0) are ORed together to generate the RB Port Change
will make the corresponding PORTB pin an output (i.e., Interrupt with Flag bit, RBIF (INTCON<0>).
put the contents of the output latch on the selected pin).
This interrupt can wake the device from Sleep mode or
The Data Latch register (LATB) is also memory any of the Idle modes. Application software can clear
mapped. Read-modify-write operations on the LATB the interrupt flag by following these steps:
register read and write the latched output value for
1. Any read or write of PORTB (except with the
PORTB.
MOVFF (ANY), PORTB instruction).
2. Wait one instruction cycle (such as executing a
EXAMPLE 10-3: INITIALIZING PORTB
NOP instruction).
CLRF PORTB ; Initialize PORTB by
3. Clear flag bit, RBIF.
; clearing output
; data latches A mismatch condition continues to set flag bit, RBIF.
CLRF LATB ; Alternate method Reading PORTB will end the mismatch condition and
; to clear output allow flag bit, RBIF, to be cleared after one instruction
; data latches cycle of delay.
MOVLW 0x3F ; Configure as digital I/O
MOVFF WREG ADCON1 ; pins in this example The interrupt-on-change feature is recommended for
wake-up on key depression operation and operations
MOVLW 0CFh ; Value used to where PORTB is only used for the interrupt-on-change
; initialize data feature. Polling of PORTB is not recommended while
; direction using the interrupt-on-change feature.
MOVWF TRISB ; Set RB<3:0> as inputs
; RB<5:4> as outputs The RB5 pin is multiplexed with the Timer0 module
; RB<7:6> as inputs clock input and one of the comparator outputs to
become the RB5/CCP5/KBI1/SDI1/SDA1/RP8 pin.

Each of the PORTB pins has a weak internal pull-up. A

single control bit can turn on all the pull-ups. This is
performed by clearing bit, RBPU (INTCON2<7>). The
weak pull-up is automatically turned off when the port
pin is configured as an output. The pull-ups are
disabled on a POR. The integrated weak pull-ups
consist of a semiconductor structure similar to, but
somewhat different from, a discrete resistor. On an
unloaded I/O pin, the weak pull-ups are intended to
provide logic high indication, but will not necessarily
pull the pin all the way to VDD levels.
Note: On a POR, the RB<3:0> bits are
configured as analog inputs by default and
read as ‘0’; RB<7:4> bits are configured
as digital inputs.

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TABLE 10-5: PORTB I/O SUMMARY
TRIS I/O
Pin Function I/O Description
Setting Type
RB0/AN12/ RB0 1 I TTL PORTB<0> data input; weak pull-up when the RBPU bit is
C3IND/INT0/ cleared. Disabled when analog input is enabled.(1)
RP3 0 O DIG LATB<0> data output; not affected by analog input.
AN12 1 I ANA A/D Input Channel 12.(1)
C3IND 1 I ANA Comparator 3 Input D.
INT0 1 I ST External Interrupt 0 input.
RP3 1 I ST Remappable Peripheral Pin 3 input.
0 O DIG Remappable Peripheral Pin 3 output.
RB1/AN10/ RB1 1 I TTL PORTB<1> data input; weak pull-up when the RBPU bit is
C3INC/PMBE/ cleared. Disabled when analog input is enabled.(1)
RTCC/ 0 O DIG LATB<1> data output; not affected by analog input.
RP4
AN10 1 I ANA A/D Input Channel 10.(1)
C3INC 1 I ANA Comparator 3 Input C.
PMBE(3) x O DIG Parallel Master Port byte enable.
RTCC 0 O DIG Asynchronous serial transmit data output (USART module).
RP4 1 I ST Remappable Peripheral Pin 4 input.
0 O DIG Remappable Peripheral Pin 4 output.
RB2/AN8/ RB2 1 I TTL PORTB<2> data input; weak pull-up when the RBPU bit is
C2INC/CTED1/ cleared. Disabled when analog input is enabled.(1)
PMA3/VMO/ 0 O DIG LATB<2> data output; not affected by analog input.
REFO/RP5
AN8 1 I ANA A/D Input Channel 8.(1)
C2INC 1 I ANA Comparator 2 Input C.
CTED1 1 I ST CTMU Edge 1 input.
PMA3(3) x O DIG Parallel Master Port address.
VMO 0 O DIG External USB transceiver D- data output.
REFO 0 O DIG Reference output clock.
RP5 1 I ST Remappable Peripheral Pin 5 input.
0 O DIG Remappable Peripheral Pin 5 output.
RB3/AN9/ RB3 0 O DIG LATB<3> data output; not affected by analog input.
C3INA/CTED2/ 1 I TTL PORTB<3> data input; weak pull-up when the RBPU bit is
PMA2/VPO/ cleared. Disabled when analog input is enabled.(1)
RP6
AN9 1 I ANA A/D Input Channel 9.(1)
C3INA 1 I ANA Comparator 3 Input A.
CTED2 1 I ST CTMU Edge 2 input.
PMA2(3) x O DIG Parallel Master Port address.
VPO 0 O DIG External USB transceiver D+ data output.
RP6 1 I ST Remappable Peripheral Pin 6 input.
0 O DIG Remappable Peripheral Pin 6 output.
Legend: DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level
input/output; x = Don’t care (TRIS bit does not affect port direction or is overridden for this option)
Note 1: Pins are configured as analog inputs by default on POR. Using these pins for digital inputs requires setting
the appropriate bits in the ANCON1 register.
2: All other pin functions are disabled when ICSP™ or ICD is enabled.
3: Available only on 44-pin devices (PIC18F46J53, PIC18F47J53, PIC18LF46J53 and PIC18LF47J53).

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TABLE 10-5: PORTB I/O SUMMARY (CONTINUED)
TRIS I/O
Pin Function I/O Description
Setting Type
RB4/CCP4/ RB4 0 O DIG LATB<4> data output; not affected by analog input.
PMA1/KBI0/ 1 I TTL PORTB<4> data input; weak pull-up when the RBPU bit is
SCK1/SCL1/ cleared. Disabled when analog input is enabled.(1)
RP7
CCP4(3) 1 I ST Capture input.
0 O DIG Compare/PWM output.
PMA1 x I/O ST/TTL/ Parallel Master Port address.
DIG
KBI0 1 I TTL Interrupt-on-change pin.
SCK1 1 I ST Parallel Master Port io_addr_in<1>.
0 O DIG Parallel Master Port address.
2C/
SCL1 1 I I I2C™ clock input (MSSP1 module).
SMBus
0 O DIG I2C clock output (MSSP1 module).
RP7 1 I ST Remappable Peripheral Pin 7 input.
0 O DIG Remappable Peripheral Pin 7 output.
RB5/CCP5/ RB5 0 O DIG LATB<5> data output.
PMA0/KBI1/ 1 I TTL PORTB<5> data input; weak pull-up when the RBPU bit is
SDI1/SDA1/ cleared.
RP8
CCP5(3) 1 I ST Capture input.
0 O DIG Compare/PWM output.
PMA0(3) x I/O ST/TTL/ Parallel Master Port address.
DIG
KBI1 1 I TTL Interrupt-on-change pin.
SDI1 1 I ST SPI data input (MSSP1 module).
SDA1 1 I I2C/ I2C data input (MSSP1 module).
SMBus
0 O DIG I2C/SMBus.
RP8 1 I ST Remappable Peripheral Pin 8 input.
0 O DIG Remappable Peripheral Pin 8 output.
RB6/CCP6/ RB6 0 O DIG LATB<6> data output.
KBI2/PGC/RP9 1 I TTL PORTB<6> data input; weak pull-up when the RBPU bit is
cleared.
CCP6(3) 1 I ST Capture input.
0 O DIG Compare/PWM output.
KBI2 1 I TTL Interrupt-on-change pin.
PGC x I ST Serial execution (ICSP™) clock input for ICSP and ICD
operation.(2)
RP9 1 I ST Remappable Peripheral Pin 9 input.
0 O DIG Remappable Peripheral Pin 9 output.
Legend: DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level
input/output; x = Don’t care (TRIS bit does not affect port direction or is overridden for this option)
Note 1: Pins are configured as analog inputs by default on POR. Using these pins for digital inputs requires setting
the appropriate bits in the ANCON1 register.
2: All other pin functions are disabled when ICSP™ or ICD is enabled.
3: Available only on 44-pin devices (PIC18F46J53, PIC18F47J53, PIC18LF46J53 and PIC18LF47J53).

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TABLE 10-5: PORTB I/O SUMMARY (CONTINUED)
TRIS I/O
Pin Function I/O Description
Setting Type
RB7/CCP7/ RB7 0 O DIG LATB<7> data output.
KBI3/PGD/ 1 I TTL PORTB<7> data input; weak pull-up when the RBPU bit is
RP10 cleared.
CCP7 1 I ST Capture input.
0 O DIG Compare/PWM output.
KBI3 1 O TTL Interrupt-on-change pin.
PGD x O DIG Serial execution data output for ICSP and ICD operation.(2)
x I ST Serial execution data input for ICSP and ICD operation.(2)
RP10 1 I ST Remappable Peripheral Pin 10 input.
0 O DIG Remappable Peripheral Pin 10 output.
Legend: DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level
input/output; x = Don’t care (TRIS bit does not affect port direction or is overridden for this option)
Note 1: Pins are configured as analog inputs by default on POR. Using these pins for digital inputs requires setting
the appropriate bits in the ANCON1 register.
2: All other pin functions are disabled when ICSP™ or ICD is enabled.
3: Available only on 44-pin devices (PIC18F46J53, PIC18F47J53, PIC18LF46J53 and PIC18LF47J53).

TABLE 10-6: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0
LATB LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0
TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF
INTCON2 RBPU INTEDG0 INTEDG1 INTEDG2 INTEDG3 TMR0IP INT3IP RBIP
INTCON3 INT2IP INT1IP INT3IE INT2IE INT1IE INT3IF INT2IF INT1IF
ANCON1 VBGEN — — PCFG12 PCFG11 PCFG10 PCFG9 PCFG8
REFOCON ROON — ROSSLP ROSEL RODIV3 RODIV2 RODIV1 RODIV0
CM3CON CON COE CPOL EVPOL1 EVPOL0 CREF CCH1 CCH0
PADCFG1 — — — — — RTSECSEL1 RTSECSEL0 PMPTTL
RTCCFG RTCEN — RTCWREN RTCSYNC HALFSEC RTCOE RTCPTR1 RTCPTR0
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTB.

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10.4 PORTC, TRISC and LATC Note: On a Power-on Reset, PORTC pins
Registers (except RC2, RC4 and RC5) are config-
ured as digital inputs. RC2 will default as
PORTC is an 8-bit wide, bidirectional port. The corre-
an analog input (controlled by the
sponding Data Direction register is TRISC. Setting a
ANCON1 register). To use pins RC4 and
TRISC bit (= 1) will make the corresponding PORTC
RC5 as digital inputs, the USB module
pin an input (i.e., put the corresponding output driver in
must be disabled (UCON<3> = 0) and the
a high-impedance mode). Clearing a TRISC bit (= 0)
on-chip USB transceiver must be disabled
will make the corresponding PORTC pin an output (i.e.,
(UCFG<3> = 1). The internal USB
put the contents of the output latch on the selected pin).
transceiver has a POR value of enabled.
The Data Latch register (LATC) is also memory
mapped. Read-modify-write operations on the LATC The contents of the TRISC register are affected by
register read and write the latched output value for peripheral overrides. Reading TRISC always returns
PORTC. the current contents, even though a peripheral device
may be overriding one or more of the pins.
PORTC is multiplexed with several peripheral functions
(see Table ). The pins have Schmitt Trigger input
buffers. EXAMPLE 10-4: INITIALIZING PORTC
When enabling peripheral functions, care should be CLRF PORTC ;
Initialize PORTC by
taken in defining TRIS bits for each PORTC pin. Some ;
clearing output
peripherals override the TRIS bit to make a pin an output, ;
data latches
CLRF LATC ;
Alternate method
while other peripherals override the TRIS bit to make a
;
to clear output
pin an input. The user should refer to the corresponding ;
data latches
peripheral section for additional information. MOVLW 0x3F ;
Value used to
Pins RC4 and RC5 are multiplexed with the USB module. ;
initialize data
Depending on the configuration of the module, they can ;
direction
MOVWF TRISC ;
Set RC<5:0> as inputs
serve as the differential data lines for the on-chip USB
;
RC<7:6> as outputs
transceiver, or the data inputs from an external USB
MOVLB 0x0F ;
ANCON register is not in
transceiver. When used as general purpose inputs, both Access Bank
RC4 and RC5 input buffers depend on the level of the BSF ANCON1,PCFG11
voltage applied to the VUSB pin, instead of VDD like all ;Configure RC2/AN11 as
other general purpose I/O pins. Therefore, if the RC4 or digital input
RC5 general purpose input capability will be used, the
VUSB pin should not be left floating.
Unlike other PORTC pins, RC4 and RC5 do not have
TRISC bits associated with them. As digital ports, they
can only function as digital inputs. When configured for
USB operation, the data direction is determined by the
configuration and status of the USB module at a given
time. If an external transceiver is used, RC4 and RC5
always function as inputs from the transceiver. If the on-
chip transceiver is used, the data direction is determined
by the operation being performed by the module at that
time.

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TABLE 10-7: PORTC I/O SUMMARY(1)
TRIS I/O
Pin Function I/O Description
Setting Type
RC0/T1OSO/ RC0 1 I ST PORTC<0> data input.
T1CKI/RP11 0 O DIG LATC<0> data output.
T1OSO x O ANA Timer1 oscillator output; enabled when Timer1 oscillator is
enabled. Disables digital I/O.
T1CKI 1 I ST Timer1 digital clock input.
RP11 1 I ST Remappable Peripheral Pin 11 input.
0 O DIG Remappable Peripheral Pin 11 output.
RC1/CCP8/ RC1 1 I ST PORTC<1> data input.
T1OSI/UOE/ 0 O DIG LATC<1> data output.
RP12
CCP8 1 I ST Capture input.
0 O DIG Compare/PWM output.
T1OSI x I ANA Timer1 oscillator input; enabled when Timer1 oscillator is
enabled. Disables digital I/O.
UOE 0 O DIG External USB transceiver NOE output.
RP12 1 I ST Remappable Peripheral Pin 12 input.
0 O DIG Remappable Peripheral Pin 12 output.
RC2/AN11/ RC2 1 I ST PORTC<2> data input.
C2IND/CTPLS/ 0 O DIG PORTC<2> data output.
RP13
AN11 1 I ANA A/D Input Channel 11.
C2IND 1 I ANA Comparator 2 Input D.
CTPLS 0 O DIG CTMU pulse generator output.
RP13 1 I ST Remappable Peripheral Pin 13 input.
0 O DIG Remappable Peripheral Pin 13 output.
RC4/D-/VM RC4 1 I ST PORTC<4> data input.
D- x I XCVR USB bus minus line output.
x O XCVR USB bus minus line input.
VM 1 I ST External USB transceiver VP input.
RC5/D+/VP RC5 1 I ST PORTC<5> data input.
D+ x I XCVR USB bus plus line input.
x O XCVR USB bus plus line output.
VP 1 I ST External USB transceiver VP input.
Legend: DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level
input/output; I2C/SMB = I2C/SMBus input buffer; x = Don’t care (TRIS bit does not affect port direction or
is overridden for this option)
Note 1: Enhanced PWM output is available only on PIC18F4XJ53 devices.
2: This bit is only available on 44-pin devices (PIC18F46J53, PIC18F47J53, PIC18LF46J53 and
PIC18LF47J53).

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TABLE 10-7: PORTC I/O SUMMARY(1) (CONTINUED)
TRIS I/O
Pin Function I/O Description
Setting Type
RC6/CCP9/ RC6 1 I ST PORTC<6> data input.
PMA5/TX1/ 0 O DIG LATC<6> data output.
CK1/RP17
CCP9 1 I ST Capture input.
0 O DIG Compare/PWM output.
PMA5(2) 1 I ST/TTL Parallel Master Port io_addr_in<5>.
0 O DIG Parallel Master Port address.
TX1 0 O DIG Asynchronous serial transmit data output (EUSART
module); takes priority over port data. User must configure
as an output.
CK1 1 I ST Synchronous serial clock input (EUSART module).
0 O DIG Synchronous serial clock output (EUSART module); takes
priority over port data.
RP17 1 I ST Remappable Peripheral Pin 17 input.
0 O DIG Remappable Peripheral Pin 17 output.
RC7/CCP10/ RC7 1 I ST PORTC<7> data input.
PMA4/RX1/ 0 O DIG LATC<7> data output.
DT1/SDO1/
CCP10 1 I ST Capture input.
RP18
0 O DIG Compare/PWM output.
PMA4(2) x I/O ST/TTL/ Parallel Master Port address.
DIG
RX1 1 I ST Asynchronous serial receive data input (EUSART module).
DT1 1 1 ST Synchronous serial data input (EUSART module). User
must configure as an input.
0 O DIG Synchronous serial data output (EUSART module); takes
priority over port data.
SDO1 0 O DIG SPI data output (MSSP1 module).
RP18 1 I ST Remappable Peripheral Pin 18 input.
0 O DIG Remappable Peripheral Pin 18 output.
Legend: DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level
input/output; I2C/SMB = I2C/SMBus input buffer; x = Don’t care (TRIS bit does not affect port direction or
is overridden for this option)
Note 1: Enhanced PWM output is available only on PIC18F4XJ53 devices.
2: This bit is only available on 44-pin devices (PIC18F46J53, PIC18F47J53, PIC18LF46J53 and
PIC18LF47J53).

TABLE 10-8: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PORTC RC7 RC6 RC5 RC4 — RC2 RC1 RC0
LATC LATC7 LATC6 — — — LATC2 LATC1 LATC0
TRISC TRISC7 TRISC6 — — — TRISC2 TRISC1 TRISC0
ANCON1 VBGEN — — PCFG12 PCFG11 PCFG10 PCFG9 PCFG8
CM2CON CON COE CPOL EVPOL1 EVPOL0 CREF CCH1 CCH0
UCON — PPBRST SE0 PKTDIS USBEN RESUME SUSPND —
UCFG UTEYE UOEMON — UPUEN UTRDIS FSEN PPB1 PPB0
RTCCFG RTCEN — RTCWREN RTCSYNC HALFSEC RTCOE RTCPTR1 RTCPTR0

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10.5 PORTD, TRISD and LATD EXAMPLE 10-5: INITIALIZING PORTD
Registers CLRF PORTD ; Initialize PORTD by
; clearing output
Note: PORTD is available only in 44-pin devices. ; data latches
CLRF LATD ; Alternate method
PORTD is an 8-bit wide, bidirectional port. The corre-
; to clear output
sponding Data Direction register is TRISD. Setting a ; data latches
TRISD bit (= 1) will make the corresponding PORTD MOVLW 0CFh ; Value used to
pin an input (i.e., put the corresponding output driver in ; initialize data
a High-Impedance mode). Clearing a TRISD bit (= 0) ; direction
will make the corresponding PORTD pin an output (i.e., MOVWF TRISD ; Set RD<3:0> as inputs
put the contents of the output latch on the selected pin). ; RD<5:4> as outputs
; RD<7:6> as inputs
The Data Latch register (LATD) is also memory
mapped. Read-modify-write operations on the LATD
register read and write the latched output value for Each of the PORTD pins has a weak internal pull-up. A
PORTD. single control bit can turn on all the pull-ups. This is per-
formed by setting bit, RDPU (TRISE<7>). The weak
All pins on PORTD are implemented with Schmitt Trigger pull-up is automatically turned off when the port pin is
input buffers. Each pin is individually configurable as an configured as an output. The pull-ups are disabled on a
input or output. POR. The integrated weak pull-ups consist of a semi-
conductor structure similar to, but somewhat different,
from, a discrete resistor. On an unloaded I/O pin the
Note: On a POR, these pins are configured as weak pull-ups are intended to provide logic high indica-
digital inputs. tion, but will not necessarily pull the pin all the way to
VDD levels.
Note that the pull-ups can be used for any set of
features, similar to the pull-ups found on PORTB.

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TABLE 10-9: PORTD I/O SUMMARY
TRIS I/O
Pin Function I/O Description
Setting Type
RD0/PMD0/ RD0 1 I ST PORTD<0> data input.
SCL2 0 O DIG LATD<0> data output.
PMD0(1) 1 I ST/TTL Parallel Master Port data in.
0 O DIG Parallel Master Port data out.
SCL2 1 I I2C/ I2C™ clock input (MSSP2 module); input type depends on
SMB module setting.
0 O DIG I2C clock output (MSSP2 module); takes priority over port data.
RD1/PMD1/ RD1 1 I ST PORTD<1> data input.
SDA2 0 O DIG LATD<1> data output.
PMD1(1) 1 I ST/TTL Parallel Master Port data in.
0 O DIG Parallel Master Port data out.
SDA2 1 I I2C/ I2C data input (MSSP2 module); input type depends on
SMB module setting.
0 O DIG I2C data output (MSSP2 module); takes priority over port data.
RD2/PMD2/ RD2 1 I ST PORTD<2> data input.
RP19 0 O DIG LATD<2> data output.
(1)
PMD2 1 I ST/TTL Parallel Master Port data in.
0 O DIG Parallel Master Port data out.
RP19 1 I ST Remappable Peripheral Pin 19 input.
0 O DIG Remappable Peripheral Pin 19 output.
RD3/PMD3/ RD3 1 I ST PORTD<3> data input.
RP20 0 O DIG LATD<3> data output.
PMD3(1) 1 I ST/TTL Parallel Master Port data in.
0 O DIG Parallel Master Port data out.
RP20 1 I ST Remappable Peripheral Pin 20 input.
0 O DIG Remappable Peripheral Pin 20 output.
RD4/PMD4/ RD4 1 I ST PORTD<4> data input.
RP21 0 O DIG LATD<4> data output.
PMD4(1) 1 I ST/TTL Parallel Master Port data in.
0 O DIG Parallel Master Port data out.
RP21 1 I ST Remappable Peripheral Pin 21 input.
0 O DIG Remappable Peripheral Pin 21 output.
RD5/PMD5/ RD5 1 I ST PORTD<5> data input.
RP22 0 O DIG LATD<5> data output.
PMD5(1) 1 I ST/TTL Parallel Master Port data in.
0 O DIG Parallel Master Port data out.
RP22 1 I ST Remappable Peripheral Pin 22 input.
0 O DIG Remappable Peripheral Pin 22 output.
Legend: DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; I2C/SMB = I2C/SMBus
input buffer; x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Note 1: This bit is only available on 44-pin devices (PIC18F46J53, PIC18F47J53, PIC18LF46J53 and
PIC18LF47J53).

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TABLE 10-9: PORTD I/O SUMMARY (CONTINUED)
TRIS I/O
Pin Function I/O Description
Setting Type
RD6/PMD6/ RD6 1 I ST PORTD<6> data input.
RP23 0 O DIG LATD<6> data output.
PMD6(1) 1 I ST/TTL Parallel Master Port data in.
0 O DIG Parallel Master Port data out.
RP23 1 I ST Remappable Peripheral Pin 23 input.
0 O DIG Remappable Peripheral Pin 23 output.
RD7/PMD7/ RD7 1 I ST PORTD<7> data input.
RP24 0 O DIG LATD<7> data output.
PMD7(1) 1 I ST/TTL Parallel Master Port data in.
0 O DIG Parallel Master Port data out.
RP24 1 I ST Remappable Peripheral Pin 24 input.
0 O DIG Remappable Peripheral Pin 24 output.
Legend: DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; I2C/SMB = I2C/SMBus
input buffer; x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Note 1: This bit is only available on 44-pin devices (PIC18F46J53, PIC18F47J53, PIC18LF46J53 and
PIC18LF47J53).

TABLE 10-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTD

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PORTD(1) RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0
LATD(1) LATD7 LATD6 LATD5 LATD4 LATD3 LATD2 LATD1 LATD0
TRISD(1) TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTD.
Note 1: These registers are not available in 28-pin devices (PIC18F26J53, PIC18F27J53, PIC18LF26J53 and
PIC18LF26J53).

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10.6 PORTE, TRISE and LATE EXAMPLE 10-6: INITIALIZING PORTE
Registers CLRF PORTE ; Initialize PORTE by
; clearing output
Note: PORTE is available only in 44-pin devices. ; data latches
CLRF LATE ; Alternate method
Depending on the particular PIC18F47J53 family ; to clear output
device selected, PORTE is implemented in two ; data latches
different ways. MOVLW 0Ah ; Configure A/D
For 44-pin devices, PORTE is a 3-bit wide port. Three MOVWF ADCON1 ; for digital inputs
MOVLW 03h ; Value used to
pins (RE0/AN5/PMRD, RE1/AN6/PMWR and RE2/
; initialize data
AN7/PMCS) are individually configurable as inputs or
; direction
outputs. These pins have Schmitt Trigger input buffers. MOVWF TRISE ; Set RE<0> as inputs
When selected as analog inputs, these pins will read as ; RE<1> as outputs
‘0’s. ; RE<2> as inputs
The corresponding Data Direction register is TRISE.
Setting a TRISE bit (= 1) will make the corresponding Each of the PORTE pins has a weak internal pull-up. A
PORTE pin an input (i.e., put the corresponding output single control bit can turn on all the pull-ups. This is per-
driver in a High-Impedance mode). Clearing a TRISE formed by setting bit, REPU (TRISE<6>). The weak
bit (= 0) will make the corresponding PORTE pin an pull-up is automatically turned off when the port pin is
output (i.e., put the contents of the output latch on the configured as an output. The pull-ups are disabled on a
selected pin). POR. The integrated weak pull-ups consist of a semi-
TRISE controls the direction of the RE pins, even when conductor structure similar to, but somewhat different,
from a discrete resistor. On an unloaded I/O pin, the
they are being used as analog inputs. The user must
make sure to keep the pins configured as inputs when weak pull-ups are intended to provide logic high indica-
using them as analog inputs. tion, but will not necessarily pull the pin all the way to
VDD levels.
Note: On a POR, RE<2:0> are configured as Note that the pull-ups can be used for any set of
analog inputs.
features, similar to the pull-ups found on PORTB.
The Data Latch register (LATE) is also memory
mapped. Read-modify-write operations on the LATE
register read and write the latched output value for
PORTE.

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TABLE 10-11: PORTE I/O SUMMARY
TRIS I/O
Pin Function I/O Description
Setting Type
RE0/AN5/ RE0 1 I ST PORTE<0> data input; disabled when analog input is enabled.
PMRD 0 O DIG LATE<0> data output; not affected by analog input.
AN5 1 I ANA A/D Input Channel 5; default input configuration on POR.
PMRD 1 I ST/TTL Parallel Master Port (io_rd_in).
0 O DIG Parallel Master Port read strobe.
RE1/AN6/ RE1 1 I ST PORTE<1> data input; disabled when analog input is enabled.
PMWR 0 O DIG LATE<1> data output; not affected by analog input.
AN6 1 I ANA A/D Input Channel 6; default input configuration on POR.
PMWR 1 I ST/TTL Parallel Master Port (io_wr_in).
0 O DIG Parallel Master Port write strobe.
RE2/AN7/ RE2 1 I ST PORTE<2> data input; disabled when analog input is enabled.
PMCS 0 O DIG LATE<2> data output; not affected by an analog input.
AN7 1 I ANA A/D Input Channel 7; default input configuration on POR.
PMCS 0 O DIG Parallel Master Port byte enable.
VSS1
— — P — Ground reference for logic and I/O pins.
VSS2
AVSS1 — — P — Ground reference for analog modules.
VDD1
— — P — Positive supply for peripheral digital logic and I/O pins.
VDD2
VDDCORE/VCAP VDDCORE — P — Positive supply for microcontroller core logic (regulator disabled).
VCAP — P — External filter capacitor connection (regulator enabled).
AVDD1 P
— — — Positive supply for analog modules.
AVDD2 —
VUSB — — P — USB voltage input pin.
Legend: DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level
I = Input; O = Output; P = Power

TABLE 10-12: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PORTE(1) — — — — — RE2 RE1 RE0
LATE(1) — — — — — LATE2 LATE1 LATE0
TRISE(1) RDPU REPU — — — TRISE2 TRISE1 TRISE0
ANCON0 PCFG7(1) PCFG6(1) PCFG5(1) PCFG4 PCFG3 PCFG2 PCFG1 PCFG0
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTE.
Note 1: These registers and/or bits are not available in 28-pin devices (PIC18F26J53, PIC18F27J53,
PIC18LF26J53 and PIC18LF26J53).

Note: bit 7 RDPU: PORTD Pull-up Enable bit

0 = All PORTD pull-ups are disabled
1 = PORTD pull-ups are enabled for any input pad
bit 6 REPU: PORTE Pull-up Enable bit
0 = All PORTE pull-ups are disabled
1 = PORTE pull-ups are enabled for any input pad

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PIC18F47J53 FAMILY
10.7 Peripheral Pin Select (PPS) 10.7.2 AVAILABLE PERIPHERALS
A major challenge in general purpose devices is provid- The peripherals managed by the PPS are all digital
ing the largest possible set of peripheral features while only peripherals. These include general serial commu-
minimizing the conflict of features on I/O pins. The nications (UART and SPI), general purpose timer clock
challenge is even greater on low pin count devices inputs, timer-related peripherals (input capture and
similar to the PIC18F47J53 family. In an application output compare) and external interrupt inputs. Also
that needs to use more than one peripheral, multi- included are the outputs of the comparator module,
plexed on a single pin, inconvenient workarounds in since these are discrete digital signals.
application code or a complete redesign may be the The PPS module is not applied to I2C, change notifica-
only option. tion inputs, RTCC alarm outputs or peripherals with
The Peripheral Pin Select (PPS) feature provides an analog inputs. Additionally, the MSSP1 and EUSART1
alternative to these choices by enabling the user’s modules are not routed through the PPS module.
peripheral set selection and their placement on a wide A key difference between pin select and non-pin select
range of I/O pins. By increasing the pinout options peripherals is that pin select peripherals are not asso-
available on a particular device, users can better tailor ciated with a default I/O pin. The peripheral must
the microcontroller to their entire application, rather than always be assigned to a specific I/O pin before it can be
trimming the application to fit the device. used. In contrast, non-pin select peripherals are always
The PPS feature operates over a fixed subset of digital available on a default pin, assuming that the peripheral
I/O pins. Users may independently map the input and/ is active and not conflicting with another peripheral.
or output of any one of the many digital peripherals to
any one of these I/O pins. PPS is performed in software 10.7.2.1 Peripheral Pin Select Function
and generally does not require the device to be Priority
reprogrammed. Hardware safeguards are included that When a pin selectable peripheral is active on a given I/O
prevent accidental or spurious changes to the pin, it takes priority over all other digital I/O and digital
peripheral mapping once it has been established. communication peripherals associated with the pin.
Priority is given regardless of the type of peripheral that
10.7.1 AVAILABLE PINS is mapped. Pin select peripherals never take priority
The PPS feature is used with a range of up to 22 pins. over any analog functions associated with the pin.
The number of available pins is dependent on the
particular device and its pin count. Pins that support the 10.7.3 CONTROLLING PERIPHERAL PIN
PPS feature include the designation “RPn” in their full SELECT
pin designation, where “RP” designates a remappable PPS features are controlled through two sets of Special
peripheral and “n” is the remappable pin number. See Function Registers (SFRs): one to map peripheral
Table 1-3 and Table 1-4 for pinout options in each inputs and the other to map outputs. Because they are
package offering. separately controlled, a particular peripheral’s input
and output (if the peripheral has both) can be placed on
any selectable function pin without constraint.
The association of a peripheral to a peripheral selectable
pin is handled in two different ways, depending on
whether an input or an output is being mapped.

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10.7.3.1 Input Mapping with one of the pin selectable peripherals. Programming
a given peripheral’s bit field with an appropriate 5-bit
The inputs of the PPS options are mapped on the basis
value maps the RPn pin with that value to that peripheral.
of the peripheral; that is, a control register associated
For any given device, the valid range of values for any of
with a peripheral dictates the pin it will be mapped to. The
the bit fields corresponds to the maximum number of
RPINRx registers are used to configure peripheral input
Peripheral Pin Selections supported by the device.
mapping (see Register 10-6 through Register 10-23).
Each register contains a 5-bit field which is associated

TABLE 10-13: SELECTABLE INPUT SOURCES (MAPS INPUT TO FUNCTION)(1)

Configuration
Input Name Function Name Register
Bits
External Interrupt 1 INT1 RPINR1 INTR1R<4:0>
External Interrupt 2 INT2 RPINR2 INTR2R<4:0>
External Interrupt 3 INT3 RPINR3 INTR3R<4:0>
Timer0 External Clock Input T0CKI RPINR4 T0CKR<4:0>
Timer3 External Clock Input T3CKI RPINR6 T3CKR<4:0>
Timer5 External Clock Input T5CKI RPINR15 T5CKR<4:0>
Input Capture 1 CCP1 RPINR7 IC1R<4:0>
Input Capture 2 CCP2 RPINR8 IC2R<4:0>
Input Capture 3 CCP3 RPINR9 IC3R<4:0>
Timer1 Gate Input T1G RPINR12 T1GR<4:0>
Timer3 Gate Input T3G RPINR13 T3GR<4:0>
Timer5 Gate Input T5G RPINR14 T5GR<4:0>
EUSART2 Asynchronous Receive/Synchronous RX2/DT2 RPINR16 RX2DT2R<4:0>
Receive
EUSART2 Asynchronous Clock Input CK2 RPINR17 CK2R<4:0>
SPI2 Data Input SDI2 RPINR21 SDI2R<4:0>
SPI2 Clock Input SCK2IN RPINR22 SCK2R<4:0>
SPI2 Slave Select Input SS2IN RPINR23 SS2R<4:0>
PWM Fault Input FLT0 RPINR24 OCFAR<4:0>
Note 1: Unless otherwise noted, all inputs use the Schmitt Trigger input buffers.

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10.7.3.2 Output Mapping Because of the mapping technique, the list of
peripherals for output mapping also includes a null value
In contrast to inputs, the outputs of the PPS options are
of ‘00000’. This permits any given pin to remain discon-
mapped on the basis of the pin. In this case, a control reg-
nected from the output of any of the pin-selectable
ister associated with a particular pin dictates the periph-
peripherals.
eral output to be mapped. The RPORx registers are used
to control output mapping. The value of the bit field corre-
sponds to one of the peripherals and that peripheral’s
output is mapped to the pin (see Table 10-14).

TABLE 10-14: SELECTABLE OUTPUT SOURCES (MAPS FUNCTION TO OUTPUT)

Output Function
Function Output Name
Number(1)
NULL 0 NULL(2)
C1OUT 1 Comparator 1 Output
C2OUT 2 Comparator 2 Output
C3OUT 3 Comparator 3 Output
TX2/CK2 6 EUSART2 Asynchronous Transmit/Asynchronous Clock Output
DT2 7 EUSART2 Synchronous Transmit
SDO2 10 SPI2 Data Output
SCK2 11 SPI2 Clock Output
SSDMA 12 SPI DMA Slave Select
ULPOUT 13 Ultra Low-Power Wake-up Event
CCP1/P1A 14 ECCP1 Compare or PWM Output Channel A
P1B 15 ECCP1 Enhanced PWM Output, Channel B
P1C 16 ECCP1 Enhanced PWM Output, Channel C
P1D 17 ECCP1 Enhanced PWM Output, Channel D
CCP2/P2A 18 ECCP2 Compare or PWM Output
P2B 19 ECCP2 Enhanced PWM Output, Channel B
P2C 20 ECCP2 Enhanced PWM Output, Channel C
P2D 21 ECCP2 Enhanced PWM Output, Channel D
CCP3/P3A 22 ECCP3 Compare or PWM Output
P3B 23 ECCP3 Enhanced PWM Output, Channel B
P3C 24 ECCP3 Enhanced PWM Output, Channel C
P3D 25 ECCP3 Enhanced PWM Output, Channel D
Note 1: Value assigned to the RP<4:0> pins corresponds to the peripheral output function number.
2: The NULL function is assigned to all RPn outputs at device Reset and disables the RPn output function.

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10.7.3.3 Mapping Limitations 10.7.4.3 Configuration Bit Pin Select Lock
The control schema of the PPS is extremely flexible. As an additional level of safety, the device can be con-
Other than systematic blocks that prevent signal con- figured to prevent more than one write session to the
tention caused by two physical pins being configured RPINRx and RPORx registers. The IOL1WAY
as the same functional input or two functional outputs (CONFIG3H<0>) Configuration bit blocks the IOLOCK
configured as the same pin, there are no hardware bit from being cleared after it has been set once. If
enforced lockouts. The flexibility extends to the point of IOLOCK remains set, the register unlock procedure will
allowing a single input to drive multiple peripherals or a not execute and the PPS Control registers cannot be
single functional output to drive multiple output pins. written to. The only way to clear the bit and re-enable
peripheral remapping is to perform a device Reset.
10.7.4 CONTROLLING CONFIGURATION
In the default (unprogrammed) state, IOL1WAY is set,
CHANGES restricting users to one write session. Programming
Because peripheral remapping can be changed during IOL1WAY allows users unlimited access (with the
run time, some restrictions on peripheral remapping proper use of the unlock sequence) to the PPS
are needed to prevent accidental configuration registers.
changes. PIC18F devices include three features to
prevent alterations to the peripheral map: 10.7.5 CONSIDERATIONS FOR
• Control register lock sequence PERIPHERAL PIN SELECTION
• Continuous state monitoring The ability to control Peripheral Pin Selection intro-
• Configuration bit remapping lock duces several considerations into application design
that could be overlooked. This is particularly true for
10.7.4.1 Control Register Lock several common peripherals that are available only as
remappable peripherals.
Under normal operation, writes to the RPINRx and
RPORx registers are not allowed. Attempted writes will The main consideration is that the PPS is not available
appear to execute normally, but the contents of the on default pins in the device’s default (Reset) state.
registers will remain unchanged. To change these reg- Since all RPINRx registers reset to ‘11111’ and all
isters, they must be unlocked in hardware. The register RPORx registers reset to ‘00000’, all PPS inputs are
lock is controlled by the IOLOCK bit (PPSCON<0>). tied to RP31 and all PPS outputs are disconnected.
Setting IOLOCK prevents writes to the control Note: In tying PPS inputs to RP31, RP31 does
registers; clearing IOLOCK allows writes. not have to exist on a device for the
To set or clear IOLOCK, a specific command sequence registers to be reset to it.
must be executed: This situation requires the user to initialize the device
1. Write 55h to EECON2<7:0>. with the proper peripheral configuration before any
2. Write AAh to EECON2<7:0>. other application code is executed. Since the IOLOCK
3. Clear (or set) IOLOCK as a single operation. bit resets in the unlocked state, it is not necessary to
execute the unlock sequence after the device has
IOLOCK remains in one state until changed. This come out of Reset.
allows all of the PPS registers to be configured with a
single unlock sequence followed by an update to all For application safety, however, it is best to set
control registers, then locked with a second lock IOLOCK and lock the configuration after writing to the
sequence. control registers.
The unlock sequence is timing-critical. Therefore, it is
10.7.4.2 Continuous State Monitoring recommended that the unlock sequence be executed
In addition to being protected from direct writes, the as an assembly language routine with interrupts
contents of the RPINRx and RPORx registers are temporarily disabled. If the bulk of the application is
constantly monitored in hardware by shadow registers. written in C or another high-level language, the unlock
If an unexpected change in any of the registers occurs sequence should be performed by writing in-line
(such as cell disturbances caused by ESD or other assembly.
external events), a Configuration Mismatch Reset will
be triggered.

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Choosing the configuration requires the review of all EXAMPLE 10-7: CONFIGURING EUSART2
PPSs and their pin assignments, especially those that INPUT AND OUTPUT
will not be used in the application. In all cases, unused FUNCTIONS
pin selectable peripherals should be disabled com-
;*************************************
pletely. Unused peripherals should have their inputs
; Unlock Registers
assigned to an unused RPn pin function. I/O pins with
;*************************************
unused RPn functions should be configured with the MOVLB 0x0E ; PPS registers in BANK 14
null peripheral output. BCF INTCON, GIE ; Disable interrupts
The assignment of a peripheral to a particular pin does MOVLW 0x55
not automatically perform any other configuration of the MOVWF EECON2, 0
MOVLW 0xAA
pin’s I/O circuitry. In theory, this means adding a pin-
MOVWF EECON2, 0
selectable output to a pin may mean inadvertently
; Turn off PPS Write Protect
driving an existing peripheral input when the output is BCF PPSCON, IOLOCK, BANKED
driven. Users must be familiar with the behavior of
other fixed peripherals that share a remappable pin and ;***************************
know when to enable or disable them. To be safe, fixed ; Configure Input Functions
digital peripherals that share the same pin should be ; (See Table 10-13)
disabled when not in use. ;***************************
;***************************
Along these lines, configuring a remappable pin for a ; Assign RX2 To Pin RP0
specific peripheral does not automatically turn that ;***************************
feature on. The peripheral must be specifically config- MOVLW 0x00
ured for operation and enabled, as if it were tied to a MOVWF RPINR16, BANKED
fixed pin. Where this happens in the application code
(immediately following device Reset and peripheral ;***************************
configuration or inside the main application routine) ; Configure Output Functions
depends on the peripheral and its use in the ; (See Table 10-14)
;***************************
application.
;***************************
A final consideration is that the PPS functions neither ; Assign TX2 To Pin RP1
override analog inputs nor reconfigure pins with analog ;***************************
functions for digital I/O. If a pin is configured as an MOVLW 0x06
analog input on device Reset, it must be explicitly MOVWF RPOR1, BANKED
reconfigured as digital I/O when used with a PPS.
;*************************************
Example 10-7 provides a configuration for bidirectional ; Lock Registers
communication with flow control using EUSART2. The ;*************************************
following input and output functions are used: BCF INTCON, GIE
MOVLW 0x55
• Input Function RX2
MOVWF EECON2, 0
• Output Function TX2 MOVLW 0xAA
MOVWF EECON2, 0

; Write Protect PPS

BSF PPSCON, IOLOCK, BANKED

Note: If the Configuration bit, IOL1WAY = 1,

once the IOLOCK bit is set, it cannot be
cleared, preventing any future RP register
changes. The IOLOCK bit is cleared back
to ‘0’ on any device Reset.

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10.7.6 PERIPHERAL PIN SELECT Note: Input and output register values can only be
REGISTERS changed if IOLOCK (PPSCON<0>) = 0.
The PIC18F47J53 family of devices implements a total See Example 10-7 for a specific command
of 37 registers for remappable peripheral configuration sequence.
of 44-pin devices. The 28-pin devices have 31 registers
for remappable peripheral configuration.

REGISTER 10-5: PPSCON: PERIPHERAL PIN SELECT INPUT REGISTER 0 (BANKED PPSCON)(1)

U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0

— — — — — — — IOLOCK
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-1 Unimplemented: Read as ‘0’

bit 0 IOLOCK: I/O Lock Enable bit
1 = I/O lock is active, RPORx and RPINRx registers are write-protected
0 = I/O lock is not active, pin configurations can be changed

Note 1: Register values can only be changed if IOLOCK (PPSCON<0>) = 0.

REGISTER 10-6: RPINR1: PERIPHERAL PIN SELECT INPUT REGISTER 1 (BANKED EE1h)

U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

— — — INTR1R4 INTR1R3 INTR1R2 INTR1R1 INTR1R0
bit 7 bit 0

Legend: R/W = Readable bit, Writable bit if IOLOCK = 0

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-5 Unimplemented: Read as ‘0’

bit 4-0 INTR1R<4:0>: Assign External Interrupt 1 (INT1) to the Corresponding RPn Pin bits

REGISTER 10-7: RPINR2: PERIPHERAL PIN SELECT INPUT REGISTER 2 (BANKED EE2h)

U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

— — — INTR2R4 INTR2R3 INTR2R2 INTR2R1 INTR2R0
bit 7 bit 0

Legend: R/W = Readable bit, Writable bit if IOLOCK = 0

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-5 Unimplemented: Read as ‘0’

bit 4-0 INTR2R<4:0>: Assign External Interrupt 2 (INT2) to the Corresponding RPn Pin bits

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REGISTER 10-8: RPINR3: PERIPHERAL PIN SELECT INPUT REGISTER 3 (BANKED EE3h)

U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

— — — INTR3R4 INTR3R3 INTR3R2 INTR3R1 INTR3R0
bit 7 bit 0

Legend: R/W = Readable bit, Writable bit if IOLOCK = 0

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-5 Unimplemented: Read as ‘0’

bit 4-0 INTR3R<4:0>: Assign External Interrupt 3 (INT3) to the Corresponding RPn Pin bits

REGISTER 10-9: RPINR4: PERIPHERAL PIN SELECT INPUT REGISTER 4 (BANKED EE4h)

U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

— — — T0CKR4 T0CKR3 T0CKR2 T0CKR1 T0CKR0
bit 7 bit 0

Legend: R/W = Readable bit, Writable bit if IOLOCK = 0

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-5 Unimplemented: Read as ‘0’

bit 4-0 T0CKR<4:0>: Timer0 External Clock Input (T0CKI) to the Corresponding RPn Pin bits

REGISTER 10-10: RPINR6: PERIPHERAL PIN SELECT INPUT REGISTER 6 (BANKED EE6h)

U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

— — — T3CKR4 T3CKR3 T3CKR2 T3CKR1 T3CKR0
bit 7 bit 0

Legend: R/W = Readable bit, Writable bit if IOLOCK = 0

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-5 Unimplemented: Read as ‘0’

bit 4-0 T3CKR<4:0>: Timer3 External Clock Input (T3CKI) to the Corresponding RPn Pin bits

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REGISTER 10-11: RPINR7: PERIPHERAL PIN SELECT INPUT REGISTER 7 (BANKED EE8h)

U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

— — — IC1R4 IC1R3 IC1R2 IC1R1 IC1R0
bit 7 bit 0

Legend: R/W = Readable bit, Writable bit if IOLOCK = 0

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-5 Unimplemented: Read as ‘0’

bit 4-0 IC1R<4:0>: Assign Input Capture 1 (ECCP1) to the Corresponding RPn Pin bits

REGISTER 10-12: RPINR8: PERIPHERAL PIN SELECT INPUT REGISTER 8 (BANKED EE9h)

U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

— — — IC2R4 IC2R3 IC2R2 IC2R1 IC2R0
bit 7 bit 0

Legend: R/W = Readable bit, Writable bit if IOLOCK = 0

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-5 Unimplemented: Read as ‘0’

bit 4-0 IC2R<4:0>: Assign Input Capture 2 (ECCP2) to the Corresponding RPn Pin bits

REGISTER 10-13: RPINR9: PERIPHERAL PIN SELECT INPUT REGISTER 9 (BANKED EEAh)

U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

— — — IC3R4 IC3R3 IC3R2 IC3R1 IC3R0
bit 7 bit 0

Legend: R/W = Readable bit, Writable bit if IOLOCK = 0

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-5 Unimplemented: Read as ‘0’

bit 4-0 IC3R<4:0>: Assign Input Capture 3 (ECCP3) to the Corresponding RPn Pin bits

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REGISTER 10-14: RPINR12: PERIPHERAL PIN SELECT INPUT REGISTER 12 (BANKED EF2h)

U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

— — — T1GR4 T1GR3 T1GR2 T1GR1 T1GR0
bit 7 bit 0

Legend: R/W = Readable bit, Writable bit if IOLOCK = 0

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-5 Unimplemented: Read as ‘0’

bit 4-0 T1GR<4:0>: Timer1 Gate Input (T1G) to the Corresponding RPn Pin bits

REGISTER 10-15: RPINR13: PERIPHERAL PIN SELECT INPUT REGISTER 13 (BANKED EF3h)

U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

— — — T3GR4 T3GR3 T3GR2 T3GR1 T3GR0
bit 7 bit 0

Legend: R/W = Readable bit, Writable bit if IOLOCK = 0

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-5 Unimplemented: Read as ‘0’

bit 4-0 T3GR<4:0>: Timer3 Gate Input (T3G) to the Corresponding RPn Pin bits

REGISTER 10-16: RPINR14: PERIPHERAL PIN SELECT INPUT REGISTER 14 (BANKED EF4h)

U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

— — — T5GR4 T5GR3 T5GR2 T5GR1 T5GR0
bit 7 bit 0

Legend: R/W = Readable bit, Writable bit if IOLOCK = 0

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-5 Unimplemented: Read as ‘0’

bit 4-0 T5GR<4:0>: Timer5 Gate Input (T5G) to the Corresponding RPn Pin bits

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REGISTER 10-17: RPINR16: PERIPHERAL PIN SELECT INPUT REGISTER 16 (BANKED EF7h)

U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

— — — RX2DT2R4 RX2DT2R3 RX2DT2R2 RX2DT2R1 RX2DT2R0
bit 7 bit 0

Legend: R/W = Readable bit, Writable bit if IOLOCK = 0

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-5 Unimplemented: Read as ‘0’

bit 4-0 RX2DT2R<4:0>: EUSART2 Synchronous/Asynchronous Receive (RX2/DT2) to the Corresponding
RPn Pin bits

REGISTER 10-18: RPINR15: PERIPHERAL PIN SELECT INPUT REGISTER 15 (BANKED EE7h)

U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

— — — T5CKR4 T5CKR3 T5CKR2 T5CKR1 T5CKR0
bit 7 bit 0

Legend: R/W = Readable bit, Writable bit if IOLOCK = 0

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-5 Unimplemented: Read as ‘0’

bit 4-0 T5CKR<4:0>: Timer5 External Clock Input (T5CKI) to the Corresponding RPn Pin bits

REGISTER 10-19: RPINR17: PERIPHERAL PIN SELECT INPUT REGISTER 17 (BANKED EF8h)

U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

— — — CK2R4 CK2R3 CK2R2 CK2R1 CK2R0
bit 7 bit 0

Legend: R/W = Readable bit, Writable bit if IOLOCK = 0

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-5 Unimplemented: Read as ‘0’

bit 4-0 CK2R<4:0>: EUSART2 Clock Input (CK2) to the Corresponding RPn Pin bits

REGISTER 10-20: RPINR21: PERIPHERAL PIN SELECT INPUT REGISTER 21 (BANKED EFCh)

U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

— — — SDI2R4 SDI2R3 SDI2R2 SDI2R1 SDI2R0
bit 7 bit 0

Legend: R/W = Readable bit, Writable bit if IOLOCK = 0

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-5 Unimplemented: Read as ‘0’

bit 4-0 SDI2R<4:0>: Assign SPI2 Data Input (SDI2) to the Corresponding RPn Pin bits

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REGISTER 10-21: RPINR22: PERIPHERAL PIN SELECT INPUT REGISTER 22 (BANKED EFDh)

U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

— — — SCK2R4 SCK2R3 SCK2R2 SCK2R1 SCK2R0
bit 7 bit 0

Legend: R/W = Readable bit, Writable bit if IOLOCK = 0

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-5 Unimplemented: Read as ‘0’

bit 4-0 SCK2R<4:0>: Assign SPI2 Clock Input (SCK2) to the Corresponding RPn Pin bits

REGISTER 10-22: RPINR23: PERIPHERAL PIN SELECT INPUT REGISTER 23 (BANKED EFEh)

U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

— — — SS2R4 SS2R3 SS2R2 SS2R1 SS2R0
bit 7 bit 0

Legend: R/W = Readable bit, Writable bit if IOLOCK = 0

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-5 Unimplemented: Read as ‘0’

bit 4-0 SS2R<4:0>: Assign SPI2 Slave Select Input (SS2) to the Corresponding RPn Pin bits

REGISTER 10-23: RPINR24: PERIPHERAL PIN SELECT INPUT REGISTER 24 (BANKED EFFh)

U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — — OCFAR4 OCFAR3 OCFAR2 OCFAR1 OCFAR0
bit 7 bit 0

Legend: R/W = Readable bit, Writable bit if IOLOCK = 0

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-5 Unimplemented: Read as ‘0’

bit 4-0 OCFAR<4:0>: Assign PWM Fault Input (FLT0) to the Corresponding RPn Pin bits

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REGISTER 10-24: RPOR0: PERIPHERAL PIN SELECT OUTPUT REGISTER 0 (BANKED EC1h)

U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — — RP0R4 RP0R3 RP0R2 RP0R1 RP0R0
bit 7 bit 0

Legend: R/W = Readable bit, Writable bit if IOLOCK = 0

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-5 Unimplemented: Read as ‘0’

bit 4-0 RP0R<4:0>: Peripheral Output Function is Assigned to RP0 Output Pin bits
(see Table 10-14 for peripheral function numbers)

REGISTER 10-25: RPOR1: PERIPHERAL PIN SELECT OUTPUT REGISTER 1 (BANKED EC7h)

U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — — RP1R4 RP1R3 RP1R2 RP1R1 RP1R0
bit 7 bit 0

Legend: R/W = Readable bit, Writable bit if IOLOCK = 0

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-5 Unimplemented: Read as ‘0’

bit 4-0 RP1R<4:0>: Peripheral Output Function is Assigned to RP1 Output Pin bits
(see Table 10-14 for peripheral function numbers)

REGISTER 10-26: RPOR2: PERIPHERAL PIN SELECT OUTPUT REGISTER 2 (BANKED EC3h)

U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — — RP2R4 RP2R3 RP2R2 RP2R1 RP2R0
bit 7 bit 0

Legend: R/W = Readable bit, Writable bit if IOLOCK = 0

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-5 Unimplemented: Read as ‘0’

bit 4-0 RP2R<4:0>: Peripheral Output Function is Assigned to RP2 Output Pin bits
(see Table 10-14 for peripheral function numbers)

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REGISTER 10-27: RPOR3: PERIPHERAL PIN SELECT OUTPUT REGISTER 3 (BANKED EC3h)

U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — — RP3R4 RP3R3 RP3R2 RP3R1 RP3R0
bit 7 bit 0

Legend: R/W = Readable bit, Writable bit if IOLOCK = 0

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-5 Unimplemented: Read as ‘0’

bit 4-0 RP3R<4:0>: Peripheral Output Function is Assigned to RP3 Output Pin bits
(see Table 10-14 for peripheral function numbers)

REGISTER 10-28: RPOR4: PERIPHERAL PIN SELECT OUTPUT REGISTER 4 (BANKED EC4h)

U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — — RP4R4 RP4R3 RP4R2 RP4R1 RP4R0
bit 7 bit 0

Legend: R/W = Readable bit, Writable bit if IOLOCK = 0

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-5 Unimplemented: Read as ‘0’

bit 4-0 RP4R<4:0>: Peripheral Output Function is Assigned to RP4 Output Pin bits
(see Table 10-14 for peripheral function numbers)

REGISTER 10-29: RPOR5: PERIPHERAL PIN SELECT OUTPUT REGISTER 5 (BANKED EC5h)

U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — — RP5R4 RP5R3 RP5R2 RP5R1 RP5R0
bit 7 bit 0

Legend: R/W = Readable bit, Writable bit if IOLOCK = 0

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-5 Unimplemented: Read as ‘0’

bit 4-0 RP5R<4:0>: Peripheral Output Function is Assigned to RP5 Output Pin bits
(see Table 10-14 for peripheral function numbers)

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REGISTER 10-30: RPOR6: PERIPHERAL PIN SELECT OUTPUT REGISTER 6 (BANKED EC6h)

U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — — RP6R4 RP6R3 RP6R2 RP6R1 RP6R0
bit 7 bit 0

Legend: R/W = Readable bit, Writable bit if IOLOCK = 0

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-5 Unimplemented: Read as ‘0’

bit 4-0 RP6R<4:0>: Peripheral Output Function is Assigned to RP6 Output Pin bits
(see Table 10-14 for peripheral function numbers)

REGISTER 10-31: RPOR7: PERIPHERAL PIN SELECT OUTPUT REGISTER 7 (BANKED EC7h)

U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — — RP7R4 RP7R3 RP7R2 RP7R1 RP7R0
bit 7 bit 0

Legend: R/W = Readable bit, Writable bit if IOLOCK = 0

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-5 Unimplemented: Read as ‘0’

bit 4-0 RP7R<4:0>: Peripheral Output Function is Assigned to RP7 Output Pin bits
(see Table 10-14 for peripheral function numbers)

REGISTER 10-32: RPOR8: PERIPHERAL PIN SELECT OUTPUT REGISTER 8 (BANKED EC8h)

U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — — RP8R4 RP8R3 RP8R2 RP8R1 RP8R0
bit 7 bit 0

Legend: R/W = Readable bit, Writable bit if IOLOCK = 0

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-5 Unimplemented: Read as ‘0’

bit 4-0 RP8R<4:0>: Peripheral Output Function is Assigned to RP8 Output Pin bits
(see Table 10-14 for peripheral function numbers)

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REGISTER 10-33: RPOR9: PERIPHERAL PIN SELECT OUTPUT REGISTER 9 (BANKED EC9h)

U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — — RP9R4 RP9R3 RP9R2 RP9R1 RP9R0
bit 7 bit 0

Legend: R/W = Readable bit, Writable bit if IOLOCK = 0

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-5 Unimplemented: Read as ‘0’

bit 4-0 RP9R<4:0>: Peripheral Output Function is Assigned to RP9 Output Pin bits
(see Table 10-14 for peripheral function numbers)

REGISTER 10-34: RPOR10: PERIPHERAL PIN SELECT OUTPUT REGISTER 10 (BANKED ECAh)

U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — — RP10R4 RP10R3 RP10R2 RP10R1 RP10R0
bit 7 bit 0

Legend: R/W = Readable bit, Writable bit if IOLOCK = 0

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-5 Unimplemented: Read as ‘0’

bit 4-0 RP10R<4:0>: Peripheral Output Function is Assigned to RP10 Output Pin bits
(see Table 10-14 for peripheral function numbers)

REGISTER 10-35: RPOR11: PERIPHERAL PIN SELECT OUTPUT REGISTER 11 (BANKED ECBh)

U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — — RP11R4 RP11R3 RP11R2 RP11R1 RP11R0
bit 7 bit 0

Legend: R/W = Readable bit, Writable bit if IOLOCK = 0

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-5 Unimplemented: Read as ‘0’

bit 4-0 RP11R<4:0>: Peripheral Output Function is Assigned to RP11 Output Pin bits
(see Table 10-14 for peripheral function numbers)

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REGISTER 10-36: RPOR12: PERIPHERAL PIN SELECT OUTPUT REGISTER 12 (BANKED ECCh)

U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — — RP12R4 RP12R3 RP12R2 RP12R1 RP12R0
bit 7 bit 0

Legend: R/W = Readable bit, Writable bit if IOLOCK = 0

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-5 Unimplemented: Read as ‘0’

bit 4-0 RP12R<4:0>: Peripheral Output Function is Assigned to RP12 Output Pin bits
(see Table 10-14 for peripheral function numbers)

REGISTER 10-37: RPOR13: PERIPHERAL PIN SELECT OUTPUT REGISTER 13 (BANKED ECDh)

U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — — RP13R4 RP13R3 RP13R2 RP13R1 RP13R0
bit 7 bit 0

Legend: R/W = Readable bit, Writable bit if IOLOCK = 0

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-5 Unimplemented: Read as ‘0’

bit 4-0 RP13R<4:0>: Peripheral Output Function is Assigned to RP13 Output Pin bits
(see Table 10-14 for peripheral function numbers)

REGISTER 10-38: RPOR17: PERIPHERAL PIN SELECT OUTPUT REGISTER 17 (BANKED ED1h)

U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — — RP17R4 RP17R3 RP17R2 RP17R1 RP17R0
bit 7 bit 0

Legend: R/W = Readable bit, Writable bit if IOLOCK = 0

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-5 Unimplemented: Read as ‘0’

bit 4-0 RP17R<4:0>: Peripheral Output Function is Assigned to RP17 Output Pin bits
(see Table 10-14 for peripheral function numbers)

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REGISTER 10-39: RPOR18: PERIPHERAL PIN SELECT OUTPUT REGISTER 18 (BANKED ED2h)

U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — — RP18R4 RP18R3 RP18R2 RP18R1 RP18R0
bit 7 bit 0

Legend: R/W = Readable bit, Writable bit if IOLOCK = 0

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-5 Unimplemented: Read as ‘0’

bit 4-0 RP18R<4:0>: Peripheral Output Function is Assigned to RP18 Output Pin bits
(see Table 10-14 for peripheral function numbers)

REGISTER 10-40: RPOR19: PERIPHERAL PIN SELECT OUTPUT REGISTER 19 (BANKED ED3h)(1)

U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — — RP19R4 RP19R3 RP19R2 RP19R1 RP19R0
bit 7 bit 0

Legend: R/W = Readable bit, Writable bit if IOLOCK = 0

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-5 Unimplemented: Read as ‘0’

bit 4-0 RP19R<4:0>: Peripheral Output Function is Assigned to RP19 Output Pin bits
(see Table 10-14 for peripheral function numbers)

Note 1: RP19 pins are not available on 28-pin devices.

REGISTER 10-41: RPOR20: PERIPHERAL PIN SELECT OUTPUT REGISTER 20 (BANKED ED4h)(1)

U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — — RP20R4 RP20R3 RP20R2 RP20R1 RP20R0
bit 7 bit 0

Legend: R/W = Readable bit, Writable bit if IOLOCK = 0

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-5 Unimplemented: Read as ‘0’

bit 4-0 RP20R<4:0>: Peripheral Output Function is Assigned to RP20 Output Pin bits
(see Table 10-14 for peripheral function numbers)

Note 1: RP20 pins are not available on 28-pin devices.

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REGISTER 10-42: RPOR21: PERIPHERAL PIN SELECT OUTPUT REGISTER 21 (BANKED ED5h)(1)

U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — — RP21R4 RP21R3 RP21R2 RP21R1 RP21R0
bit 7 bit 0

Legend: R/W = Readable bit, Writable bit if IOLOCK = 0

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-5 Unimplemented: Read as ‘0’

bit 4-0 RP21R<4:0>: Peripheral Output Function is Assigned to RP21 Output Pin bits
(see Table 10-14 for peripheral function numbers)

Note 1: RP21 pins are not available on 28-pin devices.

REGISTER 10-43: RPOR22: PERIPHERAL PIN SELECT OUTPUT REGISTER 22 (BANKED ED6h)(1)

U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — — RP22R4 RP22R3 RP22R2 RP22R1 RP22R0
bit 7 bit 0

Legend: R/W = Readable bit, Writable bit if IOLOCK = 0

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-5 Unimplemented: Read as ‘0’

bit 4-0 RP22R<4:0>: Peripheral Output Function is Assigned to RP22 Output Pin bits
(see Table 10-14 for peripheral function numbers)

Note 1: RP22 pins are not available on 28-pin devices.

REGISTER 10-44: RPOR23: PERIPHERAL PIN SELECT OUTPUT REGISTER 23 (BANKED ED7h)(1)

U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — — RP23R4 RP23R3 RP23R2 RP23R1 RP23R0
bit 7 bit 0

Legend: R/W = Readable bit, Writable bit if IOLOCK = 0

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-5 Unimplemented: Read as ‘0’

bit 4-0 RP23R<4:0>: Peripheral Output Function is Assigned to RP23 Output Pin bits
(see Table 10-14 for peripheral function numbers)

Note 1: RP23 pins are not available on 28-pin devices.

 2010 Microchip Technology Inc. Preliminary DS39964B-page 177

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REGISTER 10-45: RPOR24: PERIPHERAL PIN SELECT OUTPUT REGISTER 24 (BANKED ED8h)(1)

U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — — RP24R4 RP24R3 RP24R2 RP24R1 RP24R0
bit 7 bit 0

Legend: R/W = Readable bit, Writable bit if IOLOCK = 0

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-5 Unimplemented: Read as ‘0’

bit 4-0 RP24R<4:0>: Peripheral Output Function is Assigned to RP24 Output Pin bits
(see Table 10-14 for peripheral function numbers)

Note 1: RP24 pins are not available on 28-pin devices.

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11.0 PARALLEL MASTER PORT Key features of the PMP module are:
(PMP) • Up to 16 bits of addressing when using
data/address multiplexing
The Parallel Master Port module (PMP) is an 8-bit
• Up to 8 Programmable Address Lines
parallel I/O module, specifically designed to communi-
cate with a wide variety of parallel devices, such as • One Chip Select Line
communication peripherals, LCDs, external memory • Programmable Strobe Options:
devices and microcontrollers. Because the interface to - Individual Read and Write Strobes or;
parallel peripherals varies significantly, the PMP is - Read/Write Strobe with Enable Strobe
highly configurable. The PMP module can be • Address Auto-Increment/Auto-Decrement
configured to serve as either a PMP or as a Parallel
• Programmable Address/Data Multiplexing
Slave Port (PSP).
• Programmable Polarity on Control Signals
Note: The PMP module is not implemented on • Legacy Parallel Slave Port Support
28-pin devices. It is available only
• Enhanced Parallel Slave Support:
on the PIC18F46J53, PIC18F47J53,
PIC18LF46J53 and PIC18LF47J53. - Address Support
- 4-Byte Deep, Auto-Incrementing Buffer
• Programmable Wait States
• Selectable Input Voltage Levels

FIGURE 11-1: PMP MODULE OVERVIEW

Address Bus
Data Bus
PMA<0> Control Lines
PIC18 PMALL
Parallel Master Port
PMA<1>
PMALH

Up to 8-Bit Address
PMA<7:2> EEPROM

PMCSx

PMBE

PMRD FIFO
Microcontroller LCD
PMRD/PMWR Buffer

PMWR
PMENB

PMD<7:0>
PMA<7:0>
PMA<15:8>
8-Bit Data

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11.1 Module Registers The PMCON registers (Register 11-1 and
Register 11-2) control basic module operations, includ-
The PMP module has a total of 14 Special Function ing turning the module on or off. They also configure
Registers (SFRs) for its operation, plus one additional address multiplexing and control strobe configuration.
register to set configuration options. Of these, eight
registers are used for control and six are used for PMP The PMMODE registers (Register 11-3 and
data transfer. Register 11-4) configure the various Master and Slave
modes, the data width and interrupt generation.
11.1.1 CONTROL REGISTERS The PMEH and PMEL registers (Register 11-5 and
The eight PMP Control registers are: Register 11-6) configure the module’s operation at the
hardware (I/O pin) level.
• PMCONH and PMCONL
The PMSTAT registers (Register 11-5 and
• PMMODEH and PMMODEL Register 11-6) provide status flags for the module’s
• PMSTATL and PMSTATH input and output buffers, depending on the operating
• PMEH and PMEL mode.

REGISTER 11-1: PMCONH: PARALLEL PORT CONTROL REGISTER HIGH BYTE (BANKED F5Fh)(1)
R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PMPEN — PSIDL ADRMUX1 ADRMUX0 PTBEEN PTWREN PTRDEN
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 PMPEN: Parallel Master Port Enable bit

1 = PMP enabled
0 = PMP disabled, no off-chip access performed
bit 6 Unimplemented: Read as ‘0’
bit 5 PSIDL: Stop in Idle Mode bit
1 = Discontinue module operation when device enters Idle mode
0 = Continue module operation in Idle mode
bit 4-3 ADRMUX<1:0>: Address/Data Multiplexing Selection bits
11 = Reserved
10 = All 16 bits of address are multiplexed on PMD<7:0> pins
01 = Lower 8 bits of address are multiplexed on PMD<7:0> pins (only eight bits of address are
available in this mode)
00 = Address and data appear on separate pins (only eight bits of address are available in this mode)
bit 2 PTBEEN: Byte Enable Port Enable bit (16-Bit Master mode)
1 = PMBE port enabled
0 = PMBE port disabled
bit 1 PTWREN: Write Enable Strobe Port Enable bit
1 = PMWR/PMENB port enabled
0 = PMWR/PMENB port disabled
bit 0 PTRDEN: Read/Write Strobe Port Enable bit
1 = PMRD/PMWR port enabled
0 = PMRD/PMWR port disabled

Note 1: This register is only available on 44-pin devices.

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REGISTER 11-2: PMCONL: PARALLEL PORT CONTROL REGISTER LOW BYTE (BANKED F5Eh)(1)
R/W-0 R/W-0 R/W-0(2) U-0 R/W-0(2) R/W-0 R/W-0 R/W-0
CSF1 CSF0 ALP — CS1P BEP WRSP RDSP
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-6 CSF<1:0>: Chip Select Function bits

11 = Reserved
10 = Chip select function is enabled and PMCSx acts as chip select (in Master mode). Up to
13 address bits only can be generated.
01 = Reserved
00 = Chip select function is disabled (in Master mode). All 16 address bits can be generated.
bit 5 ALP: Address Latch Polarity bit(2)
1 = Active-high (PMALL and PMALH)
0 = Active-low (PMALL and PMALH)
bit 4 Unimplemented: Maintain as ‘0’
bit 3 CS1P: Chip Select Polarity bit(2)
1 = Active-high (PMCSx)
0 = Active-low (PMCSx)
bit 2 BEP: Byte Enable Polarity bit
1 = Byte enable active-high (PMBE)
0 = Byte enable active-low (PMBE)
bit 1 WRSP: Write Strobe Polarity bit
For Slave modes and Master Mode 2 (PMMODEH<1:0> = 00,01,10):
1 = Write strobe active-high (PMWR)
0 = Write strobe active-low (PMWR)
For Master Mode 1 (PMMODEH<1:0> = 11):
1 = Enable strobe active-high (PMENB)
0 = Enable strobe active-low (PMENB)
bit 0 RDSP: Read Strobe Polarity bit
For Slave modes and Master Mode 2 (PMMODEH<1:0> = 00,01,10):
1 = Read strobe active-high (PMRD)
0 = Read strobe active-low (PMRD)
For Master Mode 1 (PMMODEH<1:0> = 11):
1 = Read/write strobe active-high (PMRD/PMWR)
0 = Read/write strobe active-low (PMRD/PMWR)

Note 1: This register is only available on 44-pin devices.

2: These bits have no effect when their corresponding pins are used as address lines.

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REGISTER 11-3: PMMODEH: PARALLEL PORT MODE REGISTER HIGH BYTE (BANKED F5Dh)(1)
R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
BUSY IRQM1 IRQM0 INCM1 INCM0 MODE16 MODE1 MODE0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 BUSY: Busy bit (Master mode only)

1 = Port is busy
0 = Port is not busy
bit 6-5 IRQM<1:0>: Interrupt Request Mode bits
11 = Interrupt generated when Read Buffer 3 is read or Write Buffer 3 is written (Buffered PSP mode)
or on a read or write operation when PMA<1:0> = 11 (Addressable PSP mode only)
10 = No interrupt generated, processor stall activated
01 = Interrupt generated at the end of the read/write cycle
00 = No interrupt generated
bit 4-3 INCM<1:0>: Increment Mode bits
11 = PSP read and write buffers auto-increment (Legacy PSP mode only)
10 = Decrement ADDR<15,13:0> by 1 every read/write cycle
01 = Increment ADDR<15,13:0> by 1 every read/write cycle
00 = No increment or decrement of address
bit 2 MODE16: 8/16-Bit Mode bit
1 = 16-bit mode: Data register is 16 bits; a read or write to the Data register invokes two 8-bit transfers
0 = 8-bit mode: Data register is 8 bits; a read or write to the Data register invokes one 8-bit transfer
bit 1-0 MODE<1:0>: Parallel Port Mode Select bits
11 = Master Mode 1 (PMCSx, PMRD/PMWR, PMENB, PMBE, PMA<x:0> and PMD<7:0>)
10 = Master Mode 2 (PMCSx, PMRD, PMWR, PMBE, PMA<x:0> and PMD<7:0>)
01 = Enhanced PSP, control signals (PMRD, PMWR, PMCSx, PMD<7:0> and PMA<1:0>)
00 = Legacy Parallel Slave Port, control signals (PMRD, PMWR, PMCSx and PMD<7:0>)

Note 1: This register is only available on 44-pin devices.

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REGISTER 11-4: PMMODEL: PARALLEL PORT MODE REGISTER LOW BYTE (BANKED F5Ch)(1)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
WAITB1(2) WAITB0(2) WAITM3 WAITM2 WAITM1 WAITM0 WAITE1(2) WAITE0(2)
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-6 WAITB<1:0>: Data Setup to Read/Write Wait State Configuration bits(2)
11 = Data Wait of 4 TCY; multiplexed address phase of 4 TCY
10 = Data Wait of 3 TCY; multiplexed address phase of 3 TCY
01 = Data Wait of 2 TCY; multiplexed address phase of 2 TCY
00 = Data Wait of 1 TCY; multiplexed address phase of 1 TCY
bit 5-2 WAITM<3:0>: Read to Byte Enable Strobe Wait State Configuration bits
1111 = Wait of additional 15 TCY
.
.
.
0001 = Wait of additional 1 TCY
0000 = No additional Wait cycles (operation forced into one TCY)
bit 1-0 WAITE<1:0>: Data Hold After Strobe Wait State Configuration bits(2)
11 = Wait of 4 TCY
10 = Wait of 3 TCY
01 = Wait of 2 TCY
00 = Wait of 1 TCY

Note 1: This register is only available on 44-pin devices.

2: WAITBx and WAITEx bits are ignored whenever WAITM<3:0> = 0000.

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REGISTER 11-5: PMEH: PARALLEL PORT ENABLE REGISTER HIGH BYTE (BANKED F57h)(1)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PTEN15 PTEN14 PTEN13 PTEN12 PTEN11 PTEN10 PTEN9 PTEN8
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-6 PTEN<15:14>: PMCS1 Port Enable bits

1 = PMA<15:14> function as either PMA<15:14> or PMCS2 and PMCS1
0 = PMA<15:14> function as port I/O
bit 5-0 PTEN<13:8>: PMP Address Port Enable bits
1 = PMA<13:8> function as PMP address lines
0 = PMA<13:8> function as port I/O

Note 1: This register is only available on 44-pin devices.

REGISTER 11-6: PMEL: PARALLEL PORT ENABLE REGISTER LOW BYTE (BANKED F56h)(1)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PTEN7 PTEN6 PTEN5 PTEN4 PTEN3 PTEN2 PTEN1 PTEN0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-2 PTEN<7:2>: PMP Address Port Enable bits

1 = PMA<7:2> function as PMP address lines
0 = PMA<7:2> function as port I/O
bit 1-0 PTEN<1:0>: PMALH/PMALL Strobe Enable bits
1 = PMA<1:0> function as either PMA<1:0> or PMALH and PMALL
0 = PMA<1:0> pads functions as port I/O

Note 1: This register is only available on 44-pin devices.

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REGISTER 11-7: PMSTATH: PARALLEL PORT STATUS REGISTER HIGH BYTE (BANKED F55h)(1)
R-0 R/W-0 U-0 U-0 R-0 R-0 R-0 R-0
IBF IBOV — — IB3F IB2F IB1F IB0F
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 IBF: Input Buffer Full Status bit

1 = All writable input buffer registers are full
0 = Some or all of the writable input buffer registers are empty
bit 6 IBOV: Input Buffer Overflow Status bit
1 = A write attempt to a full input byte register occurred (must be cleared in software)
0 = No overflow occurred
bit 5-4 Unimplemented: Read as ‘0’
bit 3-0 IB<3:0>F: Input Buffer x Status Full bits
1 = Input buffer contains data that has not been read (reading buffer will clear this bit)
0 = Input buffer does not contain any unread data

Note 1: This register is only available on 44-pin devices.

REGISTER 11-8: PMSTATL: PARALLEL PORT STATUS REGISTER LOW BYTE (BANKED F54h)(1)
R-1 R/W-0 U-0 U-0 R-1 R-1 R-1 R-1
OBE OBUF — — OB3E OB2E OB1E OB0E
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 OBE: Output Buffer Empty Status bit

1 = All readable output buffer registers are empty
0 = Some or all of the readable output buffer registers are full
bit 6 OBUF: Output Buffer Underflow Status bit
1 = A read occurred from an empty output byte register (must be cleared in software)
0 = No underflow occurred
bit 5-4 Unimplemented: Read as ‘0’
bit 3-0 OB<3:0>E: Output Buffer x Status Empty bits
1 = Output buffer is empty (writing data to the buffer will clear this bit)
0 = Output buffer contains data that has not been transmitted

Note 1: This register is only available on 44-pin devices.

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11.1.2 DATA REGISTERS PMADDRH differs from PMADDRL in that it can also
have limited PMP control functions. When the module is
The PMP module uses eight registers for transferring
operating in select Master mode configurations, the
data into and out of the microcontroller. They are
upper two bits of the register can be used to determine
arranged as four pairs to allow the option of 16-bit data
the operation of chip select signals. If these are not
operations:
used, PMADDR simply functions to hold the upper 8 bits
• PMDIN1H and PMDIN1L of the address. Register 11-9 provides the function of
• PMDIN2H and PMDIN2L the individual bits in PMADDRH.
• PMADDRH/PMDOUT1H and PMADDRL/PMDOUT1L The PMDOUT2H and PMDOUT2L registers are only
• PMDOUT2H and PMDOUT2L used in Buffered Slave modes and serve as a buffer for
The PMDIN1 registers are used for incoming data in outgoing data.
Slave modes, and both input and output data in Master
11.1.3 PAD CONFIGURATION CONTROL
modes. The PMDIN2 registers are used for buffering
input data in select Slave modes. REGISTER
The PMADDR/PMDOUT1 registers are actually a In addition to the module level configuration options,
single register pair; the name and function are dictated the PMP module can also be configured at the I/O pin
by the module’s operating mode. In Master modes, the for electrical operation. This option allows users to
registers function as the PMADDRH and PMADDRL select either the normal Schmitt Trigger input buffer on
registers, and contain the address of any incoming or digital I/O pins shared with the PMP, or use TTL level
outgoing data. In Slave modes, the registers function compatible buffers instead. Buffer configuration is
as PMDOUT1H and PMDOUT1L, and are used for controlled by the PMPTTL bit in the PADCFG1 register.
outgoing data.

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REGISTER 11-9: PMADDRH: PARALLEL PORT ADDRESS REGISTER HIGH BYTE
(MASTER MODES ONLY) (ACCESS F6Fhh)(1)
U0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— CS1 Parallel Master Port Address High Byte<13:8>
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ r = Reserved
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 Unimplemented: Read as ‘0’

bit 6 CS1: Chip Select bit
If PMCON<7:6> = 10:
1 = Chip select is active
0 = Chip select is inactive
If PMCON<7:6> = 11 or 00:
Bit functions as ADDR<14>.
bit 5-0 Parallel Master Port Address: High Byte<13:8> bits

Note 1: In Enhanced Slave mode, PMADDRH functions as PMDOUT1H, one of the Output Data Buffer registers.

REGISTER 11-10: PMADDRL: PARALLEL PORT ADDRESS REGISTER LOW BYTE

(MASTER MODES ONLY) (ACCESS F6Eh)(1)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
Parallel Master Port Address Low Byte<7:0>
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ r = Reserved
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-0 Parallel Master Port Address: Low Byte<7:0> bits

Note 1: In Enhanced Slave mode, PMADDRL functions as PMDOUT1L, one of the Output Data Buffer registers.

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11.2 Slave Port Modes pins dedicated to the module. In this mode, an external
device, such as another microcontroller or micro-
The primary mode of operation for the module is processor, can asynchronously read and write data
configured using the MODE<1:0> bits in the using the 8-bit data bus (PMD<7:0>), the read (PMRD),
PMMODEH register. The setting affects whether the write (PMWR) and chip select (PMCS1) inputs. It acts
module acts as a slave or a master, and it determines as a slave on the bus and responds to the
the usage of the control pins. read/write-control signals.
11.2.1 LEGACY MODE (PSP) Figure 11-2 displays the connection of the PSP.
When chip select is active and a write strobe occurs
In Legacy mode (PMMODEH<1:0> = 00 and (PMCSx = 1 and PMWR = 1), the data from
PMPEN = 1), the module is configured as a Parallel PMD<7:0> is captured into the PMDIN1L register.
Slave Port (PSP) with the associated enabled module

FIGURE 11-2: LEGACY PARALLEL SLAVE PORT EXAMPLE

Address Bus
Master PIC18 Slave
Data Bus
PMD<7:0> PMD<7:0> Control Lines

PMCS1 PMCS1
PMRD PMRD
PMWR PMWR

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11.2.2 WRITE TO SLAVE PORT 11.2.3 READ FROM SLAVE PORT
When chip select is active and a write strobe occurs When chip select is active and a read strobe occurs
(PMCSx = 1 and PMWR = 1), the data from PMD<7:0> (PMCSx = 1 and PMRD = 1), the data from the
is captured into the lower PMDIN1L register. The PMDOUT1L register (PMDOUT1L<7:0>) is presented
PMPIF and IBF flag bits are set when the write on to PMD<7:0>. Figure 11-4 provides the timing for
ends.The timing for the control signals in Write mode is the control signals in Read mode.
displayed in Figure 11-3. The polarity of the control
signals are configurable.

FIGURE 11-3: PARALLEL SLAVE PORT WRITE WAVEFORMS

| Q4 | Q1 | Q2 | Q3 | Q4

PMCSx
PMWR

PMRD

PMD<7:0>

IBF

OBE

PMPIF

FIGURE 11-4: PARALLEL SLAVE PORT READ WAVEFORMS

| Q4 | Q1 | Q2 | Q3 | Q4

PMCS1

PMWR
PMRD

PMD<7:0>

IBF

OBE

PMPIF

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11.2.4 BUFFERED PARALLEL SLAVE 11.2.4.2 WRITE TO SLAVE PORT
PORT MODE For write operations, the data has to be stored
Buffered Parallel Slave Port mode is functionally sequentially, starting with Buffer 0 (PMDIN1L<7:0>)
identical to the legacy PSP mode with one exception, and ending with Buffer 3 (PMDIN2H<7:0>). As with
the implementation of 4-level read and write buffers. read operations, the module maintains an internal
Buffered PSP mode is enabled by setting the INCM bits pointer to the buffer that is to be written next.
in the PMMODEH register. If the INCM<1:0> bits are The input buffers have their own write status bits: IBxF
set to ‘11’, the PMP module will act as the buffered in the PMSTATH register. The bit is set when the buffer
PSP. contains unread incoming data and cleared when the
When the Buffered PSP mode is active, the PMDIN1L, data has been read. The flag bit is set on the write
PMDIN1H, PMDIN2L and PMDIN2H registers become strobe. If a write occurs on a buffer when its associated
the write buffers and the PMDOUT1L, PMDOUT1H, IBxF bit is set, the Buffer Overflow flag, IBOV, is set;
PMDOUT2L and PMDOUT2H registers become the any incoming data in the buffer will be lost. If all four
read buffers. Buffers are numbered, 0 through 3, start- IBxF flags are set, the Input Buffer Full Flag (IBF) is set.
ing with the lower byte of PMDIN1L to PMDIN2H as the In Buffered Slave mode, the module can be configured
read buffers and PMDOUT1L to PMDOUT2H as the to generate an interrupt on every read or write strobe
write buffers. (IRQM<1:0> = 01). It can be configured to generate an
interrupt on a read from Read Buffer 3 or a write to
11.2.4.1 READ FROM SLAVE PORT Write Buffer 3, which is essentially an interrupt every
For read operations, the bytes will be sent out fourth read or write strobe (RQM<1:0> = 11). When
sequentially, starting with Buffer 0 (PMDOUT1L<7:0>) interrupting every fourth byte for input data, all input
and ending with Buffer 3 (PMDOUT2H<7:0>) for every buffer registers should be read to clear the IBxF flags.
read strobe. The module maintains an internal pointer If these flags are not cleared, then there is a risk of
to keep track of which buffer is to be read. Each buffer hitting an overflow condition.
has a corresponding read status bit, OBxE, in the
PMSTATL register. This bit is cleared when a buffer
contains data that has not been written to the bus, and
is set when data is written to the bus. If the current buf-
fer location being read from is empty, a buffer underflow
is generated and the Buffer Overflow Flag bit, OBUF, is
set. If all four OBxE status bits are set, then the Output
Buffer Empty flag (OBE) will also be set.

FIGURE 11-5: PARALLEL MASTER/SLAVE CONNECTION BUFFERED EXAMPLE

Master PIC18 Slave

PMD<7:0> Write Read

PMD<7:0> Address Address
Pointer Pointer

PMDOUT1L (0) PMDIN1L (0)

PMCS1 PMCS1 PMDOUT1H (1) PMDIN1H (1)
PMRD PMRD PMDOUT2L (2) PMDIN2L (2)
PMWR PMWR PMDOUT2H (3) PMDIN2H (3)

Data Bus
Control Lines

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11.2.5 ADDRESSABLE PARALLEL SLAVE TABLE 11-1: SLAVE MODE BUFFER
PORT MODE ADDRESSING
In the Addressable Parallel Slave Port mode Output
Input Register
(PMMODEH<1:0> = 01), the module is configured with PMA<1:0> Register
(Buffer)
two extra inputs, PMA<1:0>, which are the address (Buffer)
lines 1 and 0. This makes the 4-byte buffer space
directly addressable as fixed pairs of read and write 00 PMDOUT1L (0) PMDIN1L (0)
buffers. As with Legacy Buffered mode, data is output 01 PMDOUT1H (1) PMDIN1H (1)
from PMDOUT1L, PMDOUT1H, PMDOUT2L and 10 PMDOUT2L (2) PMDIN2L (2)
PMDOUT2H, and is read in PMDIN1L, PMDIN1H,
11 PMDOUT2H((3) PMDIN2H (3)
PMDIN2L and PMDIN2H. Table 11-1 provides the
buffer addressing for the incoming address to the input
and output registers.

FIGURE 11-6: PARALLEL MASTER/SLAVE CONNECTION ADDRESSED BUFFER EXAMPLE

Master PIC18F Slave

PMA<1:0>
PMA<1:0>
PMD<7:0> Write Read
PMD<7:0> Address Address
Decode Decode

PMDOUT1L (0) PMDIN1L (0)

PMCS1 PMCS1 PMDOUT1H (1) PMDIN1H (1)
PMRD PMRD PMDOUT2L (2) PMDIN2L (2)
PMWR PMWR PMDOUT2H (3) PMDIN2H (3)
Address Bus
Data Bus
Control Lines

11.2.5.1 READ FROM SLAVE PORT output registers and their associated address. When an
output buffer is read, the corresponding OBxE bit is set.
When chip select is active and a read strobe occurs
The OBxE flag bit is set when all the buffers are empty.
(PMCSx = 1 and PMRD = 1), the data from one of the
If any buffer is already empty, OBxE = 1, the next read
four output bytes is presented onto PMD<7:0>. Which
to that buffer will generate an OBUF event.
byte is read depends on the 2-bit address placed on
ADDR<1:0>. Table 11-1 provides the corresponding

FIGURE 11-7: PARALLEL SLAVE PORT READ WAVEFORMS

| Q4 | Q1 | Q2 | Q3 | Q4

PMCSx

PMWR

PMRD

PMD<7:0>

PMA<1:0>

OBE

PMPIF

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11.2.5.2 WRITE TO SLAVE PORT When an input buffer is written, the corresponding IBxF
bit is set. The IBF flag bit is set when all the buffers are
When chip select is active and a write strobe occurs
written. If any buffer is already written (IBxF = 1), the
(PMCSx = 1 and PMWR = 1), the data from PMD<7:0>
next write strobe to that buffer will generate an OBUF
is captured into one of the four input buffer bytes.
event and the byte will be discarded.
Which byte is written depends on the 2-bit address
placed on ADDRL<1:0>.
Table 11-1 provides the corresponding input registers
and their associated address.

FIGURE 11-8: PARALLEL SLAVE PORT WRITE WAVEFORMS

| Q4 | Q1 | Q2 | Q3 | Q4

PMCSx

PMWR

PMRD

PMD<7:0>

PMA<1:0>

IBF

PMPIF

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11.3 MASTER PORT MODES same output pin (for example, PMWR and PMENB) are
controlled by the same bit; the configuration depends
In its Master modes, the PMP module provides an 8-bit on which Master Port mode is being used.
data bus, up to 16 bits of address, and all the necessary
control signals to operate a variety of external parallel 11.3.3 DATA WIDTH
devices, such as memory devices, peripherals and
The PMP supports data widths of both 8 bits and
slave microcontrollers. To use the PMP as a master,
16 bits. The data width is selected by the MODE16 bit
the module must be enabled (PMPEN = 1) and the
(PMMODEH<2>). Because the data path into and out
mode must be set to one of the two possible Master
of the module is only 8 bits wide, 16-bit operations are
modes (PMMODEH<1:0> = 10 or 11).
always handled in a multiplexed fashion, with the Least
Because there are a number of parallel devices with a Significant Byte (LSB) of data being presented first. To
variety of control methods, the PMP module is designed differentiate data bytes, the byte enable control strobe,
to be extremely flexible to accommodate a range of PMBE, is used to signal when the Most Significant Byte
configurations. Some of these features include: (MSB) of data is being presented on the data lines.
• 8-Bit and 16-Bit Data modes on an 8-bit data bus
11.3.4 ADDRESS MULTIPLEXING
• Configurable address/data multiplexing
• Up to two chip select lines In either of the Master modes (PMMODEH<1:0> = 1x),
the user can configure the address bus to be multiplexed
• Up to 16 selectable address lines
together with the data bus. This is accomplished by
• Address auto-increment and auto-decrement using the ADRMUX<1:0> bits (PMCONH<4:3>). There
• Selectable polarity on all control lines are three address multiplexing modes available. Typical
• Configurable Wait states at different stages of the pinout configurations for these modes are displayed in
read/write cycle Figure 11-9, Figure 11-10 and Figure 11-11.
In Demultiplexed mode (PMCONH<4:3> = 00), data and
11.3.1 PMP AND I/O PIN CONTROL
address information are completely separated. Data bits
Multiple control bits are used to configure the presence are presented on PMD<7:0> and address bits are
or absence of control and address signals in the presented on PMADDRH<6:0> and PMADDRL<7:0>.
module. These bits are PTBEEN, PTWREN, PTRDEN
In Partially Multiplexed mode (PMCONH<4:3> = 01), the
and PTEN<15:0>. They give the user the ability to con-
lower eight bits of the address are multiplexed with the
serve pins for other functions and allow flexibility to
data pins on PMD<7:0>. The upper eight bits of the
control the external address. When any one of these
address are unaffected and are presented on
bits is set, the associated function is present on its
PMADDRH<6:0>. The PMA0 pin is used as an address
associated pin; when clear, the associated pin reverts
latch and presents the Address Latch Low (PMALL)
to its defined I/O port function.
enable strobe. The read and write sequences are
Setting a PTENx bit will enable the associated pin as extended by a complete CPU cycle during which the
an address pin and drive the corresponding data address is presented on the PMD<7:0> pins.
contained in the PMADDR register. Clearing a PTENx
In Fully Multiplexed mode (PMCONH<4:3> = 10), the
bit will force the pin to revert to its original I/O function.
entire 16 bits of the address are multiplexed with the
For the pins configured as chip select (PMCS1 or data pins on PMD<7:0>. The PMA0 and PMA1 pins are
PMCS2) with the corresponding PTENx bit set, the used to present Address Latch Low (PMALL) enable
PTEN0 and PTEN1 bits will also control the PMALL and Address Latch High (PMALH) enable strobes,
and PMALH signals. When multiplexing is used, the respectively. The read and write sequences are
associated address latch signals should be enabled. extended by two complete CPU cycles. During the first
cycle, the lower eight bits of the address are presented
11.3.2 READ/WRITE-CONTROL on the PMD<7:0> pins with the PMALL strobe active.
The PMP module supports two distinct read/write During the second cycle, the upper eight bits of the
signaling methods. In Master Mode 1, read and write address are presented on the PMD<7:0> pins with the
strobes are combined into a single control line, PMALH strobe active. In the event the upper address
PMRD/PMWR. A second control line, PMENB, deter- bits are configured as chip select pins, the
mines when a read or write action is to be taken. In corresponding address bits are automatically forced
Master Mode 2, separate read and write strobes to ‘0’.
(PMRD and PMWR) are supplied on separate pins.
All control signals (PMRD, PMWR, PMBE, PMENB,
PMAL and PMCSx) can be individually configured as
either positive or negative polarity. Configuration is
controlled by separate bits in the PMCONL register.
Note that the polarity of control signals that share the

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FIGURE 11-9: DEMULTIPLEXED ADDRESSING MODE
(SEPARATE READ AND WRITE STROBES WITH CHIP SELECT)

PIC18F
PMA<7:0>

PMD<7:0>

PMCSx

PMRD Address Bus

Data Bus
PMWR
Control Lines

FIGURE 11-10: PARTIALLY MULTIPLEXED ADDRESSING MODE

(SEPARATE READ AND WRITE STROBES WITH CHIP SELECT)

PIC18F
PMD<7:0>
PMA<7:0>

PMCSx

PMALL
Address Bus
PMRD Multiplexed
Data and
Address Bus
PMWR
Control Lines

FIGURE 11-11: FULLY MULTIPLEXED ADDRESSING MODE

(SEPARATE READ AND WRITE STROBES WITH CHIP SELECT)

PIC18F PMD<7:0>
PMA<13:8>

PMCSx

PMALL

PMALH
Multiplexed
PMRD Data and
Address Bus
PMWR Control Lines

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11.3.5 CHIP SELECT FEATURES If the 16-bit mode is enabled (MODE16 = 1), the read
of the low byte of the PMDIN1L register will initiate two
Up to two chip select lines, PMCS1 and PMCS2, are
bus reads. The first read data byte is placed into the
available for the Master modes of the PMP. The two
PMDIN1L register and the second read data is placed
chip select lines are multiplexed with the Most Signifi-
into the PMDIN1H.
cant bit (MSb) of the address bus (PMADDRH<6>).
When a pin is configured as a chip select, it is not Note that the read data obtained from the PMDIN1L
included in any address auto-increment/decrement. register is actually the read value from the previous
The function of the chip select signals is configured read operation. Hence, the first user read will be a
using the chip select function bits (PMCONL<7:6>). dummy read to initiate the first bus read and fill the read
register. Also, the requested read value will not be
11.3.6 AUTO-INCREMENT/DECREMENT ready until after the BUSY bit is observed low. Thus, in
While the module is operating in one of the Master a back-to-back read operation, the data read from the
modes, the INCMx bits (PMMODEH<4:3>) control the register will be the same for both reads. The next read
behavior of the address value. The address can be of the register will yield the new value.
made to automatically increment or decrement after
11.3.9 WRITE OPERATION
each read and write operation. The address increments
once each operation is completed and the BUSY bit To perform a write onto the parallel bus, the user writes
goes to ‘0’. If the chip select signals are disabled and to the PMDIN1L register. This causes the module to
configured as address bits, the bits will participate in first output the desired values on the chip select lines
the increment and decrement operations; otherwise, and the address bus. The write data from the PMDIN1L
the CS1 bit values will be unaffected. register is placed onto the PMD<7:0> data bus. Then
the write line (PMWR) is strobed. If the 16-bit mode is
11.3.7 WAIT STATES enabled (MODE16 = 1), the write to the PMDIN1L
In Master mode, the user has control over the duration register will initiate two bus writes. The first write will
of the read, write and address cycles by configuring the consist of the data contained in PMDIN1L and the
module Wait states. Three portions of the cycle, the second write will contain the PMDIN1H.
beginning, middle and end, are configured using the
11.3.10 PARALLEL MASTER PORT STATUS
corresponding WAITBx, WAITMx and WAITEx bits in
the PMMODEL register.
11.3.10.1 The BUSY Bit
The WAITBx bits (PMMODEL<7:6>) set the number of
In addition to the PMP interrupt, a BUSY bit is provided
Wait cycles for the data setup prior to the
to indicate the status of the module. This bit is used
PMRD/PMWT strobe in Mode 10, or prior to the
only in Master mode. While any read or write operation
PMENB strobe in Mode 11. The WAITMx bits
is in progress, the BUSY bit is set for all but the very last
(PMMODEL<5:2>) set the number of Wait cycles for
CPU cycle of the operation. In effect, if a single-cycle
the PMRD/PMWT strobe in Mode 10, or for the PMENB
read or write operation is requested, the BUSY bit will
strobe in Mode 11. When this Wait state setting is ‘0’,
never be active. This allows back-to-back transfers.
then WAITB and WAITE have no effect. The WAITE
While the bit is set, any request by the user to initiate a
bits (PMMODEL<1:0>) define the number of Wait
new operation will be ignored (i.e., writing or reading
cycles for the data hold time after the PMRD/PMWT
the lower byte of the PMDIN1L register will neither
strobe in Mode 10 or after the PMENB strobe in
initiate a read nor a write).
Mode 11.
11.3.10.2 Interrupts
11.3.8 READ OPERATION
When the PMP module interrupt is enabled for Master
To perform a read on the PMP, the user reads the
mode, the module will interrupt on every completed
PMDIN1L register. This causes the PMP to output the
read or write cycle; otherwise, the BUSY bit is available
desired values on the chip select lines and the address
to query the status of the module.
bus. Then, the read line (PMRD) is strobed. The read
data is placed into the PMDIN1L register.

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11.3.11 MASTER MODE TIMING
This section contains a number of timing examples that
represent the common Master mode configuration
options. These options vary from 8-bit to 16-bit data,
fully demultiplexed to fully multiplexed address and
Wait states.

FIGURE 11-12: READ AND WRITE TIMING, 8-BIT DATA, DEMULTIPLEXED ADDRESS
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

PMCS1

PMD<7:0>

PMA<7:0>
PMWR
PMRD
PMPIF

BUSY

FIGURE 11-13: READ TIMING, 8-BIT DATA, PARTIALLY MULTIPLEXED ADDRESS

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

PMCS1

PMD<7:0> Address<7:0> Data

PMWR

PMRD

PMALL
PMPIF

BUSY

FIGURE 11-14: READ TIMING, 8-BIT DATA, WAIT STATES ENABLED,

PARTIALLY MULTIPLEXED ADDRESS
Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - Q1- - -

PMCS1
PMD<7:0> Address<7:0> Data

PMRD

PMWR

PMALL

PMPIF

BUSY
WAITB<1:0> = 01 WAITE<1:0> = 00
WAITM<3:0> = 0010

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FIGURE 11-15: WRITE TIMING, 8-BIT DATA, PARTIALLY MULTIPLEXED ADDRESS

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

PMCS1

PMD<7:0> Address<7:0> Data

PMWR

PMRD

PMALL

PMPIF

BUSY

FIGURE 11-16: WRITE TIMING, 8-BIT DATA, WAIT STATES ENABLED,

PARTIALLY MULTIPLEXED ADDRESS
Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - Q1- - -

PMCS1
PMD<7:0> Address<7:0> Data

PMWR
PMRD

PMALL
PMPIF

BUSY
WAITB<1:0> = 01 WAITE<1:0> = 00
WAITM<3:0> = 0010

FIGURE 11-17: READ TIMING, 8-BIT DATA, PARTIALLY MULTIPLEXED ADDRESS,

ENABLE STROBE

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

PMCS1

PMD<7:0> Address<7:0> Data

PMRD/PMWR
PMENB

PMALL

PMPIF

BUSY

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FIGURE 11-18: WRITE TIMING, 8-BIT DATA, PARTIALLY MULTIPLEXED ADDRESS,
ENABLE STROBE
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

PMCS1

PMD<7:0> Address<7:0> Data

PMRD/PMWR

PMENB

PMALL

PMPIF

BUSY

FIGURE 11-19: READ TIMING, 8-BIT DATA, FULLY MULTIPLEXED 16-BIT ADDRESS
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

PMCS1

PMD<7:0> Address<7:0> Address<13:8> Data

PMWR

PMRD
PMALL
PMALH
PMPIF

BUSY

FIGURE 11-20: WRITE TIMING, 8-BIT DATA, FULLY MULTIPLEXED 16-BIT ADDRESS

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

PMCS1
PMD<7:0> Address<7:0> Address<13:8> Data

PMWR
PMRD
PMALL
PMALH
PMPIF

BUSY

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FIGURE 11-21: READ TIMING, 16-BIT DATA, DEMULTIPLEXED ADDRESS

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

PMCS1
PMD<7:0> LSB MSB

PMA<7:0>
PMWR
PMRD
PMBE
PMPIF

BUSY

FIGURE 11-22: WRITE TIMING, 16-BIT DATA, DEMULTIPLEXED ADDRESS

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

PMCS1
PMD<7:0> LSB MSB

PMA<7:0>
PMWR
PMRD
PMBE
PMPIF

BUSY

FIGURE 11-23: READ TIMING, 16-BIT MULTIPLEXED DATA, PARTIALLY MULTIPLEXED ADDRESS
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

PMCS1
PMD<7:0> Address<7:0> LSB MSB
PMWR

PMRD
PMBE
PMALL
PMPIF

BUSY

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FIGURE 11-24: WRITE TIMING, 16-BIT MULTIPLEXED DATA,
PARTIALLY MULTIPLEXED ADDRESS

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

PMCS1
PMD<7:0> Address<7:0> LSB MSB

PMWR
PMRD

PMBE
PMALL
PMPIF

BUSY

FIGURE 11-25: READ TIMING, 16-BIT MULTIPLEXED DATA,

FULLY MULTIPLEXED 16-BIT ADDRESS

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

PMCS1
PMD<7:0> Address<7:0> Address<13:8> LSB MSB

PMWR
PMRD
PMBE
PMALH
PMALL
PMPIF

BUSY

FIGURE 11-26: WRITE TIMING, 16-BIT MULTIPLEXED DATA,

FULLY MULTIPLEXED 16-BIT ADDRESS

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

PMCS1
PMD<7:0> Address<7:0> Address<13:8> LSB MSB

PMWR
PMRD
PMBE
PMALH
PMALL
PMPIF

BUSY

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11.4 Application Examples 11.4.1 MULTIPLEXED MEMORY OR
PERIPHERAL
This section introduces some potential applications for
the PMP module. Figure 11-27 demonstrates the hookup of a memory or
another addressable peripheral in Full Multiplex mode.
Consequently, this mode achieves the best pin saving
from the microcontroller perspective. However, for this
configuration, there needs to be some external latches
to maintain the address.

FIGURE 11-27: MULTIPLEXED ADDRESSING APPLICATION EXAMPLE

PIC18F
PMD<7:0> 373 A<7:0>
A<13:0>
PMALL
D<7:0>
D<7:0>
CE
A<15:8>
373 OE WR
PMALH

PMCSx Address Bus

PMRD Data Bus
PMWR Control Lines

11.4.2 PARTIALLY MULTIPLEXED an external latch. If the peripheral has internal latches,
MEMORY OR PERIPHERAL as displayed in Figure 11-29, then no extra circuitry is
required except for the peripheral itself.
Partial multiplexing implies using more pins; however,
for a few extra pins, some extra performance can be
achieved. Figure 11-28 provides an example of a
memory or peripheral that is partially multiplexed with

FIGURE 11-28: EXAMPLE OF A PARTIALLY MULTIPLEXED ADDRESSING APPLICATION

PIC18F
PMD<7:0> 373 A<7:0>
A<7:0>
PMALL
D<7:0>
D<7:0>
CE
PMCSx
OE WR Address Bus
PMRD Data Bus
PMWR Control Lines

FIGURE 11-29: EXAMPLE OF AN 8-BIT MULTIPLEXED ADDRESS AND DATA APPLICATION

PIC18F Parallel Peripheral

PMD<7:0> AD<7:0>
PMALL ALE
PMCSx CS Address Bus
PMRD RD Data Bus
PMWR WR Control Lines

 2010 Microchip Technology Inc. Preliminary DS39964B-page 201

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11.4.3 PARALLEL EEPROM EXAMPLE
Figure 11-30 provides an example connecting parallel
EEPROM to the PMP. Figure 11-31 demonstrates a
slight variation to this, configuring the connection for
16-bit data from a single EEPROM.

FIGURE 11-30: PARALLEL EEPROM EXAMPLE (UP TO 15-BIT ADDRESS, 8-BIT DATA)

PIC18F Parallel EEPROM

PMA<n:0> A<n:0>

PMD<7:0> D<7:0>

PMCSx CE
Address Bus
PMRD OE
Data Bus
PMWR WR
Control Lines

FIGURE 11-31: PARALLEL EEPROM EXAMPLE (UP TO 15-BIT ADDRESS, 16-BIT DATA)

PIC18F Parallel EEPROM

PMA<n:0> A<n:1>

PMD<7:0> D<7:0>

PMBE A0
PMCSx CE
Address Bus
PMRD OE
Data Bus
PMWR WR
Control Lines

11.4.4 LCD CONTROLLER EXAMPLE

The PMP module can be configured to connect to a
typical LCD controller interface, as displayed in
Figure 11-32. In this case the PMP module is config-
ured for active-high control signals since common LCD
displays require active-high control.

FIGURE 11-32: LCD CONTROL EXAMPLE (BYTE MODE OPERATION)

PIC18F LCD Controller

PM<7:0> D<7:0>
PMA0 RS
PMRD/PMWR R/W
PMCSx E Address Bus
Data Bus
Control Lines

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TABLE 11-2: REGISTERS ASSOCIATED WITH PMP MODULE
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF
(2)
PIR1 PMPIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF
PIE1 PMPIE(2) ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE
IPR1 PMPIP(2) ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP
PMCONH(2) PMPEN — PSIDL ADRMUX1 ADRMUX0 PTBEEN PTWREN PTRDEN
PMCONL(2) CSF1 CSF0 ALP — CS1P BEP WRSP RDSP
PMADDRH(1,2) / — CS1 Parallel Master Port Address High Byte
PMDOUT1H(1,2) Parallel Port Out Data High Byte (Buffer 1)
PMADDRL(1,2)/ Parallel Master Port Address Low Byte
(1,2)
PMDOUT1L Parallel Port Out Data Low Byte (Buffer 0)
PMDOUT2H(2) Parallel Port Out Data High Byte (Buffer 3)
PMDOUT2L(2) Parallel Port Out Data Low Byte (Buffer 2)
PMDIN1H(2) Parallel Port In Data High Byte (Buffer 1)
PMDIN1L(2) Parallel Port In Data Low Byte (Buffer 0)
PMDIN2H(2) Parallel Port In Data High Byte (Buffer 3)
PMDIN2L(2) Parallel Port In Data Low Byte (Buffer 2)
PMMODEH(2) BUSY IRQM1 IRQM0 INCM1 INCM0 MODE16 MODE1 MODE0
(2)
PMMODEL WAITB1 WAITB0 WAITM3 WAITM2 WAITM1 WAITM0 WAITE1 WAITE0
PMEH(2) PTEN15 PTEN14 PTEN13 PTEN12 PTEN11 PTEN10 PTEN9 PTEN8
PMEL(2) PTEN7 PTEN6 PTEN5 PTEN4 PTEN3 PTEN2 PTEN1 PTEN0
PMSTATH(2) IBF IBOV — — IB3F IB2F IB1F IB0F
PMSTATL(2) OBE OBUF — — OB3E OB2E OB1E OB0E
PADCFG1 — — — — — RTSECSEL1 RTSECSEL0 PMPTTL
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during PMP operation.
Note 1: The PMADDRH/PMDOUT1H and PMADDRL/PMDOUT1L register pairs share the physical registers and
addresses, but have different functions determined by the module’s operating mode.
2: These bits and/or registers are only available in 44-pin devices.

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12.0 TIMER0 MODULE The T0CON register (Register 12-1) controls all
aspects of the module’s operation, including the
The Timer0 module incorporates the following features: prescale selection. It is both readable and writable.
• Software selectable operation as a timer or Figure 12-1 provides a simplified block diagram of the
counter in both 8-bit or 16-bit modes Timer0 module in 8-bit mode. Figure 12-2 provides a
• Readable and writable registers simplified block diagram of the Timer0 module in 16-bit
• Dedicated 8-bit, software programmable mode.
prescaler
• Selectable clock source (internal or external)
• Edge select for external clock
• Interrupt-on-overflow

REGISTER 12-1: T0CON: TIMER0 CONTROL REGISTER (ACCESS FD5h)

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 TMR0ON: Timer0 On/Off Control bit

1 = Enables Timer0
0 = Stops Timer0
bit 6 T08BIT: Timer0 8-Bit/16-Bit Control bit
1 = Timer0 is configured as an 8-bit timer/counter
0 = Timer0 is configured as a 16-bit timer/counter
bit 5 T0CS: Timer0 Clock Source Select bit
1 = Transition on T0CKI pin
0 = Internal instruction cycle clock (CLKO)
bit 4 T0SE: Timer0 Source Edge Select bit
1 = Increment on high-to-low transition on T0CKI pin
0 = Increment on low-to-high transition on T0CKI pin
bit 3 PSA: Timer0 Prescaler Assignment bit
1 = Timer0 prescaler is not assigned. Timer0 clock input bypasses prescaler.
0 = Timer0 prescaler is assigned. Timer0 clock input comes from prescaler output.
bit 2-0 T0PS<2:0>: Timer0 Prescaler Select bits
111 = 1:256 Prescale value
110 = 1:128 Prescale value
101 = 1:64 Prescale value
100 = 1:32 Prescale value
011 = 1:16 Prescale value
010 = 1:8 Prescale value
001 = 1:4 Prescale value
000 = 1:2 Prescale value

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12.1 Timer0 Operation internal phase clock (TOSC). There is a delay between
synchronization and the onset of incrementing the
Timer0 can operate as either a timer or a counter. The timer/counter.
mode is selected with the T0CS bit (T0CON<5>). In
Timer mode (T0CS = 0), the module increments on 12.2 Timer0 Reads and Writes in
every clock by default unless a different prescaler value 16-Bit Mode
is selected (see Section 12.3 “Prescaler”). If the
TMR0 register is written to, the increment is inhibited TMR0H is not the actual high byte of Timer0 in 16-bit
for the following two instruction cycles. The user can mode. It is actually a buffered version of the real high
work around this by writing an adjusted value to the byte of Timer0, which is not directly readable nor
TMR0 register. writable (refer to Figure 12-2). TMR0H is updated with
The Counter mode is selected by setting the T0CS bit the contents of the high byte of Timer0 during a read of
(= 1). In this mode, Timer0 increments either on every TMR0L. This provides the ability to read all 16 bits of
rising edge or falling edge of the pin, T0CKI. The Timer0 without having to verify that the read of the high
incrementing edge is determined by the Timer0 Source and low byte were valid, due to a rollover between
Edge Select bit, T0SE (T0CON<4>); clearing this bit successive reads of the high and low byte.
selects the rising edge. Restrictions on the external Similarly, a write to the high byte of Timer0 must also
clock input are discussed below. take place through the TMR0H Buffer register. The high
An external clock source can be used to drive Timer0; byte is updated with the contents of TMR0H when a
however, it must meet certain requirements to ensure write occurs to TMR0L. This allows all 16 bits of Timer0
that the external clock can be synchronized with the to be updated at once.

FIGURE 12-1: TIMER0 BLOCK DIAGRAM (8-BIT MODE)

FOSC/4 0
1
Sync with Set
1 Internal TMR0L TMR0IF
T0CKI pin Programmable 0 Clocks on Overflow
Prescaler
T0SE (2 TCY Delay)
T0CS 8
3
T0PS<2:0>
8
PSA Internal Data Bus

Note: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale.

FIGURE 12-2: TIMER0 BLOCK DIAGRAM (16-BIT MODE)

FOSC/4 0
1
Sync with Set
1 Internal TMR0
TMR0L High Byte TMR0IF
T0CKI pin Programmable 0 Clocks on Overflow
Prescaler 8
T0SE (2 TCY Delay)
T0CS 3 Read TMR0L
T0PS<2:0>
Write TMR0L
PSA
8
8
TMR0H

8
8
Internal Data Bus

Note: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale.

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12.3 Prescaler 12.3.1 SWITCHING PRESCALER
ASSIGNMENT
An 8-bit counter is available as a prescaler for the Timer0
module. The prescaler is not directly readable or writable. The prescaler assignment is fully under software
Its value is set by the PSA and T0PS<2:0> bits control and can be changed “on-the-fly” during program
(T0CON<3:0>), which determine the prescaler execution.
assignment and prescale ratio.
Clearing the PSA bit assigns the prescaler to the 12.4 Timer0 Interrupt
Timer0 module. When it is assigned, prescale values The TMR0 interrupt is generated when the TMR0
from 1:2 through 1:256, in power-of-2 increments, are register overflows from FFh to 00h in 8-bit mode, or
selectable. from FFFFh to 0000h in 16-bit mode. This overflow sets
When assigned to the Timer0 module, all instructions the TMR0IF flag bit. The interrupt can be masked by
writing to the TMR0 register (e.g., CLRF TMR0, MOVWF clearing the TMR0IE bit (INTCON<5>). Before
TMR0, BSF TMR0, etc.) clear the prescaler count. re-enabling the interrupt, the TMR0IF bit must be
cleared in software by the Interrupt Service Routine
Note: Writing to TMR0 when the prescaler is (ISR).
assigned to Timer0 will clear the prescaler
count but will not change the prescaler Since Timer0 is shut down in Sleep mode, the TMR0
assignment. interrupt cannot awaken the processor from Sleep.

TABLE 12-1: REGISTERS ASSOCIATED WITH TIMER0

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
TMR0L Timer0 Register Low Byte
TMR0H Timer0 Register High Byte
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF
T0CON TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0
Legend: Shaded cells are not used by Timer0.

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13.0 TIMER1 MODULE Figure 13-1 displays a simplified block diagram of the
Timer1 module.
The Timer1 timer/counter module incorporates these The module incorporates its own low-power oscillator
features: to provide an additional clocking option. The Timer1
• Software selectable operation as a 16-bit timer or oscillator can also be used as a low-power clock source
counter for the microcontroller in power-managed operation.
• Readable and writable 8-bit registers (TMR1H Timer1 is controlled through the T1CON Control
and TMR1L) register (Register 13-1). It also contains the Timer1
• Selectable clock source (internal or external) with Oscillator Enable bit (T1OSCEN). Timer1 can be
device clock or Timer1 oscillator internal options enabled or disabled by setting or clearing control bit,
• Interrupt-on-overflow TMR1ON (T1CON<0>).
• Reset on ECCP Special Event Trigger The FOSC clock source (TMR1CS<1:0> = 01) should not
• Device clock status flag (SOSCRUN) be used with the ECCP capture/compare features. If the
timer will be used with the capture or compare features,
• Timer with gated control
always select one of the other timer clocking options.

REGISTER 13-1: T1CON: TIMER1 CONTROL REGISTER (ACCESS FCDh)

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
TMR1CS1 TMR1CS0 T1CKPS1 T1CKPS0 T1OSCEN T1SYNC RD16 TMR1ON
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-6 TMR1CS<1:0>: Timer1 Clock Source Select bits

10 = Timer1 clock source is the T1OSC or T1CKI pin
01 = Timer1 clock source is the system clock (FOSC)(1)
00 = Timer1 clock source is the instruction clock (FOSC/4)
bit 5-4 T1CKPS<1:0>: Timer1 Input Clock Prescale Select bits
11 = 1:8 Prescale value
10 = 1:4 Prescale value
01 = 1:2 Prescale value
00 = 1:1 Prescale value
bit 3 T1OSCEN: Timer1 Oscillator Source Select bit
When TMR1CS<1:0> = 10:
1 = Power up the Timer1 crystal driver and supply the Timer1 clock from the crystal output
0 = Timer1 crystal driver is off, Timer1 clock is from the T1CKI input pin(2)
When TMR1CS<1:0> = 0x:
1 = Power up the Timer1 crystal driver
0 = Timer1 crystal driver is off(2)
bit 2 T1SYNC: Timer1 External Clock Input Synchronization Select bit
TMR1CS<1:0> = 10:
1 = Do not synchronize external clock input
0 = Synchronize external clock input
TMR1CS<1:0> = 0x:
This bit is ignored. Timer1 uses the internal clock when TMR1CS<1:0> = 0x.
bit 1 RD16: 16-Bit Read/Write Mode Enable bit
1 = Enables register read/write of Timer1 in one 16-bit operation
0 = Enables register read/write of Timer1 in two 8-bit operations
bit 0 TMR1ON: Timer1 On bit
1 = Enables Timer1
0 = Stops Timer1

Note 1: The FOSC clock source should not be selected if the timer will be used with the ECCP capture/compare features.
2: The Timer1 oscillator crystal driver is powered whenever T1OSCEN (T1CON<3>) or T3OSCEN
(T3CON<3>) = 1. The circuit is enabled by the logical OR of these two bits. When disabled, the inverter and
feedback resistor are disabled to eliminate power drain. The TMR1ON and TMR3ON bits do not have to be
enabled to power up the crystal driver.

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13.1 Timer1 Gate Control Register
The Timer1 Gate Control register (T1GCON),
displayed in Register 13-2, is used to control the
Timer1 gate.

REGISTER 13-2: T1GCON: TIMER1 GATE CONTROL REGISTER (ACCESS F9Ah)(1)

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-x R/W-0 R/W-0
TMR1GE T1GPOL T1GTM T1GSPM T1GGO/T1DONE T1GVAL T1GSS1 T1GSS0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 TMR1GE: Timer1 Gate Enable bit

If TMR1ON = 0:
This bit is ignored.
If TMR1ON = 1:
1 = Timer1 counting is controlled by the Timer1 gate function
0 = Timer1 counts regardless of the Timer1 gate function
bit 6 T1GPOL: Timer1 Gate Polarity bit
1 = Timer1 gate is active-high (Timer1 counts when gate is high)
0 = Timer1 gate is active-low (Timer1 counts when gate is low)
bit 5 T1GTM: Timer1 Gate Toggle Mode bit
1 = Timer1 Gate Toggle mode is enabled
0 = Timer1 Gate Toggle mode is disabled and toggle flip-flop is cleared
Timer1 gate flip-flop toggles on every rising edge.
bit 4 T1GSPM: Timer1 Gate Single Pulse Mode bit
1 = Timer1 Gate Single Pulse mode is enabled and is controlling the Timer1 gate
0 = Timer1 Gate Single Pulse mode is disabled
bit 3 T1GGO/T1DONE: Timer1 Gate Single Pulse Acquisition Status bit
1 = Timer1 gate single pulse acquisition is ready, waiting for an edge
0 = Timer1 gate single pulse acquisition has completed or has not been started
This bit is automatically cleared when T1GSPM is cleared.
bit 2 T1GVAL: Timer1 Gate Current State bit
Indicates the current state of the Timer1 gate that could be provided to TMR1H:TMR1L; unaffected by
Timer1 Gate Enable (TMR1GE) bit.
bit 1-0 T1GSS<1:0>: Timer1 Gate Source Select bits
00 = Timer1 gate pin
01 = TMR2 to match PR2 output
10 = Comparator 1 output
11 = Comparator 2 output

Note 1: Programming the T1GCON prior to T1CON is recommended.

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 PIC18F47J53 FAMILY
13.2 Timer1 Operation 13.3.2 EXTERNAL CLOCK SOURCE
The Timer1 module is an 8-bit or 16-bit incrementing When the external clock source is selected, the Timer1
counter, which is accessed through the module may work as a timer or a counter.
TMR1H:TMR1L register pair. When enabled to count, Timer1 is incremented on the
When used with an internal clock source, the module is rising edge of the external clock input, T1CKI, or the
a timer and increments on every instruction cycle. capacitive sensing oscillator signal. Either of these
When used with an external clock source, the module external clock sources can be synchronized to the
can be used as either a timer or counter and microcontroller system clock or they can run
increments on every selected edge of the external asynchronously.
source. When used as a timer with a clock oscillator, an
Timer1 is enabled by configuring the TMR1ON and external 32.768 kHz crystal can be used in conjunction
TMR1GE bits in the T1CON and T1GCON registers, with the dedicated internal oscillator circuit.
respectively. Note: In Counter mode, a falling edge must be
When Timer1 is enabled, the RC1/CCP8/T1OSI/UOE/ registered by the counter prior to the first
RP12 and RC0/T1OSO/T1CKI/RP11 pins become incrementing rising edge after any one or
inputs. This means the values of TRISC<1:0> are more of the following conditions:
ignored and the pins are read as ‘0’. • Timer1 enabled after POR Reset
• Write to TMR1H or TMR1L
13.3 Clock Source Selection • Timer1 is disabled
• Timer1 is disabled (TMR1ON = 0)
The TMR1CS<1:0> and T1OSCEN bits of the T1CON
when T1CKI is high, then Timer1 is
register are used to select the clock source for Timer1.
enabled (TMR1ON = 1) when T1CKI is
Register 13-1 displays the clock source selections.
low.
13.3.1 INTERNAL CLOCK SOURCE
When the internal clock source is selected, the
TMR1H:TMR1L register pair will increment on multiples
of FOSC as determined by the Timer1 prescaler.

TABLE 13-1: TIMER1 CLOCK SOURCE SELECTION

TMR1CS1 TMR1CS0 T1OSCEN Clock Source
0 1 x Clock Source (FOSC)
0 0 x Instruction Clock (FOSC/4)
1 0 0 External Clock on T1CKI Pin
1 0 1 Oscillator Circuit on T1OSI/T1OSO Pin

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FIGURE 13-1: TIMER1 BLOCK DIAGRAM

T1GSS<1:0>

T1G 00 T1GSPM

From Timer2 01
Match PR2 T1G_IN 0
T1GVAL Data Bus
Comparator 1 0 D Q
10
Output Single Pulse RD
Comparator 2 1 T1GCON
11 Acq. Control Q1 EN
Output D Q 1

Interrupt Set
CK Q T1GGO/T1DONE
TMR1ON det TMR1GIF
R
T1GPOL T1GTM
TMR1GE
Set Flag bit TMR1ON
TMR1IF on
Overflow TMR1(2)
EN Synchronized
0 Clock Input
TMR1H TMR1L T1CLK
Q D
1
TMR1CS<1:0>
T1SYNC
T1OSO/T1CKI OUT

T1OSC Prescaler Synchronize(3)

1 1, 2, 4, 8 det
T1OSI 10
EN
SOSCGO 2
0 FOSC
T1OSCEN Internal 01 T1CKPS<1:0>
T3OSCEN Clock
T5OSCEN
T1OSCEN FOSC/4 FOSC/2
00 Internal Sleep Input
Internal
Clock Clock
(1)
T1CKI

Note 1: ST buffer is high-speed type when using T1CKI.

2: Timer1 register increments on rising edge.
3: Synchronization does not operate while in Sleep.

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13.4 Timer1 16-Bit Read/Write Mode TABLE 13-2: CAPACITOR SELECTION FOR
THE TIMER
Timer1 can be configured for 16-bit reads and writes.
OSCILLATOR(2,3,4,5)
When the RD16 control bit (T1CON<1>) is set, the
address for TMR1H is mapped to a buffer register for Oscillator
Freq. C1 C2
the high byte of Timer1. A read from TMR1L loads the Type
contents of the high byte of Timer1 into the Timer1 High LP 32 kHz 12 pF(1) 12 pF(1)
Byte Buffer register. This provides the user with the
ability to accurately read all 16 bits of Timer1 without Note 1: Microchip suggests these values as a
having to determine whether a read of the high byte, starting point in validating the oscillator
followed by a read of the low byte, has become invalid circuit.
due to a rollover between reads.
2: Higher capacitance increases the stability
A write to the high byte of Timer1 must also take place of the oscillator but also increases the
through the TMR1H Buffer register. The Timer1 high start-up time.
byte is updated with the contents of TMR1H when a
3: Since each resonator/crystal has its own
write occurs to TMR1L. This allows a user to write all
characteristics, the user should consult
16 bits to both the high and low bytes of Timer1 at once.
the resonator/crystal manufacturer for
The high byte of Timer1 is not directly readable or appropriate values of external
writable in this mode. All reads and writes must take components.
place through the Timer1 High Byte Buffer register.
4: Capacitor values are for design guidance
Writes to TMR1H do not clear the Timer1 prescaler.
only. Values listed would be typical of a
The prescaler is only cleared on writes to TMR1L.
CL = 10 pF rated crystal when
SOSCSEL<1:0> = 11.
13.5 Timer1 Oscillator
5: Incorrect capacitance value may result in
An on-chip crystal oscillator circuit is incorporated a frequency not meeting the crystal
between pins, T1OSI (input) and T1OSO (amplifier manufacturer’s tolerance specification.
output). It is enabled by setting the Timer1 Oscillator
The Timer1 crystal oscillator drive level is determined
Enable bit, T1OSCEN (T1CON<3>). The oscillator is a
based on the SOSCSEL (CONFIG2L<4:3>) Configura-
low-power circuit rated for 32 kHz crystals. It will
tion bits. The Higher Drive Level mode
continue to run during all power-managed modes. The
(SOSCSEL<1:0> = 11) is intended to drive a wide vari-
circuit for a typical LP oscillator is depicted in
ety of 32.768 kHz crystals with a variety of load capac-
Figure 13-2. Table 13-2 provides the capacitor selection
itance (CL) ratings.
for the Timer1 oscillator.
The Lower Drive Level mode is highly optimized for
The user must provide a software time delay to ensure
extremely low-power consumption. It is not intended to
proper start-up of the Timer1 oscillator.
drive all types of 32.768 kHz crystals. In the Low Drive
Level mode, the crystal oscillator circuit may not work
FIGURE 13-2: EXTERNAL COMPONENTS correctly if excessively large discrete capacitors are
FOR THE TIMER1 LP placed on the T1OSI and T1OSO pins. This mode is
OSCILLATOR only designed to work with discrete capacitances of
approximately 3 pF-10 pF on each pin.
C1
PIC18F47J53
12 pF Crystal manufacturers usually specify a CL (load
T1OSI capacitance) rating for their crystals. This value is
related to, but not necessarily the same as, the values
XTAL that should be used for C1 and C2 in Figure 13-2. See
32.768 kHz the crystal manufacturer’s applications information for
more details on how to select the optimum C1 and C2
T1OSO for a given crystal. The optimum value depends in part
C2
on the amount of parasitic capacitance in the circuit,
12 pF
which is often unknown. Therefore, after values have
Note: See the Notes with Table 13-2 for additional been selected, it is highly recommended that thorough
information about capacitor selection. testing and validation of the oscillator be performed.

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13.5.1 USING TIMER1 AS A FIGURE 13-3: OSCILLATOR CIRCUIT
CLOCK SOURCE WITH GROUNDED
The Timer1 oscillator is also available as a clock source GUARD RING
in power-managed modes. By setting the clock select VDD
bits, SCS<1:0> (OSCCON<1:0>), to ‘01’, the device
switches to SEC_RUN mode; both the CPU and VSS
peripherals are clocked from the Timer1 oscillator. If the
IDLEN bit (OSCCON<7>) is cleared and a SLEEP OSC1
instruction is executed, the device enters SEC_IDLE
OSC2
mode. Additional details are available in Section 4.0
“Low-Power Modes”.
Whenever the Timer1 oscillator is providing the clock
source, the Timer1 system clock status flag, RC0
SOSCRUN (OSCCON2<6>), is set. This can be used
RC1
to determine the controller’s current clocking mode. It
can also indicate the clock source currently being used
by the Fail-Safe Clock Monitor. If the Clock Monitor is RC2
enabled and the Timer1 oscillator fails while providing
the clock, polling the SOSCRUN bit will indicate Note: Not drawn to scale.
whether the clock is being provided by the Timer1 oscil-
lator or another source. In the Low Drive Level mode (SOSCSEL<1:0> = 01), it
is critical that the RC2 I/O pin signals be kept away from
13.5.2 TIMER1 OSCILLATOR LAYOUT the oscillator circuit. Configuring RC2 as a digital out-
CONSIDERATIONS put, and toggling it, can potentially disturb the oscillator
circuit, even with relatively good PCB layout. If
The Timer1 oscillator circuit draws very little power
possible, it is recommended to either leave RC2
during operation. Due to the low-power nature of the
unused, or use it as an input pin with a slew rate limited
oscillator, it may also be sensitive to rapidly changing
signal source. If RC2 must be used as a digital output,
signals in close proximity. This is especially true when
it may be necessary to use the Higher Drive Level
the oscillator is configured for extremely Low-Power
Oscillator mode (SOSCSEL<1:0> = 11) with many
mode (SOSCSEL<1:0> = 01).
PCB layouts. Even in the High Drive Level mode, care-
The oscillator circuit, displayed in Figure 13-2, should ful layout procedures should still be followed when
be located as close as possible to the microcontroller. designing the oscillator circuit.
There should be no circuits passing within the oscillator
In addition to dV/dt induced noise considerations, it is
circuit boundaries other than VSS or VDD.
also important to ensure that the circuit board is clean.
If a high-speed circuit must be located near the Even a very small amount of conductive soldering flux
oscillator (such as the ECCP1 pin in Output Compare residue can cause PCB leakage currents which can
or PWM mode, or the primary oscillator using the overwhelm the oscillator circuit.
OSC2 pin), a grounded guard ring around the oscillator
circuit, as displayed in Figure 13-3, may be helpful
when used on a single-sided PCB or in addition to a 13.6 Timer1 Interrupt
ground plane. The TMR1 register pair (TMR1H:TMR1L) increments
from 0000h to FFFFh and rolls over to 0000h. The
Timer1 interrupt, if enabled, is generated on overflow
which is latched in interrupt flag bit, TMR1IF
(PIR1<0>). This interrupt can be enabled or disabled
by setting or clearing the Timer1 Interrupt Enable bit,
TMR1IE (PIE1<0>).

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13.7 Resetting Timer1 Using the ECCP 13.8 Timer1 Gate
Special Event Trigger The Timer1 can be configured to count freely or the count
If ECCP1 or ECCP2 is configured to use Timer1 and to can be enabled and disabled using the Timer1 gate
generate a Special Event Trigger in Compare mode circuitry. This is also referred to as Timer1 gate count
(CCPxM<3:0> = 1011), this signal will reset Timer3. enable.
The trigger from ECCP2 will also start an A/D conver- The Timer1 gate can also be driven by multiple
sion if the A/D module is enabled (see Section 19.3.4 selectable sources.
“Special Event Trigger” for more information).
The module must be configured as either a timer or a 13.8.1 TIMER1 GATE COUNT ENABLE
synchronous counter to take advantage of this feature. The Timer1 Gate Enable mode is enabled by setting
When used this way, the CCPRxH:CCPRxL register the TMR1GE bit of the T1GCON register. The polarity
pair effectively becomes a period register for Timer1. of the Timer1 Gate Enable mode is configured using
If Timer1 is running in Asynchronous Counter mode, the T1GPOL bit of the T1GCON register.
this Reset operation may not work. When Timer1 Gate Enable mode is enabled, Timer1
In the event that a write to Timer1 coincides with a will increment on the rising edge of the Timer1 clock
Special Event Trigger, the write operation will take source. When Timer1 Gate Enable mode is disabled,
precedence. no incrementing will occur and Timer1 will hold the
current count. See Figure 13-4 for timing details.
Note: The Special Event Trigger from the
ECCPx module will not set the TMR1IF TABLE 13-3: TIMER1 GATE ENABLE
interrupt flag bit (PIR1<0>). SELECTIONS
T1CLK T1GPOL T1G Timer1 Operation
 0 0 Counts
 0 1 Holds Count
 1 0 Holds Count
 1 1 Counts

FIGURE 13-4: TIMER1 GATE COUNT ENABLE MODE

TMR1GE

T1GPOL

T1G_IN

T1CKI

T1GVAL

Timer1 N N+1 N+2 N+3 N+4

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13.8.2 TIMER1 GATE SOURCE 13.8.2.2 Timer2 Match Gate Operation
SELECTION The TMR2 register will increment until it matches the
The Timer1 gate source can be selected from one of value in the PR2 register. On the very next increment
four different sources. Source selection is controlled by cycle, TMR2 will be reset to 00h. When this Reset
the T1GSSx bits of the T1GCON register. The polarity occurs, a low-to-high pulse will automatically be
for each available source is also selectable. Polarity generated and internally supplied to the Timer1 gate
selection is controlled by the T1GPOL bit of the circuitry.
T1GCON register.
13.8.3 TIMER1 GATE TOGGLE MODE
TABLE 13-4: TIMER1 GATE SOURCES When Timer1 Gate Toggle mode is enabled, it is
possible to measure the full cycle length of a Timer1
T1GSS<1:0> Timer1 Gate Source
gate signal, as opposed to the duration of a single level
00 Timer1 Gate Pin pulse.
01 TMR2 matches PR2 The Timer1 gate source is routed through a flip-flop that
10 Comparator 1 output changes state on every incrementing edge of the
11 Comparator 2 output signal. See Figure 13-5 for timing details.
The T1GVAL bit will indicate when the Toggled mode is
13.8.2.1 T1G Pin Gate Operation active and the timer is counting.
The T1G pin is one source for Timer1 gate control. It The Timer1 Gate Toggle mode is enabled by setting the
can be used to supply an external source to the Timer1 T1GTM bit of the T1GCON register. When the T1GTM
gate circuitry. bit is cleared, the flip-flop is cleared and held clear. This
is necessary in order to control which edge is
measured.

FIGURE 13-5: TIMER1 GATE TOGGLE MODE

TMR1GE

T1GPOL

T1GTM

T1G_IN

T1CKI

T1GVAL

Timer1 N N+1 N+2 N+3 N+4 N+5 N+6 N+7 N+8

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13.8.4 TIMER1 GATE SINGLE PULSE Clearing the T1GSPM bit of the T1GCON register will
MODE also clear the T1GGO/T1DONE bit. See Figure 13-6
for timing details.
When Timer1 Gate Single Pulse mode is enabled, it is
possible to capture a single pulse gate event. Timer1 Enabling the Toggle mode and the Single Pulse mode,
Gate Single Pulse mode is first enabled by setting the simultaneously, will permit both sections to work together.
T1GSPM bit in the T1GCON register. Next, the This allows the cycle times on the Timer1 gate source to
T1GGO/T1DONE bit in the T1GCON register must be be measured. See Figure 13-7 for timing details.
set. The Timer1 will be fully enabled on the next incre-
menting edge. On the next trailing edge of the pulse, 13.8.5 TIMER1 GATE VALUE STATUS
the T1GGO/T1DONE bit will automatically be cleared. When the Timer1 gate value status is utilized, it is
No other gate events will be allowed to increment possible to read the most current level of the gate
Timer1 until the T1GGO/T1DONE bit is once again set control value. The value is stored in the T1GVAL bit in
in software. the T1GCON register. The T1GVAL bit is valid even
when the Timer1 gate is not enabled (TMR1GE bit is
cleared).

FIGURE 13-6: TIMER1 GATE SINGLE PULSE MODE

TMR1GE

T1GPOL

T1GSPM
Cleared by Hardware on
T1GGO/ Set by Software Falling Edge of T1GVAL
T1DONE
Counting Enabled on
Rising Edge of T1G
T1G_IN

T1CKI

T1GVAL

Timer1 N N+1 N+2

Cleared by
TMR1GIF Cleared by Software Set by Hardware on Software
Falling Edge of T1GVAL

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FIGURE 13-7: TIMER1 GATE SINGLE PULSE AND TOGGLE COMBINED MODE

TMR1GE

T1GPOL

T1GSPM

T1GTM

Cleared by Hardware on
T1GGO/ Set by Software Falling Edge of T1GVAL
T1DONE Counting Enabled on
Rising Edge of T1G
T1G_IN

T1CKI

T1GVAL

Timer1 N N+1 N+2 N+3 N+4

Set by Hardware on Cleared by

TMR1GIF Cleared by Software Falling Edge of T1GVAL Software

TABLE 13-5: REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF
PIR1 PMPIF(1) ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF
PIE1 PMPIE(1) ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE
IPR1 PMPIP(1) ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP
TMR1L Timer1 Register Low Byte
TMR1H Timer1 Register High Byte
T1CON TMR1CS1 TMR1CS0 T1CKPS1 T1CKPS0 T1OSCEN T1SYNC RD16 TMR1ON
T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO/ T1GVAL T1GSS1 T1GSS0
T1DONE
OSCCON2 — SOSCRUN — SOSCDRV SOSCGO PRISD — —
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module.
Note 1: These bits are only available in 44-pin devices.

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14.0 TIMER2 MODULE 14.1 Timer2 Operation
The Timer2 module incorporates the following features: In normal operation, TMR2 is incremented from 00h on
each clock (FOSC/4). A 4-bit counter/prescaler on the
• 8-bit Timer and Period registers (TMR2 and PR2,
clock input gives direct input, divide-by-4 and
respectively)
divide-by-16 prescale options. These are selected by
• Readable and writable (both registers) the prescaler control bits, T2CKPS<1:0>
• Software programmable prescaler (T2CON<1:0>). The value of TMR2 is compared to that
(1:1, 1:4 and 1:16) of the Period register, PR2, on each clock cycle. When
• Software programmable postscaler the two values match, the comparator generates a
(1:1 through 1:16) match signal as the timer output. This signal also resets
• Interrupt on TMR2 to PR2 match the value of TMR2 to 00h on the next cycle and drives
• Optional use as the shift clock for the the output counter/postscaler (see Section 14.2
MSSP modules “Timer2 Interrupt”).

The module is controlled through the T2CON register The TMR2 and PR2 registers are both directly readable
(Register 14-1) which enables or disables the timer and and writable. The TMR2 register is cleared on any
configures the prescaler and postscaler. Timer2 can be device Reset, while the PR2 register initializes at FFh.
shut off by clearing control bit, TMR2ON (T2CON<2>), Both the prescaler and postscaler counters are cleared
to minimize power consumption. on the following events:

A simplified block diagram of the module is shown in • a write to the TMR2 register
Figure 14-1. • a write to the T2CON register
• any device Reset (Power-on Reset (POR), MCLR
Reset, Watchdog Timer Reset (WDTR) or
Brown-out Reset (BOR))
TMR2 is not cleared when T2CON is written.

REGISTER 14-1: T2CON: TIMER2 CONTROL REGISTER (ACCESS FCAh)

U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 Unimplemented: Read as ‘0’

bit 6-3 T2OUTPS<3:0>: Timer2 Output Postscale Select bits
0000 = 1:1 Postscale
0001 = 1:2 Postscale
•
•
•
1111 = 1:16 Postscale
bit 2 TMR2ON: Timer2 On bit
1 = Timer2 is on
0 = Timer2 is off
bit 1-0 T2CKPS<1:0>: Timer2 Clock Prescale Select bits
00 = Prescaler is 1
01 = Prescaler is 4
10 = Prescaler is 16

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14.2 Timer2 Interrupt 14.3 Timer2 Output
Timer2 can also generate an optional device interrupt. The unscaled output of TMR2 is available primarily to
The Timer2 output signal (TMR2 to PR2 match) pro- the ECCP modules, where it is used as a time base for
vides the input for the 4-bit output counter/postscaler. operations in PWM mode.
This counter generates the TMR2 Match Interrupt Flag, Timer2 can be optionally used as the shift clock source
which is latched in TMR2IF (PIR1<1>). The interrupt is for the MSSP modules operating in SPI mode.
enabled by setting the TMR2 Match Interrupt Enable Additional information is provided in Section 20.0
bit, TMR2IE (PIE1<1>). “Master Synchronous Serial Port (MSSP) Module”.
A range of 16 postscaler options (from 1:1 through 1:16
inclusive) can be selected with the postscaler control
bits, T2OUTPS<3:0> (T2CON<6:3>).

FIGURE 14-1: TIMER2 BLOCK DIAGRAM

4 1:1 to 1:16
T2OUTPS<3:0> Set TMR2IF
Postscaler
2
T2CKPS<1:0> TMR2 Output
(to PWM or MSSPx)
TMR2/PR2
Reset Match
1:1, 1:4, 1:16
FOSC/4 TMR2 Comparator PR2
Prescaler

8 8
8
Internal Data Bus

TABLE 14-1: REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF
PIR1 PMPIF(1) ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF
PIE1 PMPIE(1) ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE
IPR1 PMPIP(1) ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP
TMR2 Timer2 Register
T2CON — T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0
PR2 Timer2 Period Register
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer2 module.
Note 1: These bits are only available in 44-pin devices.

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15.0 TIMER3/5 MODULE A simplified block diagram of the Timer3/5 module is
shown in Figure 15-1.
The Timer3/5 timer/counter modules incorporate these
The Timer3/5 module is controlled through the TxCON
features:
register (Register 15-1). It also selects the clock source
• Software selectable operation as a 16-bit timer or options for the ECCP modules. (For more information,
counter see Section 19.1.1 “ECCP Module and Timer
• Readable and writable 8-bit registers (TMRxH Resources”.)
and TMRxL) The FOSC clock source should not be used with the
• Selectable clock source (internal or external) with ECCP capture/compare features. If the timer will be
device clock or Timer1 oscillator internal options used with the capture or compare features, always
• Interrupt-on-overflow select one of the other timer clocking options.
• Module Reset on ECCP Special Event Trigger
Note: Throughout this section, generic references
are used for register and bit names that are the
same – except for an ‘x’ variable that indicates
the item’s association with the Timer3 or
Timer5 module. For example, the control reg-
ister is named TxCON, and refers to T3CON
and T5CON.

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REGISTER 15-1: TxCON: TIMER3/5 CONTROL REGISTER (ACCESS F79h, BANKED F22h)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
TMRxCS1 TMRxCS0 TxCKPS1 TxCKPS0 TxOSCEN TxSYNC RD16 TMRxON
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-6 TMRxCS<1:0>: Clock Source Select bits

10 = Clock source is the pin or TxCKI input pin
01 = Clock source is the system clock (FOSC)(1)
00 = Clock source is the instruction clock (FOSC/4)
bit 5-4 TxCKPS<1:0>: Timerx Input Clock Prescale Select bits
11 = 1:8 Prescale value
10 = 1:4 Prescale value
01 = 1:2 Prescale value
00 = 1:1 Prescale value
bit 3 TxOSCEN: Timer Oscillator Enable bit
1 = T1OSC/SOSC oscillator used as clock source
0 = TxCKI digital input pin used as clock source
bit 2 TxSYNC: External Clock Input Synchronization Control bit
(Not usable if the device clock comes from Timer1/Timer3.)
When TMRxCS1:TMRxCS0 = 10:
1 = Do not synchronize external clock input
0 = Synchronize external clock input
When TMRxCS1:TMRxCS0 = 0x:
This bit is ignored; Timer3 uses the internal clock.
bit 1 RD16: 16-Bit Read/Write Mode Enable bit
1 = Enables register read/write of timer in one 16-bit operation
0 = Enables register read/write of timer in two eight-bit operations
bit 0 TMRxON: Timer On bit
1 = Enables Timer
0 = Stops Timer

Note 1: The FOSC clock source should not be selected if the timer will be used with the ECCP capture/compare
features.

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15.1 Timer3/5 Gate Control Register
The Timer3/5 Gate Control register (TxGCON), pro-
vided in Register 14-2, is used to control the Timerx
gate.

REGISTER 15-2: TxGCON: TIMER3/5 GATE CONTROL REGISTER(1) (ACCESS F97h,

BANKED F21h)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-x R/W-0 R/W-0
TMRxGE TxGPOL TxGTM TxGSPM TxGGO/TxDONE TxGVAL TxGSS1 TxGSS0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 TMRxGE: Timer Gate Enable bit

If TMRxON = 0:
This bit is ignored.
If TMRxON = 1:
1 = Timer counting is controlled by the Timerx gate function
0 = Timer counts regardless of the Timerx gate function
bit 6 TxGPOL: Gate Polarity bit
1 = Timer gate is active-high (Timerx counts when the gate is high)
0 = Timer gate is active-low (Timerx counts when the gate is low)
bit 5 TxGTM: Gate Toggle Mode bit
1 = Timer Gate Toggle mode is enabled.
0 = Timer Gate Toggle mode is disabled and toggle flip-flop is cleared
Timerx gate flip-flop toggles on every rising edge.
bit 4 TxGSPM: Timer Gate Single Pulse Mode bit
1 = Timer Gate Single Pulse mode is enabled and is controlling Timerx gate
0 = Timer Gate Single Pulse mode is disabled
bit 3 TxGGO/TxDONE: Timer Gate Single Pulse Acquisition Status bit
1 = Timer gate single pulse acquisition is ready, waiting for an edge
0 = Timer gate single pulse acquisition has completed or has not been started
This bit is automatically cleared when TxGSPM is cleared.
bit 2 TxGVAL: Timer Gate Current State bit
Indicates the current state of the Timer gate that could be provided to TMRxH:TMRxL. Unaffected by the
Timer Gate Enable bit (TMRxGE).
bit 1-0 TxGSS<1:0>: Timer Gate Source Select bits
11 = Comparator 2 output
10 = Comparator 1 output
01 = TMR4/6 to match PR4/6 output
00 = T3G/T5G gate input pin

Note 1: Programming the TxGCON prior to TxCON is recommended.

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REGISTER 15-3: OSCCON2: OSCILLATOR CONTROL REGISTER 2 (ACCESS F87h)
U-0 R-0(2) U-0 R/W-1 R/W-0(2) R/W-1 U-0 U-0
— SOSCRUN — SOSCDRV SOSCGO(3) PRISD — —
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 Unimplemented: Read as ‘0’

bit 6 SOSCRUN: SOSC Run Status bit
1 = System clock comes from secondary SOSC
0 = System clock comes from an oscillator other than SOSC
bit 5 Unimplemented: Read as ‘0’
bit 4 SOSCDRV: SOSC Drive Control bit
1 = T1OSC/SOSC circuit oscillator drive circuit selected by Configuration bits, CONFIG2L<4:3>
0 = Low-power T1OSC/SOSC circuit is selected
bit 3 SOSCGO: Oscillator Start Control bit
1 = Turns on the oscillator, even if no peripherals are requesting it.
0 = Oscillator is shut off unless peripherals are requesting it
bit 2 PRISD: Primary Oscillator Drive Circuit shutdown
1 = Oscillator drive circuit on
0 = Oscillator drive circuit off (zero power)
bit 1-0 Unimplemented: Read as ‘0’

Note 1: Reset value is ‘0’ when Two-Speed Start-up is enabled and ‘1’ if disabled.
2: Default output frequency of INTOSC on Reset (4 MHz).
3: When the SOSC is selected to run from a digital clock input, rather than an external crystal, this bit has no
effect.

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15.2 Timer3/5 Operation The operating mode is determined by the clock select
bits, TMRxCSx (TxCON<7:6>). When the TMRxCSx bits
Timer3 and Timer5 can operate in these modes: are cleared (= 00), Timer3/5 increments on every internal
• Timer instruction cycle (FOSC/4). When TMRxCSx = 01, the
• Synchronous Counter Timer3/5 clock source is the system clock (FOSC), and
when it is ‘10’, Timer3/5 works as a counter from the
• Asynchronous Counter
external clock from the TxCKI pin (on the rising edge after
• Timer with Gated Control the first falling edge) or the Timer1 oscillator.

FIGURE 15-1: TIMER3/5 BLOCK DIAGRAM

TxGSS<1:0>

TxG 00 TxGSPM

From Timer4/6 01 TxG_IN 0

Data Bus
Match PR4/6 0 TxGVAL
D Q
Comparator 1 10 Single Pulse RD
Output 1 T3GCON
Acq. Control Q1 EN
D Q 1
Comparator 2 11
Output Interrupt Set
CK Q TxGGO/TxDONE
TMRxON det TMRxGIF
R
TxGPOL TxGTM
TMRxGE
Set flag bit TMRxON
TMRxIF on
Overflow TMRx(2)
EN Synchronized
0 Clock Input
TMRxH TMRxL TxCLK
Q D
1

TMRxCS<1:0> TxSYNC
T1OSO/T1CKI OUT

T1OSC/SOSC
Prescaler Synchronize(3)
1 1, 2, 4, 8 det
T1OSI 10
EN
SOSCGO 2
0
T1OSCEN FOSC TxCKPS<1:0>
T3OSCEN Internal 01
T5OSCEN Clock
TXOSCEN FOSC/2
Internal Sleep Input
FOSC/4 Clock
Internal 00
(1) Clock
TxCKI

Note 1: ST buffer is a high-speed type when using T1CKI.

2: Timerx registers increment on rising edge.
3: Synchronization does not operate while in Sleep.

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15.3 Timer3/5 16-Bit Read/Write Mode 15.5 Timer3/5 Gates
Timer3/5 can be configured for 16-bit reads and writes Timer3/5 can be configured to count freely or the count
(see Figure 15.3). When the RD16 control bit can be enabled and disabled using the Timer3/5 gate
(TxCON<1>) is set, the address for TMRxH is mapped to circuitry. This is also referred to as the Timer3/5 gate
a buffer register for the high byte of Timer3/5. A read from count enable.
TMRxL will load the contents of the high byte of Timer3/5 The Timer3/5 gate can also be driven by multiple
into the Timerx High Byte Buffer register. This provides selectable sources.
users with the ability to accurately read all 16 bits of
Timer3/5 without having to determine whether a read of 15.5.1 TIMER3/5 GATE COUNT ENABLE
the high byte, followed by a read of the low byte, has
become invalid due to a rollover between reads. The Timerx Gate Enable mode is enabled by setting
the TMRxGE bit (TxGCON<7>). The polarity of the
A write to the high byte of Timer3/5 must also take place Timerx Gate Enable mode is configured using the
through the TMRxH Buffer register. The Timer3/5 high TxGPOL bit (TxGCON<6>).
byte is updated with the contents of TMRxH when a write
occurs to TMRxL. This allows users to write all 16 bits to When Timerx Gate Enable mode is enabled, Timer3/5
both the high and low bytes of Timer3/5 at once. will increment on the rising edge of the Timer3/5 clock
source. When Timerx Gate Enable mode is disabled,
The high byte of Timer3/5 is not directly readable or no incrementing will occur and Timer3/5 will hold the
writable in this mode. All reads and writes must take current count. See Figure 15-2 for timing details.
place through the Timerx High Byte Buffer register.
Writes to TMRxH do not clear the Timer3/5 prescaler. TABLE 15-1: TIMER3/5 GATE ENABLE
The prescaler is only cleared on writes to TMRxL. SELECTIONS
TxGPOL TxG Timerx
15.4 Using the Timer1 Oscillator as the TxCLK(†)
(TxGCON<6>) Pin Operation
Timer3/5 Clock Source
 0 0 Counts
The Timer1 internal oscillator may be used as the clock
 0 1 Holds Count
source for Timer3/5. The Timer1 oscillator is enabled
by setting the T1OSCEN (T1CON<3>) bit. To use it as  1 0 Holds Count
the Timer3/5 clock source, the TMRxCS bits must also  1 1 Counts
be set. As previously noted, this also configures † The clock on which TMR3/5 is running. For more
Timer3/5 to increment on every rising edge of the information, see TxCLK in Figure 15-1.
oscillator source.
The Timer1 oscillator is described in Section 13.0
“Timer1 Module”.

FIGURE 15-2: TIMER3/5 GATE COUNT ENABLE MODE

TMRxGE

TxGPOL

TxG_IN

TxCKI

TxGVAL

Timer3/5 N N+1 N+2 N+3 N+4

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15.5.2 TIMER3/5 GATE SOURCE 15.5.2.2 Timer4/6 Match Gate Operation
SELECTION The TMR4/6 register will increment until it matches the
The Timer3/5 gate source can be selected from one of value in the PR4/6 register. On the very next increment
four different sources. Source selection is controlled by cycle, TMR4/6 will be reset to 00h. When this Reset
the TxGSS<1:0> bits (TxGCON<1:0>). The polarity for occurs, a low-to-high pulse will automatically be
each available source is also selectable and is generated and internally supplied to the Timer3/5 gate
controlled by the TxGPOL bit (TxGCON<6>). circuitry.

TABLE 15-2: TIMER3/5 GATE SOURCES 15.5.3 TIMER3/5 GATE-TOGGLE MODE

When Timer3/5 Gate Toggle mode is enabled, it is
TxGSS<1:0> Timerx Gate Source
possible to measure the full cycle length of a Timer3/5
00 TxG timer gate pin gate signal, as opposed to the duration of a single level
01 TMR4/6 matches PR4/6 pulse.
10 Comparator 1 output The Timer1 gate source is routed through a flip-flop that
11 Comparator 2 output changes state on every incrementing edge of the
signal. (For timing details, see Figure 15-3.)
15.5.2.1 TxG Pin Gate Operation The TxGVAL bit will indicate when the Toggled mode is
The TxG pin is one source for Timer3/5 gate control. It active and the timer is counting.
can be used to supply an external source to the gate Timer3/5 Gate Toggle mode is enabled by setting the
circuitry. TxGTM bit (TxGCON<5>). When the TxGTM bit is
cleared, the flip-flop is cleared and held clear. This is
necessary in order to control which edge is measured.

FIGURE 15-3: TIMER3/5 GATE TOGGLE MODE

TMRxGE

TxGPOL

TxGTM

TxG_IN

TxCKI

TxGVAL

Timer3/5 N N+1 N+2 N+3 N+4 N+5 N+6 N+7 N+8

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15.5.4 TIMER3/5 GATE SINGLE PULSE No other gate events will be allowed to increment
MODE Timer3/5 until the TxGGO/TxDONE bit is once again
set in software.
When Timer3/5 Gate Single Pulse mode is enabled, it
is possible to capture a single pulse gate event. Clearing the TxGSPM bit will also clear the
Timer3/5 Gate Single Pulse mode is first enabled by TxGGO/TxDONE bit. (For timing details, see
setting the TxGSPM bit (TxGCON<4>). Next, the Figure 15-4.)
TxGGO/TxDONE bit (TxGCON<3>) must be set. Simultaneously, enabling the Toggle mode and the
The Timer3/5 will be fully enabled on the next incre- Single Pulse mode will permit both sections to work
menting edge. On the next trailing edge of the pulse, together. This allows the cycle times on the Timer3/5
the TxGGO/TxDONE bit will automatically be cleared. gate source to be measured. (For timing details, see
Figure 15-5.)

FIGURE 15-4: TIMER3/5 GATE SINGLE PULSE MODE

TMRxGE

TxGPOL

TxGSPM

Cleared by Hardware on
TxGGO/ Set by Software Falling Edge of TxGVAL
TxDONE
Counting Enabled on
Rising Edge of TxG
TxG_IN

TxCKI

TxGVAL

Timer3/5 N N+1 N+2

Cleared by
TMRxGIF Cleared by Software Set by Hardware on Software
Falling Edge of TxGVAL

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FIGURE 15-5: TIMER3/5 GATE SINGLE PULSE AND TOGGLE COMBINED MODE

TMRxGE

TxGPOL

TxGSPM

TxGTM

Cleared by Hardware on
TxGGO/ Set by Software Falling Edge of TxGVAL
TxDONE
Counting Enabled on
Rising Edge of TxG
TxG_IN

TxCKI

TxGVAL

Timer3/5 N N+1 N+2 N+3 N+4

Set by Hardware on Cleared by

TMRxGIF Cleared by Software Falling Edge of TxGVAL Software

15.5.5 TIMER3/5 GATE VALUE STATUS 15.5.6 TIMER3/5 GATE EVENT

When Timer3/5 gate value status is utilized, it is INTERRUPT
possible to read the most current level of the gate con- When the Timer3/5 gate event interrupt is enabled, it is
trol value. The value is stored in the TxGVAL bit possible to generate an interrupt upon the completion
(TxGCON<2>). The TxGVAL bit is valid even when the of a gate event. When the falling edge of TxGVAL
Timer3/5 gate is not enabled (TMRxGE bit is cleared). occurs, the TMRxGIF flag bit in the PIRx register will be
set. If the TMRxGIE bit in the PIEx register is set, then
an interrupt will be recognized.
The TMRxGIF flag bit operates even when the
Timer3/5 gate is not enabled (TMRxGE bit is cleared).

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15.6 Timer3/5 Interrupt 15.7 Resetting Timer3/5 Using the
The TMRx register pair (TMRxH:TMRxL) increments
ECCP Special Event Trigger
from 0000h to FFFFh and overflows to 0000h. The If the ECCP modules are configured to use Timerx and
Timerx interrupt, if enabled, is generated on overflow to generate a Special Event Trigger in Compare mode
and is latched in the interrupt flag bit, TMRxIF. (CCPxM<3:0> = 1011), this signal will reset Timerx.
Table 15-3 gives each module’s flag bit. The trigger from ECCP2 will also start an A/D conver-
TABLE 15-3: TIMER3/5 INTERRUPT FLAG sion if the A/D module is enabled. (For more informa-
BITS tion, see Section 19.3.4 “Special Event Trigger”.)
The module must be configured as either a timer or
Timer Module Flag Bit
synchronous counter to take advantage of this feature.
3 PIR2<1> When used this way, the CCPRxH:CCPRxL register
5 PIR5<1> pair effectively becomes a Period register for TimerX.
If Timerx is running in Asynchronous Counter mode,
This interrupt can be enabled or disabled by setting or
the Reset operation may not work.
clearing the TMRxIE bit, respectively. Table 15-4 gives
each module’s enable bit. In the event that a write to Timerx coincides with a
Special Event Trigger from an ECCP module, the write
TABLE 15-4: TIMER3/5 INTERRUPT will take precedence.
ENABLE BITS
Note: The Special Event Triggers from the
Timer Module Flag Bit ECCPx module will only clear the TMR3
3 PIE2<1> register’s content, but not set the TMR3IF
interrupt flag bit (PIR1<0>).
5 PIE5<2>

Note: The CCP and ECCP modules use Timers

1 through 8 for some modes. The assign-
ment of a particular timer to a CCP/ECCP
module is determined by the Timer to CCP
enable bits in the CCPTMRSx registers.
For more details, see Register 19-2 and
Register 18-3.

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TABLE 15-5: REGISTERS ASSOCIATED WITH TIMER3/5 AS A TIMER/COUNTER
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF
PIR5 — — CM3IF TMR8IF TMR6IF TMR5IF TMR5GIF TMR1GIF
PIE5 — — CM3IE TMR8IE TMR6IE TMR5IE TMR5GIE TMR1GIE
PIR2 OSCFIF CM2IF CM1IF USBIF BCL1IF HLVDIF TMR3IF CCP2IF
PIE2 OSCFIE CM2IE CM1IE USBIE BCL1IE HLVDIE TMR3IE CCP2IE
TMR3H Timer3 Register High Byte
TMR3L Timer3 Register Low Byte
T3GCON TMR3GE T3GPOL T3GTM T3GSPM T3GGO/ T3GVAL T3GSS1 T3GSS0
T3DONE
T3CON TMR3CS1 TMR3CS0 T3CKPS1 T3CKPS0 T3OSCEN T3SYNC RD16 TMR3ON
TMR5H Timer5 Register High Byte
TMR5L Timer5 Register Low Byte
T5GCON TMR5GE T5GPOL T5GTM T5GSPM T5GGO/ T5GVAL T5GSS1 T5GSS0
T5DONE
T5CON TMR5CS1 TMR5CS0 T5CKPS1 T5CKPS0 T5OSCEN T5SYNC RD16 TMR5ON
OSCCON2 — SOSCRUN — SOSCDRV SOSCGO PRISD — —
CCPTMRS0 C3TSEL1 C3TSEL0 C2TSEL2 C2TSEL1 C2TSEL0 C1TSEL2 C1TSEL1 C1TSEL0
CCPTMRS1 C7TSEL1 C7TSEL0 — C6TSEL0 — C5TSEL0 C4TSEL1 C4TSEL0
CCPTMRS1 — — — C10TSEL0 — C9TSEL0 C8TSEL1 C8TSEL0
CCPTMRS2 — — — C10TSEL0 — C9TSEL0 C8TSEL1 C8TSEL0
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer3 module.

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16.0 TIMER4/6/8 MODULE 1:1 to 1:16 inclusive scaling) to generate a TMRx
interrupt, latched in the flag bit, TMRxIF. Table 16-1
The Timer4/6/8 timer modules have the following gives each module’s flag bit.
features:
TABLE 16-1: TIMER4/6/8 FLAG BITS
• Eight-bit Timer register (TMRx)
Timer Module Flag Bit
• Eight-bit Period register (PRx)
• Readable and writable (all registers) 4 PIR3<3>
• Software programmable prescaler (1:1, 1:4, 1:16) 6 PIR5<3>
• Software programmable postscaler (1:1 to 1:16) 8 PIR5<4>
• Interrupt on TMRx match of PRx The interrupt can be enabled or disabled by setting or
Note: Throughout this section, generic references clearing the Timerx Interrupt Enable bit (TMRxIE),
are used for register and bit names that are the shown in Table 16-2.
same – except for an ‘x’ variable that indicates TABLE 16-2: TIMER4/6/8 INTERRUPT
the item’s association with the Timer4, Timer6 ENABLE BITS
or Timer8 module. For example, the control
register is named TxCON and refers to Timer Module Flag Bit
T4CON, T6CON and T8CON. 4 PIE3<3>
The Timer4/6/8 modules have a control register shown 6 PIE5<3>
in Register 16-1. Timer4/6/8 can be shut off by clearing 8 PIE5<4>
control bit, TMRxON (TxCON<2>), to minimize power
consumption. The prescaler and postscaler selection of The prescaler and postscaler counters are cleared
Timer4/6/8 are also controlled by this register. when any of the following occurs:
Figure 16-1 is a simplified block diagram of the • A write to the TMRx register
Timer4/6/8 modules. • A write to the TxCON register
• Any device Reset (Power-on Reset (POR), MCLR
16.1 Timer4/6/8 Operation Reset, Watchdog Timer Reset (WDTR) or
Timer4/6/8 can be used as the PWM time base for the Brown-out Reset (BOR))
PWM mode of the ECCP modules. The TMRx registers A TMRx is not cleared when a TxCON is written.
are readable and writable, and are cleared on any
device Reset. The input clock (FOSC/4) has a prescale Note: The CCP and ECCP modules use Timers
option of 1:1, 1:4 or 1:16, selected by control bits, 1 through 8 for some modes. The assign-
TxCKPS<1:0> (TxCON<1:0>). The match output of ment of a particular timer to a CCP/ECCP
TMRx goes through a four-bit postscaler (that gives a module is determined by the Timer to CCP
enable bits in the CCPTMRSx registers.
For more details, see Register 19-2,
Register 18-2 and Register 18-3.

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REGISTER 16-1: TxCON: TIMER4/6/8 CONTROL REGISTER (ACCESS F76h, BANKED F1Eh,
BANKED F1Bh)
U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— TxOUTPS3 TxOUTPS2 TxOUTPS1 TxOUTPS0 TMRxON TxCKPS1 TxCKPS0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 Unimplemented: Read as ‘0’

bit 6-3 TxOUTPS<3:0>: Timerx Output Postscale Select bits
0000 = 1:1 Postscale
0001 = 1:2 Postscale
•
•
•
1111 = 1:16 Postscale
bit 2 TMRxON: Timerx On bit
1 = Timerx is on
0 = Timerx is off
bit 1-0 TxCKPS<1:0>: Timerx Clock Prescale Select bits
00 = Prescaler is 1
01 = Prescaler is 4
1x = Prescaler is 16

16.2 Timer4/6/8 Interrupt 16.3 Output of TMRx

The Timer4/6/8 modules have 8-bit Period registers, The outputs of TMRx (before the postscaler) are used
PRx, that are both readable and writable. Timer4/6/8 only as a PWM time base for the ECCP modules. They
increment from 00h until they match PR4/6/8 and then are not used as baud rate clocks for the MSSP
reset to 00h on the next increment cycle. The PRx modules as is the Timer2 output.
registers are initialized to FFh upon Reset.

FIGURE 16-1: TIMER4 BLOCK DIAGRAM

4
1:1 to 1:16
TxOUTPS<3:0> Set TMRxIF
Postscaler
2
TxCKPS<1:0> TMRx Output
(to PWM)
TMRx/PRx
Reset Match
1:1, 1:4, 1:16
FOSC/4 TMRx Comparator PRx
Prescaler

8 8
8
Internal Data Bus

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TABLE 16-3: REGISTERS ASSOCIATED WITH TIMER4/6/8 AS A TIMER/COUNTER
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF
IPR5 TMR7GIP TMR12IP TMR10IP TMR8IP TMR7IP TMR6IP TMR5IP TMR4IP
PIR5 — — CM3IF TMR8IF TMR6IF TMR5IF TMR5GIF TMR1GIF
PIE5 — — CM3IE TMR8IE TMR6IE TMR5IE TMR5GIE TMR1GIE
TMR4 Timer4 Register
T4CON — T4OUTPS3 T4OUTPS2 T4OUTPS1 T4OUTPS0 TMR4ON T4CKPS1 T4CKPS0
PR4 Timer4 Period Register
TMR6 Timer6 Register
T6CON — T6OUTPS3 T6OUTPS2 T6OUTPS1 T6OUTPS0 TMR6ON T6CKPS1 T6CKPS0
PR6 Timer6 Period Register
TMR8 Timer8 Register
T8CON — T8OUTPS3 T8OUTPS2 T8OUTPS1 T8OUTPS0 TMR8ON T8CKPS1 T8CKPS0
PR8 Timer8 Period Register
CCPTMRS0 C3TSEL1 C3TSEL0 C2TSEL2 C2TSEL1 C2TSEL0 C1TSEL2 C1TSEL1 C1TSEL0
CCPTMRS1 C7TSEL1 C7TSEL0 — C6TSEL0 — C5TSEL0 C4TSEL1 C4TSEL0
CCPTMRS2 — — — C10TSEL0 — C9TSEL0 C8TSEL1 C8TSEL0
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer4 module.

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17.0 REAL-TIME CLOCK AND The RTCC module is intended for applications where
accurate time must be maintained for an extended
CALENDAR (RTCC) period with minimum to no intervention from the CPU.
The key features of the Real-Time Clock and Calendar The module is optimized for low-power usage in order
(RTCC) module are: to provide extended battery life while keeping track of
time.
• Time: hours, minutes and seconds
• 24-hour format (military time) The module is a 100-year clock and calendar with auto-
matic leap year detection. The range of the clock is
• Calendar: weekday, date, month and year
from 00:00:00 (midnight) on January 1, 2000 to
• Alarm configurable 23:59:59 on December 31, 2099. Hours are measured
• Year range: 2000 to 2099 in 24-hour (military time) format. The clock provides a
• Leap year correction granularity of one second with half-second visibility to
• BCD format for compact firmware the user.
• Optimized for low-power operation
• User calibration with auto-adjust
• Calibration range: 2.64 seconds error per month
• Requirements: external 32.768 kHz clock crystal
• Alarm pulse or seconds clock output on RTCC pin

FIGURE 17-1: RTCC BLOCK DIAGRAM

RTCC Clock Domain CPU Clock Domain

32.768 kHz Input

from Timer1 Oscillator RTCCFG
RTCC Prescalers
ALRMRPT
Internal RC YEAR
0.5s
MTHDY
RTCC Timer RTCVAL
WKDYHR
Alarm
Event MINSEC
Comparator

ALMTHDY
Compare Registers
ALRMVAL ALWDHR
with Masks
ALMINSEC

Repeat Counter

RTCC Interrupt
RTCC Interrupt Logic
Alarm Pulse

RTCC Pin

RTCOE

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17.1 RTCC MODULE REGISTERS Alarm Value Registers
The RTCC module registers are divided into following • ALRMVALH and ALRMVALL – Can access the
categories: following registers:
- ALRMMNTH
RTCC Control Registers - ALRMDAY
• RTCCFG - ALRMWD
• RTCCAL - ALRMHR
• PADCFG1 - ALRMMIN
• ALRMCFG - ALRMSEC
• ALRMRPT Note: The RTCVALH and RTCVALL registers
can be accessed through RTCRPT<1:0>.
RTCC Value Registers ALRMVALH and ALRMVALL can be
accessed through ALRMPTR<1:0>.
• RTCVALH and RTCVALL – Can access the
following registers
- YEAR
- MONTH
- DAY
- WEEKDAY
- HOUR
- MINUTE
- SECOND

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17.1.1 RTCC CONTROL REGISTERS

REGISTER 17-1: RTCCFG: RTCC CONFIGURATION REGISTER (BANKED F3Fh)(1)

R/W-0 U-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0

RTCEN(2) — RTCWREN RTCSYNC HALFSEC (3)
RTCOE RTCPTR1 RTCPTR0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 RTCEN: RTCC Enable bit(2)

1 = RTCC module is enabled
0 = RTCC module is disabled
bit 6 Unimplemented: Read as ‘0’
bit 5 RTCWREN: RTCC Value Registers Write Enable bit
1 = RTCVALH and RTCVALL registers can be written to by the user
0 = RTCVALH and RTCVALL registers are locked out from being written to by the user
bit 4 RTCSYNC: RTCC Value Registers Read Synchronization bit
1 = RTCVALH, RTCVALL and ALCFGRPT registers can change while reading due to a rollover ripple
resulting in an invalid data read
If the register is read twice and results in the same data, the data can be assumed to be valid.
0 = RTCVALH, RTCVALL or ALCFGRPT registers can be read without concern over a rollover ripple
bit 3 HALFSEC: Half-Second Status bit(3)
1 = Second half period of a second
0 = First half period of a second
bit 2 RTCOE: RTCC Output Enable bit
1 = RTCC clock output enabled
0 = RTCC clock output disabled
bit 1-0 RTCPTR<1:0>: RTCC Value Register Window Pointer bits
Points to the corresponding RTCC Value registers when reading the RTCVALH and RTCVALL registers.
The RTCPTR<1:0> value decrements on every read or write of RTCVALH until it reaches ‘00’.
RTCVAL<15:8>:
00 = Minutes
01 = Weekday
10 = Month
11 = Reserved
RTCVAL<7:0>:
00 = Seconds
01 = Hours
10 = Day
11 = Year

Note 1: The RTCCFG register is only affected by a POR.

2: A write to the RTCEN bit is only allowed when RTCWREN = 1.
3: This bit is read-only. It is cleared to ‘0’ on a write to the lower half of the MINSEC register.

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REGISTER 17-2: RTCCAL: RTCC CALIBRATION REGISTER (BANKED F3Eh)

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

CAL7 CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-0 CAL<7:0>: RTCC Drift Calibration bits

01111111 = Maximum positive adjustment; adds 508 RTC clock pulses every minute
.
.
.
00000001 = Minimum positive adjustment; adds four RTCC clock pulses every minute
00000000 = No adjustment
11111111 = Minimum negative adjustment; subtracts four RTCC clock pulses every minute
.
.
.
10000000 = Maximum negative adjustment; subtracts 512 RTCC clock pulses every minute

REGISTER 17-3: PADCFG1: PAD CONFIGURATION REGISTER (BANKED F3Ch)

U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0
— — — — — RTSECSEL1(1) RTSECSEL0(1) PMPTTL(2)
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-3 Unimplemented: Read as ‘0’

bit 2-1 RTSECSEL<1:0>: RTCC Seconds Clock Output Select bits(1)
11 = Reserved; do not use
10 = RTCC source clock is selected for the RTCC pin (pin can be INTRC or T1OSC, depending on the
RTCOSC (CONFIG3L<1>) setting)
01 = RTCC seconds clock is selected for the RTCC pin
00 = RTCC alarm pulse is selected for the RTCC pin
bit 0 PMPTTL: PMP Module TTL Input Buffer Select bit(2)
1 = PMP module uses TTL input buffers
0 = PMP module uses Schmitt input buffers

Note 1: To enable the actual RTCC output, the RTCOE (RTCCFG<2>) bit must be set.
2: Available only on 44-pin devices (PIC18F46J53, PIC18F47J53, PIC18LF46J53 and PIC18LF47J53). For
28-pin devices, the bit is U-0.

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REGISTER 17-4: ALRMCFG: ALARM CONFIGURATION REGISTER (ACCESS F47h)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
ALRMEN CHIME AMASK3 AMASK2 AMASK1 AMASK0 ALRMPTR1 ALRMPTR0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 ALRMEN: Alarm Enable bit

1 = Alarm is enabled (cleared automatically after an alarm event whenever ARPT<7:0> = 0000 0000
and CHIME = 0)
0 = Alarm is disabled
bit 6 CHIME: Chime Enable bit
1 = Chime is enabled; ARPT<7:0> bits are allowed to roll over from 00h to FFh
0 = Chime is disabled; ARPT<7:0> bits stop once they reach 00h
bit 5-2 AMASK<3:0>: Alarm Mask Configuration bits
0000 = Every half second
0001 = Every second
0010 = Every 10 seconds
0011 = Every minute
0100 = Every 10 minutes
0101 = Every hour
0110 = Once a day
0111 = Once a week
1000 = Once a month
1001 = Once a year (except when configured for February 29th, once every four years)
101x = Reserved – do not use
11xx = Reserved – do not use
bit 1-0 ALRMPTR<1:0>: Alarm Value Register Window Pointer bits
Points to the corresponding Alarm Value registers when reading the ALRMVALH and ALRMVALL
registers. The ALRMPTR<1:0> value decrements on every read or write of ALRMVALH until it reaches
‘00’.
ALRMVAL<15:8>:
00 = ALRMMIN
01 = ALRMWD
10 = ALRMMNTH
11 = Unimplemented
ALRMVAL<7:0>:
00 = ALRMSEC
01 = ALRMHR
10 = ALRMDAY
11 = Unimplemented

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REGISTER 17-5: ALRMRPT: ALARM REPEAT COUNTER (ACCESS F46h)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
ARPT7 ARPT6 ARPT5 ARPT4 ARPT3 ARPT2 ARPT1 ARPT0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-0 ARPT<7:0>: Alarm Repeat Counter Value bits

11111111 = Alarm will repeat 255 more times
.
.
.
00000000 = Alarm will not repeat
The counter decrements on any alarm event. The counter is prevented from rolling over from 00h to
FFh unless CHIME = 1.

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17.1.2 RTCVALH AND RTCVALL
REGISTER MAPPINGS

REGISTER 17-6: RESERVED REGISTER

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-0 Unimplemented: Read as ‘0’

REGISTER 17-7: YEAR: YEAR VALUE REGISTER(1)

R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
YRTEN3 YRTEN2 YRTEN1 YRTEN0 YRONE3 YRONE2 YRONE1 YRONE0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-4 YRTEN<3:0>: Binary Coded Decimal Value of Year’s Tens Digit bits
Contains a value from 0 to 9.
bit 3-0 YRONE<3:0>: Binary Coded Decimal Value of Year’s Ones Digit bits
Contains a value from 0 to 9.

Note 1: A write to the YEAR register is only allowed when RTCWREN = 1.

REGISTER 17-8: MONTH: MONTH VALUE REGISTER(1)

U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x
— — — MTHTEN0 MTHONE3 MTHONE2 MTHONE1 MTHONE0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-5 Unimplemented: Read as ‘0’

bit 4 MTHTEN0: Binary Coded Decimal Value of Month’s Tens Digit bit
Contains a value of 0 or 1.
bit 3-0 MTHONE<3:0>: Binary Coded Decimal Value of Month’s Ones Digit bits
Contains a value from 0 to 9.

Note 1: A write to this register is only allowed when RTCWREN = 1.

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REGISTER 17-9: DAY: DAY VALUE REGISTER(1)
U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
— — DAYTEN1 DAYTEN0 DAYONE3 DAYONE2 DAYONE1 DAYONE0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-6 Unimplemented: Read as ‘0’

bit 5-4 DAYTEN<1:0>: Binary Coded Decimal value of Day’s Tens Digit bits
Contains a value from 0 to 3.
bit 3-0 DAYONE<3:0>: Binary Coded Decimal Value of Day’s Ones Digit bits
Contains a value from 0 to 9.

Note 1: A write to this register is only allowed when RTCWREN = 1.

REGISTER 17-10: WKDY: WEEKDAY VALUE REGISTER(1)

U-0 U-0 U-0 U-0 U-0 R/W-x R/W-x R/W-x
— — — — — WDAY2 WDAY1 WDAY0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-3 Unimplemented: Read as ‘0’

bit 2-0 WDAY<2:0>: Binary Coded Decimal Value of Weekday Digit bits
Contains a value from 0 to 6.

Note 1: A write to this register is only allowed when RTCWREN = 1.

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REGISTER 17-11: HOURS: HOURS VALUE REGISTER(1)
U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
— — HRTEN1 HRTEN0 HRONE3 HRONE2 HRONE1 HRONE0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-6 Unimplemented: Read as ‘0’

bit 5-4 HRTEN<1:0>: Binary Coded Decimal Value of Hour’s Tens Digit bits
Contains a value from 0 to 2.
bit 3-0 HRONE<3:0>: Binary Coded Decimal Value of Hour’s Ones Digit bits
Contains a value from 0 to 9.

Note 1: A write to this register is only allowed when RTCWREN = 1.

REGISTER 17-12: MINUTES: MINUTES VALUE REGISTER

U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
— MINTEN2 MINTEN1 MINTEN0 MINONE3 MINONE2 MINONE1 MINONE0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 Unimplemented: Read as ‘0’

bit 6-4 MINTEN<2:0>: Binary Coded Decimal Value of Minute’s Tens Digit bits
Contains a value from 0 to 5.
bit 3-0 MINONE<3:0>: Binary Coded Decimal Value of Minute’s Ones Digit bits
Contains a value from 0 to 9.

REGISTER 17-13: SECONDS: SECONDS VALUE REGISTER

U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
— SECTEN2 SECTEN1 SECTEN0 SECONE3 SECONE2 SECONE1 SECONE0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 Unimplemented: Read as ‘0’

bit 6-4 SECTEN<2:0>: Binary Coded Decimal Value of Second’s Tens Digit bits
Contains a value from 0 to 5.
bit 3-0 SECONE<3:0>: Binary Coded Decimal Value of Second’s Ones Digit bits
Contains a value from 0 to 9.

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17.1.3 ALRMVALH AND ALRMVALL
REGISTER MAPPINGS

REGISTER 17-14: ALRMMNTH: ALARM MONTH VALUE REGISTER(1)

U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x
— — — MTHTEN0 MTHONE3 MTHONE2 MTHONE1 MTHONE0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-5 Unimplemented: Read as ‘0’

bit 4 MTHTEN0: Binary Coded Decimal Value of Month’s Tens Digit bit
Contains a value of 0 or 1.
bit 3-0 MTHONE<3:0>: Binary Coded Decimal Value of Month’s Ones Digit bits
Contains a value from 0 to 9.

Note 1: A write to this register is only allowed when RTCWREN = 1.

REGISTER 17-15: ALRMDAY: ALARM DAY VALUE REGISTER(1)

U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
— — DAYTEN1 DAYTEN0 DAYONE3 DAYONE2 DAYONE1 DAYONE0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-6 Unimplemented: Read as ‘0’

bit 5-4 DAYTEN<1:0>: Binary Coded Decimal Value of Day’s Tens Digit bits
Contains a value from 0 to 3.
bit 3-0 DAYONE<3:0>: Binary Coded Decimal Value of Day’s Ones Digit bits
Contains a value from 0 to 9.

Note 1: A write to this register is only allowed when RTCWREN = 1.

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REGISTER 17-16: ALRMWD: ALARM WEEKDAY VALUE REGISTER(1)
U-0 U-0 U-0 U-0 U-0 R/W-x R/W-x R/W-x
— — — — — WDAY2 WDAY1 WDAY0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-3 Unimplemented: Read as ‘0’

bit 2-0 WDAY<2:0>: Binary Coded Decimal Value of Weekday Digit bits
Contains a value from 0 to 6.

Note 1: A write to this register is only allowed when RTCWREN = 1.

REGISTER 17-17: ALRMHR: ALARM HOURS VALUE REGISTER(1)

U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
— — HRTEN1 HRTEN0 HRONE3 HRONE2 HRONE1 HRONE0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-6 Unimplemented: Read as ‘0’

bit 5-4 HRTEN<1:0>: Binary Coded Decimal Value of Hour’s Tens Digit bits
Contains a value from 0 to 2.
bit 3-0 HRONE<3:0>: Binary Coded Decimal Value of Hour’s Ones Digit bits
Contains a value from 0 to 9.

Note 1: A write to this register is only allowed when RTCWREN = 1.

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REGISTER 17-18: ALRMMIN: ALARM MINUTES VALUE REGISTER
U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
— MINTEN2 MINTEN1 MINTEN0 MINONE3 MINONE2 MINONE1 MINONE0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 Unimplemented: Read as ‘0’

bit 6-4 MINTEN<2:0>: Binary Coded Decimal Value of Minute’s Tens Digit bits
Contains a value from 0 to 5.
bit 3-0 MINONE<3:0>: Binary Coded Decimal Value of Minute’s Ones Digit bits
Contains a value from 0 to 9.

REGISTER 17-19: ALRMSEC: ALARM SECONDS VALUE REGISTER

U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
— SECTEN2 SECTEN1 SECTEN0 SECONE3 SECONE2 SECONE1 SECONE0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 Unimplemented: Read as ‘0’

bit 6-4 SECTEN<2:0>: Binary Coded Decimal Value of Second’s Tens Digit bits
Contains a value from 0 to 5.
bit 3-0 SECONE<3:0>: Binary Coded Decimal Value of Second’s Ones Digit bits
Contains a value from 0 to 9.

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17.1.4 RTCEN BIT WRITE 17.2 Operation
An attempt to write to the RTCEN bit while
RTCWREN = 0 will be ignored. RTCWREN must be 17.2.1 REGISTER INTERFACE
set before a write to RTCEN can take place. The register interface for the RTCC and alarm values is
Like the RTCEN bit, the RTCVALH and RTCVALL implemented using the Binary Coded Decimal (BCD)
registers can only be written to when RTCWREN = 1. format. This simplifies the firmware when using the
A write to these registers, while RTCWREN = 0, will be module, as each of the digits is contained within its own
ignored. 4-bit value (see Figure 17-2 and Figure 17-3).

FIGURE 17-2: TIMER DIGIT FORMAT

Year Month Day Day Of Week

0-9 0-9 0-1 0-9 0-3 0-9 0-6

Hours 1/2 Second Bit

(24-hour format) Minutes Seconds (binary format)

0-2 0-9 0-5 0-9 0-5 0-9 0/1

FIGURE 17-3: ALARM DIGIT FORMAT

Month Day Day Of Week

0-1 0-9 0-3 0-9 0-6

Hours
(24-hour format) Minutes Seconds

0-2 0-9 0-5 0-9 0-5 0-9

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17.2.2 CLOCK SOURCE Calibration of the crystal can be done through this
module to yield an error of 3 seconds or less per month.
As mentioned earlier, the RTCC module is intended to
(For further details, see Section 17.2.9 “Calibration”.)
be clocked by an external Real-Time Clock (RTC)
crystal oscillating at 32.768 kHz, but can also be
clocked by the INTRC. The RTCC clock selection is
decided by the RTCOSC bit (CONFIG3L<1>).

FIGURE 17-4: CLOCK SOURCE MULTIPLEXING

32.768 kHz XTAL

Half-Second
from T1OSC 1:16384 Clock One-Second Clock
Half Second(1)
Clock Prescaler(1)
Internal RC

CONFIG 3L<1>

Day
Second Hour:Minute Month Year
Day of Week

Note 1: Writing to the lower half of the MINSEC register resets all counters, allowing fraction of a second synchronization.
The clock prescaler is held in Reset when RTCEN = 0.

17.2.2.1 Real-Time Clock Enable For the day to month rollover schedule, see Table 17-2.
The RTCC module can be clocked by an external, Considering that the following values are in BCD
32.768 kHz crystal (Timer1 oscillator or T1CKI input) or format, the carry to the upper BCD digit will occur at a
the INTRC oscillator, which can be selected in count of 10 and not at 16 (SECONDS, MINUTES,
CONFIG3L<1>. HOURS, WEEKDAY, DAYS and MONTHS).
If the Timer1 oscillator will be used as the clock source
for the RTCC, make sure to enable it by setting TABLE 17-1: DAY OF WEEK SCHEDULE
T1CON<3> (T1OSCEN). The selected RTC clock can Day of Week
be brought out to the RTCC pin by the
RTSECSEL<1:0> bits in the PADCFG register. Sunday 0
Monday 1
17.2.3 DIGIT CARRY RULES Tuesday 2
This section explains which timer values are affected Wednesday 3
when there is a rollover.
Thursday 4
• Time of Day: From 23:59:59 to 00:00:00 with a
Friday 5
carry to the Day field
Saturday 6
• Month: From 12/31 to 01/01 with a carry to the
Year field
• Day of Week: From 6 to 0 with no carry (see
Table 17-1)
• Year Carry: From 99 to 00; this also surpasses the
use of the RTCC

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TABLE 17-2: DAY TO MONTH ROLLOVER 17.2.6 SAFETY WINDOW FOR REGISTER
SCHEDULE READS AND WRITES
Month Maximum Day Field The RTCSYNC bit indicates a time window during
which the RTCC Clock Domain registers can be safely
01 (January) 31 read and written without concern about a rollover.
02 (February) 28 or 29(1) When RTCSYNC = 0, the registers can be safely
03 (March) 31 accessed by the CPU.
04 (April) 30 Whether RTCSYNC = 1 or 0, the user should employ a
05 (May) 31 firmware solution to ensure that the data read did not
fall on a rollover boundary, resulting in an invalid or
06 (June) 30 partial read. This firmware solution would consist of
07 (July) 31 reading each register twice and then comparing the two
08 (August) 31 values. If the two values matched, then, a rollover did
not occur.
09 (September) 30
10 (October) 31 17.2.7 WRITE LOCK
11 (November) 30 In order to perform a write to any of the RTCC Timer
12 (December) 31 registers, the RTCWREN bit (RTCCFG<5>) must be
Note 1: See Section 17.2.4 “Leap Year”. set.
To avoid accidental writes to the RTCC Timer register,
17.2.4 LEAP YEAR it is recommended that the RTCWREN bit
Since the year range on the RTCC module is 2000 to (RTCCFG<5>) be kept clear at any time other than
2099, the leap year calculation is determined by any while writing to it. For the RTCWREN bit to be set, there
year divisible by ‘4’ in the above range. Only February is only one instruction cycle time window allowed
is effected in a leap year. between the 55h/AA sequence and the setting of
RTCWREN. For that reason, it is recommended that
February will have 29 days in a leap year and 28 days in users follow the code example in Example 17-1.
any other year.

17.2.5 GENERAL FUNCTIONALITY EXAMPLE 17-1: SETTING THE RTCWREN

BIT
All Timer registers containing a time value of seconds or
movlb 0x0F ;RTCCFG is banked
greater are writable. The user configures the time by
bcf INTCON, GIE ;Disable interrupts
writing the required year, month, day, hour, minutes and movlw 0x55
seconds to the Timer registers, via register pointers (see movwf EECON2
Section 17.2.8 “Register Mapping”). movlw 0xAA
The timer uses the newly written values and proceeds movwf EECON2
with the count from the required starting point. bsf RTCCFG,RTCWREN

The RTCC is enabled by setting the RTCEN bit

(RTCCFG<7>). If enabled, while adjusting these 17.2.8 REGISTER MAPPING
registers, the timer still continues to increment. However, To limit the register interface, the RTCC Timer and
any time the MINSEC register is written to, both of the Alarm Timer registers are accessed through
timer prescalers are reset to ‘0’. This allows fraction of a corresponding register pointers. The RTCC Value reg-
second synchronization. ister window (RTCVALH<15:8> and RTCVALL<7:0>)
The Timer registers are updated in the same cycle as uses the RTCPTR bits (RTCCFG<1:0>) to select the
the write instruction’s execution by the CPU. The user required Timer register pair.
must ensure that when RTCEN = 1, the updated By reading or writing to the RTCVALH register, the
registers will not be incremented at the same time. This RTCC Pointer value (RTCPTR<1:0>) decrements by 1
can be accomplished in several ways: until it reaches ‘00’. Once it reaches ‘00’, the MINUTES
• By checking the RTCSYNC bit (RTCCFG<4>) and SECONDS value will be accessible through
• By checking the preceding digits from which a RTCVALH and RTCVALL until the pointer value is
carry can occur manually changed.
• By updating the registers immediately following
the seconds pulse (or alarm interrupt)
The user has visibility to the half-second field of the
counter. This value is read-only and can be reset only
by writing to the lower half of the SECONDS register.

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TABLE 17-3: RTCVALH AND RTCVALL To calibrate the RTCC module:
REGISTER MAPPING 1. Use another timer resource on the device to find
RTCC Value Register Window the error of the 32.768 kHz crystal.
RTCPTR<1:0> 2. Convert the number of error clock pulses per
RTCVAL<15:8> RTCVAL<7:0> minute (see Equation 17-1).
00 MINUTES SECONDS
01 WEEKDAY HOURS EQUATION 17-1: CONVERTING ERROR
CLOCK PULSES
10 MONTH DAY
11 — YEAR (Ideal Frequency (32,768) – Measured Frequency) *
60 = Error Clocks per Minute
The Alarm Value register window (ALRMVALH and
ALRMVALL) uses the ALRMPTR bits (ALRMCFG<1:0>)
to select the desired Alarm register pair. • If the oscillator is faster than ideal (negative
result from step 2), the RTCCFG register value
By reading or writing to the ALRMVALH register, the needs to be negative. This causes the specified
Alarm Pointer value, ALRMPTR<1:0>, decrements number of clock pulses to be subtracted from
by 1 until it reaches ‘00’. Once it reaches ‘00’, the the timer counter, once every minute.
ALRMMIN and ALRMSEC value will be accessible
• If the oscillator is slower than ideal (positive
through ALRMVALH and ALRMVALL until the pointer
result from step 2), the RTCCFG register value
value is manually changed.
needs to be positive. This causes the specified
number of clock pulses to be added to the timer
TABLE 17-4: ALRMVAL REGISTER
counter, once every minute.
MAPPING
3. Load the RTCCAL register with the correct
Alarm Value Register Window value.
ALRMPTR<1:0>
ALRMVAL<15:8> ALRMVAL<7:0> Writes to the RTCCAL register should occur only when
the timer is turned off, or immediately after the rising
00 ALRMMIN ALRMSEC edge of the seconds pulse.
01 ALRMWD ALRMHR
Note: In determining the crystal’s error value, it
10 ALRMMNTH ALRMDAY is the user’s responsibility to include the
11 — — crystal’s initial error from drift due to
temperature or crystal aging.
17.2.9 CALIBRATION
The real-time crystal input can be calibrated using the
periodic auto-adjust feature. When properly calibrated,
the RTCC can provide an error of less than three
seconds per month.
To perform this calibration, find the number of error
clock pulses and store the value in the lower half of the
RTCCAL register. The 8-bit, signed value, loaded into
RTCCAL, is multiplied by four and will either be added
or subtracted from the RTCC timer, once every minute.

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17.3 Alarm The alarm can also be configured to repeat based on a
preconfigured interval. The number of times this
The alarm features and characteristics are: occurs, after the alarm is enabled, is stored in the
• Configurable from half a second to one year ALRMRPT register.
• Enabled using the ALRMEN bit (ALRMCFG<7>,
Note: While the alarm is enabled (ALRMEN = 1),
Register 17-4)
changing any of the registers, other than
• Offers one-time and repeat alarm options the RTCCAL, ALRMCFG and ALRMRPT
registers, and the CHIME bit, can result in
17.3.1 CONFIGURING THE ALARM a false alarm event leading to a false
The alarm feature is enabled using the ALRMEN bit. alarm interrupt. To avoid this, only change
the timer and alarm values while the alarm
This bit is cleared when an alarm is issued. The bit will is disabled (ALRMEN = 0). It is recom-
not be cleared if the CHIME bit = 1 or if ALRMRPT  0. mended that the ALRMCFG and
The interval selection of the alarm is configured ALRMRPT registers and CHIME bit be
through the ALRMCFG bits (AMASK<3:0>). (See changed when RTCSYNC = 0.
Figure 17-5.) These bits determine which and how
many digits of the alarm must match the clock value for
the alarm to occur.

FIGURE 17-5: ALARM MASK SETTINGS

Alarm Mask Setting Day of the
AMASK<3:0> Week Month Day Hours Minutes Seconds
0000 – Every half second
0001 – Every second

0010 – Every 10 seconds s

0011 – Every minute s s

0100 – Every 10 minutes m s s

0101 – Every hour m m s s

0110 – Every day h h m m s s

0111 – Every week d h h m m s s

1000 – Every month d d h h m m s s

1001 – Every year(1) m m d d h h m m s s

Note 1: Annually, except when configured for February 29.

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When ALRMCFG = 00 and the CHIME bit = 0 17.3.2 ALARM INTERRUPT
(ALRMCFG<6>), the repeat function is disabled and
At every alarm event, an interrupt is generated. Addi-
only a single alarm will occur. The alarm can be
tionally, an alarm pulse output is provided that operates
repeated up to 255 times by loading the ALRMRPT
at half the frequency of the alarm.
register with FFh.
The alarm pulse output is completely synchronous with
After each alarm is issued, the ALRMRPT register is
the RTCC clock and can be used as a trigger clock to
decremented by one. Once the register has reached
other peripherals. This output is available on the RTCC
‘00’, the alarm will be issued one last time.
pin. The output pulse is a clock with a 50% duty cycle
After the alarm is issued a last time, the ALRMEN bit is and a frequency half that of the alarm event (see
cleared automatically and the alarm turned off. Indefinite Figure 17-6).
repetition of the alarm can occur if the CHIME bit = 1.
The RTCC pin can also output the seconds clock. The
When CHIME = 1, the alarm is not disabled when the user can select between the alarm pulse, generated by
ALRMRPT register reaches ‘00’, but it rolls over to FF the RTCC module, or the seconds clock output.
and continues counting indefinitely.
The RTSECSEL (PADCFG1<2:1>) bits select between
these two outputs:
• Alarm pulse – RTSECSEL<2:1> = 00
• Seconds clock – RTSECSEL<2:1> = 01

FIGURE 17-6: TIMER PULSE GENERATION

RTCEN bit

ALRMEN bit

RTCC Alarm Event

RTCC Pin

17.4 Low-Power Modes 17.5.2 POWER-ON RESET (POR)

The timer and alarm can optionally continue to operate The RTCCFG and ALRMRPT registers are reset only
while in Sleep, Idle and even Deep Sleep mode. An on a POR. Once the device exits the POR state, the
alarm event can be used to wake-up the microcontroller clock registers should be reloaded with the desired
from any of these Low-Power modes. values.
The timer prescaler values can be reset only by writing
17.5 Reset to the SECONDS register. No device Reset can affect
the prescalers.
17.5.1 DEVICE RESET
When a device Reset occurs, the ALCFGRPT register
is forced to its Reset state, causing the alarm to be dis-
abled (if enabled prior to the Reset). If the RTCC was
enabled, it will continue to operate when a basic device
Reset occurs.

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17.6 Register Maps
Table 17-5, Table 17-6 and Table 17-7 summarize the
registers associated with the RTCC module.

TABLE 17-5: RTCC CONTROL REGISTERS

All
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Resets

RTCCFG RTCEN — RTCWREN RTCSYNC HALFSEC RTCOE RTCPTR1 RTCPTR0 0000

RTCCAL CAL7 CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 0000
PADCFG1 — — — — — RTSECSEL1 RTSECSEL0 PMPTTL 0000
ALRMCFG ALRMEN CHIME AMASK3 AMASK2 AMASK1 AMASK0 ALRMPTR1 ALRMPTR0 0000
ALRMRPT ARPT7 ARPT6 ARPT5 ARPT4 ARPT3 ARPT2 ARPT1 ARPT0 0000
PIR3 SSP2IF BCL2IF RC2IF TX2IF TMR4IF CTMUIF TMR3GIF RTCCCIF 0000
PIE3 SSP2IE BCL2IE RC2IE TX2IE TMR4IE CTMUIE TMR3GIE RTCCCIE 0000
IPR3 SSP2IP BCL2IP RC2IP TX2IP TMR4IP CTMUIP TMR3GIP RTCCCIP 0000
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for 44-pin devices.

TABLE 17-6: RTCC VALUE REGISTERS

File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets

RTCVALH RTCC Value Register Window High Byte, Based on RTCPTR<1:0> xxxx
RTCVALL RTCC Value Register Window Low Byte, Based on RTCPTR<1:0> xxxx
RTCCFG RTCEN — RTCWREN RTCSYNC HALFSEC RTCOE RTCPTR1 RTCPTR0 0000
ALRMCFG ALRMEN CHIME AMASK3 AMASK2 AMASK1 AMASK0 ALRMPTR1 ALRMPTR0 0000
ALRMVALH Alarm Value Register Window High Byte, Based on ALRMPTR<1:0> xxxx
ALRMVALL Alarm Value Register Window Low Byte, Based on ALRMPTR<1:0> xxxx
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for 44-pin devices.

TABLE 17-7: ALARM VALUE REGISTERS

All
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Resets

ALRMRPT ARPT7 ARPT6 ARPT5 ARPT4 ARPT3 ARPT2 ARPT1 ARPT0 0000
ALRMVALH Alarm Value Register Window High Byte, Based on ALRMPTR<1:0> xxxx
ALRMVALL Alarm Value Register Window Low Byte, Based on ALRMPTR<1:0> xxxx
RTCCAL CAL7 CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 0000
RTCVALH RTCC Value Register Window High Byte, Based on RTCPTR<1:0> xxxx
RTCVALL RTCC Value Register Window Low Byte, Based on RTCPTR<1:0> xxxx
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for 44-pin devices.

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NOTES:

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18.0 CAPTURE/COMPARE/PWM Each CCP module contains a 16-bit register that can
operate as a 16-bit Capture register, a 16-bit Compare
(CCP) MODULES
register or a PWM Master/Slave Duty Cycle register.
PIC18F47J53 family devices have seven CCP For the sake of clarity, all CCP module operation in the
(Capture/Compare/PWM) modules, designated CCP4 following sections is described with respect to CCP4,
through CCP10. All the modules implement standard but is equally applicable to CCP5 through CCP10.
Capture, Compare and Pulse-Width Modulation (PWM)
modes.
Note: Throughout this section, generic references
are used for register and bit names that are
the same – except for an ‘x’ variable that
indicates the item’s association with the
specific CCP module. For example, the con-
trol register is named CCPxCON and refers
to CCP4CON through CCP10CON.

REGISTER 18-1: CCPxCON: CCP4-10 CONTROL REGISTER (4, BANKED F12h; 5, F0Fh; 6, F0Ch;
7, F09h; 8, F06h; 9, F03h; 10, F00h)
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — DCxB1 DCxB0 CCPxM3 CCPxM2 CCPxM1 CCPxM0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-6 Unimplemented: Read as ‘0’

bit 5-4 DCxB<1:0>: PWM Duty Cycle bit 1 and bit 0 for CCPx Module
Capture mode:
Unused.
Compare mode:
Unused.
PWM mode:
These bits are the two Least Significant bits (bit 1 and bit 0) of the 10-bit PWM duty cycle. The eight Most
Significant bits (DCxB<9:2>) of the duty cycle are found in CCPRxL.
bit 3-0 CCPxM<3:0>: CCPx Module Mode Select bits
0000 = Capture/Compare/PWM disabled (resets CCPx module)
0001 = Reserved
0010 = Compare mode, toggle output on match (CCPxIF bit is set)
0011 = Reserved
0100 = Capture mode: every falling edge
0101 = Capture mode: every rising edge
0110 = Capture mode: every 4th rising edge
0111 = Capture mode: every 16th rising edge
1000 = Compare mode: initialize CCPx pin low; on compare match, force CCPx pin high (CCPxIF bit is set)
1001 = Compare mode: initialize CCPx pin high; on compare match, force CCPx pin low (CCPxIF bit is set)
1010 = Compare mode: generate software interrupt on compare match (CCPxIF bit is set, CCPx pin
reflects I/O state)
1011 = Compare mode: Special Event Trigger; reset timer on CCPx match (CCPxIF bit is set)
11xx = PWM mode
Note 1: CCPxM<3:0> = 1011 will only reset timer and not start A/D conversion on CCPx match.

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REGISTER 18-2: CCPTMRS1: CCP4-10 TIMER SELECT 1 REGISTER (BANKED F51h)
R/W-0 R/W-0 U-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0
C7TSEL1 C7TSEL0 — C6TSEL0 — C5TSEL0 C4TSEL1 C4TSEL0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-6 C7TSEL<1:0>: CCP7 Timer Selection bit

00 = CCP7 is based off of TMR1/TMR2
01 = CCP7 is based off of TMR5/TMR4
10 = CCP7 is based off of TMR5/TMR6
11 = CCP7 is based off of TMR5/TMR8
bit 5 Unimplemented: Read as ‘0’
bit 4 C6TSEL0: CCP6 Timer Selection bit
0 = CCP6 is based off of TMR1/TMR2
1 = CCP6 is based off of TMR5/TMR2
bit 3 Unimplemented: Read as ‘0’
bit 2 C5TSEL0: CCP5 Timer Selection bit
0 = CCP5 is based off of TMR1/TMR2
1 = CCP5 is based off of TMR5/TMR4
bit 1-0 C4TSEL<1:0>: CCP4 Timer Selection bits
00 = CCP4 is based off of TMR1/TMR2
01 = CCP4 is based off of TMR3/TMR4
10 = CCP4 is based off of TMR3/TMR6
11 = Reserved; do not use

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REGISTER 18-3: CCPTMRS2: CCP4-10 TIMER SELECT 2 REGISTER (BANKED F50h)
U-0 U-0 U-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0
— — — C10TSEL0 — C9TSEL0 C8TSEL1 C8TSEL0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-5 Unimplemented: Read as ‘0’

bit 4 C10TSEL0: CCP10 Timer Selection bit
0 = CCP10 is based off of TMR1/TMR2
1 = Reserved; do not use
bit 3 Unimplemented: Read as ‘0’
bit 2 C9TSEL0: CCP9 Timer Selection bit
0 = CCP9 is based off of TMR1/TMR2
1 = CCP9 is based off of TMR1/TMR4
bit 1-0 C8TSEL<1:0>: CCP8 Timer Selection bits
00 = CCP8 is based off of TMR1/TMR2
01 = CCP8 is based off of TMR1/TMR4
10 = CCP8 is based off of TMR1/TMR6
11 = Reserved; do not use

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REGISTER 18-4: CCPRxL: CCP4-10 PERIOD LOW BYTE REGISTER (4, BANKED F13h; 5, F10h; 6,
F0Dh; 7, F0Ah; 8, F07h; 9, F04h; 10, F01h)
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
CCPRxL7 CCPRxL6 CCPRxL5 CCPRxL4 CCPRxL3 CCPRxL2 CCPRxL1 CCPRxL0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-0 CCPRxL<7:0>: CCPx Period Register Low Byte bits

Capture Mode: Capture register low byte
Compare Mode: Compare register low byte
PWM Mode: PWM Period register low byte

REGISTER 18-5: CCPRxH: CCP4-10 PERIOD HIGH BYTE REGISTER (4, BANKED F14h; 5, F11h; 6,
F0Eh; 7, F0Bh; 8, F08h; 9, F05h; 10, F02h)
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
CCPRxH7 CCPRxH6 CCPRxH5 CCPRxH4 CCPRxH3 CCPRxH2 CCPRxH1 CCPRxH0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-0 CCPRxH<7:0>: CCPx Period Register High Byte bits

Capture Mode: Capture register high byte
Compare Mode: Compare register high byte
PWM Mode: PWM Period register high byte

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18.1 CCP Module Configuration TABLE 18-1: CCP MODE – TIMER
RESOURCE
Each Capture/Compare/PWM module is associated
with a control register (generically, CCPxCON) and a CCP Mode Timer Resource
data register (CCPRx). The data register, in turn, is
Capture
comprised of two eight-bit registers: CCPRxL (low Timer1, Timer3 or Timer 5
byte) and CCPRxH (high byte). All registers are both Compare
readable and writable. PWM Timer2, Timer4, Timer 6 or Timer8
18.1.1 CCP MODULES AND TIMER The assignment of a particular timer to a module is
RESOURCES determined by the Timer to CCP enable bits in the
The CCP modules utilize Timers 1 through 8, varying CCPTMRSx registers. (See Register 18-2 and
with the selected mode. Various timers are available to Register 18-3.) All of the modules may be active at
the CCP modules in Capture, Compare or PWM once and may share the same timer resource if they
modes, as shown in Table 18-1. are configured to operate in the same mode
(Capture/Compare or PWM), at the same time.
The CCPTMRS1 register selects the timers for CCP
modules, 7, 6, 5 and 4, and the CCPTMRS2 register
selects the timers for CCP modules, 10, 9 and 8. The
possible configurations are shown in Table 18-2 and
Table 18-3.

TABLE 18-2: TIMER ASSIGNMENTS FOR CCP MODULES 4, 5, 6 AND 7

CCPTMRS1 Register

CCP4 CCP5 CCP6 CCP7

Capture/ Capture/ Capture/ Capture/

C4TSEL PWM PWM PWM C7TSEL PWM
Compare C5TSEL0 Compare C6TSEL0 Compare Compare
<1:0> Mode Mode Mode <1:0> Mode
Mode Mode Mode Mode
0 0 TMR1 TMR2 0 TMR1 TMR2 0 TMR1 TMR2 0 0 TMR1 TMR2
0 1 TMR3 TMR4 1 TMR5 TMR4 1 TMR5 TMR2 0 1 TMR5 TMR4
1 0 TMR3 TMR6 1 0 TMR5 TMR6
1 1 Reserved(1) 1 1 TMR5 TMR8
Note 1: Do not use the reserved bit configuration.

TABLE 18-3: TIMER ASSIGNMENTS FOR CCP MODULES 8, 9 AND 10

CCPTMRS2 Register

CCP8
CCP8 CCP9 CCP10
Devices with 64 Kbyte

Capture/ Capture/ Capture/ Capture/

C8TSEL PWM C8TSEL PWM PWM PWM
Compare Compare C9TSEL0 Compare C10TSEL0 Compare
<1:0> Mode <1:0> Mode Mode Mode
Mode Mode Mode Mode
0 0 TMR1 TMR2 0 0 TMR1 TMR2 0 TMR1 TMR2 0 TMR1 TMR2
0 1 TMR1 TMR4 0 1 TMR1 TMR4 1 TMR1 TMR4 1 Reserved(1)
1 0 TMR1 TMR6 1 0 TMR1 TMR6
(1)
1 1 Reserved 1 1 Reserved(1)
Note 1: Do not use the reserved bit configuration.

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18.1.2 OPEN-DRAIN OUTPUT OPTION The event is selected by the mode select bits,
CCP4M<3:0> (CCP4CON<3:0>). When a capture is
When operating in Output mode (the Compare or PWM
made, the interrupt request flag bit, CCP4IF (PIR4<1>),
modes), the drivers for the CCPx pins can be optionally
is set. (It must be cleared in software.) If another
configured as open-drain outputs. This feature allows
capture occurs before the value in register, CCPR4, is
the voltage level on the pin to be pulled to a higher level
read, the old captured value is overwritten by the new
through an external pull-up resistor and allows the out-
captured value.
put to communicate with external circuits without the
need for additional level shifters. Figure 18-1 shows the Capture mode block diagram.
The open-drain output option is controlled by the
18.2.1 CCP PIN CONFIGURATION
CCPxOD bits (ODCON1<7:0> and ODCON2<3:2>).
Setting the appropriate bit configures the pin for the In Capture mode, the appropriate CCPx pin should be
corresponding module for open-drain operation. configured as an input by setting the corresponding
TRIS direction bit.
18.2 Capture Mode Note: If RB4 is configured as a CCP4 output, a
write to the port causes a capture condition.
In Capture mode, the CCPR4H:CCPR4L register pair
captures the 16-bit value of the TMR1 or TMR3 register
when an event occurs on the CCP4 pin, RB4. An event 18.2.2 TIMER1/3/5 MODE SELECTION
is defined as one of the following: For the available timers (1/3/5) to be used for the capture
• Every falling edge feature, the used timers must be running in Timer mode
or Synchronized Counter mode. In Asynchronous
• Every rising edge
Counter mode, the capture operation may not work.
• Every 4th rising edge
The timer to be used with each CCP module is selected
• Every 16th rising edge
in the CCPTMRSx registers. (See Section 18.1.1 “CCP
Modules and Timer Resources”.)
Details of the timer assignments for the CCP modules
are given in Table 18-2 and Table 18-3.

FIGURE 18-1: CAPTURE MODE OPERATION BLOCK DIAGRAM

TMR5H TMR5L
Set CCP5IF
C5TSEL0 TMR5
CCP5 Pin Enable
Prescaler and CCPR5H CCPR5L
 1, 4, 16 Edge Detect
TMR1
C5TSEL0 Enable

4 TMR1H TMR1L
CCP5CON<3:0> Set CCP4IF
4
Q1:Q4
4
CCP4CON<3:0>
C4TSEL1 TMR3H TMR3L
C4TSEL0
TMR3
Enable
CCP4 Pin
Prescaler and CCPR4H CCPR4L
 1, 4, 16 Edge Detect
TMR1
Enable
C4TSEL0
TMR1H TMR1L
C4TSEL1

Note: This block diagram uses CCP4 and CCP5 and their appropriate timers as an example. For details on all of
the CCP modules and their timer assignments, see Table 18-2 and Table 18-3.

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18.2.3 SOFTWARE INTERRUPT 18.3.1 CCP PIN CONFIGURATION
When the Capture mode is changed, a false capture The user must configure the CCPx pin as an output by
interrupt may be generated. The user should keep the clearing the appropriate TRIS bit.
CCP4IE bit (PIE4<1>) clear to avoid false interrupts
Note: Clearing the CCP4CON register will force
and should clear the flag bit, CCP4IF, following any
the RB4 compare output latch (depending
such change in operating mode.
on device configuration) to the default low
18.2.4 CCP PRESCALER level. This is not the PORTB I/O data latch.

There are four prescaler settings in Capture mode. 18.3.2 TIMER1/3/5 MODE SELECTION
They are specified as part of the operating mode
selected by the mode select bits (CCP4M<3:0>). If the CCP module is using the compare feature in
Whenever the CCP module is turned off, or the CCP conjunction with any of the Timer1/3/5 timers, the tim-
module is not in Capture mode, the prescaler counter ers must be running in Timer mode or Synchronized
is cleared. This means that any Reset will clear the Counter mode. In Asynchronous Counter mode, the
prescaler counter. compare operation may not work.

Switching from one capture prescaler to another may Note: Details of the timer assignments for the
generate an interrupt. Doing that also will not clear the CCP modules are given in Table 18-2 and
prescaler counter – meaning the first capture may be Table 18-3.
from a non-zero prescaler.
18.3.3 SOFTWARE INTERRUPT MODE
Example 18-1 shows the recommended method for
switching between capture prescalers. This example When the Generate Software Interrupt mode is chosen
also clears the prescaler counter and will not generate (CCP4M<3:0> = 1010), the CCP4 pin is not affected.
the “false” interrupt. Only a CCP interrupt is generated, if enabled, and the
CCP4IE bit is set.
EXAMPLE 18-1: CHANGING BETWEEN
CAPTURE PRESCALERS 18.3.4 SPECIAL EVENT TRIGGER
CLRF CCP4CON ; Turn CCP module off
Both CCP modules are equipped with a Special Event
MOVLW NEW_CAPT_PS ; Load WREG with the Trigger. This is an internal hardware signal generated
; new prescaler mode in Compare mode to trigger actions by other modules.
; value and CCP ON The Special Event Trigger is enabled by selecting
MOVWF CCP4CON ; Load CCP4CON with the Compare Special Event Trigger mode
; this value (CCP4M<3:0> = 1011).
For either CCP module, the Special Event Trigger resets
the Timer register pair for whichever timer resource is
18.3 Compare Mode
currently assigned as the module’s time base. This
In Compare mode, the 16-bit CCPR4 register value is allows the CCPRx registers to serve as a programmable
constantly compared against either the TMR1 or TMR3 period register for either timer.
register pair value. When a match occurs, the CCP4 The Special Event Trigger for CCP4 cannot start an
pin can be: A/D conversion.
• Driven high
Note: The Special Event Trigger of ECCP1 can
• Driven low start an A/D conversion, but the A/D
• Toggled (high-to-low or low-to-high) Converter must be enabled. For more
• Unchanged (that is, reflecting the state of the I/O information, see Section 19.0 “Enhanced
latch) Capture/Compare/PWM (ECCP) Module”.
The action on the pin is based on the value of the mode
select bits (CCP4M<3:0>). At the same time, the inter-
rupt flag bit, CCP4IF, is set.
Figure 18-2 gives the Compare mode block diagram

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FIGURE 18-2: COMPARE MODE OPERATION BLOCK DIAGRAM
Special Event Trigger
Set CCP5IF (Timer1/5 Reset)
CCPR5H CCPR5L
CCP5 Pin

Compare Output S Q
Comparator
Match Logic
R
TRIS
4 Output Enable

CCP5CON<3:0>
TMR1H TMR1L 0

TMR5H TMR5L 1

C5TSEL0

0 TMR1H TMR1L

1 TMR5H TMR5L
Special Event Trigger
(Timer1/Timer3 Reset, A/D Trigger)
C4TSEL1
C4TSEL0

Set CCP4IF CCP4 Pin

Compare Output S Q
Comparator
Match Logic
R
TRIS
4 Output Enable
CCPR4H CCPR4L
CCP4CON<3:0>

Note: This block diagram uses CCP4 and CCP5 and their appropriate timers as an example. For details on all of
the CCP modules and their timer assignments, see Table 18-2 and Table 18-3.

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TABLE 18-4: REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, TIMER1/3/5/7

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF
RCON IPEN — CM RI TO PD POR BOR
PIR4 CCP10IF CCP9IF CCP8IF CCP7IF CCP6IF CCP5IF CCP4IF CCP3IF
PIE4 CCP10IE CCP9IE CCP8IE CCP7IE CCP6IE CCP5IE CCP4IE CCP3IE
IPR4 CCP10IP CCP9IP CCP8IP CCP7IP CCP6IP CCP5IP CCP4IP CCP3IP
TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0
TRISC TRISC7 TRISC6 — — — TRISC2 TRISC1 TRISC0
TRISE RDPU REPU — — — TRISE2 TRISE1 TRISE0
TMR1L Timer1 Register Low Byte
TMR1H Timer1 Register High Byte
TMR3L Timer3 Register Low Byte
TMR3H Timer3 Register High Byte
TMR5L Timer5 Register Low Byte
TMR5H Timer5 Register High Byte
T1CON TMR1CS1 TMR1CS0 T1CKPS1 T1CKPS0 T1OSCEN T1SYNC RD16 TMR1ON
T3CON TMR3CS1 TMR3CS0 T3CKPS1 T3CKPS0 T3OSCEN T3SYNC RD16 TMR3ON
T5CON TMR5CS1 TMR5CS0 T5CKPS1 T5CKPS0 T5OSCEN T5SYNC RD16 TMR5ON
CCPR4L CCPR4L7 CCPR4L6 CCPR4L5 CCPR4L4 CCPR4L3 CCPR4L2 CCPR4L1 CCPR4L0
CCPR4H CCPR4H7 CCPR4H6 CCPR4H5 CCPR4H4 CCPR4H3 CCPR4H2 CCPR4H1 CCPR4H0
CCPR5L CCPR5L7 CCPR5L6 CCPR5L5 CCPR5L4 CCPR5L3 CCPR5L2 CCPR5L1 CCPR5L0
CCPR5H CCPR5H7 CCPR5H6 CCPR5H5 CCPR5H4 CCPR5H3 CCPR5H2 CCPR5H1 CCPR5H0
CCPR6L CCPR6L7 CCPR6L6 CCPR6L5 CCPR6L4 CCPR6L3 CCPR6L2 CCPR6L1 CCPR6L0
CCPR6H CCPR6H7 CCPR6H6 CCPR6H5 CCPR6H4 CCPR6H3 CCPR6H2 CCPR6H1 CCPR6H0
CCPR7L CCPR7L7 CCPR7L6 CCPR7L5 CCPR7L4 CCPR7L3 CCPR7L2 CCPR7L1 CCPR7L0
CCPR7H CCPR7H7 CCPR7H6 CCPR7H5 CCPR7H4 CCPR7H3 CCPR7H2 CCPR7H1 CCPR7H0
CCPR8L CCPR8L7 CCPR8L6 CCPR8L5 CCPR8L4 CCPR8L3 CCPR8L2 CCPR8L1 CCPR8L0
CCPR8H CCPR8H7 CCPR8H6 CCPR8H5 CCPR8H4 CCPR8H3 CCPR8H2 CCPR8H1 CCPR8H0
CCPR9L CCPR9L7 CCPR9L6 CCPR9L5 CCPR9L4 CCPR9L3 CCPR9L2 CCPR9L1 CCPR9L0
CCPR9H CCPR9H7 CCPR9H6 CCPR9H5 CCPR9H4 CCPR9H3 CCPR9H2 CCPR9H1 CCPR9H0
CCPR10L CCPR10L7 CCPR10L6 CCPR10L5 CCPR10L4 CCPR10L3 CCPR10L2 CCPR10L1 CCPR10L0
CCPR10H CCPR10H7 CCPR10H6 CCPR10H5 CCPR10H4 CCPR10H3 CCPR10H2 CCPR10H1 CCPR10H0
CCP4CON — — DC4B1 DC4B0 CCP4M3 CCP4M2 CCP4M1 CCP4M0
CCP5CON — — DC5B1 DC5B0 CCP5M3 CCP5M2 CCP5M1 CCP5M0
CCP6CON — — DC6B1 DC6B0 CCP6M3 CCP6M2 CCP6M1 CCP6M0
CCP7CON — — DC7B1 DC7B0 CCP7M3 CCP7M2 CCP7M1 CCP7M0
CCP8CON — — DC8B1 DC8B0 CCP8M3 CCP8M2 CCP8M1 CCP8M0
CCP9CON — — DC9B1 DC9B0 CCP9M3 CCP9M2 CCP9M1 CCP9M0
CCP10CON — — DC10B1 DC10B0 CCP10M3 CCP10M2 CCP10M1 CCP10M0
CCPTMRS1 C7TSEL1 C7TSEL0 — C6TSEL0 — C5TSEL0 C4TSEL1 C4TSEL0
CCPTMRS2 — — — C10TSEL0 — C9TSEL0 C8TSEL1 C8TSEL0
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by Capture/Compare or Timer1/3/5.

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18.4 PWM Mode A PWM output (Figure 18-4) has a time base (period)
and a time that the output stays high (duty cycle). The
In Pulse-Width Modulation (PWM) mode, the CCP4 pin frequency of the PWM is the inverse of the period
produces up to a 10-bit resolution PWM output. Since (1/period).
the CCP4 pin is multiplexed with a PORTB data latch,
the appropriate TRIS bit must be cleared to make the
FIGURE 18-4: PWM OUTPUT
CCP4 pin an output.
Period
Figure 18-3 shows a simplified block diagram of the
CCP1 module in PWM mode.
For a step-by-step procedure on how to set up the CCP
module for PWM operation, see Section 18.4.3 Duty Cycle

“Setup for PWM Operation”. TMR2 = PR2

FIGURE 18-3: SIMPLIFIED PWM BLOCK TMR2 = Duty Cycle

DIAGRAM TMR2 = PR2

Duty Cycle Registers CCP4CON<5:4>

CCPR4L 18.4.1 PWM PERIOD

The PWM period is specified by writing to the PR2
register. The PWM period can be calculated using the
following formula:
CCPR4H (Slave)

EQUATION 18-1:
Comparator R Q
PWM Period = [(PR2) + 1] • 4 • TOSC •
RC2/CCP1 (TMR2 Prescale Value)
TMR2 (Note 1)
S
PWM frequency is defined as 1/[PWM period].
TRISC<2> When TMR2 is equal to PR2, the following three events
Comparator
Clear Timer, occur on the next increment cycle:
CCP1 pin and
PR2
latch D.C. • TMR2 is cleared
• The CCP4 pin is set
Note 1: The 8-bit TMR2 value is concatenated with the 2-bit (An exception: If the PWM duty cycle = 0%, the
internal Q clock, or 2 bits of the prescaler, to create CCP4 pin will not be set)
the 10-bit time base.
2: CCP4 and its appropriate timers are used as an • The PWM duty cycle is latched from CCPR4L into
example. For details on all of the CCP modules and CCPR4H
their timer assignments, see Table 18-2 and
Table 18-3. Note: The Timer2 postscalers (see Section 14.0
“Timer2 Module”) are not used in the
determination of the PWM frequency. The
postscaler could be used to have a servo
update rate at a different frequency than
the PWM output.

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18.4.2 PWM DUTY CYCLE The CCPR4H register and a two-bit internal latch are
used to double-buffer the PWM duty cycle. This
The PWM duty cycle is specified by writing to the
double-buffering is essential for glitchless PWM
CCPR4L register and to the CCP4CON<5:4> bits. Up
operation.
to 10-bit resolution is available. The CCPR4L contains
the eight MSbs and the CCP4CON<5:4> contains the When the CCPR4H and two-bit latch match TMR2,
two LSbs. This 10-bit value is represented by concatenated with an internal two-bit Q clock or two
CCPR4L:CCP4CON<5:4>. The following equation is bits of the TMR2 prescaler, the CCP4 pin is cleared.
used to calculate the PWM duty cycle in time: The maximum PWM resolution (bits) for a given PWM
frequency is given by the equation:
EQUATION 18-2:
PWM Duty Cycle = (CCPR4L:CCP4CON<5:4>) • EQUATION 18-3:
TOSC • (TMR2 Prescale Value) F OSC
log  ---------------
 F PWM
CCPR4L and CCP4CON<5:4> can be written to at any PWM Resolution (max) = -----------------------------bits
log  2 
time, but the duty cycle value is not latched into
CCPR4H until after a match between PR2 and TMR2
occurs (that is, the period is complete). In PWM mode, Note: If the PWM duty cycle value is longer than
CCPR4H is a read-only register. the PWM period, the CCP4 pin will not be
cleared.

TABLE 18-5: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz

PWM Frequency 2.44 kHz 9.77 kHz 39.06 kHz 156.25 kHz 312.50 kHz 416.67 kHz
Timer Prescaler (1, 4, 16) 16 4 1 1 1 1
PR2 Value FFh FFh FFh 3Fh 1Fh 17h
Maximum Resolution (bits) 14 12 10 8 7 6.58

18.4.3 SETUP FOR PWM OPERATION

To configure the CCP module for PWM operation:
1. Set the PWM period by writing to the PR2
register.
2. Set the PWM duty cycle by writing to the
CCPR4L register and CCP4CON<5:4> bits.
3. Make the CCP4 pin an output by clearing the
appropriate TRIS bit.
4. Set the TMR2 prescale value, then enable
Timer2 by writing to T2CON.
5. Configure the CCP4 module for PWM operation.

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TABLE 18-6: REGISTERS ASSOCIATED WITH PWM AND TIMERS
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF
RCON IPEN — CM RI TO PD POR BOR
PIR4 CCP10IF CCP9IF CCP8IF CCP7IF CCP6IF CCP5IF CCP4IF CCP3IF
PIE4 CCP10IE CCP9IE CCP8IE CCP7IE CCP6IE CCP5IE CCP4IE CCP3IE
IPR4 CCP10IP CCP9IP CCP8IP CCP7IP CCP6IP CCP5IP CCP4IP CCP3IP
TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0
TRISC TRISC7 TRISC6 — — — TRISC2 TRISC1 TRISC0
TRISE RDPU REPU — — — TRISE2 TRISE1 TRISE0
TMR2 Timer2 Register
TMR4 Timer4 Register
TMR6 Timer6 Register
TMR8 Timer8 Register
PR2 Timer2 Period Register
PR4 Timer4 Period Register
PR6 Timer6 Period Register
PR8 Timer8 Period Register
T2CON — T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0
T4CON — T4OUTPS3 T4OUTPS2 T4OUTPS1 T4OUTPS0 TMR4ON T4CKPS1 T4CKPS0
T6CON — T6OUTPS3 T6OUTPS2 T6OUTPS1 T6OUTPS0 TMR6ON T6CKPS1 T6CKPS0
T8CON — T8OUTPS3 T8OUTPS2 T8OUTPS1 T8OUTPS0 TMR8ON T8CKPS1 T8CKPS0
CCPR4L CCPR4L7 CCPR4L6 CCPR4L5 CCPR4L4 CCPR4L3 CCPR4L2 CCPR4L1 CCPR4L0
CCPR4H CCPR4H7 CCPR4H6 CCPR4H5 CCPR4H4 CCPR4H3 CCPR4H2 CCPR4H1 CCPR4H0
CCPR5L CCPR5L7 CCPR5L6 CCPR5L5 CCPR5L4 CCPR5L3 CCPR5L2 CCPR5L1 CCPR5L0
CCPR5H CCPR5H7 CCPR5H6 CCPR5H5 CCPR5H4 CCPR5H3 CCPR5H2 CCPR5H1 CCPR5H0
CCPR6L CCPR6L7 CCPR6L6 CCPR6L5 CCPR6L4 CCPR6L3 CCPR6L2 CCPR6L1 CCPR6L0
CCPR6H CCPR6H7 CCPR6H6 CCPR6H5 CCPR6H4 CCPR6H3 CCPR6H2 CCPR6H1 CCPR6H0
CCPR7L CCPR7L7 CCPR7L6 CCPR7L5 CCPR7L4 CCPR7L3 CCPR7L2 CCPR7L1 CCPR7L0
CCPR7H CCPR7H7 CCPR7H6 CCPR7H5 CCPR7H4 CCPR7H3 CCPR7H2 CCPR7H1 CCPR7H0
CCPR8L CCPR8L7 CCPR8L6 CCPR8L5 CCPR8L4 CCPR8L3 CCPR8L2 CCPR8L1 CCPR8L0
CCPR8H CCPR8H7 CCPR8H6 CCPR8H5 CCPR8H4 CCPR8H3 CCPR8H2 CCPR8H1 CCPR8H0
CCPR9L CCPR9L7 CCPR9L6 CCPR9L5 CCPR9L4 CCPR9L3 CCPR9L2 CCPR9L1 CCPR9L0
CCPR9H CCPR9H7 CCPR9H6 CCPR9H5 CCPR9H4 CCPR9H3 CCPR9H2 CCPR9H1 CCPR9H0
CCPR10L CCPR10L7 CCPR10L6 CCPR10L5 CCPR10L4 CCPR10L3 CCPR10L2 CCPR10L1 CCPR10L0
CCPR10H CCPR10H7 CCPR10H6 CCPR10H5 CCPR10H4 CCPR10H3 CCPR10H2 CCPR10H1 CCPR10H0
CCP4CON — — DC4B1 DC4B0 CCP4M3 CCP4M2 CCP4M1 CCP4M0
CCP5CON — — DC5B1 DC5B0 CCP5M3 CCP5M2 CCP5M1 CCP5M0
CCP6CON — — DC6B1 DC6B0 CCP6M3 CCP6M2 CCP6M1 CCP6M0
CCP7CON — — DC7B1 DC7B0 CCP7M3 CCP7M2 CCP7M1 CCP7M0
CCP8CON — — DC8B1 DC8B0 CCP8M3 CCP8M2 CCP8M1 CCP8M0
CCP9CON — — DC9B1 DC9B0 CCP9M3 CCP9M2 CCP9M1 CCP9M0
CCP10CON — — DC10B1 DC10B0 CCP10M3 CCP10M2 CCP10M1 CCP10M0
CCPTMRS1 C7TSEL1 C7TSEL0 — C6TSEL0 — C5TSEL0 C4TSEL1 C4TSEL0
CCPTMRS2 — — — C10TSEL0 — C9TSEL0 C8TSEL1 C8TSEL0
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PWM or Timer2/4/6/8.

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19.0 ENHANCED The ECCP modules are implemented as standard CCP
modules with enhanced PWM capabilities. These
CAPTURE/COMPARE/PWM
include:
(ECCP) MODULE
• Provision for two or four output channels
PIC18F47J53 family devices have three Enhanced • Output Steering modes
Capture/Compare/PWM (ECCP) modules: ECCP1,
• Programmable polarity
ECCP2 and ECCP3. These modules contain a 16-bit
register, which can operate as a 16-bit Capture register, • Programmable dead-band control
a 16-bit Compare register or a PWM Master/Slave Duty • Automatic shutdown and restart
Cycle register. These ECCP modules are upwardly The enhanced features are discussed in detail in
compatible with CCP. Section 19.4 “PWM (Enhanced Mode)”.
Note: Throughout this section, generic references
are used for register and bit names that are
the same – except for an ‘x’ variable that
indicates the item’s association with the
ECCP1, ECCP2 or ECCP3 module. For
example, the control register is named
CCPxCON and refers to CCP1CON,
CCP2CON and CCP3CON.

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REGISTER 19-1: CCPxCON: ECCP1/2/3 CONTROL (1, ACCESS FBAh; 2, FB4h; 3, BANKED F15h)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PxM1 PxM0 DCxB1 DCxB0 CCPxM3 CCPxM2 CCPxM1 CCPxM0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-6 PxM<1:0>: Enhanced PWM Output Configuration bits

If CCPxM<3:2> = 00, 01, 10:
xx = PxA assigned as capture/compare input/output; PxB, PxC and PxD assigned as port pins
If CCPxM<3:2> = 11:
00 = Single output: PxA, PxB, PxC and PxD are controlled by steering (see Section 19.4.7 “Pulse
Steering Mode”)
01 = Full-bridge output forward: PxD modulated; PxA active; PxB, PxC inactive
10 = Half-bridge output: PxA, PxB modulated with dead-band control; PxC and PxD assigned as
port pins
11 = Full-bridge output reverse: PxB modulated; PxC active; PxA and PxD inactive
bit 5-4 DCxB<1:0>: PWM Duty Cycle bit 1 and bit 0
Capture mode:
Unused.
Compare mode:
Unused.
PWM mode:
These bits are the two LSbs of the 10-bit PWM duty cycle. The eight MSbs of the duty cycle are found
in ECCPRxL.
bit 3-0 CCPxM<3:0>: ECCPx Mode Select bits
0000 = Capture/Compare/PWM off (resets ECCPx module)
0001 = Reserved
0010 = Compare mode, toggle output on match
0011 = Capture mode
0100 = Capture mode; every falling edge
0101 = Capture mode; every rising edge
0110 = Capture mode; every fourth rising edge
0111 = Capture mode; every 16th rising edge
1000 = Compare mode; initialize ECCPx pin low, set output on compare match (set CCPxIF)
1001 = Compare mode; initialize ECCPx pin high, clear output on compare match (set CCPxIF)
1010 = Compare mode; generate software interrupt only, ECCPx pin reverts to I/O state
1011 = Compare mode; trigger special event (ECCPx resets TMR1 or TMR3, starts A/D conversion,
sets CCPxIF bit)
1100 = PWM mode; PxA and PxC active-high; PxB and PxD active-high
1101 = PWM mode; PxA and PxC active-high; PxB and PxD active-low
1110 = PWM mode; PxA and PxC active-low; PxB and PxD active-high
1111 = PWM mode; PxA and PxC active-low; PxB and PxD active-low

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REGISTER 19-2: CCPTMRS0: ECCP1/2/3 TIMER SELECT 0 REGISTER (BANKED F52h)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
C3TSEL1 C3TSEL0 C2TSEL2 C2TSEL1 C2TSEL0 C1TSEL2 C1TSEL1 C1TSEL0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-6 C3TSEL<1:0>: ECCP3 Timer Selection bits

00 = ECCP3 is based off of TMR1/TMR2
01 = ECCP3 is based off of TMR3/TMR4
10 = ECCP3 is based off of TMR3/TMR6
11 = ECCP3 is based off of TMR3/TMR8
bit 5-3 C2TSEL<2:0>: ECCP2 Timer Selection bits
000 = ECCP2 is based off of TMR1/TMR2
001 = ECCP2 is based off of TMR3/TMR4
010 = ECCP2 is based off of TMR3/TMR6
011 = ECCP2 is based off of TMR3/TMR8
1xx = Reserved; do not use
bit 2-0 C1TSEL<2:0>: ECCP1 Timer Selection bits
000 = ECCP1 is based off of TMR1/TMR2
001 = ECCP1 is based off of TMR3/TMR4
010 = ECCP1 is based off of TMR3/TMR6
011 = ECCP1 is based off of TMR3/TMR8
1xx = Reserved; do not use

In addition to the expanded range of modes available

through the CCPxCON and ECCPxAS registers, the
ECCP modules have two additional registers associated
with Enhanced PWM operation and auto-shutdown
features. They are:
• ECCPxDEL – Enhanced PWM Control
• PSTRxCON – Pulse Steering Control

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19.1 ECCP Outputs and Configuration 19.2 Capture Mode
The Enhanced CCP module may have up to four PWM In Capture mode, the CCPRxH:CCPRxL register pair
outputs, depending on the selected operating mode. captures the 16-bit value of the TMR1 or TMR3
These outputs, designated PxA through PxD, are registers when an event occurs on the corresponding
routed through the Peripheral Pin Select (PPS) ECCPx pin. An event is defined as one of the following:
module. Therefore, individual functions can be mapped • Every falling edge
to any of the remappable I/O pins (RPn).
• Every rising edge
The outputs that are active depend on the ECCP • Every fourth rising edge
operating mode selected. The pin assignments are
• Every 16th rising edge
summarized in Table 19-3.
The event is selected by the mode select bits,
To configure the I/O pins as PWM outputs, the proper
CCPxM<3:0> (CCPxCON register<3:0>). When a
PWM mode must be selected by setting the PxM<1:0>
capture is made, the interrupt request flag bit, CCPxIF,
and CCPxM<3:0> bits. The appropriate TRIS direction
is set (see Table 19-2). The flag must be cleared by
bits for the port pins must also be set as outputs.
software. If another capture occurs before the value in
19.1.1 ECCP MODULE AND TIMER the CCPRxH/L register pair is read, the old captured
value is overwritten by the new captured value.
RESOURCES
The ECCP modules use Timers 1, 2, 3, 4, 6 or 8, TABLE 19-2: ECCP1/2/3 INTERRUPT FLAG
depending on the mode selected. These timers are BITS
available to CCP modules in Capture, Compare or PWM ECCP Module Flag-Bit
modes, as shown in Table 19-1.
1 PIR1<2>
TABLE 19-1: ECCP MODE – TIMER 2 PIR2<0>
RESOURCE 3 PIR4<0>
ECCP Mode Timer Resource
19.2.1 ECCP PIN CONFIGURATION
Capture Timer1 or Timer3 In Capture mode, the appropriate ECCPx pin should be
Compare Timer1 or Timer3 configured as an input by setting the corresponding
PWM Timer2, Timer4, Timer6 or Timer8 TRIS direction bit.
Additionally, the ECCPx input function needs to be
The assignment of a particular timer to a module is
assigned to an I/O pin through the Peripheral Pin
determined by the Timer to ECCP enable bits in the
Select module. For details on setting up the
CCPTMRS0 register (Register 19-2). The interactions
remappable pins, see Section 10.7 “Peripheral Pin
between the two modules are depicted in Figure 19-1.
Select (PPS)”.
Capture operations are designed to be used when the
timer is configured for Synchronous Counter mode. Note: If the ECCPx pin is configured as an out-
Capture operations may not work as expected if the put, a write to the port can cause a capture
associated timer is configured for Asynchronous Counter condition.
mode.

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19.2.2 TIMER1/TIMER3 MODE SELECTION ECCP module is turned off, or Capture mode is dis-
abled, the prescaler counter is cleared. This means
The timers that are to be used with the capture feature
that any Reset will clear the prescaler counter.
(Timer1 and/or Timer3) must be running in Timer mode
or Synchronized Counter mode. In Asynchronous Switching from one capture prescaler to another may
Counter mode, the capture operation may not work. generate an interrupt. Also, the prescaler counter will
The timer to be used with each ECCP module is not be cleared; therefore, the first capture may be from
selected in the CCPTMRS0 register (Register 19-2). a non-zero prescaler. Example 19-1 provides the
recommended method for switching between capture
19.2.3 SOFTWARE INTERRUPT prescalers. This example also clears the prescaler
When the Capture mode is changed, a false capture counter and will not generate the “false” interrupt.
interrupt may be generated. The user should keep the
CCPxIE interrupt enable bit clear to avoid false interrupts. EXAMPLE 19-1: CHANGING BETWEEN
The interrupt flag bit, CCPxIF, should also be cleared CAPTURE PRESCALERS
following any such change in operating mode. CLRF ECCP1CON ; Turn ECCP module off
MOVLW NEW_CAPT_PS ; Load WREG with the
19.2.4 ECCP PRESCALER ; new prescaler mode
There are four prescaler settings in Capture mode; they ; value and ECCP ON
MOVWF CCP1CON ; Load ECCP1CON with
are specified as part of the operating mode selected by
; this value
the mode select bits (CCPxM<3:0>). Whenever the

FIGURE 19-1: CAPTURE MODE OPERATION BLOCK DIAGRAM

TMR3H TMR3L
Set CCP1IF
C1TSEL0
C1TSEL1 TMR3
ECCP1 Pin C1TSEL2 Enable
Prescaler and CCPR1H CCPR1L
 1, 4, 16 Edge Detect
C1TSEL0 TMR1
C1TSEL1 Enable
C1TSEL2
4 TMR1H TMR1L
CCP1CON<3:0>
4
Q1:Q4

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19.3 Compare Mode 19.3.2 TIMER1/TIMER3 MODE SELECTION
In Compare mode, the 16-bit CCPRx register pair value Timer1 and/or Timer3 must be running in Timer mode
is constantly compared against either the TMR1 or or Synchronized Counter mode if the ECCP module is
TMR3 register pair value. When a match occurs, the using the compare feature. In Asynchronous Counter
ECCPx pin can be: mode, the compare operation will not work reliably.

• Driven high 19.3.3 SOFTWARE INTERRUPT MODE

• Driven low
When the Generate Software Interrupt mode is chosen
• Toggled (high-to-low or low-to-high) (CCPxM<3:0> = 1010), the ECCPx pin is not affected;
• Unchanged (that is, reflecting the state of the I/O only the CCPxIF interrupt flag is affected.
latch)
The action on the pin is based on the value of the mode 19.3.4 SPECIAL EVENT TRIGGER
select bits (CCPxM<3:0>). At the same time, the The ECCP module is equipped with a Special Event
interrupt flag bit, CCPxIF, is set. Trigger. This is an internal hardware signal generated
in Compare mode to trigger actions by other modules.
19.3.1 ECCP PIN CONFIGURATION The Special Event Trigger is enabled by selecting
Users must configure the ECCPx pin as an output by the Compare Special Event Trigger mode
clearing the appropriate TRIS bit. (CCPxM<3:0> = 1011).
The Special Event Trigger resets the Timer register pair
Note: Clearing the CCPxCON register will force
for whichever timer resource is currently assigned as the
the ECCPx compare output latch (depend-
module’s time base. This allows the CCPRx registers to
ing on device configuration) to the default
serve as a Programmable Period register for either
low level. This is not the PORTx I/O data
timer.
latch.
The Special Event Trigger can also start an A/D conver-
sion. In order to do this, the A/D Converter must
already be enabled.

FIGURE 19-2: COMPARE MODE OPERATION BLOCK DIAGRAM

0 TMR1H TMR1L

1 TMR3H TMR3L

Special Event Trigger

C1TSEL0 (Timer1/Timer3 Reset, A/D Trigger)
C1TSEL1
C1TSEL2

Set CCP1IF ECCP1 Pin

Compare Output S Q
Comparator
Match Logic
R
TRIS
4 Output Enable
CCPR1H CCPR1L
CCP1CON<3:0>

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19.4 PWM (Enhanced Mode) The PWM outputs are multiplexed with I/O pins and are
designated: PxA, PxB, PxC and PxD. The polarity of the
The Enhanced PWM mode can generate a PWM signal PWM pins is configurable and is selected by setting the
on up to four different output pins with up to 10 bits of CCPxM bits in the CCPxCON register appropriately.
resolution. It can do this through four different PWM
Output modes: Table 19-1 provides the pin assignments for each
Enhanced PWM mode.
• Single PWM mode
Figure 19-3 provides an example of a simplified block
• Half-Bridge PWM mode
diagram of the Enhanced PWM module.
• Full-Bridge PWM, Forward mode
• Full-Bridge PWM, Reverse mode Note: To prevent the generation of an
incomplete waveform when the PWM is
To select an Enhanced PWM mode, the PxM bits of the first enabled, the ECCP module waits until
CCPxCON register must be set appropriately. the start of a new PWM period before
generating a PWM signal.

FIGURE 19-3: SIMPLIFIED BLOCK DIAGRAM OF THE ENHANCED PWM MODE EXAMPLE
DC1B<1:0> PxM<1:0> CCPxM<3:0>
Duty Cycle Registers
2 4
CCPR1L
ECCPx/PxA ECCPx/Output Pin
TRIS

CCPR1H (Slave)
PxB Output Pin

Output TRIS
Comparator R Q
Controller
PxC Output Pin
TMR2 (1)
S TRIS

PxD Output Pin

Comparator
Clear Timer2, TRIS
toggle PWM pin and
latch duty cycle
PR2 ECCP1DEL

Note 1: The 8-bit timer TMR2 register is concatenated with the 2-bit internal Q clock, or 2 bits of the prescaler, to
create the 10-bit time base.

Note 1: The TRIS register value for each PWM output must be configured appropriately.
2: Any pin not used by an Enhanced PWM mode is available for alternate pin functions.

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TABLE 19-3: EXAMPLE PIN ASSIGNMENTS FOR VARIOUS PWM ENHANCED MODES
ECCP Mode PxM<1:0> PxA PxB PxC PxD
Single 00 Yes(1) Yes(1) Yes(1) Yes(1)
Half-Bridge 10 Yes Yes No No
Full-Bridge, Forward 01 Yes Yes Yes Yes
Full-Bridge, Reverse 11 Yes Yes Yes Yes
Note 1: Outputs are enabled by pulse steering in Single mode (see Register 19-5).

FIGURE 19-4: PWM (ENHANCED MODE) OUTPUT RELATIONSHIPS

(ACTIVE-HIGH STATE) EXAMPLE
Pulse Width PR2 + 1
PxM<1:0> Signal 0

Period

00 (Single Output) PxA Modulated

Delay(1) Delay(1)
PxA Modulated

10 (Half-Bridge) PxB Modulated

PxA Active

(Full-Bridge, PxB Inactive

01 Forward)
PxC Inactive

PxD Modulated

PxA Inactive

(Full-Bridge, PxB Modulated

11
Reverse)
PxC Active

PxD Inactive

Relationships:
• Period = 4 * TOSC * (PR2 + 1) * (TMR2 Prescale Value)
• Pulse Width = TOSC * (CCPRxL<7:0>:CCPxCON<5:4>) * (TMR2 Prescale Value)
• Delay = 4 * TOSC * (ECCPxDEL<6:0>)
Note 1: Dead-band delay is programmed using the ECCPxDEL register (see Section 19.4.6 “Programmable
Dead-Band Delay Mode”).

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FIGURE 19-5: ENHANCED PWM OUTPUT RELATIONSHIPS (ACTIVE-LOW STATE) EXAMPLE

Pulse PR2 + 1
PxM<1:0> Signal 0
Width
Period

00 (Single Output) PxA Modulated

PxA Modulated
Delay(1) Delay(1)
10 (Half-Bridge) PxB Modulated

PxA Active

(Full-Bridge, PxB Inactive

01 Forward)
PxC Inactive

PxD Modulated

PxA Inactive

(Full-Bridge, PxB Modulated

11
Reverse)
PxC Active

PxD Inactive

Relationships:
• Period = 4 * TOSC * (PR2 + 1) * (TMR2 Prescale Value)
• Pulse Width = TOSC * (CCPRxL<7:0>:CCPxCON<5:4>) * (TMR2 Prescale Value)
• Delay = 4 * TOSC * (ECCPxDEL<6:0>)
Note 1: Dead-band delay is programmed using the ECCPxDEL register (see Section 19.4.6 “Programmable Dead-Band
Delay Mode”).

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19.4.1 HALF-BRIDGE MODE Since the PxA and PxB outputs are multiplexed with the
port data latches, the associated TRIS bits must be
In Half-Bridge mode, two pins are used as outputs to
cleared to configure PxA and PxB as outputs.
drive push-pull loads. The PWM output signal is output
on the PxA pin, while the complementary PWM output
signal is output on the PxB pin (see Figure 19-6). This FIGURE 19-6: EXAMPLE OF
mode can be used for half-bridge applications, as HALF-BRIDGE PWM
shown in Figure 19-7, or for full-bridge applications, OUTPUT
where four power switches are being modulated with Period Period
two PWM signals.
Pulse Width
In Half-Bridge mode, the programmable dead-band delay
can be used to prevent shoot-through current in PxA(2)
half-bridge power devices. The value of the PxDC<6:0> td
bits of the ECCPxDEL register sets the number of td
instruction cycles before the output is driven active. If the PxB(2)
value is greater than the duty cycle, the corresponding
output remains inactive during the entire cycle. For more (1) (1) (1)
details on the dead-band delay operations, see
Section 19.4.6 “Programmable Dead-Band Delay td = Dead-Band Delay
Mode”. Note 1: At this time, the TMR2 register is equal to the
PR2 register.
2: Output signals are shown as active-high.

FIGURE 19-7: EXAMPLE OF HALF-BRIDGE APPLICATIONS

Standard Half-Bridge Circuit (“Push-Pull”)

FET
Driver +
PxA
-

Load
FET
Driver
+
PxB
-

Half-Bridge Output Driving a Full-Bridge Circuit

V+

FET FET
Driver Driver
PxA

Load
FET FET
Driver Driver
PxB

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19.4.2 FULL-BRIDGE MODE In the Reverse mode, the PxC pin is driven to its active
state and the PxB pin is modulated, while the PxA and
In Full-Bridge mode, all four pins are used as outputs.
PxD pins are driven to their inactive state, as shown in
An example of a full-bridge application is provided in
Figure 19-9.
Figure 19-8.
The PxA, PxB, PxC and PxD outputs are multiplexed
In the Forward mode, the PxA pin is driven to its active
with the port data latches. The associated TRIS bits
state and the PxD pin is modulated, while the PxB and
must be cleared to configure the PxA, PxB, PxC and
PxC pins are driven to their inactive state, as shown in
PxD pins as outputs.
Figure 19-9.

FIGURE 19-8: EXAMPLE OF FULL-BRIDGE APPLICATION

V+

FET QA QC FET
Driver Driver
PxA

Load
PxB
FET FET
Driver Driver

PxC
QB QD

V-
PxD

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FIGURE 19-9: EXAMPLE OF FULL-BRIDGE PWM OUTPUT
Forward Mode
Period
(2)
PxA
Pulse Width

PxB(2)

PxC(2)

PxD(2)

(1) (1)

Reverse Mode

Period
Pulse Width

PxA(2)

PxB(2)

PxC(2)

PxD(2)
(1) (1)

Note 1: At this time, the TMR2 register is equal to the PR2 register.
2: The output signal is shown as active-high.

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19.4.2.1 Direction Change in Full-Bridge Figure 19-11 shows an example of the PWM direction
Mode changing from forward to reverse at a near 100% duty
cycle. In this example, at time t1, the PxA and PxD
In the Full-Bridge mode, the PxM1 bit in the CCPxCON
outputs become inactive, while the PxC output
register allows users to control the forward/reverse
becomes active. Since the turn-off time of the power
direction. When the application firmware changes this
devices is longer than the turn-on time, a shoot-through
direction control bit, the module will change to the new
current will flow through power devices, QC and QD
direction on the next PWM cycle.
(see Figure 19-8), for the duration of ‘t’. The same
A direction change is initiated in software by changing phenomenon will occur to power devices, QA and QB,
the PxM1 bit of the CCPxCON register. The following for PWM direction change from reverse to forward.
sequence occurs prior to the end of the current PWM
If changing PWM direction at high duty cycle is required
period:
for an application, two possible solutions for eliminating
• The modulated outputs (PxB and PxD) are placed the shoot-through current are:
in their inactive state.
• Reduce PWM duty cycle for one PWM period
• The associated unmodulated outputs (PxA and before changing directions.
PxC) are switched to drive in the opposite direction.
• Use switch drivers that can drive the switches off
• PWM modulation resumes at the beginning of the faster than they can drive them on.
next period.
Other options to prevent shoot-through current may
For an illustration of this sequence, see Figure 19-10. exist.
The Full-Bridge mode does not provide a dead-band
delay. As one output is modulated at a time, a dead-band
delay is generally not required. There is a situation where
a dead-band delay is required. This situation occurs
when both of the following conditions are true:
• The direction of the PWM output changes when
the duty cycle of the output is at or near 100%.
• The turn-off time of the power switch, including
the power device and driver circuit, is greater than
the turn-on time.

FIGURE 19-10: EXAMPLE OF PWM DIRECTION CHANGE

Signal Period(1) Period

PxA (Active-High)

PxB (Active-High)
Pulse Width

PxC (Active-High)

(2)
PxD (Active-High)

Pulse Width

Note 1: The direction bit, PxM1 of the CCPxCON register, is written any time during the PWM cycle.
2: When changing directions, the PxA and PxC signals switch before the end of the current PWM cycle. The
modulated PxB and PxD signals are inactive at this time. The length of this time is:
(1/FOSC) • TMR2 Prescale Value.

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FIGURE 19-11: EXAMPLE OF PWM DIRECTION CHANGE AT NEAR 100% DUTY CYCLE
Forward Period t1 Reverse Period

PxA

PxB
PW

PxC

PxD PW
TON
External Switch C
TOFF

External Switch D

Potential T = TOFF – TON

Shoot-Through Current

Note 1: All signals are shown as active-high.

2: TON is the turn-on delay of power switch, QC, and its driver.
3: TOFF is the turn-off delay of power switch, QD, and its driver.

19.4.3 START-UP CONSIDERATIONS pin output drivers. The completion of a full PWM cycle
is indicated by the TMR2IF or TMR4IF bit of the PIR1
When any PWM mode is used, the application
or PIR3 register being set as the second PWM period
hardware must use the proper external pull-up and/or
begins.
pull-down resistors on the PWM output pins.
Note: When the microcontroller is released from 19.4.4 ENHANCED PWM
Reset, all of the I/O pins are in the AUTO-SHUTDOWN MODE
high-impedance state. The external The PWM mode supports an Auto-Shutdown mode that
circuits must keep the power switch will disable the PWM outputs when an external
devices in the OFF state until the micro- shutdown event occurs. Auto-Shutdown mode places
controller drives the I/O pins with the the PWM output pins into a predetermined state. This
proper signal levels or activates the PWM mode is used to help prevent the PWM from damaging
output(s). the application.
The CCPxM<1:0> bits of the CCPxCON register allow The auto-shutdown sources are selected using the
the user to choose whether the PWM output signals are ECCPxAS<2:0> bits (ECCPxAS<6:4>). A shutdown
active-high or active-low for each pair of PWM output event may be generated by:
pins (PxA/PxC and PxB/PxD). The PWM output
polarities must be selected before the PWM pin output • A logic ‘0’ on the pin that is assigned to the FLT0
drivers are enabled. Changing the polarity configura- input function
tion while the PWM pin output drivers are enabled is • Comparator C1
not recommended, since it may result in damage to the • Comparator C2
application circuits. • Setting the ECCPxASE bit in firmware
The PxA, PxB, PxC and PxD output latches may not be A shutdown condition is indicated by the ECCPxASE
in the proper states when the PWM module is (Auto-Shutdown Event Status) bit (ECCPxAS<7>). If
initialized. Enabling the PWM pin output drivers at the the bit is a ‘0’, the PWM pins are operating normally. If
same time as the Enhanced PWM modes may cause the bit is a ‘1’, the PWM outputs are in the shutdown
damage to the application circuit. The Enhanced PWM state.
modes must be enabled in the proper Output mode and
complete a full PWM cycle before enabling the PWM

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When a shutdown event occurs, two things happen: (PxB/PxD). The state of each pin pair is deter-
• The ECCPxASE bit is set to ‘1’. The ECCPxASE mined by the PSSxAC and PSSxBD bits
will remain set until cleared in firmware or an (ECCPxAS<3:0>).
auto-restart occurs. (See Section 19.4.5 Each pin pair may be placed into one of three states:
“Auto-Restart Mode”.) • Drive logic ‘1’
• The enabled PWM pins are asynchronously • Drive logic ‘0’
placed in their shutdown states. The PWM output
• Tri-state (high-impedance)
pins are grouped into pairs (PxA/PxC) and

REGISTER 19-3: ECCPxAS: ECCP1/2/3 AUTO-SHUTDOWN CONTROL REGISTER (1, ACCESS

FBEh; 2, FB8h; 3, BANKED F19h)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
ECCPxASE ECCPxAS2 ECCPxAS1 ECCPxAS0 PSSxAC1 PSSxAC0 PSSxBD1 PSSxBD0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 ECCPxASE: ECCP Auto-Shutdown Event Status bit

1 = A shutdown event has occurred; ECCP outputs are in a shutdown state
0 = ECCP outputs are operating
bit 6-4 ECCPxAS<2:0>: ECCP Auto-Shutdown Source Select bits
000 = Auto-shutdown is disabled
001 = Comparator, C1OUT, output is high
010 = Comparator, C2OUT, output is high
011 = Either comparator, C1OUT or C2OUT, is high
100 = VIL on FLT0 pin
101 = VIL on FLT0 pin or comparator, C1OUT, output is high
110 = VIL on FLT0 pin or comparator, C2OUT, output is high
111 = VIL on FLT0 pin or comparator, C1OUT, or comparator, C2OUT, is high
bit 3-2 PSSxAC<1:0>: PxA and PxC Pins Shutdown State Control bits
00 = Drive pins, PxA and PxC, to ‘0’
01 = Drive pins, PxA and PxC, to ‘1’
1x = PxA and PxC pins tri-state
bit 1-0 PSSxBD<1:0>: PxB and PxD Pins Shutdown State Control bits
00 = Drive pins, PxB and PxD, to ‘0’
01 = Drive pins, PxB and PxD, to ‘1’
1x = PxB and PxD pins tri-state

Note 1: The auto-shutdown condition is a level-based signal, not an edge-based signal. As long as the level is
present, the auto-shutdown will persist.
2: Writing to the ECCPxASE bit is disabled while an auto-shutdown condition persists.
3: Once the auto-shutdown condition has been removed and the PWM restarted (either through firmware or
auto-restart), the PWM signal will always restart at the beginning of the next PWM period.

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FIGURE 19-12: PWM AUTO-SHUTDOWN WITH FIRMWARE RESTART (PxRSEN = 0)
PWM Period

Shutdown Event

ECCPxASE bit

PWM Activity

Normal PWM
ECCPxASE
Cleared by
Start of Shutdown Shutdown Firmware PWM
PWM Period Event Occurs Event Clears Resumes

19.4.5 AUTO-RESTART MODE The module will wait until the next PWM period begins,
however, before re-enabling the output pin. This behav-
The Enhanced PWM can be configured to automatically
ior allows the auto-shutdown with auto-restart features
restart the PWM signal once the auto-shutdown condi-
to be used in applications based on the current mode
tion has been removed. Auto-restart is enabled by
of PWM control.
setting the PxRSEN bit (ECCPxDEL<7>).
If auto-restart is enabled, the ECCPxASE bit will
remain set as long as the auto-shutdown condition is
active. When the auto-shutdown condition is removed,
the ECCPxASE bit will be cleared via hardware and
normal operation will resume.

FIGURE 19-13: PWM AUTO-SHUTDOWN WITH AUTO-RESTART ENABLED (PxRSEN = 1)

PWM Period

Shutdown Event

ECCPxASE bit

PWM Activity

Normal PWM

Start of Shutdown Shutdown PWM

PWM Period Event Occurs Event Clears Resumes

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19.4.6 PROGRAMMABLE DEAD-BAND FIGURE 19-14: EXAMPLE OF
DELAY MODE HALF-BRIDGE PWM
In half-bridge applications, where all power switches OUTPUT
are modulated at the PWM frequency, the power Period Period
switches normally require more time to turn off than to
Pulse Width
turn on. If both the upper and lower power switches are
switched at the same time (one turned on and the other (2)
PxA
turned off), both switches may be on for a short period td
until one switch completely turns off. During this brief
td
interval, a very high current (shoot-through current) will PxB(2)
flow through both power switches, shorting the bridge
supply. To avoid this potentially destructive (1) (1) (1)
shoot-through current from flowing during switching,
turning on either of the power switches is normally td = Dead-Band Delay
delayed to allow the other switch to completely turn off.
In Half-Bridge mode, a digitally programmable, Note 1: At this time, the TMR2 register is equal to the
dead-band delay is available to avoid shoot-through PR2 register.
current from destroying the bridge power switches. The 2: Output signals are shown as active-high.
delay occurs at the signal transition from the non-active
state to the active state. For an illustration, see
Figure 19-14. The lower seven bits of the associated
ECCPxDEL register (Register 19-4) sets the delay
period in terms of microcontroller instruction cycles
(TCY or 4 TOSC).

FIGURE 19-15: EXAMPLE OF HALF-BRIDGE APPLICATIONS

V+
Standard Half-Bridge Circuit (“Push-Pull”)

FET
Driver +
PxA V
-

Load
FET
Driver
+
PxB V
-

V-

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REGISTER 19-4: ECCPxDEL: ECCP1/2/3 ENHANCED PWM CONTROL REGISTER
(1, ACCESS FBDh; 2, FB7h; 3, BANKED F18h)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PxRSEN PxDC6 PxDC5 PxDC4 PxDC3 PxDC2 PxDC1 PxDC0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 PxRSEN: PWM Restart Enable bit

1 = Upon auto-shutdown, the ECCPxASE bit clears automatically once the shutdown event goes
away; the PWM restarts automatically
0 = Upon auto-shutdown, ECCPxASE must be cleared by software to restart the PWM
bit 6-0 PxDC<6:0>: PWM Delay Count bits
PxDCn = Number of FOSC/4 (4 * TOSC) cycles between the scheduled time when a PWM signal
should transition active and the actual time it transitions active.

19.4.7 PULSE STEERING MODE While the PWM Steering mode is active, the
CCPxM<1:0> bits (CCPxCON<1:0>) select the PWM
In Single Output mode, pulse steering allows any of the
output polarity for the Px<D:A> pins.
PWM pins to be the modulated signal. Additionally, the
same PWM signal can simultaneously be available on The PWM auto-shutdown operation also applies to
multiple pins. PWM Steering mode, as described in Section 19.4.4
“Enhanced PWM Auto-shutdown mode”. An
Once the Single Output mode is selected
auto-shutdown event will only affect pins that have
(CCPxM<3:2> = 11 and PxM<1:0> = 00 of the
PWM outputs enabled.
CCPxCON register), the user firmware can bring out
the same PWM signal to one, two, three or four output
pins by setting the appropriate STR<D:A> bits
(PSTRxCON<3:0>), as provided in Table 19-3.
Note: The associated TRIS bits must be set to
output (‘0’), to enable the pin output driver,
in order to see the PWM signal on the pin.

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REGISTER 19-5: PSTRxCON: PULSE STEERING CONTROL (1, ACCESS FBFh; 2, FB9h;
3, BANKED F1Ah)(1)
R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1
CMPL1 CMPL0 — STRSYNC STRD STRC STRB STRA
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-6 CMPL<1:0>: Complementary Mode Output Assignment Steering Sync bits
1 = Modulated output pin toggles between PxA and PxB for each period
0 = Complementary output assignment disabled; the STRD:STRA bits are used to determine Steering
mode
bit 5 Unimplemented: Read as ‘0’
bit 4 STRSYNC: Steering Sync bit
1 = Output steering update occurs on next PWM period
0 = Output steering update occurs at the beginning of the instruction cycle boundary
bit 3 STRD: Steering Enable D bit
1 = PxD pin has the PWM waveform with polarity control from CCPxM<1:0>
0 = PxD pin is assigned to port pin
bit 2 STRC: Steering Enable C bit
1 = PxC pin has the PWM waveform with polarity control from CCPxM<1:0>
0 = PxC pin is assigned to port pin
bit 1 STRB: Steering Enable B bit
1 = PxB pin has the PWM waveform with polarity control from CCPxM<1:0>
0 = PxB pin is assigned to port pin
bit 0 STRA: Steering Enable A bit
1 = PxA pin has the PWM waveform with polarity control from CCPxM<1:0>
0 = PxA pin is assigned to port pin

Note 1: The PWM Steering mode is available only when the CCPxCON register bits, CCPxM<3:2> = 11 and
PxM<1:0> = 00.

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FIGURE 19-16: SIMPLIFIED STEERING 19.4.7.1 Steering Synchronization
BLOCK DIAGRAM The STRSYNC bit of the PSTRxCON register gives the
STRA(2) user two choices for when the steering event will
PxA Signal happen. When the STRSYNC bit is ‘0’, the steering
Output Pin
CCPxM1 1 event will happen at the end of the instruction that
writes to the PSTRxCON register. In this case, the out-
PORT Data(1) put signal at the Px<D:A> pins may be an incomplete
0
TRIS PWM waveform. This operation is useful when the user
STRB(2)
firmware needs to immediately remove a PWM signal
from the pin.
CCPxM0 1 Output Pin
When the STRSYNC bit is ‘1’, the effective steering
PORT Data(1) update will happen at the beginning of the next PWM
0
TRIS period. In this case, steering on/off the PWM output will
(2)
STRC always produce a complete PWM waveform.
Figure 19-17 and Figure 19-18 illustrate the timing
1 Output Pin
CCPxM1 diagrams of the PWM steering depending on the
STRSYNC setting.
PORT Data(1) 0
TRIS
STRD(2)

CCPxM0 1 Output Pin

PORT Data(1)
0
TRIS
Note 1: Port outputs are configured as displayed when
the CCPxCON register bits, PxM<1:0> = 00
and CCP1M<3:2> = 11.
2: Single PWM output requires setting at least
one of the STR<D:A> bits.

FIGURE 19-17: EXAMPLE OF STEERING EVENT AT END OF INSTRUCTION (STRSYNC = 0)

PWM Period

PWM

STRn

P1<D:A> PORT Data PORT Data

P1n = PWM

FIGURE 19-18: EXAMPLE OF STEERING EVENT AT BEGINNING OF INSTRUCTION (STRSYNC = 1)

PWM

STRn

P1<D:A> PORT Data PORT Data

P1n = PWM

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19.4.8 OPERATION IN POWER-MANAGED will be set. The ECCPx will then be clocked from the
MODES internal oscillator clock source, which may have a
different clock frequency than the primary clock.
In Sleep mode, all clock sources are disabled. Timer2
will not increment and the state of the module will not 19.4.9 EFFECTS OF A RESET
change. If the ECCPx pin is driving a value, it will con-
tinue to drive that value. When the device wakes up, it Both Power-on Reset and subsequent Resets will force
will continue from this state. If Two-Speed Start-ups are all ports to Input mode and the ECCP registers to their
enabled, the initial start-up frequency from HFINTOSC Reset states.
and the postscaler may not be immediately stable. This forces the ECCP module to reset to a state
In PRI_IDLE mode, the primary clock will continue to compatible with previous, non-enhanced CCP modules
clock the ECCPx module without change. used on other PIC18 and PIC16 devices.

19.4.8.1 Operation with Fail-Safe

Clock Monitor (FSCM)
If the Fail-Safe Clock Monitor (FSCM) is enabled, a clock
failure will force the device into the power-managed
RC_RUN mode and the OSCFIF bit of the PIR2 register

TABLE 19-4: REGISTERS ASSOCIATED WITH ECCP1/2/3 MODULE AND

TIMER1/2/3/4/6/8

File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF
RCON IPEN — CM RI TO PD POR BOR
PIR1 PMPIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF
PIR2 OSCFIF CM2IF CM1IF USBIF BCL1IF HLVDIF TMR3IF CCP2IF
PIR4 CCP10IF CCP9IF CCP8IF CCP7IF CCP6IF CCP5IF CCP4IF CCP3IF
PIE1 PMPIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE
PIE2 OSCFIE CM2IE CM1IE USBIE BCL1IE HLVDIE TMR3IE CCP2IE
PIE4 CCP10IE CCP9IE CCP8IE CCP7IE CCP6IE CCP5IE CCP4IE CCP3IE
IPR1 PMPIP ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP
IPR2 OSCFIP CM2IP CM1IP USBIP BCL1IP HLVDIP TMR3IP CCP2IP
IPR4 CCP10IP CCP9IP CCP8IP CCP7IP CCP6IP CCP5IP CCP4IP CCP3IP
TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0
TRISC TRISC7 TRISC6 — — — TRISC2 TRISC1 TRISC0
TRISE RDPU REPU — — — TRISE2 TRISE1 TRISE0
TMR1H Timer1 Register High Byte
TMR1L Timer1 Register Low Byte
TMR2 Timer2 Register
TMR3H Timer3 Register High Byte
TMR3L Timer3 Register Low Byte
TMR4 Timer4 Register
TMR6 Timer6 Register
TMR8 Timer8 Register
PR2 Timer2 Period Register
PR4 Timer4 Period Register
PR6 Timer6 Period Register
PR8 Timer8 Period Register
T1CON TMR1CS1 TMR1CS0 T1CKPS1 T1CKPS0 T1OSCEN T1SYNC RD16 TMR1ON
T2CON — T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0
T3CON TMR3CS1 TMR3CS0 T3CKPS1 T3CKPS0 T3OSCEN T3SYNC RD16 TMR3ON
T4CON — T4OUTPS3 T4OUTPS2 T4OUTPS1 T4OUTPS0 TMR4ON T4CKPS1 T4CKPS0
T6CON — T6OUTPS3 T6OUTPS2 T6OUTPS1 T6OUTPS0 TMR6ON T6CKPS1 T6CKPS0

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TABLE 19-4: REGISTERS ASSOCIATED WITH ECCP1/2/3 MODULE AND
TIMER1/2/3/4/6/8 (CONTINUED)

File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
T8CON — T8OUTPS3 T8OUTPS2 T8OUTPS1 T8OUTPS0 TMR8ON T8CKPS1 T8CKPS0
CCPR1H Capture/Compare/PWM Register1 High Byte
CCPR1L Capture/Compare/PWM Register1 Low Byte
CCPR2H Capture/Compare/PWM Register2 High Byte
CCPR2L Capture/Compare/PWM Register2 Low Byte
CCPR3H Capture/Compare/PWM Register3 High Byte
CCPR3L Capture/Compare/PWM Register3 Low Byte
CCP1CON P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0
CCP2CON P2M1 P2M0 DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0
CCP3CON P3M1 P3M0 DC3B1 DC3B0 CCP3M3 CCP3M2 CCP3M1 CCP3M0

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20.0 MASTER SYNCHRONOUS All of the MSSP1 module related SPI and I2C I/O
functions are hard-mapped to specific I/O pins.
SERIAL PORT (MSSP)
MODULE For MSSP2 functions:
• SPI I/O functions (SDO2, SDI2, SCK2 and SS2)
The Master Synchronous Serial Port (MSSP) module is are all routed through the Peripheral Pin Select
a serial interface, useful for communicating with other (PPS) module.
peripheral or microcontroller devices. These peripheral
These functions may be configured to use any of
devices include serial EEPROMs, shift registers,
the RPn remappable pins, as described in
display drivers and A/D Converters.
Section 10.7 “Peripheral Pin Select (PPS)”.
• I2C functions (SCL2 and SDA2) have fixed pin
20.1 Master SSP (MSSP) Module
locations.
Overview
On all PIC18F47J53 family devices, the SPI DMA
The MSSP module can operate in one of two modes: capability can only be used in conjunction with MSSP2.
• Serial Peripheral Interface (SPI) The SPI DMA feature is described in Section 20.4
“SPI DMA Module”.
• Inter-Integrated Circuit (I2C™)
- Full Master mode Note: Throughout this section, generic
- Slave mode (with general address call) references to an MSSP module in any of its
operating modes may be interpreted as
The I2C interface supports the following modes in being equally applicable to MSSP1 or
hardware: MSSP2. Register names and module I/O
• Master mode signals use the generic designator ‘x’ to
indicate the use of a numeral to distinguish
• Multi-Master mode
a particular module when required. Control
• Slave mode with 5-bit and 7-bit address masking bit names are not individuated.
(with address masking for both 10-bit and 7-bit
addressing)
All members of the PIC18F47J53 family have two
MSSP modules, designated as MSSP1 and MSSP2.
The modules operate independently:
• PIC18F4XJ53 devices – Both modules can be
configured for either I2C or SPI communication
• PIC18F2XJ53 devices:
- MSSP1 can be used for either I2C or SPI
communication
- MSSP2 can be used only for SPI
communication

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20.2 Control Registers FIGURE 20-1: MSSPx BLOCK DIAGRAM
(SPI MODE)
Each MSSP module has three associated control
registers. These include a status register (SSPxSTAT) Internal
Data Bus
and two control registers (SSPxCON1 and SSPxCON2).
The use of these registers and their individual Configura- Read Write
tion bits differs significantly depending on whether the
MSSP module is operated in SPI or I2C mode. SSPxBUF reg
Additional details are provided under the individual
sections.
SDIx
Note: In devices with more than one MSSP SSPxSR reg
module, it is very important to pay close Shift
SDOx bit 0
attention to the SSPxCON register names. Clock
SSP1CON1 and SSP1CON2 control
different operational aspects of the same
module, while SSP1CON1 and
SSP2CON1 control the same features for
two different modules. SSx
SSx Control
Enable

20.3 SPI Mode Edge

Select
The SPI mode allows 8 bits of data to be synchronously
transmitted and received simultaneously. All four 2
modes of SPI are supported. Clock Select
When MSSP2 is used in SPI mode, it can optionally be
SSPM<3:0>
configured to work with the SPI DMA submodule
described in Section 20.4 “SPI DMA Module”.
SCKx
SMP:CKE 4
2 (TMR2 Output
2
)
To accomplish communication, typically three pins are Edge
used: Select Prescaler TOSC
4, 8, 16, 64
• Serial Data Out (SDOx) –
RC7/CCP10/RX1/DT1/SDO1/RP18 or Data to TXx/RXx in SSPxSR
SDO2/Remappable TRIS bit
• Serial Data In (SDIx) –
RB5/CCP5/KBI1/SDI1/SDA1/RP8 or Note: Only port I/O names are used in this diagram for
SDI2/Remappable the sake of brevity. Refer to the text for a full list of
multiplexed functions.
• Serial Clock (SCKx) –
RB4/CCP4/KBI0/SCK1/SCL1/RP7 or
SCK2/Remappable
Additionally, a fourth pin may be used when in a Slave
mode of operation:
• Slave Select (SSx) – RA5/AN4/C1INC/SS1/
HLVDIN/RCV/RP2 or SS2/Remappable
Figure 20-1 depicts the block diagram of the MSSP
module when operating in SPI mode.

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20.3.1 REGISTERS SSPxSR is the shift register used for shifting data in or
out. SSPxBUF is the buffer register to which data
Each MSSP module has four registers for SPI mode
bytes are written to or read from.
operation. These are:
In receive operations, SSPxSR and SSPxBUF
• MSSPx Control Register 1 (SSPxCON1)
together, create a double-buffered receiver. When
• MSSPx Status Register (SSPxSTAT) SSPxSR receives a complete byte, it is transferred to
• Serial Receive/Transmit Buffer Register SSPxBUF and the SSPxIF interrupt is set.
(SSPxBUF)
During transmission, the SSPxBUF is not
• MSSPx Shift Register (SSPxSR) – Not directly double-buffered. A write to SSPxBUF will write to both
accessible SSPxBUF and SSPxSR.
SSPxCON1 and SSPxSTAT are the control and status
registers in SPI mode operation. The SSPxCON1
register is readable and writable. The lower six bits of
the SSPxSTAT are read-only. The upper two bits of the
SSPxSTAT are read/write.

REGISTER 20-1: SSPxSTAT: MSSPx STATUS REGISTER (SPI MODE) (ACCESS 1, FC7h; 2, F73h)
R/W-1 R/W-1 R-1 R-1 R-1 R-1 R-1 R-1
(1)
SMP CKE D/A P S R/W UA BF
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 SMP: Sample bit

SPI Master mode:
1 = Input data sampled at end of data output time
0 = Input data sampled at middle of data output time
SPI Slave mode:
SMP must be cleared when SPI is used in Slave mode.
bit 6 CKE: SPI Clock Select bit(1)
1 = Transmit occurs on transition from active to Idle clock state
0 = Transmit occurs on transition from Idle to active clock state
bit 5 D/A: Data/Address bit
Used in I2C™ mode only.
bit 4 P: Stop bit
Used in I2C mode only; this bit is cleared when the MSSP module is disabled, SSPEN is cleared.
bit 3 S: Start bit
Used in I2C mode only.
bit 2 R/W: Read/Write Information bit
Used in I2C mode only.
bit 1 UA: Update Address bit
Used in I2C mode only.
bit 0 BF: Buffer Full Status bit
1 = Receive complete, SSPxBUF is full
0 = Receive not complete, SSPxBUF is empty

Note 1: Polarity of the clock state is set by the CKP bit (SSPxCON1<4>).

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REGISTER 20-2: SSPxCON1: MSSPx CONTROL REGISTER 1 (SPI MODE)
(1, ACCESS FC6h; 2, F72h)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
WCOL SSPOV(1) SSPEN(2) CKP SSPM3(3) SSPM2(3) SSPM1(3) SSPM0(3)
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 WCOL: Write Collision Detect bit

1 = The SSPxBUF register is written while it is still transmitting the previous word (must be cleared in
software)
0 = No collision
bit 6 SSPOV: Receive Overflow Indicator bit(1)
SPI Slave mode:
1 = A new byte is received while the SSPxBUF register is still holding the previous data. In case of over-
flow, the data in SSPxSR is lost. Overflow can only occur in Slave mode. The user must read the
SSPxBUF, even if only transmitting data, to avoid setting overflow (must be cleared in software).
0 = No overflow
bit 5 SSPEN: Master Synchronous Serial Port Enable bit(2)
1 = Enables serial port and configures SCKx, SDOx, SDIx and SSx as serial port pins
0 = Disables serial port and configures these pins as I/O port pins
bit 4 CKP: Clock Polarity Select bit
1 = Idle state for clock is a high level
0 = Idle state for clock is a low level
bit 3-0 SSPM<3:0>: Master Synchronous Serial Port Mode Select bits(3)
0101 = SPI Slave mode, clock = SCKx pin; SSx pin control disabled, SSx can be used as I/O pin
0100 = SPI Slave mode, clock = SCKx pin; SSx pin control enabled
0011 = SPI Master mode, clock = TMR2 output/2
0010 = SPI Master mode, clock = FOSC/64
0001 = SPI Master mode, clock = FOSC/16
1010 = SPI Master mode, clock = FOSC/8
0000 = SPI Master mode, clock = FOSC/4

Note 1: In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by
writing to the SSPxBUF register.
2: When enabled, this pin must be properly configured as input or output.
3: Bit combinations not specifically listed here are either reserved or implemented in I2C™ mode only.

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20.3.2 OPERATION The Buffer Full bit, BF (SSPxSTAT<0>), indicates when
SSPxBUF has been loaded with the received data
When initializing the SPI, several options need to be
(transmission is complete). When the SSPxBUF is read,
specified. This is done by programming the appropriate
the BF bit is cleared. This data may be irrelevant if the
control bits (SSPxCON1<5:0> and SSPxSTAT<7:6>).
SPI is only a transmitter. Generally, the MSSP interrupt
These control bits allow the following to be specified:
is used to determine when the transmission/reception
• Master mode (SCKx is the clock output) has completed. If the interrupt method is not going to be
• Slave mode (SCKx is the clock input) used, then software polling can be done to ensure that a
• Clock Polarity (Idle state of SCKx) write collision does not occur.
• Data Input Sample Phase (middle or end of data Example 20-1 provides the loading of the SSPxBUF
output time) (SSPxSR) for data transmission.
• Clock Edge (output data on rising/falling edge of The SSPxSR is not directly readable or writable and
SCKx) can only be accessed by addressing the SSPxBUF
• Clock Rate (Master mode only) register. Additionally, the SSPxSTAT register indicates
• Slave Select mode (Slave mode only) the various status conditions.
Each MSSP module consists of a transmit/receive shift 20.3.3 OPEN-DRAIN OUTPUT OPTION
register (SSPxSR) and a buffer register (SSPxBUF).
The SSPxSR shifts the data in and out of the device, The drivers for the SDOx output and SCKx clock pins
MSb first. The SSPxBUF holds the data that was written can be optionally configured as open-drain outputs.
to the SSPxSR until the received data is ready. Once the This feature allows the voltage level on the pin to be
8 bits of data have been received, that byte is moved to pulled to a higher level through an external pull-up
the SSPxBUF register. Then, the Buffer Full (BF) detect resistor, provided the SDOx or SCKx pin is not multi-
bit (SSPxSTAT<0>) and the interrupt flag bit, SSPxIF, plexed with an ANx analog function. This allows the
are set. This double-buffering of the received data output to communicate with external circuits without the
(SSPxBUF) allows the next byte to start reception before need for additional level shifters. For more information,
reading the data that was just received. see Section 10.1.4 “Open-Drain Outputs”.

Any write to the SSPxBUF register during transmission The open-drain output option is controlled by the
or reception of data will be ignored and the Write SPI2OD and SPI1OD bits (ODCON3<1:0>). Setting an
Collision Detect bit, WCOL (SSPxCON1<7>), will be set. SPIxOD bit configures both the SDOx and SCKx pins for
User software must clear the WCOL bit so that it can be the corresponding open-drain operation.
determined if the following write(s) to the SSPxBUF
register completed successfully.
Note: When the application software is expecting
to receive valid data, the SSPxBUF should
be read before the next byte of transfer
data is written to the SSPxBUF. Application
software should follow this process even
when the current contents of SSPxBUF
are not important.

EXAMPLE 20-1: LOADING THE SSP1BUF (SSP1SR) REGISTER

LOOP BTFSS SSP1STAT, BF ;Has data been received (transmit complete)?
BRA LOOP ;No
MOVF SSP1BUF, W ;WREG reg = contents of SSP1BUF
MOVWF RXDATA ;Save in user RAM, if data is meaningful
MOVF TXDATA, W ;W reg = contents of TXDATA
MOVWF SSP1BUF ;New data to xmit

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20.3.4 ENABLING SPI I/O Any MSSP1 serial port function that is not desired may
be overridden by programming the corresponding Data
To enable the serial port, MSSP Enable bit, SSPEN
Direction (TRIS) register to the opposite value. If
(SSPxCON1<5>), must be set. To reset or reconfigure
individual MSSP2 serial port functions will not be used,
SPI mode, clear the SSPEN bit, re-initialize the
they may be left unmapped.
SSPxCON1 registers and then set the SSPEN bit. This
configures the SDIx, SDOx, SCKx and SSx pins as Note: When MSSP2 is used in SPI Master
serial port pins. For the pins to behave as the serial port mode, the SCK2 function must be config-
function, the appropriate TRISx bits, PCFGx bits and ured as both an output and an input in the
Peripheral Pin Select registers (if using MSSP2) should PPS module. SCK2 must be initialized as
be correctly initialized prior to setting the SSPEN bit. an output pin (by writing 0x0A to one of the
A typical SPI serial port initialization process follows: RPORx registers). Additionally, SCK2IN
must also be mapped to the same pin by
• Initialize the ODCON3 register (optional initializing the RPINR22 register. Failure to
open-drain output control) initialize SCK2/SCK2IN as both output
• Initialize the remappable pin functions (if using and input will prevent the module from
MSSP2, see Section 10.7 “Peripheral Pin receiving data on the SDI2 pin, as the
Select (PPS)”) module uses the SCK2IN signal to latch
• Initialize the SCKx/LAT value to the desired Idle the received data.
SCKx level (if master device)
• Initialize the SCKx/PCFGx bit (if in Slave mode 20.3.5 TYPICAL CONNECTION
and multiplexed with the ANx function) Figure 20-2 illustrates a typical connection between two
• Initialize the SCKx/TRIS bit as output (Master microcontrollers. The master controller (Processor 1)
mode) or input (Slave mode) initiates the data transfer by sending the SCKx signal.
• Initialize the SDIx/PCFGx bit (if SDIx is Data is shifted out of both shift registers on their pro-
multiplexed with the ANx function) grammed clock edge and latched on the opposite edge
• Initialize the SDIx/TRIS bit of the clock. Both processors should be programmed to
the same Clock Polarity (CKP), then both controllers
• Initialize the SSx/PCFG bit (if in Slave mode and
would send and receive data at the same time. Whether
multiplexed the with ANx function)
the data is meaningful (or dummy data) depends on the
• Initialize the SSx/TRIS bit (Slave modes) application software. This leads to three scenarios for
• Initialize the SDOx/TRIS bit data transmission:
• Initialize the SSPxSTAT register • Master sends valid data–Slave sends dummy
• Initialize the SSPxCON1 register data
• Set the SSPEN bit to enable the module • Master sends valid data–Slave sends valid data
• Master sends dummy data–Slave sends valid data

FIGURE 20-2: SPI MASTER/SLAVE CONNECTION

SPI Master SSPM<3:0> = 00xxb SPI Slave SSPM<3:0> = 010xb

SDOx SDIx

Serial Input Buffer Serial Input Buffer

(SSPxBUF) (SSPxBUF)

Shift Register SDIx SDOx Shift Register

(SSPxSR) (SSPxSR)

MSb LSb MSb LSb

Serial Clock
SCKx SCKx
PROCESSOR 1 PROCESSOR 2

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20.3.6 MASTER MODE Most Significant Byte (MSB) is transmitted first. In
Master mode, the SPI clock rate (bit rate) is
The master can initiate the data transfer at any time
user-programmable to be one of the following:
because it controls the SCKx. The master determines
when the slave (Processor 2, Figure 20-2) is to • FOSC/4 (or TCY)
broadcast data by the software protocol. • FOSC/8 (or 2 • TCY)
In Master mode, the data is transmitted/received as • FOSC/16 (or 4 • TCY)
soon as the SSPxBUF register is written to. If the SPI • FOSC/64 (or 16 • TCY)
is only going to receive, the SDOx output could be dis- • Timer2 output/2
abled (programmed as an input). The SSPxSR register
will continue to shift in the signal present on the SDIx When using the Timer2 output/2 option, the Period
pin at the programmed clock rate. As each byte is Register 2 (PR2) can be used to determine the SPI bit
received, it will be loaded into the SSPxBUF register as rate. However, only PR2 values of 0x01 to 0xFF are
if it is a normal received byte (interrupts and status bits valid in this mode.
are appropriately set). This could be useful in receiver Figure 20-3 illustrates the waveforms for Master mode.
applications as a “Line Activity Monitor” mode. When the CKE bit is set, the SDOx data is valid before
The CKP is selected by appropriately programming the there is a clock edge on SCKx. The change of the input
CKP bit (SSPxCON1<4>). This then, would give sample is shown based on the state of the SMP bit. The
waveforms for SPI communication, as illustrated in time when the SSPxBUF is loaded with the received
Figure 20-3, Figure 20-5 and Figure 20-6, where the data is shown.

FIGURE 20-3: SPI MODE WAVEFORM (MASTER MODE)

Write to
SSPxBUF

SCKx
(CKP = 0
CKE = 0)

SCKx
(CKP = 1
CKE = 0)
4 Clock
SCKx Modes
(CKP = 0
CKE = 1)

SCKx
(CKP = 1
CKE = 1)

SDOx bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

(CKE = 0)

SDOx bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

(CKE = 1)
SDIx
(SMP = 0) bit 7 bit 0
Input
Sample
(SMP = 0)
SDIx
(SMP = 1) bit 0
bit 7

Input
Sample
(SMP = 1)
SSPxIF
Next Q4 Cycle
SSPxSR to after Q2
SSPxBUF

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20.3.7 SLAVE MODE transmitted byte and becomes a floating output.
External pull-up/pull-down resistors may be desirable
In Slave mode, the data is transmitted and received as
depending on the application.
the external clock pulses appear on SCKx. When the
last bit is latched, the SSPxIF interrupt flag bit is set. Note 1: When the SPI is in Slave mode with
While in Slave mode, the external clock is supplied by the SSx pin control enabled
the external clock source on the SCKx pin. This (SSPxCON1<3:0> = 0100), the SPI
external clock must meet the minimum high and low module will reset if the SSx pin is set to
times as specified in the electrical specifications. VDD.
While in Sleep mode, the slave can transmit/receive 2: If the SPI is used in Slave mode with CKE
data. When a byte is received, the device can be set, then the SSx pin control must be
configured to wake-up from Sleep. enabled.
When the SPI module resets, the bit counter is forced
20.3.8 SLAVE SELECT to ‘0’. This can be done by either forcing the SSx pin to
SYNCHRONIZATION a high level or clearing the SSPEN bit.
The SSx pin allows a Synchronous Slave mode. The To emulate two-wire communication, the SDOx pin can
SPI must be in Slave mode with the SSx pin control be connected to the SDIx pin. When the SPI needs to
enabled (SSPxCON1<3:0> = 04h). When the SSx pin operate as a receiver, the SDOx pin can be configured
is low, transmission and reception are enabled and the as an input. This disables transmissions from the
SDOx pin is driven. When the SSx pin goes high, the SDOx. The SDIx can always be left as an input (SDIx
SDOx pin is no longer driven, even if in the middle of a function) since it cannot create a bus conflict.

FIGURE 20-4: SLAVE SYNCHRONIZATION WAVEFORM

SSx

SCKx
(CKP = 0
CKE = 0)

SCKx
(CKP = 1
CKE = 0)

Write to
SSPxBUF

SDOx bit 7 bit 6 bit 7 bit 0

SDIx bit 0
(SMP = 0) bit 7 bit 7
Input
Sample
(SMP = 0)

SSPxIF
Interrupt
Flag
Next Q4 Cycle
SSPxSR to after Q2
SSPxBUF

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FIGURE 20-5: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0)

SSx
Optional

SCKx
(CKP = 0
CKE = 0)

SCKx
(CKP = 1
CKE = 0)
Write to
SSPxBUF

SDOx bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

SDIx
(SMP = 0) bit 7 bit 0
Input
Sample
(SMP = 0)
SSPxIF
Interrupt
Flag
Next Q4 Cycle
SSPxSR to after Q2
SSPxBUF

FIGURE 20-6: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1)

SSx
Not Optional

SCKx
(CKP = 0
CKE = 1)

SCKx
(CKP = 1
CKE = 1)
Write to
SSPxBUF

SDOx bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

SDIx
(SMP = 0) bit 7 bit 0
Input
Sample
(SMP = 0)

SSPxIF
Interrupt
Flag
Next Q4 Cycle
after Q2
SSPxSR to
SSPxBUF

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20.3.9 OPERATION IN POWER-MANAGED 20.3.11 BUS MODE COMPATIBILITY
MODES Table 20-1 provides the compatibility between the
In SPI Master mode, module clocks may be operating standard SPI modes and the states of the CKP and
at a different speed than when in full-power mode. In CKE control bits.
the case of Sleep mode, all clocks are halted.
TABLE 20-1: SPI BUS MODES
In Idle modes, a clock is provided to the peripherals.
That clock can be from the primary clock source, the Standard SPI Mode Control Bits State
secondary clock (Timer1 oscillator) or the INTOSC Terminology
source. See Section 3.5 “Clock Sources and CKP CKE
Oscillator Switching” for additional information. 0, 0 0 1
In most cases, the speed that the master clocks SPI 0, 1 0 0
data is not important; however, this should be 1, 0 1 1
evaluated for each system.
1, 1 1 0
If MSSP interrupts are enabled, they can wake the
controller from Sleep mode, or one of the Idle modes, There is also an SMP bit, which controls when the data
when the master completes sending data. If an exit is sampled.
from Sleep or Idle mode is not desired, MSSP
interrupts should be disabled. 20.3.12 SPI CLOCK SPEED AND MODULE
INTERACTIONS
If the Sleep mode is selected, all module clocks are
halted and the transmission/reception will remain in Because MSSP1 and MSSP2 are independent
that state until the device wakes. After the device modules, they can operate simultaneously at different
returns to Run mode, the module will resume data rates. Setting the SSPM<3:0> bits of the
transmitting and receiving data. SSPxCON1 register determines the rate for the
corresponding module.
In SPI Slave mode, the SPI Transmit/Receive Shift
register operates asynchronously to the device. This An exception is when both modules use Timer2 as a
allows the device to be placed in any power-managed time base in Master mode. In this instance, any
mode and data to be shifted into the SPI changes to the Timer2 module’s operation will affect
Transmit/Receive Shift register. When all 8 bits have both MSSP modules equally. If different bit rates are
been received, the MSSPx interrupt flag bit will be set, required for each module, the user should select one of
and if enabled, will wake the device. the other three time base options for one of the
modules.
20.3.10 EFFECTS OF A RESET
A Reset disables the MSSP modules and terminates
the current transfer.

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TABLE 20-2: REGISTERS ASSOCIATED WITH SPI OPERATION
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF
PIR1 (2)
PMPIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF
(2)
PIE1 PMPIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE
IPR1 PMPIP(2) ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP
PIR3 SSP2IF BCL2IF RC2IF TX2IF TMR4IF CTMUIF TMR3GIF RTCCIF
PIE3 SSP2IE BCL2IE RC2IE TX2IE TMR4IE CTMUIE TMR3GIE RTCCIE
IPR3 SSP2IP BCL2IP RC2IP TX2IP TMR4IP CTMUIP TMR3GIP RTCCIP
TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0
TRISC TRISC7 TRISC6 — — — TRISC2 TRISC1 TRISC0
TRISD TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0
SSP1BUF MSSP1 Receive Buffer/Transmit Register
SSPxCON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0
SSPxSTAT SMP CKE D/A P S R/W UA BF
SSP2BUF MSSP2 Receive Buffer/Transmit Register
ODCON3(1) — — — — — — SPI2OD SPI1OD
Legend: Shaded cells are not used by the MSSPx module in SPI mode.
Note 1: Configuration SFR overlaps with default SFR at this address; available only when WDTCON<4> = 1.
2: These bits are only available on 44-pin devices.

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20.4 SPI DMA MODULE 20.4.3 IDLE AND SLEEP
CONSIDERATIONS
The SPI DMA module contains control logic to allow the
MSSP2 module to perform SPI direct memory access The SPI DMA module remains fully functional when the
transfers. This enables the module to quickly transmit microcontroller is in Idle mode.
or receive large amounts of data with relatively little During normal Sleep, the SPI DMA module is not func-
CPU intervention. When the SPI DMA module is used, tional and should not be used. To avoid corrupting a
MSSP2 can directly read and write to general purpose transfer, user firmware should be careful to make
SRAM. When the SPI DMA module is not enabled, certain that pending DMA operations are complete by
MSSP2 functions normally, but without DMA capability. polling the DMAEN bit in the DMACON1 register prior
The SPI DMA module is composed of control logic, a to putting the microcontroller into Sleep.
Destination Receive Address Pointer, a Transmit In SPI Slave modes, the MSSP2 module is capable of
Source Address Pointer, an interrupt manager and a transmitting and/or receiving one byte of data while in
Byte Count register for setting the size of each DMA Sleep mode. This allows the SSP2IF flag in the PIR3
transfer. The DMA module may be used with all SPI register to be used as a wake-up source. When the
Master and Slave modes, and supports both DMAEN bit is cleared, the SPI DMA module is
half-duplex and full-duplex transfers. effectively disabled, and the MSSP2 module functions
normally, but without DMA capabilities. If the DMAEN
20.4.1 I/O PIN CONSIDERATIONS bit is clear prior to entering Sleep, it is still possible to
When enabled, the SPI DMA module uses the MSSP2 use the SSP2IF as a wake-up source without any data
module. All SPI input and output signals, related to loss.
MSSP2, are routed through the Peripheral Pin Select Neither MSSP2 nor the SPI DMA module will provide
module. The appropriate initialization procedure, as any functionality in Deep Sleep. Upon exiting from
described in Section 20.4.6 “Using the SPI DMA Deep Sleep, all of the I/O pins, MSSP2 and SPI DMA
Module”, will need to be followed prior to using the SPI related registers will need to be fully re-initialized
DMA module. The output pins assigned to the SDO2 before the SPI DMA module can be used again.
and SCK2 functions can optionally be configured as
open-drain outputs, such as for level shifting operations 20.4.4 REGISTERS
mentioned in the same section.
The SPI DMA engine is enabled and controlled by the
20.4.2 RAM TO RAM COPY OPERATIONS following Special Function Registers:

Although the SPI DMA module is primarily intended to • DMACON1 • DMACON2

be used for SPI communication purposes, the module • TXADDRH • TXADDRL
can also be used to perform RAM to RAM copy opera- • RXADDRH • RXADDRL
tions. To do this, configure the module for Full-Duplex
Master mode operation, but assign the SDO2 output • DMABCH • DMABCL
and SDI2 input functions onto the same RPn pin in the
PPS module. Also assign SCK2 out and SCK2 in onto
the same RPn pin (a different pin than used for SDO2
and SDI2). This will allow the module to operate in
Loopback mode, providing RAM copy capability.

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20.4.4.1 DMACON1 protocols involving time-outs if the bus remains Idle for
too long. When DLYINTEN = 1, the DLYLVL<3:0>
The DMACON1 register is used to select the main
interrupts occur normally according to the selected
operating mode of the SPI DMA module. The SSCON1
setting.
and SSCON0 bits are used to control the slave select
pin. SPI Slave mode, DLYINTEN = 0: In this mode, the
time-out based interrupt is disabled. No additional
When MSSP2 is used in SPI Master mode with the SPI
SSP2IF interrupt events will be generated by the SPI
DMA module, SSDMA can be controlled by the DMA
DMA module, other than those indicated by the
module as an output pin. If MSSP2 will be used to com-
INTLVL<3:0> bits in the DMACON2 register. In this
municate with an SPI slave device that needs the SSx
mode, always set DLYCYC<3:0> = 0000.
pin to be toggled periodically, the SPI DMA hardware
can automatically be used to deassert SSx between SPI Master mode, DLYINTEN = 0: The DLYCYC<3:0>
each byte, every two bytes or every four bytes. bits in the DMACON2 register determine the amount of
additional inter-byte delay, which is added by the SPI
Alternatively, user firmware can manually generate
DMA module during a transfer. The Master mode SS2
slave select signals with normal general purpose I/O
output feature may be used.
pins, if required by the slave device(s).
SPI Master mode, DLYINTEN = 1: The amount of
When the TXINC bit is set, the TXADDR register will
hardware overhead is slightly reduced in this mode,
automatically increment after each transmitted byte.
and the minimum inter-byte delay is 8 TCY for FOSC/4,
Automatic transmit address increment can be disabled
9 TCY for FOSC/16 and 15 TCY for FOSC/64. This mode
by clearing the TXINC bit. If the automatic transmit
can potentially be used to obtain slightly higher effec-
address increment is disabled, each byte which is out-
tive SPI bandwidth. In this mode, the SS2 control
put on SDO2, will be the same (the contents of the
feature cannot be used, and should always be disabled
SRAM pointed to by the TXADDR register) for the
(DMACON1<7:6> = 00). Additionally, the interrupt
entire DMA transaction.
generating hardware (used in Slave mode) remains
When the RXINC bit is set, the RXADDR register will active. To avoid extraneous SSP2IF interrupt events,
automatically increment after each received byte. set the DMACON2 delay bits, DLYCYC<3:0> = 1111,
Automatic receive address increment can be disabled and ensure that the SPI serial clock rate is no slower
by clearing the RXINC bit. If RXINC is disabled in than FOSC/64.
Full-Duplex or Half-Duplex Receive modes, all incom-
In SPI Master modes, the DMAEN bit is used to enable
ing data bytes on SDI2 will overwrite the same memory
the SPI DMA module and to initiate an SPI DMA trans-
location pointed to by the RXADDR register. After the
action. After user firmware sets the DMAEN bit, the
SPI DMA transaction has completed, the last received
DMA hardware will begin transmitting and/or receiving
byte will reside in the memory location pointed to by the
data bytes according to the configuration used. In SPI
RXADDR register.
Slave modes, setting the DMAEN bit will finish the
The SPI DMA module can be used for either half-duplex initialization steps needed to prepare the SPI DMA
receive only communication, half-duplex transmit only module for communication (which must still be initiated
communication or full-duplex simultaneous transmit and by the master device).
receive operations. All modes are available for both SPI
To avoid possible data corruption, once the DMAEN bit
master and SPI slave configurations. The DUPLEX0
is set, user firmware should not attempt to modify any
and DUPLEX1 bits can be used to select the desired
of the MSSP2 or SPI DMA related registers, with the
operating mode.
exception of the INTLVL bits in the DMACON2 register.
The behavior of the DLYINTEN bit varies greatly
If user firmware wants to halt an ongoing DMA transac-
depending on the SPI operating mode. For example
tion, the DMAEN bit can be manually cleared by the
behavior for each of the modes, see Figure 20-3
firmware. Clearing the DMAEN bit while a byte is
through Figure 20-6.
currently being transmitted will not immediately halt the
SPI Slave mode, DLYINTEN = 1: In this mode, an byte in progress. Instead, any byte currently in
SSP2IF interrupt will be generated during a transfer if progress will be completed before the MSSP2 and SPI
the time between successful byte transmission events DMA modules go back to their Idle conditions. If user
is longer than the value set by the DLYCYC<3:0> bits firmware clears the DMAEN bit, the TXADDR,
in the DMACON2 register. This interrupt allows slave RXADDR and DMABC registers will no longer update,
firmware to know that the master device is taking an and the DMA module will no longer make any
unusually large amount of time between byte transmis- additional read or writes to SRAM; therefore, state
sions. For example, this information may be useful for information can be lost.
implementing application defined communication

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REGISTER 20-3: DMACON1: DMA CONTROL REGISTER 1 (ACCESS F88h)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
SSCON1 SSCON0 TXINC RXINC DUPLEX1 DUPLEX0 DLYINTEN DMAEN
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-6 SSCON<1:0>: SSDMA Output Control bits (Master modes only)
11 = SSDMA is asserted for the duration of 4 bytes; DLYINTEN is always reset low
01 = SSDMA is asserted for the duration of 2 bytes; DLYINTEN is always reset low
10 = SSDMA is asserted for the duration of 1 byte; DLYINTEN is always reset low
00 = SSDMA is not controlled by the DMA module; DLYINTEN bit is software programmable
bit 5 TXINC: Transmit Address Increment Enable bit
Allows the transmit address to increment as the transfer progresses.
1 = The transmit address is to be incremented from the initial value of TXADDR<11:0>
0 = The transmit address is always set to the initial value of TXADDR<11:0>
bit 4 RXINC: Receive Address Increment Enable bit
Allows the receive address to increment as the transfer progresses.
1 = The received address is to be incremented from the intial value of RXADDR<11:0>
0 = The received address is always set to the initial value of RXADDR<11:0>
bit 3-2 DUPLEX<1:0>: Transmit/Receive Operating Mode Select bits
10 = SPI DMA operates in Full-Duplex mode, data is simultaneously transmitted and received
01 = DMA operates in Half-Duplex mode, data is transmitted only
00 = DMA operates in Half-Duplex mode, data is received only
bit 1 DLYINTEN: Delay Interrupt Enable bit
Enables the interrupt to be invoked after the number of TCY cycles specified in DLYCYC<2:0> has
elapsed from the latest completed transfer.
1 = The interrupt is enabled, SSCON<1:0> must be set to ‘00’
0 = The interrupt is disabled
bit 0 DMAEN: DMA Operation Start/Stop bit
This bit is set by the users’ software to start the DMA operation. It is reset back to zero by the DMA
engine when the DMA operation is completed or aborted.
1 = DMA is in session
0 = DMA is not in session

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20.4.4.2 DMACON2 to control how much time the module will Idle between
bytes in a transfer. By default, the hardware requires a
The DMACON2 register contains control bits for
minimum delay of 8 TCY for FOSC/4, 9 TCY for FOSC/16
controlling interrupt generation and inter-byte delay
and 15 TCY for FOSC/64. An additional delay can be
behavior. The INTLVL<3:0> bits are used to select when
added with the DLYCYC bits. In SPI Slave modes, the
an SSP2IF interrupt should be generated. The function
DLYCYC<3:0> bits may optionally be used to trigger an
of the DLYCYC<3:0> bits depends on the SPI operating
additional time-out based interrupt.
mode (Master/Slave), as well as the DLYINTEN setting.
In SPI Master mode, the DLYCYC<3:0> bits can be used

REGISTER 20-4: DMACON2: DMA CONTROL REGISTER 2 (ACCESS F86h)

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
DLYCYC3 DLYCYC2 DLYCYC1 DLYCYC0 INTLVL3 INTLVL2 INTLVL1 INTLVL0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-4 DLYCYC<3:0>: Delay Cycle Selection bits

When DLYINTEN = 0, these bits specify the additional delay (above the base overhead of the hard-
ware) in number of TCY cycles before the SSP2BUF register is written again for the next transfer. When
DLYINTEN = 1, these bits specify the delay in number of TCY cycles from the latest completed transfer
before an interrupt to the CPU is invoked. In this case, the additional delay before the SSP2BUF
register is written again is 1 TCY + (base overhead of hardware).
1111 = Delay time in number of instruction cycles is 2,048 cycles
1110 = Delay time in number of instruction cycles is 1,024 cycles
1101 = Delay time in number of instruction cycles is 896 cycles
1100 = Delay time in number of instruction cycles is 768 cycles
1011 = Delay time in number of instruction cycles is 640 cycles
1010 = Delay time in number of instruction cycles is 512 cycles
1001 = Delay time in number of instruction cycles is 384 cycles
1000 = Delay time in number of instruction cycles is 256 cycles
0111 = Delay time in number of instruction cycles is 128 cycles
0110 = Delay time in number of instruction cycles is 64 cycles
0101 = Delay time in number of instruction cycles is 32 cycles
0100 = Delay time in number of instruction cycles is 16 cycles
0011 = Delay time in number of instruction cycles is 8 cycles
0010 = Delay time in number of instruction cycles is 4 cycles
0001 = Delay time in number of instruction cycles is 2 cycles
0000 = Delay time in number of instruction cycles is 1 cycle
bit 3-0 INTLVL<3:0>: Watermark Interrupt Enable bits
These bits specify the amount of remaining data yet to be transferred (transmitted and/or received)
upon which an interrupt is generated.
1111 = Amount of remaining data to be transferred is 576 bytes
1110 = Amount of remaining data to be transferred is 512 bytes
1101 = Amount of remaining data to be transferred is 448 bytes
1100 = Amount of remaining data to be transferred is 384 bytes
1011 = Amount of remaining data to be transferred is 320 bytes
1010 = Amount of remaining data to be transferred is 256 bytes
1001 = Amount of remaining data to be transferred is 192 bytes
1000 = Amount of remaining data to be transferred is 128 bytes
0111 = Amount of remaining data to be transferred is 67 bytes
0110 = Amount of remaining data to be transferred is 32 bytes
0101 = Amount of remaining data to be transferred is 16 bytes
0100 = Amount of remaining data to be transferred is 8 bytes
0011 = Amount of remaining data to be transferred is 4 bytes
0010 = Amount of remaining data to be transferred is 2 bytes
0001 = Amount of remaining data to be transferred is 1 byte
0000 = Transfer complete

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20.4.4.3 DMABCH and DMABCL The SPI DMA module can write received data to all
general purpose memory on the device, including
The DMABCH and DMABCL register pair forms a 10-bit
memory used for USB endpoint buffers. The SPI DMA
Byte Count register, which is used by the SPI DMA
module cannot be used to modify the Special Function
module to send/receive up to 1,024 bytes for each DMA
Registers contained in Banks 14 and 15.
transaction. When the DMA module is actively running
(DMAEN = 1), the DMA Byte Count register decrements
20.4.5 INTERRUPTS
after each byte is transmitted/received. The DMA trans-
action will halt and the DMAEN bit will be automatically The SPI DMA module alters the behavior of the SSP2IF
cleared by hardware after the last byte has completed. interrupt flag. In normal non-DMA modes, the SSP2IF is
After a DMA transaction is complete, the DMABC set once after every single byte is transmitted/received
register will read 0x000. through the MSSP2 module. When MSSP2 is used with
the SPI DMA module, the SSP2IF interrupt flag will be
Prior to initiating a DMA transaction by setting the
set according to the user-selected INTLVL<3:0> value
DMAEN bit, user firmware should load the appropriate
specified in the DMACON2 register. The SSP2IF inter-
value into the DMABCH/DMABCL registers. The
rupt condition will also be generated once the SPI DMA
DMABC is a “base zero” counter, so the actual number
transaction has fully completed and the DMAEN bit has
of bytes which will be transmitted follows in
been cleared by hardware.
Equation 20-1.
The SSP2IF flag becomes set once the DMA byte count
For example, if user firmware wants to transmit 7 bytes
value indicates that the specified INTLVL has been
in one transaction, DMABC should be loaded with
reached. For example, if DMACON2<3:0> = 0101
006h. Similarly, if user firmware wishes to transmit
(16 bytes remaining), the SSP2IF interrupt flag will
1,024 bytes, DMABC should be loaded with 3FFh.
become set once DMABC reaches 00Fh. If user
firmware then clears the SSP2IF interrupt flag, the flag
EQUATION 20-1: BYTES TRANSMITTED will not be set again by the hardware until after all bytes
FOR A GIVEN DMABC have been fully transmitted and the DMA transaction is
complete.
Bytes XMIT   DMABC + 1 
Note: User firmware may modify the INTLVL bits
while a DMA transaction is in progress
20.4.4.4 TXADDRH and TXADDRL (DMAEN = 1). If an INTLVL value is
selected which is higher than the actual
The TXADDRH and TXADDRL registers pair together remaining number of bytes (indicated by
to form a 12-bit Transmit Source Address Pointer DMABC + 1), the SSP2IF interrupt flag
register. In modes that use TXADDR (Full-Duplex and will immediately become set.
Half-Duplex Transmit), the TXADDR will be incre-
mented after each byte is transmitted. Transmitted data For example, if DMABC = 00Fh (implying 16 bytes are
bytes will be taken from the memory location pointed to remaining) and user firmware writes ‘1111’ to
by the TXADDR register. The contents of the memory INTLVL<3:0> (interrupt when 576 bytes remaining),
locations pointed to by TXADDR will not be modified by the SSP2IF interrupt flag will immediately become set.
the DMA module during a transmission. If user firmware clears this interrupt flag, a new inter-
rupt condition will not be generated until either: user
The SPI DMA module can read from, and transmit data firmware again writes INTLVL with an interrupt level
from, all general purpose memory on the device, includ- higher than the actual remaining level, or the DMA
ing memory used for USB endpoint buffers. The SPI transaction completes and the DMAEN bit is cleared.
DMA module cannot be used to read from the Special
Function Registers (SFRs) contained in Banks 14 and Note: If the INTLVL bits are modified while a
15. DMA transaction is in progress, care
should be taken to avoid inadvertently
20.4.4.5 RXADDRH and RXADDRL changing the DLYCYC<3:0> value.
The RXADDRH and RXADDRL registers pair together
to form a 12-bit Receive Destination Address Pointer.
In modes that use RXADDR (Full-Duplex and
Half-Duplex Receive), the RXADDR register will be
incremented after each byte is received. Received data
bytes will be stored at the memory location pointed to
by the RXADDR register.

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20.4.6 USING THE SPI DMA MODULE 4. Detect the SSP2IF interrupt condition (PIR3<7).
The following steps would typically be taken to enable a) If the interrupt was configured to occur at
and use the SPI DMA module: the completion of the SPI DMA transaction,
the DMAEN bit (DMACON1<0>) will be
1. Configure the I/O pins, which will be used by clear. User firmware may prepare the
MSSP2. module for another transaction by repeating
a) Assign SCK2, SDO2, SDI2 and SS2 to the steps 3.b through 3.e.
RPn pins as appropriate for the SPI mode b) If the interrupt was configured to occur prior
which will be used. Only functions which will to the completion of the SPI DMA trans-
be used need to be assigned to a pin. action, the DMAEN bit may still be set,
b) Initialize the associated LATx registers for indicating the transaction is still in progress.
the desired Idle SPI bus state. User firmware would typically use this inter-
c) If Open-Drain Output mode on SDO2 and rupt condition to begin preparing new data
SCK2 (Master mode) is desired, set for the next DMA transaction. Firmware
ODCON3<1>. should not repeat steps 3.b. through 3.e.
d) Configure corresponding TRISx bits for until the DMAEN bit is cleared by the
each I/O pin used. hardware, indicating the transaction is
2. Configure and enable MSSP2 for the desired complete.
SPI operating mode. Example 20-2 provides example code demonstrating
a) Select the desired operating mode (Master the initialization process and the steps needed to use
or Slave, SPI Mode 0, 1, 2 and 3) and con- the SPI DMA module to perform a 512-byte Full-Duplex
figure the module by writing to the Master mode transfer.
SSP2STAT and SSP2CON1 registers.
b) Enable MSSP2 by setting SSP2CON1<5> = 1.
3. Configure the SPI DMA engine.
a) Select the desired operating mode by
writing the appropriate values to
DMACON2 and DMACON1.
b) Initialize the TXADDRH/TXADDRL Pointer
(Full-Duplex or Half-Duplex Transmit Only
mode).
c) Initialize the RXADDRH/RXADDRL Pointer
(Full-Duplex or Half-Duplex Receive Only
mode).
d) Initialize the DMABCH/DMABCL Byte Count
register with the number of bytes to be
transferred in the next SPI DMA operation.
e) Set the DMAEN bit (DMACON1<0>).
In SPI Master modes, this will initiate a DMA
transaction. In SPI Slave modes, this will
complete the initialization process, and the
module will now be ready to begin receiving
and/or transmitting data to the master
device once the master starts the
transaction.

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EXAMPLE 20-2: 512-BYTE SPI MASTER MODE Init AND TRANSFER
;For this example, let's use RP5(RB2) for SCK2,
;RP4(RB1) for SDO2, and RP3(RB0) for SDI2

;Let’s use SPI master mode, CKE = 0, CKP = 0,

;without using slave select signalling.

InitSPIPins:
movlb 0x0F ;Select bank 15, for access to ODCON3 register
bcf ODCON3, SPI2OD ;Let’s not use open drain outputs in this example

bcf LATB, RB2 ;Initialize our (to be) SCK2 pin low (idle).
bcf LATB, RB1 ;Initialize our (to be) SDO2 pin to an idle state
bcf TRISB, RB1 ;Make SDO2 output, and drive low
bcf TRISB, RB2 ;Make SCK2 output, and drive low (idle state)
bsf TRISB, RB0 ;SDI2 is an input, make sure it is tri-stated

;Now we should unlock the PPS registers, so we can

;assign the MSSP2 functions to our desired I/O pins.

movlb 0x0E ;Select bank 14 for access to PPS registers

bcf INTCON, GIE ;I/O Pin unlock sequence will not work if CPU
;services an interrupt during the sequence
movlw 0x55 ;Unlock sequence consists of writing 0x55
movwf EECON2 ;and 0xAA to the EECON2 register.
movlw 0xAA
movwf EECON2
bcf PPSCON, IOLOCK ;We may now write to RPINRx and RPORx registers
bsf INTCON, GIE ;May now turn back on interrupts if desired

movlw 0x03 ;RP3 will be SDI2

movwf RPINR21 ;Assign the SDI2 function to pin RP3

movlw 0x0A ;Let’s assign SCK2 output to pin RP4

movwf RPOR4 ;RPOR4 maps output signals to RP4 pin
movlw 0x04 ;SCK2 also needs to be configured as an input on the
same pin
movwf RPINR22 ;SCK2 input function taken from RP4 pin
movlw 0x09 ;0x09 is SDO2 output
movwf RPOR5 ;Assign SDO2 output signal to the RP5 (RB2) pin
movlb 0x0F ;Done with PPS registers, bank 15 has other SFRs

InitMSSP2:
clrf SSP2STAT ;CKE = 0, SMP = 0 (sampled at middle of bit)
movlw b'00000000' ;CKP = 0, SPI Master mode, Fosc/4
movwf SSP2CON1 ;MSSP2 initialized
bsf SSP2CON1, SSPEN ;Enable the MSSP2 module

InitSPIDMA:
movlw b'00111010' ;Full duplex, RX/TXINC enabled, no SSCON
movwf DMACON1 ;DLYINTEN is set, so DLYCYC3:DLYCYC0 = 1111
movlw b'11110000' ;Minimum delay between bytes, interrupt
movwf DMACON2 ;only once when the transaction is complete

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EXAMPLE 20-2: 512-BYTE SPI MASTER MODE Init AND TRANSFER (CONTINUED)

;Somewhere else in our project, lets assume we have

;allocated some RAM for use as SPI receive and
;transmit buffers.

; udata 0x500
;DestBuf res 0x200 ;Let’s reserve 0x500-0x6FF for use as our SPI
; ;receive data buffer in this example
;SrcBuf res 0x200 ;Lets reserve 0x700-0x8FF for use as our SPI
; ;transmit data buffer in this example

PrepareTransfer:
movlw HIGH(DestBuf) ;Get high byte of DestBuf address (0x05)
movwf RXADDRH ;Load upper four bits of the RXADDR register
movlw LOW(DestBuf) ;Get low byte of the DestBuf address (0x00)
movwf RXADDRL ;Load lower eight bits of the RXADDR register

movlw HIGH(SrcBuf) ;Get high byte of SrcBuf address (0x07)

movwf TXADDRH ;Load upper four bits of the TXADDR register
movlw LOW(SrcBuf) ;Get low byte of the SrcBuf address (0x00)
movwf TXADDRL ;Load lower eight bits of the TXADDR register

movlw 0x01 ;Lets move 0x200 (512) bytes in one DMA xfer
movwf DMABCH ;Load the upper two bits of DMABC register
movlw 0xFF ;Actual bytes transferred is (DMABC + 1), so
movwf DMABCL ;we load 0x01FF into DMABC to xfer 0x200 bytes

BeginXfer:
bsf DMACON1, DMAEN ;The SPI DMA module will now begin transferring
;the data taken from SrcBuf, and will store
;received bytes into DestBuf.

;Execute whatever ;CPU is now free to do whatever it wants to

;and the DMA operation will continue without
;intervention, until it completes.

;When the transfer is complete, the SSP2IF flag in

;the PIR3 register will become set, and the DMAEN bit
;is automatically cleared by the hardware.
;The DestBuf (0x500-0x7FF) will contain the received
;data. To start another transfer, firmware will need
;to reinitialize RXADDR, TXADDR, DMABC and then
;set the DMAEN bit.

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PIC18F47J53 FAMILY
20.5 I2C Mode 20.5.1 REGISTERS
The MSSP module in I2C mode fully implements all The MSSP module has six registers for I2C operation.
master and slave functions (including general call These are:
support), and provides interrupts on Start and Stop bits • MSSPx Control Register 1 (SSPxCON1)
in hardware to determine a free bus (multi-master • MSSPx Control Register 2 (SSPxCON2)
function). The MSSP module implements the standard
• MSSPx Status Register (SSPxSTAT)
mode specifications and 7-bit and 10-bit addressing.
• Serial Receive/Transmit Buffer Register
Two pins are used for data transfer: (SSPxBUF)
• Serial Clock (SCLx) – • MSSPx Shift Register (SSPxSR) – Not directly
RB4/CCP4/PMA1/KBI0/SCK1/SCL1/RP7 or accessible
RD0/PMD0/SCL2 • MSSPx Address Register (SSPxADD)
• Serial Data (SDAx) – • MSSPx 7-Bit Address Mask Register (SSPxMSK)
RB5/CCP5/PMA0/KBI1/SDI1/SDA1/RP8 or
RD1/PMD1/SDA2 SSPxCON1, SSPxCON2 and SSPxSTAT are the
control and status registers in I2C mode operation. The
The user must configure these pins as inputs by setting SSPxCON1 and SSPxCON2 registers are readable and
the associated TRIS bits. These pins are up to 5.5V writable. The lower six bits of the SSPxSTAT are
tolerant, allowing direct use in I2C busses operating at read-only. The upper two bits of the SSPxSTAT are
voltages higher than VDD. read/write.
SSPxSR is the shift register used for shifting data in or
FIGURE 20-7: MSSPx BLOCK DIAGRAM
out. SSPxBUF is the buffer register to which data
(I2C™ MODE) bytes are written to or read from.
Internal SSPxADD contains the slave device address when the
Data Bus MSSP is configured in I2C Slave mode. When the
Read Write MSSP is configured in Master mode, the lower seven
bits of SSPxADD act as the Baud Rate Generator
SSPxBUF reg
(BRG) reload value.
SCLx
SSPxMSK holds the slave address mask value when
Shift the module is configured for 7-Bit Address Masking
Clock mode. While it is a separate register, it shares the same
SSPxSR reg SFR address as SSPxADD; it is only accessible when
SDAx MSb LSb the SSPM<3:0> bits are specifically set to permit
access. Additional details are provided in
Section 20.5.3.4 “7-Bit Address Masking Mode”.
Match Detect Addr Match
In receive operations, SSPxSR and SSPxBUF
Address Mask
together, create a double-buffered receiver. When
SSPxSR receives a complete byte, it is transferred to
SSPxADD reg SSPxBUF and the SSPxIF interrupt is set.
During transmission, the SSPxBUF is not
double-buffered. A write to SSPxBUF will write to both
Set, Reset SSPxBUF and SSPxSR.
Start and
Stop bit Detect S, P bits
(SSPxSTAT reg)

Note: Only port I/O names are used in this diagram for
the sake of brevity. Refer to the text for a full list of
multiplexed functions.

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REGISTER 20-5: SSPxSTAT: MSSPx STATUS REGISTER (I2C™ MODE) (1, ACCESS FC7h; 2, F73h)
R/W-1 R/W-1 R-1 R-1 R-1 R-1 R-1 R-1
(1) (1) (2,3)
SMP CKE D/A P S R/W UA BF
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 SMP: Slew Rate Control bit

In Master or Slave mode:
1 = Slew rate control disabled for Standard Speed mode (100 kHz and 1 MHz)
0 = Slew rate control enabled for High-Speed mode (400 kHz)
bit 6 CKE: SMBus Select bit
In Master or Slave mode:
1 = Enable SMBus specific inputs
0 = Disable SMBus specific inputs
bit 5 D/A: Data/Address bit
In Master mode:
Reserved.
In Slave mode:
1 = Indicates that the last byte received or transmitted was data
0 = Indicates that the last byte received or transmitted was address
bit 4 P: Stop bit(1)
1 = Indicates that a Stop bit has been detected last
0 = Stop bit was not detected last
bit 3 S: Start bit(1)
1 = Indicates that a Start bit has been detected last
0 = Start bit was not detected last
bit 2 R/W: Read/Write Information bit(2,3)
In Slave mode:
1 = Read
0 = Write
In Master mode:
1 = Transmit is in progress
0 = Transmit is not in progress
bit 1 UA: Update Address bit (10-Bit Slave mode only)
1 = Indicates that the user needs to update the address in the SSPxADD register
0 = Address does not need to be updated
bit 0 BF: Buffer Full Status bit
In Transmit mode:
1 = SSPxBUF is full
0 = SSPxBUF is empty
In Receive mode:
1 = SSPxBUF is full (does not include the ACK and Stop bits)
0 = SSPxBUF is empty (does not include the ACK and Stop bits)

Note 1: This bit is cleared on Reset and when SSPEN is cleared.

2: This bit holds the R/W bit information following the last address match. This bit is only valid from the
address match to the next Start bit, Stop bit or not ACK bit.
3: ORing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSPx is in Active mode.

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REGISTER 20-6: SSPxCON1: MSSPx CONTROL REGISTER 1 (I2C MODE) (1, ACCESS FC6h; 2, F73h)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
(1) (2) (2) (2)
WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0(2)
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 WCOL: Write Collision Detect bit

In Master Transmit mode:
1 = A write to the SSPxBUF register was attempted while the I2C conditions were not valid for a
transmission to be started (must be cleared in software)
0 = No collision
In Slave Transmit mode:
1 = The SSPxBUF register is written while it is still transmitting the previous word (must be cleared in
software)
0 = No collision
In Receive mode (Master or Slave modes):
This is a “don’t care” bit.
bit 6 SSPOV: Receive Overflow Indicator bit
In Receive mode:
1 = A byte is received while the SSPxBUF register is still holding the previous byte (must be cleared in
software)
0 = No overflow
In Transmit mode:
This is a “don’t care” bit in Transmit mode.
bit 5 SSPEN: Master Synchronous Serial Port Enable bit(1)
1 = Enables the serial port and configures the SDAx and SCLx pins as the serial port pins
0 = Disables the serial port and configures these pins as I/O port pins
bit 4 CKP: SCKx Release Control bit
In Slave mode:
1 = Releases clock
0 = Holds clock low (clock stretch); used to ensure data setup time
In Master mode:
Unused in this mode.
bit 3-0 SSPM<3:0>: Master Synchronous Serial Port Mode Select bits(2)
1111 = I2C Slave mode, 10-bit address with Start and Stop bit interrupts enabled
1110 = I2C Slave mode, 7-bit address with Start and Stop bit interrupts enabled
1011 = I2C Firmware Controlled Master mode (slave Idle)
1001 = Load the SSPxMSK register at the SSPxADD SFR address(3,4)
1000 = I2C Master mode, clock = FOSC/(4 * (SSPxADD + 1))
0111 = I2C Slave mode, 10-bit address
0110 = I2C Slave mode, 7-bit address

Note 1: When enabled, the SDAx and SCLx pins must be configured as inputs.
2: Bit combinations not specifically listed here are either reserved or implemented in SPI mode only.
3: When SSPM<3:0> = 1001, any reads or writes to the SSPxADD SFR address actually accesses the
SSPxMSK register.
4: This mode is only available when 7-Bit Address Masking mode is selected (MSSPMSK Configuration bit is ‘1’).

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REGISTER 20-7: SSPxCON2: MSSPx CONTROL REGISTER 2 (I2C™ MASTER MODE)
(1, ACCESS FC5h; 2, F71h)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
(3)
GCEN ACKSTAT ACKDT(1) ACKEN(2) RCEN(2) PEN(2) RSEN(2) SEN(2)
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 GCEN: General Call Enable bit (Slave mode only)(3)

1 = Enable interrupt when a general call address (0000h) is received in the SSPxSR
0 = General call address disabled
bit 6 ACKSTAT: Acknowledge Status bit (Master Transmit mode only)
1 = Acknowledge was not received from slave
0 = Acknowledge was received from slave
bit 5 ACKDT: Acknowledge Data bit (Master Receive mode only)(1)
1 = Not Acknowledge
0 = Acknowledge
bit 4 ACKEN: Acknowledge Sequence Enable bit(2)
1 = Initiates Acknowledge sequence on SDAx and SCLx pins, and transmits ACKDT data bit;
automatically cleared by hardware
0 = Acknowledge sequence Idle
bit 3 RCEN: Receive Enable bit (Master Receive mode only)(2)
1 = Enables Receive mode for I2C
0 = Receive Idle
bit 2 PEN: Stop Condition Enable bit(2)
1 = Initiates Stop condition on SDAx and SCLx pins; automatically cleared by hardware
0 = Stop condition Idle
bit 1 RSEN: Repeated Start Condition Enable bit(2)
1 = Initiates Repeated Start condition on SDAx and SCLx pins; automatically cleared by hardware
0 = Repeated Start condition Idle
bit 0 SEN: Start Condition Enable bit(2)
1 = Initiates Start condition on SDAx and SCLx pins; automatically cleared by hardware
0 = Start condition Idle

Note 1: Value that will be transmitted when the user initiates an Acknowledge sequence at the end of a receive.
2: If the I2C module is active, these bits may not be set (no spooling) and the SSPxBUF may not be written
(or writes to the SSPxBUF are disabled).
3: This bit is not implemented in I2C Master mode.

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REGISTER 20-8: SSPxCON2: MSSPx CONTROL REGISTER 2 (I2C™ SLAVE MODE)
(1, ACCESS FC5h; 2, F71h)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
(2)
GCEN ACKSTAT ADMSK5 ADMSK4 ADMSK3 ADMSK2 ADMSK1 SEN(1)
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 GCEN: General Call Enable bit (Slave mode only)

1 = Enables interrupt when a general call address (0000h) is received in the SSPxSR
0 = General call address disabled
bit 6 ACKSTAT: Acknowledge Status bit(2)
Unused in Slave mode.
bit 5-2 ADMSK<5:2>: Slave Address Mask Select bits (5-bit address masking)
1 = Masking of the corresponding bits of SSPxADD are enabled
0 = Masking of the corresponding bits of SSPxADD are disabled
bit 1 ADMSK1: Slave Address Least Significant bit(s) Mask Select bit
In 7-Bit Addressing mode:
1 = Masking of SSPxADD<1> only enabled
0 = Masking of SSPxADD<1> only disabled
In 10-Bit Addressing mode:
1 = Masking of SSPxADD<1:0> enabled
0 = Masking of SSPxADD<1:0> disabled
bit 0 SEN: Start Condition Enable/Stretch Enable bit(1)
1 = Clock stretching is enabled for both slave transmit and slave receive (stretch enabled)
0 = Clock stretching is disabled

Note 1: If the I2C module is active, these bits may not be set (no spooling) and the SSPxBUF may not be written
(or writes to the SSPxBUF are disabled).
2: This bit is unimplemented in I2C Slave mode.

REGISTER 20-9: SSPxMSK: I2C™ SLAVE ADDRESS MASK REGISTER (7-BIT MASKING MODE)
(1, ACCESS FC8h; 2, F74h)(1)
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
MSK7 MSK6 MSK5 MSK4 MSK3 MSK2 MSK1 MSK0(2)
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-0 MSK<7:0>: Slave Address Mask Select bits

1 = Masking of the corresponding bit of SSPxADD is enabled
0 = Masking of the corresponding bit of SSPxADD is disabled

Note 1: This register shares the same SFR address as SSPxADD and is only addressable in select MSSP
operating modes. See Section 20.5.3.4 “7-Bit Address Masking Mode” for more details.
2: MSK0 is not used as a mask bit in 7-bit addressing.

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20.5.2 OPERATION The SCLx clock input must have a minimum high and
low for proper operation. The high and low times of the
The MSSP module functions are enabled by setting the
I2C specification, as well as the requirement of the
MSSP Enable bit, SSPEN (SSPxCON1<5>).
MSSP module, are shown in timing parameter 100 and
The SSPxCON1 register allows control of the I2C parameter 101.
operation. Four mode selection bits (SSPxCON1<3:0>)
allow one of the following I2C modes to be selected: 20.5.3.1 Addressing
2
• I C Master mode, clock Once the MSSP module has been enabled, it waits for
• I2C Slave mode (7-bit address) a Start condition to occur. Following the Start condition,
• I2C Slave mode (10-bit address) the 8 bits are shifted into the SSPxSR register. All
incoming bits are sampled with the rising edge of the
• I2C Slave mode (7-bit address) with Start and
clock (SCLx) line. The value of register, SSPxSR<7:1>,
Stop bit interrupts enabled
is compared to the value of the SSPxADD register. The
• I2C Slave mode (10-bit address) with Start and address is compared on the falling edge of the eighth
Stop bit interrupts enabled clock (SCLx) pulse. If the addresses match and the BF
• I2C Firmware Controlled Master mode, slave is and SSPOV bits are clear, the following events occur:
Idle
1. The SSPxSR register value is loaded into the
Selection of any I2C mode, with the SSPEN bit set, SSPxBUF register.
forces the SCLx and SDAx pins to be open-drain, 2. The Buffer Full bit, BF, is set.
provided these pins are programmed as inputs by
3. An ACK pulse is generated.
setting the appropriate TRISB or TRISD bits. To ensure
proper operation of the module, pull-up resistors must 4. The MSSPx Interrupt Flag bit, SSPxIF, is set
be provided externally to the SCLx and SDAx pins. (and an interrupt is generated, if enabled) on the
falling edge of the ninth SCLx pulse.
20.5.3 SLAVE MODE In 10-Bit Addressing mode, two address bytes need to
In Slave mode, the SCLx and SDAx pins must be be received by the slave. The five Most Significant bits
configured as inputs (TRISB<5:4> set). The MSSP (MSbs) of the first address byte specify if this is a 10-bit
module will override the input state with the output data address. Bit, R/W (SSPxSTAT<2>), must specify a
when required (slave-transmitter). write so the slave device will receive the second
address byte. For a 10-bit address, the first byte would
The I2C Slave mode hardware will always generate an equal ‘11110 A9 A8 0’, where ‘A9’ and ‘A8’ are the
interrupt on an address match. Address masking will two MSbs of the address. The sequence of events for
allow the hardware to generate an interrupt for more 10-bit addressing is as follows, with steps 7 through 9
than one address (up to 31 in 7-bit addressing and up for the slave-transmitter:
to 63 in 10-bit addressing). Through the mode select
bits, the user can also choose to interrupt on Start and 1. Receive the first (high) byte of address (bits,
Stop bits. SSPxIF, BF and UA, are set on an address
match).
When an address is matched, or the data transfer after
2. Update the SSPxADD register with the second
an address match is received, the hardware will auto-
(low) byte of the address (clears bit, UA, and
matically generate the Acknowledge (ACK) pulse and
releases the SCLx line).
load the SSPxBUF register with the received value
currently in the SSPxSR register. 3. Read the SSPxBUF register (clears bit, BF) and
clear flag bit, SSPxIF.
Any combination of the following conditions will cause
4. Receive the second (low) byte of address (bits,
the MSSP module not to give this ACK pulse:
SSPxIF, BF and UA, are set).
• The Buffer Full bit, BF (SSPxSTAT<0>), was set 5. Update the SSPxADD register with the first
before the transfer was received. (high) byte of the address. If a match releases
• The overflow bit, SSPOV (SSPxCON1<6>), was the SCLx line, this will clear bit, UA.
set before the transfer was received. 6. Read the SSPxBUF register (clears bit, BF) and
In this case, the SSPxSR register value is not loaded clear flag bit, SSPxIF.
into the SSPxBUF, but bit, SSPxIF, is set. The BF bit is 7. Receive Repeated Start condition.
cleared by reading the SSPxBUF register, while bit, 8. Receive the first (high) byte of address (bits,
SSPOV, is cleared through software. SSPxIF and BF, are set).
9. Read the SSPxBUF register (clears bit, BF) and
clear flag bit, SSPxIF.

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20.5.3.2 Address Masking Modes the incoming address. This allows the module to
Acknowledge up to 31 addresses when using 7-bit
Masking an address bit causes that bit to become a
addressing or 63 addresses with 10-bit addressing (see
“don’t care”. When one address bit is masked, two
Example 20-3). This Masking mode is selected when
addresses will be Acknowledged and cause an inter-
the MSSPMSK Configuration bit is programmed (‘0’).
rupt. It is possible to mask more than one address bit at
a time, which greatly expands the number of addresses The address mask in this mode is stored in the
Acknowledged. SSPxCON2 register, which stops functioning as a control
register in I2C Slave mode (Register 20-8). In 7-Bit
The I2C slave behaves the same way, whether address
Address Masking mode, address mask bits,
masking is used or not. However, when address mask-
ADMSK<5:1> (SSPxCON2<5:1>), mask the
ing is used, the I2C slave can Acknowledge multiple
corresponding address bits in the SSPxADD register. For
addresses and cause interrupts. When this occurs, it is
any ADMSK bits that are set (ADMSK<n> = 1), the cor-
necessary to determine which address caused the
responding address bit is ignored (SSPxADD<n> = x).
interrupt by checking SSPxBUF.
For the module to issue an address Acknowledge, it is
The PIC18F47J53 family of devices is capable of using sufficient to match only on addresses that do not have an
two different Address Masking modes in I2C slave active address mask.
operation: 5-Bit Address Masking and 7-Bit Address
In 10-Bit Address Masking mode, bits, ADMSK<5:2>,
Masking. The Masking mode is selected at device
mask the corresponding address bits in the SSPxADD
configuration using the MSSPMSK Configuration bit.
register. In addition, ADMSK1 simultaneously masks
The default device configuration is 7-Bit Address
the two LSbs of the address (SSPxADD<1:0>). For any
Masking.
ADMSK bits that are active (ADMSK<n> = 1), the cor-
Both Masking modes, in turn, support address masking responding address bit is ignored (SPxADD<n> = x).
of 7-bit and 10-bit addresses. The combination of Also note, that although in 10-Bit Address Masking
Masking modes and addresses provides different mode, the upper address bits reuse part of the
ranges of Acknowledgable addresses for each SSPxADD register bits. The address mask bits do not
combination. interact with those bits; they only affect the lower
While both Masking modes function in roughly the address bits.
same manner, the way they use address masks is Note 1: ADMSK1 masks the two Least Significant
different. bits of the address.
20.5.3.3 5-Bit Address Masking Mode 2: The two MSbs of the address are not
affected by address masking.
As the name implies, 5-Bit Address Masking mode uses
an address mask of up to five bits to create a range of
addresses to be Acknowledged, using bits 5 through 1 of

EXAMPLE 20-3: ADDRESS MASKING EXAMPLES IN 5-BIT MASKING MODE

7-Bit Addressing:
SSPxADD<7:1>= A0h (1010000) (SSPxADD<0> is assumed to be ‘0’)
ADMSK<5:1> = 00111
Addresses Acknowledged: A0h, A2h, A4h, A6h, A8h, AAh, ACh, AEh
10-Bit Addressing:
SSPxADD<7:0> = A0h (10100000) (the two MSbs of the address are ignored in this example, since
they are not affected by masking)
ADMSK<5:1> = 00111
Addresses Acknowledged: A0h, A1h, A2h, A3h, A4h, A5h, A6h, A7h, A8h, A9h, AAh, ABh, ACh, ADh,
AEh, AFh

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20.5.3.4 7-Bit Address Masking Mode Setting or clearing mask bits in SSPxMSK behaves in
the opposite manner of the ADMSK bits in 5-Bit
Unlike 5-Bit Address Masking mode, 7-Bit Address
Address Masking mode. That is, clearing a bit in
Masking mode uses a mask of up to eight bits (in 10-bit
SSPxMSK causes the corresponding address bit to be
addressing) to define a range of addresses than can be
masked; setting the bit requires a match in that
Acknowledged, using the lowest bits of the incoming
position. SSPxMSK resets to all ‘1’s upon any Reset
address. This allows the module to Acknowledge up to
condition, and therefore, has no effect on the standard
127 different addresses with 7-bit addressing, or
MSSP operation until written with a mask value.
255 with 10-bit addressing (see Example 20-4). This
mode is the default configuration of the module and is With 7-Bit Address Masking mode, the
selected when MSSPMSK is unprogrammed (‘1’). SSPxMSK<7:1> bits mask the corresponding address
bits in the SSPxADD register. For any SSPxMSK bits
The address mask for 7-Bit Address Masking mode is
that are active (SSPxMSK<n> = 0), the corresponding
stored in the SSPxMSK register, instead of the
SSPxADD address bit is ignored (SSPxADD<n> = x).
SSPxCON2 register. SSPxMSK is a separate, hard-
For the module to issue an address Acknowledge, it is
ware register within the module, but it is not directly
sufficient to match only on addresses that do not have
addressable. Instead, it shares an address in the SFR
an active address mask.
space with the SSPxADD register. To access the
SSPxMSK register, it is necessary to select MSSP With 10-Bit Address Masking mode, SSPxMSK<7:0>
mode, ‘1001’ (SSPCON1<3:0> = 1001), and then read bits mask the corresponding address bits in the
or write to the location of SSPxADD. SSPxADD register. For any SSPxMSK bits that are
active (= 0), the corresponding SSPxADD address bit
To use 7-Bit Address Masking mode, it is necessary to
is ignored (SSPxADD<n> = x).
initialize SSPxMSK with a value before selecting the
I2C Slave Addressing mode. Thus, the required Note: The two MSbs of the address are not
sequence of events is: affected by address masking.
1. Select SSPxMSK Access mode
(SSPxCON2<3:0> = 1001).
2. Write the mask value to the appropriate
SSPxADD register address (FC8h for MSSP1,
F6Eh for MSSP2).
3. Set the appropriate I2C Slave mode
(SSPxCON2<3:0> = 0111 for 10-bit addressing,
0110 for 7-bit addressing).

EXAMPLE 20-4: ADDRESS MASKING EXAMPLES IN 7-BIT MASKING MODE

7-Bit Addressing:
SSPxADD<7:1>= 1010 000
SSPxMSK<7:1>= 1111 001
Addresses Acknowledged = A8h, A6h, A4h, A0h
10-Bit Addressing:
SSPxADD<7:0> = 1010 0000 (the two MSbs are ignored in this example since they are not affected)
SSPxMSK<5:1> = 1111 0
Addresses Acknowledged = A8h, A6h, A4h, A0h

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20.5.3.5 Reception 20.5.3.6 Transmission
When the R/W bit of the address byte is clear and an When the R/W bit of the incoming address byte is set
address match occurs, the R/W bit of the SSPxSTAT and an address match occurs, the R/W bit of the
register is cleared. The received address is loaded into SSPxSTAT register is set. The received address is
the SSPxBUF register and the SDAx line is held low loaded into the SSPxBUF register. The ACK pulse will
(ACK). be sent on the ninth bit and pin, SCLx, is held low
When the address byte overflow condition exists, then regardless of SEN (see Section 20.5.4 “Clock
the no Acknowledge (ACK) pulse is given. An overflow Stretching” for more details). By stretching the clock,
condition is defined as either bit, BF (SSPxSTAT<0>), the master will be unable to assert another clock pulse
is set or bit, SSPOV (SSPxCON1<6>), is set. until the slave is done preparing the transmit data. The
transmit data must be loaded into the SSPxBUF regis-
An MSSP interrupt is generated for each data transfer ter, which also loads the SSPxSR register. Then, the
byte. The interrupt flag bit, SSPxIF, must be cleared in SCLx pin should be enabled by setting bit, CKP
software. The SSPxSTAT register is used to determine (SSPxCON1<4>). The eight data bits are shifted out on
the status of the byte. the falling edge of the SCLx input. This ensures that the
If SEN is enabled (SSPxCON2<0> = 1), SCLx will be SDAx signal is valid during the SCLx high time
held low (clock stretch) following each data transfer. (Figure 20-10).
The clock must be released by setting bit, CKP The ACK pulse from the master-receiver is latched on
(SSPxCON1<4>). See Section 20.5.4 “Clock the rising edge of the ninth SCLx input pulse. If the
Stretching” for more details. SDAx line is high (not ACK), then the data transfer is
complete. In this case, when the ACK is latched by the
slave, the slave logic is reset (resets the SSPxSTAT
register) and the slave monitors for another occurrence
of the Start bit. If the SDAx line was low (ACK), the next
transmit data must be loaded into the SSPxBUF
register. Again, the SCLx pin must be enabled by
setting bit, CKP.
An MSSP interrupt is generated for each data transfer
byte. The SSPxIF bit must be cleared in software and
the SSPxSTAT register is used to determine the status
of the byte. The SSPxIF bit is set on the falling edge of
the ninth clock pulse.

DS39964B-page 318 Preliminary  2010 Microchip Technology Inc.

 FIGURE 20-8:

 2010 Microchip Technology Inc.

Receiving Address R/W = 0 Receiving Data ACK Receiving Data ACK

SDAx A7 A6 A5 A4 A3 A2 A1 ACK D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0

SCLx 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
S P

SSPxIF (PIR1<3> or PIR3<7>)

Bus master
terminates
transfer

BF (SSPxSTAT<0>)

Preliminary
Cleared in software
SSPxBUF is read

SSPOV (SSPxCON1<6>)

SSPOV is set
because SSPxBUF is
still full. ACK is not sent.

CKP (SSPxCON1<4>)
(CKP does not reset to ‘0’ when SEN = 0)
I2C™ SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 7-BIT ADDRESS)

DS39964B-page 319
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 FIGURE 20-9:

DS39964B-page 320
Receiving Address R/W = 0 Receiving Data ACK Receiving Data ACK

SDAx A7 A6 A5 X A3 X X ACK D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0

SCLx 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
S P

SSPxIF (PIR1<3> or PIR3<7>)

PIC18F47J53 FAMILY

Bus master
terminates
transfer
(RECEPTION, 7-BIT ADDRESS)(1)

BF (SSPxSTAT<0>)

Preliminary
Cleared in software
SSPxBUF is read

SSPOV (SSPxCON1<6>)

SSPOV is set
because SSPxBUF is
still full. ACK is not sent.

CKP (SSPxCON1<4>)

(CKP does not reset to ‘0’ when SEN = 0)

Note 1: In this example, an address equal to A7.A6.A5.X.A3.X.X will be Acknowledged and cause an interrupt.
I2C™ SLAVE MODE TIMING WITH SEN = 0 AND ADMSK<5:1> = 01011

 2010 Microchip Technology Inc.

 FIGURE 20-10:

Receiving Address R/W = 1 Transmitting Data Transmitting Data

ACK ACK
SDAx

 2010 Microchip Technology Inc.

A7 A6 A5 A4 A3 A2 A1 ACK D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0

SCLx
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
S
Data in SCLx held low P
sampled while CPU
responds to SSPxIF

SSPxIF (PIR1<3>)

BF (SSPxSTAT<0>)
Cleared in software Cleared in software
From SSPxIF ISR From SSPxIF ISR

Preliminary
SSPxBUF is written in software SSPxBUF is written in software

Clear by reading

CKP

CKP is set in software CKP is set in software

I2C™ SLAVE MODE TIMING (TRANSMISSION, 7-BIT ADDRESS)

DS39964B-page 321
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 FIGURE 20-11:

DS39964B-page 322
Clock is held low until Clock is held low until
update of SSPxADD has update of SSPxADD has
taken place taken place

Receive First Byte of Address Receive Second Byte of Address Receive Data Byte Receive Data Byte
R/W = 0 ACK

SDAx 1 1 1 1 0 A9 A8 ACK A7 A6 A5 X A3 A2 X X ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 D1 D0

SCLx 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
S P

Bus master
terminates
SSPxIF (PIR1<3> or PIR3<7>) transfer

Cleared in software Cleared in software Cleared in software

Cleared in software

BF (SSPxSTAT<0>)
PIC18F47J53 FAMILY

SSPxBUF is written with Dummy read of SSPxBUF

contents of SSPxSR to clear BF flag
SSPOV (SSPxCON1<6>)
(RECEPTION, 10-BIT ADDRESS)(1,2)

SSPOV is set

Preliminary
because SSPxBUF is
still full. ACK is not sent.

UA (SSPxSTAT<1>)

UA is set indicating that Cleared by hardware Cleared by hardware when

the SSPxADD needs to be when SSPxADD is updated SSPxADD is updated with high
updated with low byte of address byte of address

UA is set indicating that

SSPxADD needs to be
updated
CKP (SSPxCON1<4>)
(CKP does not reset to ‘0’ when SEN = 0)

Note 1: In this example, an address equal to A9.A8.A7.A6.A5.X.A3.A2.X.X will be Acknowledged and cause an interrupt.
I2C™ SLAVE MODE TIMING WITH SEN = 0 AND ADMSK<5:1> = 01001

2: Note that the Most Significant bits of the address are not affected by the bit masking.

 2010 Microchip Technology Inc.

 FIGURE 20-12:

Clock is held low until Clock is held low until

update of SSPxADD has update of SSPxADD has
taken place taken place

Receive First Byte of Address Receive Second Byte of Address Receive Data Byte Receive Data Byte
R/W = 0 ACK

SDAx 1 1 1 1 0 A9 A8 ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 D1 D0

 2010 Microchip Technology Inc.

SCLx 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
S P

Bus master
terminates
SSPxIF (PIR1<3> or PIR3<7>) transfer

Cleared in software Cleared in software Cleared in software

Cleared in software

BF (SSPxSTAT<0>)

SSPxBUF is written with Dummy read of SSPxBUF

contents of SSPxSR to clear BF flag
SSPOV (SSPxCON1<6>)

SSPOV is set

Preliminary
because SSPxBUF is
still full. ACK is not sent.

UA (SSPxSTAT<1>)

UA is set indicating that Cleared by hardware Cleared by hardware when

the SSPxADD needs to be when SSPxADD is updated SSPxADD is updated with high
updated with low byte of address byte of address

UA is set indicating that

SSPxADD needs to be
updated
CKP (SSPxCON1<4>)
(CKP does not reset to ‘0’ when SEN = 0)
I2C™ SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 10-BIT ADDRESS)

DS39964B-page 323
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 FIGURE 20-13:

DS39964B-page 324
Bus master
terminates
Clock is held low until Clock is held low until transfer
update of SSPxADD has update of SSPxADD has Clock is held low until
taken place taken place CKP is set to ‘1’
R/W = 0
Receive First Byte of Address Receive Second Byte of Address Receive First Byte of Address R/W = 1 Transmitting Data Byte ACK
SDAx 1 1 1 1 0 A9 A8 ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK 1 1 1 1 0 A9 A8 ACK D7 D6 D5 D4 D3 D2 D1 D0

SCLx 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
S Sr P

SSPxIF (PIR1<3> or PIR3<7>)

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Cleared in software Cleared in software Cleared in software

BF (SSPxSTAT<0>)

SSPxBUF is written with Dummy read of SSPxBUF

Preliminary
Dummy read of SSPxBUF Write of SSPxBUF Completion of
contents of SSPxSR to clear BF flag BF flag is clear
to clear BF flag initiates transmit data transmission
at the end of the
UA (SSPxSTAT<1>) third address sequence clears BF flag

UA is set indicating that Cleared by hardware when Cleared by hardware when

the SSPxADD needs to be SSPxADD is updated with low SSPxADD is updated with high
updated byte of address byte of address.

UA is set indicating that

SSPxADD needs to be
updated
CKP (SSPxCON1<4>)

CKP is set in software

CKP is automatically cleared in hardware, holding SCLx low

I2C™ SLAVE MODE TIMING (TRANSMISSION, 10-BIT ADDRESS)

 2010 Microchip Technology Inc.

 PIC18F47J53 FAMILY
20.5.4 CLOCK STRETCHING 20.5.4.3 Clock Stretching for 7-Bit Slave
Both 7-Bit and 10-Bit Slave modes implement Transmit Mode
automatic clock stretching during a transmit sequence. The 7-Bit Slave Transmit mode implements clock
The SEN bit (SSPxCON2<0>) allows clock stretching stretching by clearing the CKP bit, after the falling
to be enabled during receives. Setting SEN will cause edge of the ninth clock, if the BF bit is clear. This
the SCLx pin to be held low at the end of each data occurs regardless of the state of the SEN bit.
receive sequence. The user’s Interrupt Service Routine (ISR) must set
the CKP bit before transmission is allowed to continue.
20.5.4.1 Clock Stretching for 7-Bit Slave By holding the SCLx line low, the user has time to
Receive Mode (SEN = 1) service the ISR and load the contents of the SSPxBUF
In 7-Bit Slave Receive mode, on the falling edge of the before the master device can initiate another transmit
ninth clock at the end of the ACK sequence, if the BF sequence (see Figure 20-10).
bit is set, the CKP bit in the SSPxCON1 register is Note 1: If the user loads the contents of
automatically cleared, forcing the SCLx output to be SSPxBUF, setting the BF bit before the
held low. The CKP bit being cleared to ‘0’ will assert falling edge of the ninth clock, the CKP bit
the SCLx line low. The CKP bit must be set in the will not be cleared and clock stretching
user’s ISR before reception is allowed to continue. By will not occur.
holding the SCLx line low, the user has time to service
the ISR and read the contents of the SSPxBUF before 2: The CKP bit can be set in software
the master device can initiate another receive regardless of the state of the BF bit.
sequence. This will prevent buffer overruns from
occurring (see Figure 20-15). 20.5.4.4 Clock Stretching for 10-Bit Slave
Transmit Mode
Note 1: If the user reads the contents of the
SSPxBUF before the falling edge of the In 10-Bit Slave Transmit mode, clock stretching is
ninth clock, thus clearing the BF bit, the controlled during the first two address sequences by
CKP bit will not be cleared and clock the state of the UA bit, just as it is in 10-Bit Slave
stretching will not occur. Receive mode. The first two addresses are followed
by a third address sequence, which contains the
2: The CKP bit can be set in software
high-order bits of the 10-bit address and the R/W bit
regardless of the state of the BF bit. The
set to ‘1’. After the third address sequence is
user should be careful to clear the BF bit
performed, the UA bit is not set, the module is now
in the ISR before the next receive
configured in Transmit mode and clock stretching is
sequence in order to prevent an overflow
controlled by the BF flag as in 7-Bit Slave Transmit
condition.
mode (see Figure 20-13).
20.5.4.2 Clock Stretching for 10-Bit Slave
Receive Mode (SEN = 1)
In 10-Bit Slave Receive mode, during the address
sequence, clock stretching automatically takes place
but CKP is not cleared. During this time, if the UA bit is
set after the ninth clock, clock stretching is initiated.
The UA bit is set after receiving the upper byte of the
10-bit address and following the receive of the second
byte of the 10-bit address with the R/W bit cleared to
‘0’. The release of the clock line occurs upon updating
SSPxADD. Clock stretching will occur on each data
receive sequence, as described in 7-bit mode.
Note: If the user polls the UA bit and clears it by
updating the SSPxADD register before the
falling edge of the ninth clock occurs, and
if the user has not cleared the BF bit by
reading the SSPxBUF register before that
time, then the CKP bit will still NOT be
asserted low. Clock stretching on the basis
of the state of the BF bit only occurs during
a data sequence, not an address
sequence.

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PIC18F47J53 FAMILY
20.5.4.5 Clock Synchronization and CKP bit already asserted the SCLx line. The SCLx output will
remain low until the CKP bit is set and all other
When the CKP bit is cleared, the SCLx output is forced
devices on the I2C bus have deasserted SCLx. This
to ‘0’. However, clearing the CKP bit will not assert the
ensures that a write to the CKP bit will not violate the
SCLx output low until the SCLx output is already
minimum high time requirement for SCLx (see
sampled low. Therefore, the CKP bit will not assert the
Figure 20-14).
SCLx line until an external I2C master device has

FIGURE 20-14: CLOCK SYNCHRONIZATION TIMING

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

SDAx DX DX – 1

SCLx

Master device
CKP asserts clock

Master device
deasserts clock
WR
SSPxCON1

DS39964B-page 326 Preliminary  2010 Microchip Technology Inc.

 FIGURE 20-15:

Clock is not held low

because buffer full bit is

 2010 Microchip Technology Inc.

clear prior to falling edge Clock is held low until Clock is not held low
of 9th clock CKP is set to ‘1’ because ACK = 1

Receiving Address R/W = 0 Receiving Data ACK Receiving Data ACK

SDAx A7 A6 A5 A4 A3 A2 A1 ACK D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0

SCLx 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
S P

SSPxIF (PIR1<3> or PIR3<7>)

Bus master
terminates
transfer

BF (SSPxSTAT<0>)

Preliminary
Cleared in software
SSPxBUF is read

SSPOV (SSPxCON1<6>)

SSPOV is set
because SSPxBUF is
still full. ACK is not sent.

CKP (SSPxCON1<4>)
CKP
written
to ‘1’ in
If BF is cleared
software
prior to the falling
edge of the 9th clock,
CKP will not be reset BF is still set after falling
to ‘0’ and no clock edge of the 9th clock,
stretching will occur CKP is reset to ‘0’ and
clock stretching occurs
I2C™ SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 7-BIT ADDRESS)

DS39964B-page 327
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 FIGURE 20-16:

Clock is held low until

DS39964B-page 328
Clock is held low until
update of SSPxADD has update of SSPxADD has Clock is not held low
Clock is held low until
taken place taken place because ACK = 1
CKP is set to ‘1’
Receive First Byte of Address Receive Second Byte of Address Receive Data Byte Receive Data Byte
R/W = 0 ACK
ACK ACK
SDAx 1 1 1 1 0 A9 A8 ACK A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0

SCLx 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
S P

SSPxIF (PIR1<3> or PIR3<7>)

Bus master
terminates
Cleared in software Cleared in software Cleared in software transfer
Cleared in software

BF (SSPxSTAT<0>)
PIC18F47J53 FAMILY

SSPxBUF is written with Dummy read of SSPxBUF Dummy read of SSPxBUF

contents of SSPxSR to clear BF flag to clear BF flag
SSPOV (SSPxCON1<6>)

SSPOV is set

Preliminary
because SSPxBUF is
still full. ACK is not sent.

UA (SSPxSTAT<1>)

UA is set indicating that Cleared by hardware when Cleared by hardware when

the SSPxADD needs to be SSPxADD is updated with low SSPxADD is updated with high
updated byte of address after falling edge byte of address after falling edge
of ninth clock of ninth clock

UA is set indicating that

SSPxADD needs to be
updated
CKP (SSPxCON1<4>)
Note: An update of the SSPxADD
register before the falling
edge of the ninth clock will CKP written to ‘1’
have no effect on UA and in software
UA will remain set.

Note: An update of the SSPxADD register before

the falling edge of the ninth clock will have no
effect on UA and UA will remain set.
I2C™ SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 10-BIT ADDRESS)

 2010 Microchip Technology Inc.

 PIC18F47J53 FAMILY
20.5.5 GENERAL CALL ADDRESS If the general call address matches, the SSPxSR is
SUPPORT transferred to the SSPxBUF, the BF flag bit is set (eighth
bit), and on the falling edge of the ninth bit (ACK bit), the
The addressing procedure for the I2C bus is such that
SSPxIF interrupt flag bit is set.
the first byte after the Start condition usually
determines which device will be the slave addressed by When the interrupt is serviced, the source for the
the master. The exception is the general call address interrupt can be checked by reading the contents of the
which can address all devices. When this address is SSPxBUF. The value can be used to determine if the
used, all devices should, in theory, respond with an address was device-specific or a general call address.
Acknowledge. In 10-bit mode, the SSPxADD is required to be updated
The general call address is one of eight addresses for the second half of the address to match and the UA
reserved for specific purposes by the I2C protocol. It bit is set (SSPxSTAT<1>). If the general call address is
consists of all ‘0’s with R/W = 0. sampled when the GCEN bit is set, while the slave is
configured in 10-Bit Addressing mode, then the second
The general call address is recognized when the
half of the address is not necessary. The UA bit will not
General Call Enable bit, GCEN, is enabled
be set and the slave will begin receiving data after the
(SSPxCON2<7> set). Following a Start bit detect, 8 bits
Acknowledge (Figure 20-17).
are shifted into the SSPxSR and the address is
compared against the SSPxADD. It is also compared to
the general call address and fixed in hardware.

FIGURE 20-17: SLAVE MODE GENERAL CALL ADDRESS SEQUENCE

(7-BIT OR 10-BIT ADDRESSING MODE)
Address is compared to General Call Address
after ACK, set interrupt

R/W = 0 Receiving Data ACK

General Call Address ACK D7 D6 D5 D4 D3 D2 D1 D0
SDAx

SCLx
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
S

SSPxIF

BF (SSPxSTAT<0>)

Cleared in software
SSPxBUF is read
SSPOV (SSPxCON1<6>) ‘0’

GCEN (SSPxCON2<7>)
‘1’

20.5.6 MASTER MODE Once Master mode is enabled, the user has six
options.
Master mode is enabled by setting and clearing the
appropriate SSPM bits in SSPxCON1 and by setting 1. Assert a Start condition on SDAx and SCLx.
the SSPEN bit. In Master mode, the SCLx and SDAx 2. Assert a Repeated Start condition on SDAx and
lines are manipulated by the MSSP hardware if the SCLx.
TRIS bits are set. 3. Write to the SSPxBUF register initiating
Master mode of operation is supported by interrupt transmission of data/address.
generation on the detection of the Start and Stop con- 4. Configure the I2C port to receive data.
ditions. The Start (S) and Stop (P) bits are cleared from 5. Generate an Acknowledge condition at the end
a Reset or when the MSSP module is disabled. Control of a received byte of data.
of the I2C bus may be taken when the Stop bit is set, or
6. Generate a Stop condition on SDAx and SCLx.
the bus is Idle, with both the Start and Stop bits clear.
In Firmware Controlled Master mode, user code
conducts all I2C bus operations based on Start and
Stop bit conditions.

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Note: The MSSP module, when configured in The following events will cause the MSSP Interrupt
I2C Master mode, does not allow queueing Flag bit, SSPxIF, to be set (and MSSP interrupt, if
of events. For instance, the user is not enabled):
allowed to initiate a Start condition and • Start condition
immediately write the SSPxBUF register to • Stop condition
initiate transmission before the Start • Data transfer byte transmitted/received
condition is complete. In this case, the
• Acknowledge transmitted
SSPxBUF will not be written to and the
WCOL bit will be set, indicating that a write • Repeated Start
to the SSPxBUF did not occur.

FIGURE 20-18: MSSPx BLOCK DIAGRAM (I2C™ MASTER MODE)

Internal SSPM<3:0>
Data Bus SSPxADD<6:0>
Read Write

SSPxBUF Baud
Rate
Generator
SDAx Shift
SDAx In

Clock Arbitrate/WCOL Detect

Clock
SSPxSR

(hold off clock source)

MSb LSb
Receive Enable

Start bit, Stop bit,

Clock Cntl
Acknowledge
Generate
SCLx

Start bit Detect

Stop bit Detect
SCLx In Write Collision Detect Set/Reset S, P (SSPxSTAT), WCOL (SSPxCON1)
Clock Arbitration Set SSPxIF, BCLxIF
Bus Collision State Counter for Reset ACKSTAT, PEN (SSPxCON2)
End of XMIT/RCV

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 PIC18F47J53 FAMILY
20.5.6.1 I2C Master Mode Operation A typical transmit sequence would go as follows:
The master device generates all of the serial clock 1. The user generates a Start condition by setting
pulses and the Start and Stop conditions. A transfer is the Start Enable bit, SEN (SSPxCON2<0>).
ended with a Stop condition or with a Repeated Start 2. SSPxIF is set. The MSSP module will wait for
condition. Since the Repeated Start condition is also the required start time before any other
the beginning of the next serial transfer, the I2C bus will operation takes place.
not be released. 3. The user loads the SSPxBUF with the slave
In Master Transmitter mode, serial data is output address to transmit.
through SDAx while SCLx outputs the serial clock. The 4. The address is shifted out of the SDAx pin until
first byte transmitted contains the slave address of the all 8 bits are transmitted.
receiving device (7 bits) and the Read/Write (R/W) bit. 5. The MSSP module shifts in the ACK bit from the
In this case, the R/W bit will be logic ‘0’. Serial data is slave device and writes its value into the
transmitted, 8 bits at a time. After each byte is transmit- SSPxCON2 register (SSPxCON2<6>).
ted, an Acknowledge bit is received. S and P conditions
6. The MSSP module generates an interrupt at the
are output to indicate the beginning and end of a serial
end of the ninth clock cycle by setting the
transfer.
SSPxIF bit.
In Master Receive mode, the first byte transmitted 7. The user loads the SSPxBUF with 8 bits of data.
contains the slave address of the transmitting device
8. Data is shifted out of the SDAx pin until all 8 bits
(7 bits) and the R/W bit. In this case, the R/W bit will be
are transmitted.
logic ‘1’. Thus, the first byte transmitted is a 7-bit slave
address, followed by a ‘1’ to indicate the receive bit. 9. The MSSP module shifts in the ACK bit from the
Serial data is received via SDAx, while SCLx outputs slave device and writes its value into the
the serial clock. Serial data is received 8 bits at a time. SSPxCON2 register (SSPxCON2<6>).
After each byte is received, an Acknowledge bit is 10. The MSSP module generates an interrupt at the
transmitted. S and P conditions indicate the beginning end of the ninth clock cycle by setting the
and end of transmission. SSPxIF bit.
The BRG used for the SPI mode operation is used to 11. The user generates a Stop condition by setting
set the SCLx clock frequency for either 100 kHz, the Stop Enable bit, PEN (SSPxCON2<2>).
400 kHz or 1 MHz I2C operation. See Section 20.5.7 12. The interrupt is generated once the Stop
“Baud Rate” for more details. condition is complete.

20.5.7 BAUD RATE

In I2C Master mode, the BRG reload value is placed in
the lower seven bits of the SSPxADD register
(Figure 20-19). When a write occurs to SSPxBUF, the
Baud Rate Generator will automatically begin counting.
The BRG counts down to 0 and stops until another reload
has taken place. The BRG count is decremented twice
per instruction cycle (TCY) on the Q2 and Q4 clocks. In
I2C Master mode, the BRG is reloaded automatically.
Once the given operation is complete (i.e., transmis-
sion of the last data bit is followed by ACK), the internal
clock will automatically stop counting and the SCLx pin
will remain in its last state.
Table 20-3 demonstrates clock rates based on
instruction cycles and the BRG value loaded into
SSPxADD.

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PIC18F47J53 FAMILY
20.5.7.1 Baud Rate and Module Because this mode derives its basic clock source from
Interdependence the system clock, any changes to the clock will affect
both modules in the same proportion. It may be
Because MSSP1 and MSSP2 are independent, they
possible to change one or both baud rates back to a
can operate simultaneously in I2C Master mode at
previous value by changing the BRG reload value.
different baud rates. This is done by using different
BRG reload values for each module.

FIGURE 20-19: BAUD RATE GENERATOR BLOCK DIAGRAM

SSPM<3:0> SSPxADD<6:0>

SSPM<3:0> Reload Reload

SCLx Control

CLKO BRG Down Counter FOSC/4

TABLE 20-3: I2C™ CLOCK RATE w/BRG

FSCL
FOSC FCY FCY * 2 BRG Value
(2 Rollovers of BRG)
40 MHz 10 MHz 20 MHz 18h 400 kHz(1)
40 MHz 10 MHz 20 MHz 1Fh 312.5 kHz
40 MHz 10 MHz 20 MHz 63h 100 kHz
16 MHz 4 MHz 8 MHz 09h 400 kHz(1)
16 MHz 4 MHz 8 MHz 0Ch 308 kHz
16 MHz 4 MHz 8 MHz 27h 100 kHz
4 MHz 1 MHz 2 MHz 02h 333 kHz(1)
4 MHz 1 MHz 2 MHz 09h 100 kHz
4 MHz 1 MHz 2 MHz 00h 1 MHz(1)
Note 1: The I2C interface does not conform to the 400 kHz I2C specification (which applies to rates greater than
100 kHz) in all details, but may be used with care where higher rates are required by the application.

DS39964B-page 332 Preliminary  2010 Microchip Technology Inc.

 PIC18F47J53 FAMILY
20.5.7.2 Clock Arbitration sampled high. When the SCLx pin is sampled high, the
BRG is reloaded with the contents of SSPxADD<6:0>
Clock arbitration occurs when the master, during any
and begins counting. This ensures that the SCLx high
receive, transmit or Repeated Start/Stop condition,
time will always be at least one BRG rollover count in
deasserts the SCLx pin (SCLx allowed to float high).
the event that the clock is held low by an external
When the SCLx pin is allowed to float high, the BRG is
device (Figure 20-20).
suspended from counting until the SCLx pin is actually

FIGURE 20-20: BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION

SDAx DX DX – 1

SCLx deasserted but slave holds SCLx allowed to transition high

SCLx low (clock arbitration)
SCLx

BRG decrements on
Q2 and Q4 cycles

BRG
03h 02h 01h 00h (hold off) 03h 02h
Value

SCLx is sampled high, reload takes

place and BRG starts its count
BRG
Reload

20.5.8 I2C MASTER MODE START Note: If, at the beginning of the Start condition, the
CONDITION TIMING SDAx and SCLx pins are already sampled
To initiate a Start condition, the user sets the Start low, or if during the Start condition, the
Enable bit, SEN (SSPxCON2<0>). If the SDAx and SCLx line is sampled low before the SDAx
SCLx pins are sampled high, the BRG is reloaded with line is driven low, a bus collision occurs.
the contents of SSPxADD<6:0> and starts its count. If The Bus Collision Interrupt Flag, BCLxIF, is
SCLx and SDAx are both sampled high when the Baud set, the Start condition is aborted and the
Rate Generator times out (TBRG), the SDAx pin is I2C module is reset into its Idle state.
driven low. The action of the SDAx being driven low
while SCLx is high is the Start condition and causes the 20.5.8.1 WCOL Status Flag
Start bit (SSPxSTAT<3>) to be set. Following this, the If the user writes the SSPxBUF when a Start sequence
BRG is reloaded with the contents of SSPxADD<6:0> is in progress, the WCOL bit is set and the contents of
and resumes its count. When the BRG times out the buffer are unchanged (the write does not occur).
(TBRG), the SEN bit (SSPxCON2<0>) will be
Note: Because queueing of events is not
automatically cleared by hardware. The BRG is
allowed, writing to the lower five bits of
suspended, leaving the SDAx line held low and the Start
SSPxCON2 is disabled until the Start
condition is complete.
condition is complete.

FIGURE 20-21: FIRST START BIT TIMING

Write to SEN bit occurs here Set S bit (SSPxSTAT<3>)
SDAx = 1,
At completion of Start bit,
SCLx = 1
hardware clears SEN bit
and sets SSPxIF bit
TBRG TBRG Write to SSPxBUF occurs here

1st bit 2nd bit

SDAx
TBRG

SCLx
TBRG
S

 2010 Microchip Technology Inc. Preliminary DS39964B-page 333

PIC18F47J53 FAMILY
20.5.9 I2C MASTER MODE REPEATED Note 1: If RSEN is programmed while any other
START CONDITION TIMING event is in progress, it will not take effect.
A Repeated Start condition occurs when the RSEN bit 2: A bus collision during the Repeated Start
(SSPxCON2<1>) is programmed high and the I2C logic condition occurs if:
module is in the Idle state. When the RSEN bit is set,
• SDAx is sampled low when SCLx
the SCLx pin is asserted low. When the SCLx pin is
goes from low-to-high.
sampled low, the BRG is loaded with the contents of
SSPxADD<5:0> and begins counting. The SDAx pin is • SCLx goes low before SDAx is
released (brought high) for one BRG count (TBRG). asserted low. This may indicate that
When the BRG times out, and if SDAx is sampled high, another master is attempting to
the SCLx pin will be deasserted (brought high). When transmit a data ‘1’.
SCLx is sampled high, the BRG is reloaded with the
Immediately following the SSPxIF bit getting set, the
contents of SSPxADD<6:0> and begins counting.
user may write the SSPxBUF with the 7-bit address in
SDAx and SCLx must be sampled high for one TBRG.
7-bit mode, or the default first address in 10-bit mode.
This action is then followed by assertion of the SDAx
After the first eight bits are transmitted and an ACK is
pin (SDAx = 0) for one TBRG while SCLx is high.
received, the user may then transmit an additional 8 bits
Following this, the RSEN bit (SSPxCON2<1>) will be
of address (10-bit mode) or 8 bits of data (7-bit mode).
automatically cleared and the BRG will not be
reloaded, leaving the SDAx pin held low. As soon as a 20.5.9.1 WCOL Status Flag
Start condition is detected on the SDAx and SCLx pins,
the Start bit (SSPxSTAT<3>) will be set. The SSPxIF bit If the user writes the SSPxBUF when a Repeated Start
will not be set until the BRG has timed out. sequence is in progress, the WCOL is set and the
contents of the buffer are unchanged (the write does
not occur).
Note: Because queueing of events is not
allowed, writing of the lower five bits of
SSPxCON2 is disabled until the Repeated
Start condition is complete.

FIGURE 20-22: REPEATED START CONDITION WAVEFORM

S bit set by hardware

SDAx = 1, At completion of Start bit,
Write to SSPxCON2 occurs here: SDAx = 1, SCLx = 1 hardware clears RSEN bit
SCLx (no change). and sets SSPxIF

TBRG TBRG TBRG

SDAx 1st bit

RSEN bit set by hardware

on falling edge of ninth clock,
Write to SSPxBUF occurs here
end of XMIT
TBRG
SCLx
TBRG

Sr = Repeated Start

DS39964B-page 334 Preliminary  2010 Microchip Technology Inc.

 PIC18F47J53 FAMILY
20.5.10 I2C MASTER MODE The user should verify that the WCOL bit is clear after
TRANSMISSION each write to SSPxBUF to ensure the transfer is correct.
In all cases, WCOL must be cleared in software.
Transmission of a data byte, a 7-bit address or the
other half of a 10-bit address is accomplished by simply 20.5.10.3 ACKSTAT Status Flag
writing a value to the SSPxBUF register. This action will
set the Buffer Full flag bit, BF, and allow the BRG to In Transmit mode, the ACKSTAT bit (SSPxCON2<6>)
begin counting and start the next transmission. Each bit is cleared when the slave has sent an Acknowledge
of address/data will be shifted out onto the SDAx pin (ACK = 0) and is set when the slave does not Acknowl-
after the falling edge of SCLx is asserted (see data hold edge (ACK = 1). A slave sends an Acknowledge when
time specification, parameter 106). SCLx is held low for it has recognized its address (including a general call)
one BRG rollover count (TBRG). Data should be valid or when the slave has properly received its data.
before SCLx is released high (see data setup time
20.5.11 I2C MASTER MODE RECEPTION
specification, parameter 107). When the SCLx pin is
released high, it is held that way for TBRG. Master mode reception is enabled by programming the
Receive Enable bit, RCEN (SSPxCON2<3>).
The data on the SDAx pin must remain stable for that
duration, and some hold time, after the next falling Note: The MSSP module must be in an inactive
edge of SCLx. After the eighth bit is shifted out (the fall- state before the RCEN bit is set or the
ing edge of the eighth clock), the BF flag is cleared and RCEN bit will be disregarded.
the master releases SDAx. This allows the slave device
being addressed to respond with an ACK bit during the The BRG begins counting, and on each rollover, the
ninth bit time if an address match occurred or if data state of the SCLx pin changes (high-to-low/low-to-high)
was received properly. The status of ACK is written into and data is shifted into the SSPxSR. After the falling
the ACKDT bit on the falling edge of the ninth clock. edge of the eighth clock, the receive enable flag is
automatically cleared, the contents of the SSPxSR are
If the master receives an Acknowledge, the Acknowl- loaded into the SSPxBUF, the BF flag bit is set, the
edge Status bit, ACKSTAT, is cleared; if not, the bit is SSPxIF flag bit is set and the BRG is suspended from
set. After the ninth clock, the SSPxIF bit is set and the counting, holding SCLx low. The MSSP is now in an
master clock (BRG) is suspended until the next data Idle state awaiting the next command. When the buffer
byte is loaded into the SSPxBUF, leaving SCLx low and is read by the CPU, the BF flag bit is automatically
SDAx unchanged (Figure 20-23). cleared. The user can then send an Acknowledge bit at
After the write to the SSPxBUF, each bit of the address the end of reception by setting the Acknowledge
will be shifted out on the falling edge of SCLx until all Sequence Enable bit, ACKEN (SSPxCON2<4>).
seven address bits and the R/W bit are completed. On
the falling edge of the eighth clock, the master will 20.5.11.1 BF Status Flag
deassert the SDAx pin, allowing the slave to respond In receive operation, the BF bit is set when an address
with an Acknowledge. On the falling edge of the ninth or data byte is loaded into SSPxBUF from SSPxSR. It
clock, the master will sample the SDAx pin to see if the is cleared when the SSPxBUF register is read.
address was recognized by a slave. The status of the
ACK bit is loaded into the ACKSTAT status bit 20.5.11.2 SSPOV Status Flag
(SSPxCON2<6>). Following the falling edge of the In receive operation, the SSPOV bit is set when 8 bits
ninth clock transmission of the address, the SSPxIF are received into the SSPxSR and the BF flag bit is
flag is set, the BF flag is cleared and the BRG is turned already set from a previous reception.
off until another write to the SSPxBUF takes place,
holding SCLx low and allowing SDAx to float. 20.5.11.3 WCOL Status Flag
20.5.10.1 BF Status Flag If users write the SSPxBUF when a receive is already
in progress (i.e., SSPxSR is still shifting in a data byte),
In Transmit mode, the BF bit (SSPxSTAT<0>) is set the WCOL bit is set and the contents of the buffer are
when the CPU writes to SSPxBUF and is cleared when unchanged (the write does not occur).
all eight bits are shifted out.

20.5.10.2 WCOL Status Flag

If the user writes the SSPxBUF when a transmit is
already in progress (i.e., SSPxSR is still shifting out a
data byte), the WCOL bit is set and the contents of the
buffer are unchanged (the write does not occur) after
2 TCY after the SSPxBUF write. If SSPxBUF is rewritten
within 2 TCY, the WCOL bit is set and SSPxBUF is
updated. This may result in a corrupted transfer.

 2010 Microchip Technology Inc. Preliminary DS39964B-page 335

 FIGURE 20-23:

DS39964B-page 336
Write SSPxCON2<0> (SEN = 1), ACKSTAT in
Start condition begins SSPxCON2 = 1
From slave, clear ACKSTAT bit (SSPxCON2<6>)
SEN = 0
Transmitting Data or Second Half
Transmit Address to Slave R/W = 0
of 10-bit Address ACK

SDAx A7 A6 A5 A4 A3 A2 A1 ACK = 0 D7 D6 D5 D4 D3 D2 D1 D0

SSPxBUF written with 7-bit address and R/W,

start transmit
SCLx 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
S P
SCLx held low
while CPU
responds to SSPxIF
SSPxIF
PIC18F47J53 FAMILY

Cleared in software service routine

Cleared in software from MSSP interrupt
Cleared in software

Preliminary
BF (SSPxSTAT<0>)

SSPxBUF written SSPxBUF is written in software

SEN

After Start condition, SEN cleared by hardware

PEN

R/W
I 2C™ MASTER MODE WAVEFORM (TRANSMISSION, 7-BIT OR 10-BIT ADDRESS)

 2010 Microchip Technology Inc.

 FIGURE 20-24:

Write to SSPxCON2<4>
to start Acknowledge sequence,
SDAx = ACKDT (SSPxCON2<5>) = 0
Write to SSPxCON2<0> (SEN = 1),
begin Start condition ACK from master, Set ACKEN, start Acknowledge sequence,
Master configured as a receiver SDAx = ACKDT = 0 SDAx = ACKDT = 1
SEN = 0 by programming SSPxCON2<3> (RCEN = 1)

 2010 Microchip Technology Inc.

PEN bit = 1
Write to SSPxBUF occurs here, RCEN cleared RCEN = 1, start RCEN cleared
ACK from Slave next receive automatically written here
start XMIT automatically
Transmit Address to Slave R/W = 0 Receiving Data from Slave Receiving Data from Slave
SDAx A7 A6 A5 A4 A3 A2 A1 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK

Bus master
ACK is not sent terminates
transfer
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
SCLx S P
Data shifted in on falling edge of CLK Set SSPxIF at end
of receive Set SSPxIF interrupt
Set SSPxIF interrupt at end of Acknowledge
Set SSPxIF interrupt sequence
at end of receive
at end of Acknowledge
SSPxIF sequence

Set P bit
Cleared in software Cleared in software Cleared in software Cleared in software (SSPxSTAT<4>)
Cleared in

Preliminary
SDAx = 0, SCLx = 1, software and SSPxIF
while CPU
responds to SSPxIF

BF
(SSPxSTAT<0>) Last bit is shifted into SSPxSR and
contents are unloaded into SSPxBUF

SSPOV

SSPOV is set because

SSPxBUF is still full

ACKEN
I2C™ MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS)

DS39964B-page 337
PIC18F47J53 FAMILY
PIC18F47J53 FAMILY
20.5.12 ACKNOWLEDGE SEQUENCE 20.5.13 STOP CONDITION TIMING
TIMING A Stop bit is asserted on the SDAx pin at the end of a
An Acknowledge sequence is enabled by setting the receive/transmit by setting the Stop Sequence Enable
Acknowledge Sequence Enable bit, ACKEN bit, PEN (SSPxCON2<2>). At the end of a
(SSPxCON2<4>). When this bit is set, the SCLx pin is receive/transmit, the SCLx line is held low after the
pulled low and the contents of the Acknowledge data bit falling edge of the ninth clock. When the PEN bit is set,
are presented on the SDAx pin. If the user wishes to the master will assert the SDAx line low. When the
generate an Acknowledge, then the ACKDT bit should SDAx line is sampled low, the BRG is reloaded and
be cleared. If not, the user should set the ACKDT bit counts down to 0. When the BRG times out, the SCLx
before starting an Acknowledge sequence. The BRG pin will be brought high and one Baud Rate Generator
then counts for one rollover period (TBRG) and the SCLx rollover count (TBRG) later, the SDAx pin will be
pin is deasserted (pulled high). When the SCLx pin is deasserted. When the SDAx pin is sampled high while
sampled high (clock arbitration), the BRG counts for SCLx is high, the Stop bit (SSPxSTAT<4>) is set. A
TBRG; the SCLx pin is then pulled low. Following this, the TBRG later, the PEN bit is cleared and the SSPxIF bit is
ACKEN bit is automatically cleared, the BRG is turned set (Figure 20-26).
off and the MSSP module then goes into an inactive
state (Figure 20-25). 20.5.13.1 WCOL Status Flag
If the user writes the SSPxBUF when a Stop sequence
20.5.12.1 WCOL Status Flag is in progress, then the WCOL bit is set and the
If the user writes the SSPxBUF when an Acknowledge contents of the buffer are unchanged (the write does
sequence is in progress, then WCOL is set and the not occur).
contents of the buffer are unchanged (the write does
not occur).

FIGURE 20-25: ACKNOWLEDGE SEQUENCE WAVEFORM

Acknowledge sequence starts here, ACKEN automatically cleared
write to SSPxCON2,
ACKEN = 1, ACKDT = 0
TBRG TBRG
SDAx D0 ACK

SCLx 8 9

SSPxIF

Cleared in
SSPxIF set at software
the end of receive Cleared in
software SSPxIF set at the end
of Acknowledge sequence
Note: TBRG = one Baud Rate Generator period.

FIGURE 20-26: STOP CONDITION RECEIVE OR TRANSMIT MODE

Write to SSPxCON2, SCLx = 1 for TBRG, followed by SDAx = 1 for TBRG
set PEN after SDAx sampled high. P bit (SSPxSTAT<4>) is set

Falling edge of PEN bit (SSPxCON2<2>) is cleared by

9th clock hardware and the SSPxIF bit is set

TBRG
SCLx

SDAx ACK

P
TBRG TBRG TBRG
SCLx brought high after TBRG
SDAx asserted low before rising edge of clock
to set up Stop condition

Note: TBRG = one Baud Rate Generator period.

DS39964B-page 338 Preliminary  2010 Microchip Technology Inc.

 PIC18F47J53 FAMILY
20.5.14 SLEEP OPERATION 20.5.17 MULTI -MASTER COMMUNICATION,
2
While in Sleep mode, the I C module can receive BUS COLLISION AND BUS
addresses or data and when an address match or ARBITRATION
complete byte transfer occurs, wake the processor Multi-Master mode support is achieved by bus arbitra-
from Sleep (if the MSSP interrupt is enabled). tion. When the master outputs address/data bits onto the
SDAx pin, arbitration takes place when the master out-
20.5.15 EFFECTS OF A RESET puts a ‘1’ on SDAx, by letting SDAx float high, and
A Reset disables the MSSP module and terminates the another master asserts a ‘0’. When the SCLx pin floats
current transfer. high, data should be stable. If the expected data on
SDAx is a ‘1’ and the data sampled on the SDAx pin = 0,
20.5.16 MULTI-MASTER MODE then a bus collision has taken place. The master will set
In Multi-Master mode, the interrupt generation on the the Bus Collision Interrupt Flag, BCLxIF, and reset the
detection of the Start and Stop conditions allows the I2C port to its Idle state (Figure 20-27).
determination of when the bus is free. The Start and If a transmit was in progress when the bus collision
Stop bits are cleared from a Reset or when the MSSP occurred, the transmission is Halted, the BF flag is
module is disabled. Control of the I2C bus may be taken cleared, the SDAx and SCLx lines are deasserted and
when the P bit (SSPxSTAT<4>) is set, or the bus is Idle, the SSPxBUF can be written to. When the user services
with both the Start and Stop bits clear. When the bus is the bus collision Interrupt Service Routine, and if the I2C
busy, enabling the MSSP interrupt will generate the bus is free, the user can resume communication by
interrupt when the Stop condition occurs. asserting a Start condition.
In multi-master operation, the SDAx line must be If a Start, Repeated Start, Stop or Acknowledge condition
monitored for arbitration to see if the signal level is the was in progress when the bus collision occurred, the con-
expected output level. This check is performed in dition is aborted, the SDAx and SCLx lines are
hardware with the result placed in the BCLxIF bit. deasserted and the respective control bits in the
The states where arbitration can be lost are: SSPxCON2 register are cleared. When the user services
the bus collision Interrupt Service Routine (ISR), and if
• Address Transfer the I2C bus is free, the user can resume communication
• Data Transfer by asserting a Start condition.
• A Start Condition The master will continue to monitor the SDAx and SCLx
• A Repeated Start Condition pins. If a Stop condition occurs, the SSPxIF bit will be set.
• An Acknowledge Condition A write to the SSPxBUF will start the transmission of
data at the first data bit regardless of where the
transmitter left off when the bus collision occurred.
In Multi-Master mode, the interrupt generation on the
detection of Start and Stop conditions allows the deter-
mination of when the bus is free. Control of the I2C bus
can be taken when the Stop bit is set in the SSPxSTAT
register, or the bus is Idle and the Start and Stop bits
are cleared.

FIGURE 20-27: BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE

Sample SDAx. While SCLx is high,
Data changes SDAx line pulled low data doesn’t match what is driven
while SCLx = 0 by another source by the master;
SDAx released bus collision has occurred
by master

SDAx

SCLx Set bus collision

interrupt (BCLxIF)

BCLxIF

 2010 Microchip Technology Inc. Preliminary DS39964B-page 339

PIC18F47J53 FAMILY
20.5.17.1 Bus Collision During a Start If the SDAx pin is sampled low during this count, the
Condition BRG is reset and the SDAx line is asserted early
(Figure 20-30). If, however, a ‘1’ is sampled on the
During a Start condition, a bus collision occurs if:
SDAx pin, the SDAx pin is asserted low at the end of
a) SDAx or SCLx is sampled low at the beginning the BRG count. The BRG is then reloaded and counts
of the Start condition (Figure 20-28). down to 0. If the SCLx pin is sampled as ‘0’ during this
b) SCLx is sampled low before SDAx is asserted time, a bus collision does not occur. At the end of the
low (Figure 20-29). BRG count, the SCLx pin is asserted low.
During a Start condition, both the SDAx and the SCLx Note: The reason that a bus collision is not a fac-
pins are monitored. tor during a Start condition is that no two
If the SDAx pin is already low, or the SCLx pin is bus masters can assert a Start condition at
already low, then all of the following occur: the exact same time. Therefore, one mas-
ter will always assert SDAx before the
• The Start condition is aborted
other. This condition does not cause a bus
• The BCLxIF flag is set collision because the two masters must be
• The MSSP module is reset to its inactive state allowed to arbitrate the first address
(Figure 20-28) following the Start condition. If the address
The Start condition begins with the SDAx and SCLx is the same, arbitration must be allowed to
pins deasserted. When the SDAx pin is sampled high, continue into the data portion, Repeated
the BRG is loaded from SSPxADD<6:0> and counts Start or Stop conditions.
down to 0. If the SCLx pin is sampled low while SDAx
is high, a bus collision occurs because it is assumed
that another master is attempting to drive a data ‘1’
during the Start condition.

FIGURE 20-28: BUS COLLISION DURING START CONDITION (SDAx ONLY)

SDAx goes low before the SEN bit is set.

Set BCLxIF,
S bit and SSPxIF set because
SDAx = 0, SCLx = 1.

SDAx

SCLx
Set SEN, enable Start SEN cleared automatically because of bus collision.
condition if SDAx = 1, SCLx = 1 MSSPx module reset into Idle state.
SEN
SDAx sampled low before
Start condition. Set BCLxIF.
S bit and SSPxIF set because
BCLxIF SDAx = 0, SCLx = 1.
SSPxIF and BCLxIF are
cleared in software

SSPxIF

SSPxIF and BCLxIF are

cleared in software

DS39964B-page 340 Preliminary  2010 Microchip Technology Inc.

 PIC18F47J53 FAMILY
FIGURE 20-29: BUS COLLISION DURING START CONDITION (SCLx = 0)
SDAx = 0, SCLx = 1

TBRG TBRG

SDAx

SCLx Set SEN, enable Start

sequence if SDAx = 1, SCLx = 1
SCLx = 0 before SDAx = 0,
bus collision occurs. Set BCLxIF.
SEN
SCLx = 0 before BRG time-out,
bus collision occurs. Set BCLxIF.
BCLxIF
Interrupt cleared
in software
S ‘0’ ‘0’

SSPxIF ‘0’ ‘0’

FIGURE 20-30: BRG RESET DUE TO SDAx ARBITRATION DURING START CONDITION

SDAx = 0, SCLx = 1
Set S Set SSPxIF
Less than TBRG
TBRG

SDAx SDAx pulled low by other master.

Reset BRG and assert SDAx.

SCLx S
SCLx pulled low after BRG
time-out
SEN
Set SEN, enable Start
sequence if SDAx = 1, SCLx = 1
BCLxIF ‘0’

SSPxIF
SDAx = 0, SCLx = 1, Interrupts cleared
set SSPxIF in software

 2010 Microchip Technology Inc. Preliminary DS39964B-page 341

PIC18F47J53 FAMILY
20.5.17.2 Bus Collision During a Repeated If SDAx is low, a bus collision has occurred (i.e., another
Start Condition master is attempting to transmit a data ‘0’; see
Figure 20-31). If SDAx is sampled high, the BRG is
During a Repeated Start condition, a bus collision
reloaded and begins counting. If SDAx goes from
occurs if:
high-to-low before the BRG times out, no bus collision
a) A low level is sampled on SDAx when SCLx occurs because no two masters can assert SDAx at
goes from a low level to a high level. exactly the same time.
b) SCLx goes low before SDAx is asserted low, If SCLx goes from high-to-low before the BRG times
indicating that another master is attempting to out and SDAx has not already been asserted, a bus
transmit a data ‘1’. collision occurs. In this case, another master is
When the user deasserts SDAx and the pin is allowed attempting to transmit a data ‘1’ during the Repeated
to float high, the BRG is loaded with SSPxADD<6:0> Start condition (see Figure 20-32).
and counts down to 0. The SCLx pin is then deasserted If, at the end of the BRG time-out, both SCLx and SDAx
and when sampled high, the SDAx pin is sampled. are still high, the SDAx pin is driven low and the BRG is
reloaded and begins counting. At the end of the count,
regardless of the status of the SCLx pin, the SCLx pin is
driven low and the Repeated Start condition is complete.

FIGURE 20-31: BUS COLLISION DURING A REPEATED START CONDITION (CASE 1)

SDAx

SCLx

Sample SDAx when SCLx goes high.

If SDAx = 0, set BCLxIF and release SDAx and SCLx.

RSEN

BCLxIF

Cleared in software
S ‘0’

SSPxIF ‘0’

FIGURE 20-32: BUS COLLISION DURING REPEATED START CONDITION (CASE 2)

TBRG TBRG

SDAx

SCLx

SCLx goes low before SDAx,

BCLxIF set BCLxIF. Release SDAx and SCLx.
Interrupt cleared
in software
RSEN

S ‘0’

SSPxIF

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20.5.17.3 Bus Collision During a Stop The Stop condition begins with SDAx asserted low.
Condition When SDAx is sampled low, the SCLx pin is allowed to
float. When the pin is sampled high (clock arbitration),
Bus collision occurs during a Stop condition if:
the BRG is loaded with SSPxADD<6:0> and counts
a) After the SDAx pin has been deasserted and down to 0. After the BRG times out, SDAx is sampled. If
allowed to float high, SDAx is sampled low after SDAx is sampled low, a bus collision has occurred. This
the BRG has timed out. is due to another master attempting to drive a data ‘0’
b) After the SCLx pin is deasserted, SCLx is (Figure 20-33). If the SCLx pin is sampled low before
sampled low before SDAx goes high. SDAx is allowed to float high, a bus collision occurs. This
is another case of another master attempting to drive a
data ‘0’ (Figure 20-34).

FIGURE 20-33: BUS COLLISION DURING A STOP CONDITION (CASE 1)

TBRG TBRG TBRG SDAx sampled

low after TBRG,
set BCLxIF
SDAx

SDAx asserted low

SCLx

PEN

BCLxIF

P ‘0’

SSPxIF ‘0’

FIGURE 20-34: BUS COLLISION DURING A STOP CONDITION (CASE 2)

TBRG TBRG TBRG

SDAx
SCLx goes low before SDAx goes high,
Assert SDAx
set BCLxIF
SCLx

PEN

BCLxIF

P ‘0’

SSPxIF ‘0’

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TABLE 20-4: REGISTERS ASSOCIATED WITH I2C™ OPERATION
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF
(3)
PIR1 PMPIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF
PIE1 PMPIE(3) ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE
IPR1 PMPIP(3) ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP
PIR2 OSCFIF CM2IF CM1IF USBIF BCL1IF HLVDIF TMR3IF CCP2IF
PIE2 OSCFIE CM2IE CM1IE USBIE BCL1IE HLVDIE TMR3IE CCP2IE
IPR2 OSCFIP CM2IP CM1IP USBIP BCL1IP HLVDIP TMR3IP CCP2IP
PIR3 SSP2IF BCL2IF RC2IF TX2IF TMR4IF CTMUIF TMR3GIF RTCCIF
PIE3 SSP2IE BCL2IE RC2IE TX2IE TMR4IE CTMUIE TMR3GIE RTCCIE
IPR3 SSP2IP BCL2IP RC2IP TX2IP TMR4IP CTMUIP TMR3GIP RTCCIP
TRISC TRISC7 TRISC6 — — — TRISC2 TRISC1 TRISC0
TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0
SSP1BUF MSSP1 Receive Buffer/Transmit Register
SSP1ADD MSSP1 Address Register (I2C™ Slave mode), MSSP1 Baud Rate Reload Register (I2C Master mode)
SSPxMSK(1) MSK7 MSK6 MSK5 MSK4 MSK3 MSK2 MSK1 MSK0
SSPxCON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0
SSPxCON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN
(2) (2) (2) (2) (2)
GCEN ACKSTAT ADMSK5 ADMSK4 ADMSK3 ADMSK2 ADMSK1 SEN
SSPxSTAT SMP CKE D/A P S R/W UA BF
SSP2BUF MSSP2 Receive Buffer/Transmit Register
SSP2ADD MSSP2 Address Register (I2C Slave mode), MSSP2 Baud Rate Reload Register (I2C Master mode)
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the MSSPx module in I2C™ mode.
Note 1: SSPxMSK shares the same address in SFR space as SSPxADD, but is only accessible in certain I2C Slave
mode operations in 7-Bit Masking mode. See Section 20.5.3.4 “7-Bit Address Masking Mode” for more
details.
2: Alternate bit definitions for use in I2C Slave mode operations only.
3: These bits are only available on 44-pin devices.

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21.0 ENHANCED UNIVERSAL The pins of EUSART1 and EUSART2 are multiplexed
with the functions of PORTC (RC6/CCP9/TX1/CK1/RP17
SYNCHRONOUS
and RC7/CCP10/RX1/DT1/SDO1/RP18) and remapped
ASYNCHRONOUS RECEIVER (RPn1/TX2/CK2 and RPn2/RX2/DT2), respectively. In
TRANSMITTER (EUSART) order to configure these pins as an EUSART:
The Enhanced Universal Synchronous Asynchronous • For EUSART1:
Receiver Transmitter (EUSART) module is one of two - SPEN bit (RCSTA1<7>) must be set (= 1)
serial I/O modules. (Generically, the EUSART is also - TRISC<7> bit must be set (= 1)
known as a Serial Communications Interface or SCI.) - TRISC<6> bit must be cleared (= 0) for
The EUSART can be configured as a full-duplex Asynchronous and Synchronous Master
asynchronous system that can communicate with modes
peripheral devices, such as CRT terminals and
- TRISC<6> bit must be set (= 1) for
personal computers. It can also be configured as a
Synchronous Slave mode
half-duplex synchronous system that can communicate
with peripheral devices, such as A/D or D/A integrated • For EUSART2:
circuits, serial EEPROMs and so on. - SPEN bit (RCSTA2<7>) must be set (= 1)
The Enhanced USART module implements additional - TRIS bit for RPn2/RX2/DT2 = 1
features, including Automatic Baud Rate Detection and - TRIS bit for RPn1/TX2/CK2 = 0 for
calibration, automatic wake-up on Sync Break recep- Asynchronous and Synchronous Master
tion, and 12-bit Break character transmit. These make modes
it ideally suited for use in Local Interconnect Network - TRISC<6> bit must be set (= 1) for
bus (LIN/J2602 bus) systems. Synchronous Slave mode
All members of the PIC18F47J53 family are equipped Note: The EUSART control will automatically
with two independent EUSART modules, referred to as reconfigure the pin from input to output as
EUSART1 and EUSART2. They can be configured in needed.
the following modes: The TXx/CKx I/O pins have an optional open-drain
• Asynchronous (full-duplex) with: output capability. By default, when this pin is used by
- Auto-wake-up on character reception the EUSART as an output, it will function as a standard
- Auto-baud calibration push-pull CMOS output. The TXx/CKx I/O pins’
open-drain, output feature can be enabled by setting
- 12-bit Break character transmission
the corresponding UxOD bit in the ODCON2 register.
• Synchronous – Master (half-duplex) with For more details, see Section 20.3.3 “Open-Drain
selectable clock polarity Output Option”.
• Synchronous – Slave (half-duplex) with selectable
The operation of each Enhanced USART module is
clock polarity
controlled through three registers:
• Transmit Status and Control (TXSTAx)
• Receive Status and Control (RCSTAx)
• Baud Rate Control (BAUDCONx)
These are covered in detail in Register 21-1,
Register 21-2 and Register 21-3, respectively.
Note: Throughout this section, references to
register and bit names that may be associ-
ated with a specific EUSART module are
referred to generically by the use of ‘x’ in
place of the specific module number.
Thus, “RCSTAx” might refer to the
Receive Status register for either
EUSART1 or EUSART2.

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REGISTER 21-1: TXSTAx: TRANSMIT STATUS AND CONTROL REGISTER
(1, ACCESS FADh; 2, FA8h)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-1 R/W-0
CSRC TX9 TXEN(1) SYNC SENDB BRGH TRMT TX9D
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 CSRC: Clock Source Select bit

Asynchronous mode:
Don’t care.
Synchronous mode:
1 = Master mode (clock generated internally from BRG)
0 = Slave mode (clock from external source)
bit 6 TX9: 9-Bit Transmit Enable bit
1 = Selects 9-bit transmission
0 = Selects 8-bit transmission
bit 5 TXEN: Transmit Enable bit(1)
1 = Transmit is enabled
0 = Transmit is disabled
bit 4 SYNC: EUSART Mode Select bit
1 = Synchronous mode
0 = Asynchronous mode
bit 3 SENDB: Send Break Character bit
Asynchronous mode:
1 = Send Sync Break on next transmission (cleared by hardware upon completion)
0 = Sync Break transmission completed
Synchronous mode:
Don’t care.
bit 2 BRGH: High Baud Rate Select bit
Asynchronous mode:
1 = High speed
0 = Low speed
Synchronous mode:
Unused in this mode.
bit 1 TRMT: Transmit Shift Register Status bit
1 = TSR is empty
0 = TSR is full
bit 0 TX9D: 9th bit of Transmit Data
Can be address/data bit or a parity bit.

Note 1: SREN/CREN overrides TXEN in Sync mode.

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REGISTER 21-2: RCSTAx: RECEIVE STATUS AND CONTROL REGISTER
(1, ACCESS FACh; 2, FC9h)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-x
SPEN RX9 SREN CREN ADDEN FERR OERR RX9D
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 SPEN: Serial Port Enable bit

1 = Serial port enabled (configures RXx/DTx and TXx/CKx pins as serial port pins)
0 = Serial port disabled (held in Reset)
bit 6 RX9: 9-Bit Receive Enable bit
1 = Selects 9-bit reception
0 = Selects 8-bit reception
bit 5 SREN: Single Receive Enable bit
Asynchronous mode:
Don’t care.
Synchronous mode – Master:
1 = Enables single receive
0 = Disables single receive
This bit is cleared after reception is complete.
Synchronous mode – Slave:
Don’t care.
bit 4 CREN: Continuous Receive Enable bit
Asynchronous mode:
1 = Enables receiver
0 = Disables receiver
Synchronous mode:
1 = Enables continuous receive until enable bit, CREN, is cleared (CREN overrides SREN)
0 = Disables continuous receive
bit 3 ADDEN: Address Detect Enable bit
Asynchronous mode 9-Bit (RX9 = 1):
1 = Enables address detection, enables interrupt and loads the receive buffer when RSR<8> is set
0 = Disables address detection, all bytes are received and the ninth bit can be used as a parity bit
Asynchronous mode 9-Bit (RX9 = 0):
Don’t care.
bit 2 FERR: Framing Error bit
1 = Framing error (can be updated by clearing the RCREGx register and receiving the next valid byte)
0 = No framing error
bit 1 OERR: Overrun Error bit
1 = Overrun error (can be cleared by clearing bit, CREN)
0 = No overrun error
bit 0 RX9D: 9th bit of Received Data
This can be address/data bit or a parity bit and must be calculated by user firmware.

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REGISTER 21-3: BAUDCONx: BAUD RATE CONTROL REGISTER (ACCESS F7Eh, F7Ch)
R/W-0 R-1 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0
ABDOVF RCIDL RXDTP TXCKP BRG16 — WUE ABDEN
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 ABDOVF: Auto-Baud Acquisition Rollover Status bit

1 = A BRG rollover has occurred during Auto-Baud Rate Detect mode (must be cleared in software)
0 = No BRG rollover has occurred
bit 6 RCIDL: Receive Operation Idle Status bit
1 = Receive operation is Idle
0 = Receive operation is active
bit 5 RXDTP: Data/Receive Polarity Select bit
Asynchronous mode:
1 = Receive data (RXx) is inverted (active-low)
0 = Receive data (RXx) is not inverted (active-high)
Synchronous mode:
1 = Data (DTx) is inverted (active-low)
0 = Data (DTx) is not inverted (active-high)
bit 4 TXCKP: Synchronous Clock Polarity Select bit
Asynchronous mode:
1 = Idle state for transmit (TXx) is a low level
0 = Idle state for transmit (TXx) is a high level
Synchronous mode:
1 = Idle state for clock (CKx) is a high level
0 = Idle state for clock (CKx) is a low level
bit 3 BRG16: 16-Bit Baud Rate Register Enable bit
1 = 16-bit Baud Rate Generator – SPBRGHx and SPBRGx
0 = 8-bit Baud Rate Generator – SPBRGx only (Compatible mode), SPBRGHx value is ignored
bit 2 Unimplemented: Read as ‘0’
bit 1 WUE: Wake-up Enable bit
Asynchronous mode:
1 = EUSART will continue to sample the RXx pin – interrupt is generated on the falling edge; bit is
cleared in hardware on the following rising edge
0 = RXx pin is not monitored or the rising edge detected
Synchronous mode:
Unused in this mode.
bit 0 ABDEN: Auto-Baud Detect Enable bit
Asynchronous mode:
1 = Enable baud rate measurement on the next character; requires reception of a Sync field (55h);
cleared in hardware upon completion
0 = Baud rate measurement disabled or completed
Synchronous mode:
Unused in this mode.

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21.1 Baud Rate Generator (BRG) Writing a new value to the SPBRGHx:SPBRGx
registers causes the BRG timer to be reset (or cleared).
The BRG is a dedicated, 8-bit or 16-bit generator that This ensures the BRG does not wait for a timer
supports both the Asynchronous and Synchronous overflow before outputting the new baud rate.
modes of the EUSART. By default, the BRG operates
in 8-bit mode; setting the BRG16 bit (BAUDCONx<3>) 21.1.1 OPERATION IN POWER-MANAGED
selects 16-bit mode. MODES
The SPBRGHx:SPBRGx register pair controls the period The device clock is used to generate the desired baud
of a free-running timer. In Asynchronous mode, the rate. When one of the power-managed modes is
BRGH (TXSTAx<2>) and BRG16 (BAUDCONx<3>) bits entered, the new clock source may be operating at a
also control the baud rate. In Synchronous mode, BRGH different frequency. This may require an adjustment to
is ignored. the value in the SPBRGx register pair.
Table 21-1 provides the formula for computation of the
baud rate for different EUSART modes, which only apply 21.1.2 SAMPLING
in Master mode (internally generated clock). The data on the RXx pin (either RC7/CCP10/PMA4/
Given the desired baud rate and FOSC, the nearest RX1/DT1/SDO1/RP18 or RPn2/RX2/DT2) is sampled
integer value for the SPBRGHx:SPBRGx registers can three times by a majority detect circuit to determine if a
be calculated using the formulas in Table 21-1. From high or a low level is present at the RXx pin.
this, the error in baud rate can be determined. An
example calculation is provided in Example 21-1.
Typical baud rates and error values for the various
Asynchronous modes are provided in Table 21-2. It
may be advantageous to use the high baud rate
(BRGH = 1) or the 16-bit BRG to reduce the baud rate
error, or achieve a slow baud rate for a fast oscillator
frequency.

TABLE 21-1: BAUD RATE FORMULAS

Configuration Bits
BRG/EUSART Mode Baud Rate Formula
SYNC BRG16 BRGH
0 0 0 8-bit/Asynchronous FOSC/[64 (n + 1)]
0 0 1 8-bit/Asynchronous
FOSC/[16 (n + 1)]
0 1 0 16-bit/Asynchronous
0 1 1 16-bit/Asynchronous
1 0 x 8-bit/Synchronous FOSC/[4 (n + 1)]
1 1 x 16-bit/Synchronous
Legend: x = Don’t care, n = value of SPBRGHx:SPBRGx register pair

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EXAMPLE 21-1: CALCULATING BAUD RATE ERROR
For a device with Fosc of 16 MHz, desired baud rate of 9600, Asynchronous mode, and
8-bit BRG:
Desired Baud Rate = Fosc/(64 ([SPBRGHx:SPBRGx] + 1))
Solving for SPBRGHx:SPBRGx:
X = ((Fosc/Desired Baud Rate)/64) – 1
= ((16000000/9600)/64) – 1
= [25.042] = 25
Calculated Baud Rate=16000000/(64 (25 + 1))
= 9615
Error = (Calculated Baud Rate – Desired Baud Rate)/Desired Baud Rate
= (9615 – 9600)/9600 = 0.16%

TABLE 21-2: REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
TXSTAx CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D
RCSTAx SPEN RX9 SREN CREN ADDEN FERR OERR RX9D
BAUDCONx ABDOVF RCIDL RXDTP TXCKP BRG16 — WUE ABDEN
SPBRGHx EUSARTx Baud Rate Generator High Byte
SPBRGx EUSARTx Baud Rate Generator Low Byte
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the BRG.

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TABLE 21-3: BAUD RATES FOR ASYNCHRONOUS MODES
SYNC = 0, BRGH = 0, BRG16 = 0
BAUD
FOSC = 40.000 MHz FOSC = 20.000 MHz FOSC = 10.000 MHz FOSC = 8.000 MHz
RATE
(K) Actual SPBRG Actual SPBRG Actual SPBRG Actual SPBRG
% % % %
Rate value Rate value Rate value Rate value
Error Error Error Error
(K) (decimal) (K) (decimal) (K) (decimal) (K) (decimal)

0.3 — — — — — — — — — — — —
1.2 — — — 1.221 1.73 255 1.202 0.16 129 1.201 -0.16 103
2.4 2.441 1.73 255 2.404 0.16 129 2.404 0.16 64 2.403 -0.16 51
9.6 9.615 0.16 64 9.766 1.73 31 9.766 1.73 15 9.615 -0.16 12
19.2 19.531 1.73 31 19.531 1.73 15 19.531 1.73 7 — — —
57.6 56.818 -1.36 10 62.500 8.51 4 52.083 -9.58 2 — — —
115.2 125.000 8.51 4 104.167 -9.58 2 78.125 -32.18 1 — — —

SYNC = 0, BRGH = 0, BRG16 = 0

BAUD
FOSC = 4.000 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz
RATE
(K) Actual SPBRG Actual SPBRG Actual SPBRG
% % %
Rate value Rate value Rate value
Error Error Error
(K) (decimal) (K) (decimal) (K) (decimal)

0.3 0.300 0.16 207 0.300 -0.16 103 0.300 -0.16 51

1.2 1.202 0.16 51 1.201 -0.16 25 1.201 -0.16 12
2.4 2.404 0.16 25 2.403 -0.16 12 — — —
9.6 8.929 -6.99 6 — — — — — —
19.2 20.833 8.51 2 — — — — — —
57.6 62.500 8.51 0 — — — — — —
115.2 62.500 -45.75 0 — — — — — —

SYNC = 0, BRGH = 1, BRG16 = 0

BAUD
FOSC = 40.000 MHz FOSC = 20.000 MHz FOSC = 10.000 MHz FOSC = 8.000 MHz
RATE
(K) Actual SPBRG Actual SPBRG Actual SPBRG Actual SPBRG
% % % %
Rate value Rate value Rate value Rate value
Error Error Error Error
(K) (decimal) (K) (decimal) (K) (decimal) (K) (decimal)

0.3 — — — — — — — — — — — —
1.2 — — — — — — — — — — — —
2.4 — — — — — — 2.441 1.73 255 2.403 -0.16 207
9.6 9.766 1.73 255 9.615 0.16 129 9.615 0.16 64 9615. -0.16 51
19.2 19.231 0.16 129 19.231 0.16 64 19.531 1.73 31 19.230 -0.16 25
57.6 58.140 0.94 42 56.818 -1.36 21 56.818 -1.36 10 55.555 3.55 8
115.2 113.636 -1.36 21 113.636 -1.36 10 125.000 8.51 4 — — —

SYNC = 0, BRGH = 1, BRG16 = 0

BAUD
FOSC = 4.000 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz
RATE
(K) Actual SPBRG Actual SPBRG Actual SPBRG
% % %
Rate value Rate value Rate value
Error Error Error
(K) (decimal) (K) (decimal) (K) (decimal)

0.3 — — — — — — 0.300 -0.16 207

1.2 1.202 0.16 207 1.201 -0.16 103 1.201 -0.16 51
2.4 2.404 0.16 103 2.403 -0.16 51 2.403 -0.16 25
9.6 9.615 0.16 25 9.615 -0.16 12 — — —
19.2 19.231 0.16 12 — — — — — —
57.6 62.500 8.51 3 — — — — — —
115.2 125.000 8.51 1 — — — — — —

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TABLE 21-3: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED)
SYNC = 0, BRGH = 0, BRG16 = 1
BAUD FOSC = 40.000 MHz FOSC = 20.000 MHz FOSC = 10.000 MHz FOSC = 8.000 MHz
RATE
(K) Actual SPBRG Actual SPBRG Actual SPBRG Actual SPBRG
% % % %
Rate value Rate value Rate value Rate value
Error Error Error Error
(K) (decimal) (K) (decimal) (K) (decimal) (K) (decimal)

0.3 0.300 0.00 8332 0.300 0.02 4165 0.300 0.02 2082 0.300 -0.04 1665
1.2 1.200 0.02 2082 1.200 -0.03 1041 1.200 -0.03 520 1.201 -0.16 415
2.4 2.402 0.06 1040 2.399 -0.03 520 2.404 0.16 259 2.403 -0.16 207
9.6 9.615 0.16 259 9.615 0.16 129 9.615 0.16 64 9.615 -0.16 51
19.2 19.231 0.16 129 19.231 0.16 64 19.531 1.73 31 19.230 -0.16 25
57.6 58.140 0.94 42 56.818 -1.36 21 56.818 -1.36 10 55.555 3.55 8
115.2 113.636 -1.36 21 113.636 -1.36 10 125.000 8.51 4 — — —

SYNC = 0, BRGH = 0, BRG16 = 1

BAUD
FOSC = 4.000 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz
RATE
(K) Actual SPBRG Actual SPBRG Actual SPBRG
% % %
Rate value Rate value Rate value
Error Error Error
(K) (decimal) (K) (decimal) (K) (decimal)

0.3 0.300 0.04 832 0.300 -0.16 415 0.300 -0.16 207
1.2 1.202 0.16 207 1.201 -0.16 103 1.201 -0.16 51
2.4 2.404 0.16 103 2.403 -0.16 51 2.403 -0.16 25
9.6 9.615 0.16 25 9.615 -0.16 12 — — —
19.2 19.231 0.16 12 — — — — — —
57.6 62.500 8.51 3 — — — — — —
115.2 125.000 8.51 1 — — — — — —

SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1

BAUD FOSC = 40.000 MHz FOSC = 20.000 MHz FOSC = 10.000 MHz FOSC = 8.000 MHz
RATE
(K) Actual SPBRG Actual SPBRG Actual SPBRG Actual SPBRG
% % % %
Rate value Rate value Rate value Rate value
Error Error Error Error
(K) (decimal) (K) (decimal) (K) (decimal) (K) (decimal)

0.3 0.300 0.00 33332 0.300 0.00 16665 0.300 0.00 8332 0.300 -0.01 6665
1.2 1.200 0.00 8332 1.200 0.02 4165 1.200 0.02 2082 1.200 -0.04 1665
2.4 2.400 0.02 4165 2.400 0.02 2082 2.402 0.06 1040 2.400 -0.04 832
9.6 9.606 0.06 1040 9.596 -0.03 520 9.615 0.16 259 9.615 -0.16 207
19.2 19.193 -0.03 520 19.231 0.16 259 19.231 0.16 129 19.230 -0.16 103
57.6 57.803 0.35 172 57.471 -0.22 86 58.140 0.94 42 57.142 0.79 34
115.2 114.943 -0.22 86 116.279 0.94 42 113.636 -1.36 21 117.647 -2.12 16

SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1

BAUD FOSC = 4.000 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz
RATE
(K) Actual SPBRG Actual SPBRG Actual SPBRG
% % %
Rate value Rate value Rate value
Error Error Error
(K) (decimal) (K) (decimal) (K) (decimal)

0.3 0.300 0.01 3332 0.300 -0.04 1665 0.300 -0.04 832
1.2 1.200 0.04 832 1.201 -0.16 415 1.201 -0.16 207
2.4 2.404 0.16 415 2.403 -0.16 207 2.403 -0.16 103
9.6 9.615 0.16 103 9.615 -0.16 51 9.615 -0.16 25
19.2 19.231 0.16 51 19.230 -0.16 25 19.230 -0.16 12
57.6 58.824 2.12 16 55.555 3.55 8 — — —
115.2 111.111 -3.55 8 — — — — — —

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21.1.3 AUTO-BAUD RATE DETECT Note 1: If the WUE bit is set with the ABDEN bit,
The Enhanced USART module supports the automatic Auto-Baud Rate Detection will occur on
detection and calibration of baud rate. This feature is the byte following the Break character.
active only in Asynchronous mode and while the WUE 2: It is up to the user to determine that the
bit is clear. incoming character baud rate is within the
The automatic baud rate measurement sequence range of the selected BRG clock source.
(Figure 21-1) begins whenever a Start bit is received Some combinations of oscillator frequency
and the ABDEN bit is set. The calculation is and EUSART baud rates are not possible
self-averaging. due to bit error rates. Overall system
timing and communication baud rates
In the Auto-Baud Rate Detect (ABD) mode, the clock to
must be taken into consideration when
the BRG is reversed. Rather than the BRG clocking the
using the Auto-Baud Rate Detection
incoming RXx signal, the RXx signal is timing the BRG.
feature.
In ABD mode, the internal BRG is used as a counter to
time the bit period of the incoming serial byte stream.
TABLE 21-4: BRG COUNTER
Once the ABDEN bit is set, the state machine will clear
the BRG and look for a Start bit. The ABD must receive CLOCK RATES
a byte with the value, 55h (ASCII “U”, which is also the BRG16 BRGH BRG Counter Clock
LIN/J2602 bus Sync character), in order to calculate the
proper bit rate. The measurement is taken over both a 0 0 FOSC/512
low and high bit time in order to minimize any effects 0 1 FOSC/128
caused by asymmetry of the incoming signal. After a 1 0 FOSC/128
Start bit, the SPBRGx begins counting up, using the pre-
1 1 FOSC/32
selected clock source on the first rising edge of RXx.
After eight bits on the RXx pin, or the fifth rising edge, an Note: During the ABD sequence, SPBRGx and
accumulated value totalling the proper BRG period is left SPBRGHx are both used as a 16-bit
in the SPBRGHx:SPBRGx register pair. Once the 5th counter, independent of the BRG16 setting.
edge is seen (this should correspond to the Stop bit), the
ABDEN bit is automatically cleared. 21.1.3.1 ABD and EUSART Transmission
If a rollover of the BRG occurs (an overflow from FFFFh Since the BRG clock is reversed during ABD acquisi-
to 0000h), the event is trapped by the ABDOVF status tion, the EUSART transmitter cannot be used during
bit (BAUDCONx<7>). It is set in hardware by BRG roll- ABD. This means that whenever the ABDEN bit is set,
overs and can be set or cleared by the user in software. TXREGx cannot be written to. Users should also
ABD mode remains active after rollover events and the ensure that ABDEN does not become set during a
ABDEN bit remains set (Figure 21-2). transmit sequence. Failing to do this may result in
While calibrating the baud rate period, the BRG unpredictable EUSART operation.
registers are clocked at 1/8th the preconfigured clock
rate. Note that the BRG clock will be configured by the
BRG16 and BRGH bits. Independent of the BRG16 bit
setting, both the SPBRGx and SPBRGHx will be used
as a 16-bit counter. This allows the user to verify that
no carry occurred for 8-bit modes by checking for 00h
in the SPBRGHx register.
Refer to Table 21-4 for counter clock rates to the BRG.
While the ABD sequence takes place, the EUSART
state machine is held in Idle. The RCxIF interrupt is set
once the fifth rising edge on RXx is detected. The value
in the RCREGx needs to be read to clear the RCxIF
interrupt. The contents of RCREGx should be
discarded.

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FIGURE 21-1: AUTOMATIC BAUD RATE CALCULATION

BRG Value XXXXh 0000h 001Ch

Edge #1 Edge #2 Edge #3 Edge #4 Edge #5

RXx pin Start Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Stop Bit

BRG Clock

Set by User Auto-Cleared

ABDEN bit

RCxIF bit
(Interrupt)

Read
RCREGx

SPBRGx XXXXh 1Ch

SPBRGHx XXXXh 00h

Note: The ABD sequence requires the EUSART module to be configured in Asynchronous mode and WUE = 0.

FIGURE 21-2: BRG OVERFLOW SEQUENCE

BRG Clock

ABDEN bit

RXx pin Start Bit 0

ABDOVF bit
FFFFh
BRG Value XXXXh 0000h 0000h

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21.2 EUSART Asynchronous Mode Once the TXREGx register transfers the data to the TSR
register (occurs in one TCY), the TXREGx register is
The Asynchronous mode of operation is selected by empty and the TXxIF flag bit is set. This interrupt can be
clearing the SYNC bit (TXSTAx<4>). In this mode, the enabled or disabled by setting or clearing the interrupt
EUSART uses standard Non-Return-to-Zero (NRZ) enable bit, TXxIE. TXxIF will be set regardless of the
format (one Start bit, eight or nine data bits and one Stop state of TXxIE; it cannot be cleared in software. TXxIF is
bit). The most common data format is 8 bits. An on-chip
also not cleared immediately upon loading TXREGx, but
dedicated 8-bit/16-bit BRG can be used to derive
becomes valid in the second instruction cycle following
standard baud rate frequencies from the oscillator.
the load instruction. Polling TXxIF immediately following
The EUSART transmits and receives the LSb first. The a load of TXREGx will return invalid results.
EUSART’s transmitter and receiver are functionally
independent but use the same data format and baud While TXxIF indicates the status of the TXREGx
rate. The BRG produces a clock, either x16 or x64 of the register; another bit, TRMT (TXSTAx<1>), shows the
bit shift rate, depending on the BRGH and BRG16 bits status of the TSR register. TRMT is a read-only bit,
(TXSTAx<2> and BAUDCONx<3>). Parity is not which is set when the TSR register is empty. No inter-
supported by the hardware but can be implemented in rupt logic is tied to this bit, so the user has to poll this
software and stored as the ninth data bit. bit in order to determine if the TSR register is empty.
When operating in Asynchronous mode, the EUSART Note 1: The TSR register is not mapped in data
module consists of the following important elements: memory, so it is not available to the user.
• Baud Rate Generator 2: Flag bit, TXxIF, is set when enable bit,
• Sampling Circuit TXEN, is set.
• Asynchronous Transmitter To set up an Asynchronous Transmission:
• Asynchronous Receiver
1. Initialize the SPBRGHx:SPBRGx registers for
• Auto-Wake-up on Sync Break Character the appropriate baud rate. Set or clear the
• 12-Bit Break Character Transmit BRGH and BRG16 bits, as required, to achieve
• Auto-Baud Rate Detection the desired baud rate.
2. Enable the asynchronous serial port by clearing
21.2.1 EUSART ASYNCHRONOUS bit, SYNC, and setting bit, SPEN.
TRANSMITTER 3. If interrupts are desired, set enable bit, TXxIE.
Figure 21-3 displays the EUSART transmitter block 4. If 9-bit transmission is desired, set transmit bit,
diagram. TX9; can be used as an address/data bit.
The heart of the transmitter is the Transmit (Serial) Shift 5. Enable the transmission by setting bit, TXEN,
Register (TSR). The shift register obtains its data from which will also set bit, TXxIF.
the Read/Write Transmit Buffer register, TXREGx. The 6. If 9-bit transmission is selected, the ninth bit
TXREGx register is loaded with data in software. The should be loaded in bit, TX9D.
TSR register is not loaded until the Stop bit has been 7. Load data to the TXREGx register (starts
transmitted from the previous load. As soon as the Stop transmission).
bit is transmitted, the TSR is loaded with new data from 8. If using interrupts, ensure that the GIE and PEIE
the TXREGx register (if available). bits in the INTCON register (INTCON<7:6>) are
set.

FIGURE 21-3: EUSART TRANSMIT BLOCK DIAGRAM

Data Bus

TXxIF TXREGx Register

TXxIE
8
MSb LSb
(8)  0 Pin Buffer
and Control
TSR Register TXx Pin
Interrupt

TXEN Baud Rate CLK

TRMT SPEN
BRG16 SPBRGHx SPBRGx
TX9
Baud Rate Generator TX9D

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FIGURE 21-4: ASYNCHRONOUS TRANSMISSION

Write to TXREGx
Word 1
BRG Output
(Shift Clock)

TXx (pin)
Start bit bit 0 bit 1 bit 7/8 Stop bit
Word 1
TXxIF bit
(Transmit Buffer 1 TCY
Reg. Empty Flag)

Word 1
TRMT bit
Transmit Shift Reg
(Transmit Shift
Reg. Empty Flag)

FIGURE 21-5: ASYNCHRONOUS TRANSMISSION (BACK-TO-BACK)

Write to TXREGx
Word 1 Word 2
BRG Output
(Shift Clock)

TXx (pin)
Start bit bit 0 bit 1 bit 7/8 Stop bit Start bit bit 0

TXxIF bit 1 TCY Word 1 Word 2

(Interrupt Reg. Flag)
1 TCY
Word 1 Word 2
TRMT bit Transmit Shift Reg. Transmit Shift Reg.
(Transmit Shift
Reg. Empty Flag)

Note: This timing diagram shows two consecutive transmissions.

TABLE 21-5: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF
PIR1 PMPIF(1) ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF
PIE1 PMPIE(1) ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE
IPR1 PMPIP(1) ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP
PIR3 SSP2IF BCL2IF RC2IF TX2IF TMR4IF CTMUIF TMR3GIF RTCCIF
PIE3 SSP2IE BCL2IE RC2IE TX2IE TMR4IE CTMUIE TMR3GIE RTCCIE
IPR3 SSP2IP BCL2IP RC2IP TX2IP TMR4IP CTMUIP TMR3GIP RTCCIP
RCSTAx SPEN RX9 SREN CREN ADDEN FERR OERR RX9D
TXREGx EUSARTx Transmit Register
TXSTAx CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D
BAUDCONx ABDOVF RCIDL RXDTP TXCKP BRG16 — WUE ABDEN
SPBRGHx EUSARTx Baud Rate Generator Register High Byte
SPBRGx EUSARTx Baud Rate Generator Register Low Byte
ODCON2 — — — — CCP10OD CCP9OD U2OD U1OD
Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous transmission.
Note 1: These bits are only available on 44-pin devices.

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 PIC18F47J53 FAMILY
21.2.2 EUSART ASYNCHRONOUS 21.2.3 SETTING UP 9-BIT MODE WITH
RECEIVER ADDRESS DETECT
The receiver block diagram is displayed in Figure 21-6. This mode would typically be used in RS-485 systems.
The data is received on the RXx pin and drives the data To set up an Asynchronous Reception with Address
recovery block. The data recovery block is actually a Detect Enable:
high-speed shifter, operating at x16 times the baud 1. Initialize the SPBRGHx:SPBRGx registers for
rate, whereas the main receive serial shifter operates the appropriate baud rate. Set or clear the
at the bit rate or at FOSC. This mode would typically be BRGH and BRG16 bits, as required, to achieve
used in RS-232 systems. the desired baud rate.
To set up an Asynchronous Reception: 2. Enable the asynchronous serial port by clearing
1. Initialize the SPBRGHx:SPBRGx registers for the SYNC bit and setting the SPEN bit.
the appropriate baud rate. Set or clear the 3. If interrupts are required, set the RCEN bit and
BRGH and BRG16 bits, as required, to achieve select the desired priority level with the RCxIP bit.
the desired baud rate. 4. Set the RX9 bit to enable 9-bit reception.
2. Enable the asynchronous serial port by clearing 5. Set the ADDEN bit to enable address detect.
bit, SYNC, and setting bit, SPEN. 6. Enable reception by setting the CREN bit.
3. If interrupts are desired, set enable bit, RCxIE. 7. The RCxIF bit will be set when reception is
4. If 9-bit reception is desired, set bit, RX9. complete. The interrupt will be Acknowledged if
5. Enable the reception by setting bit, CREN. the RCxIE and GIE bits are set.
6. Flag bit, RCxIF, will be set when reception is 8. Read the RCSTAx register to determine if any
complete and an interrupt will be generated if error occurred during reception, as well as read
enable bit, RCxIE, was set. bit 9 of data (if applicable).
7. Read the RCSTAx register to get the ninth bit (if 9. Read RCREGx to determine if the device is
enabled) and determine if any error occurred being addressed.
during reception. 10. If any error occurred, clear the CREN bit.
8. Read the 8-bit received data by reading the 11. If the device has been addressed, clear the
RCREGx register. ADDEN bit to allow all received data into the
9. If any error occurred, clear the error by clearing receive buffer and interrupt the CPU.
enable bit, CREN.
10. If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.

FIGURE 21-6: EUSARTx RECEIVE BLOCK DIAGRAM

CREN OERR FERR

x64 Baud Rate CLK

 64 MSb RSR Register LSb
BRG16 SPBRGHx SPBRGx or
 16 Stop 
or (8) 7 1 0 Start
Baud Rate Generator 4

RX9

Pin Buffer Data

and Control Recovery
RXx RX9D RCREGx Register
FIFO

SPEN
8

Interrupt RCxIF Data Bus

RCxIE

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FIGURE 21-7: ASYNCHRONOUS RECEPTION
Start Start Start
RXx (pin) bit bit 0 bit 1 bit 7/8 Stop bit bit 0 bit 7/8 Stop bit bit 7/8 Stop
bit bit bit
Rcv Shift Reg
Rcv Buffer Reg
Word 1 Word 2
RCREGx RCREGx
Read Rcv
Buffer Reg
RCREGx

RCxIF
(Interrupt Flag)

OERR bit
CREN

Note: This timing diagram shows three words appearing on the RXx input. The RCREGx (Receive Buffer) is read after
the third word causing the OERR (Overrun) bit to be set.

TABLE 21-6: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF
PIR1 PMPIF(1) ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF
PIE1 PMPIE(1) ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE
IPR1 PMPIP(1) ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP
PIR3 SSP2IF BCL2IF RC2IF TX2IF TMR4IF CTMUIF TMR3GIF RTCCIF
PIE3 SSP2IE BCL2IE RC2IE TX2IE TMR4IE CTMUIE TMR3GIE RTCCIE
IPR3 SSP2IP BCL2IP RC2IP TX2IP TMR4IP CTMUIP TMR3GIP RTCCIP
RCSTAx SPEN RX9 SREN CREN ADDEN FERR OERR RX9D
RCREGx EUSARTx Receive Register
TXSTAx CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D
BAUDCONx ABDOVF RCIDL RXDTP TXCKP BRG16 — WUE ABDEN
SPBRGHx EUSARTx Baud Rate Generator High Byte
SPBRGx EUSARTx Baud Rate Generator Low Byte
Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception.
Note 1: These bits are only available on 44-pin devices.

21.2.4 AUTO-WAKE-UP ON SYNC BREAK wake-up event independent of the CPU mode. A
CHARACTER wake-up event consists of a high-to-low transition on
the RXx/DTx line. (This coincides with the start of a
During Sleep mode, all clocks to the EUSART are
Sync Break or a Wake-up Signal character for the
suspended. Because of this, the BRG is inactive and a
LIN/J2602 protocol.)
proper byte reception cannot be performed. The
auto-wake-up feature allows the controller to wake-up Following a wake-up event, the module generates an
due to activity on the RXx/DTx line while the EUSART RCxIF interrupt. The interrupt is generated synchro-
is operating in Asynchronous mode. nously to the Q clocks in normal operating modes
(Figure 21-8) and asynchronously if the device is in
The auto-wake-up feature is enabled by setting the
Sleep mode (Figure 21-9). The interrupt condition is
WUE bit (BAUDCONx<1>). Once set, the typical
cleared by reading the RCREGx register.
receive sequence on RXx/DTx is disabled and the
EUSART remains in an Idle state, monitoring for a

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 PIC18F47J53 FAMILY
The WUE bit is automatically cleared once a 21.2.4.2 Special Considerations Using the
low-to-high transition is observed on the RXx line WUE Bit
following the wake-up event. At this point, the EUSART
The timing of WUE and RCxIF events may cause some
module is in Idle mode and returns to normal operation.
confusion when it comes to determining the validity of
This signals to the user that the Sync Break event is
received data. As noted, setting the WUE bit places the
over.
EUSART in an Idle mode. The wake-up event causes a
21.2.4.1 Special Considerations Using receive interrupt by setting the RCxIF bit. The WUE bit
is cleared after this when a rising edge is seen on
Auto-Wake-up
RXx/DTx. The interrupt condition is then cleared by
Since auto-wake-up functions by sensing rising edge reading the RCREGx register. Ordinarily, the data in
transitions on RXx/DTx, information with any state RCREGx will be dummy data and should be discarded.
changes before the Stop bit may signal a false
The fact that the WUE bit has been cleared (or is still
End-Of-Character (EOC) and cause data or framing
set) and the RCxIF flag is set should not be used as an
errors. To work properly, therefore, the initial character
indicator of the integrity of the data in RCREGx. Users
in the transmission must be all ‘0’s. This can be 00h
should consider implementing a parallel method in
(8 bytes) for standard RS-232 devices or 000h
firmware to verify received data integrity.
(12 bits) for LIN/J2602 bus.
To assure that no actual data is lost, check the RCIDL
Oscillator start-up time must also be considered,
bit to verify that a receive operation is not in process. If
especially in applications using oscillators with
a receive operation is not occurring, the WUE bit may
longer start-up intervals (i.e., HS or HSPLL mode).
then be set just prior to entering Sleep mode.
The Sync Break (or Wake-up Signal) character must
be of sufficient length and be followed by a sufficient
interval to allow enough time for the selected
oscillator to start and provide proper initialization of
the EUSART.

FIGURE 21-8: AUTO-WAKE-UP BIT (WUE) TIMINGS DURING NORMAL OPERATION

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
Bit set by user Auto-Cleared
WUE bit(1)

RXx/DTx Line

RCxIF
Cleared due to user read of RCREGx

Note 1: The EUSART remains in Idle while the WUE bit is set.

FIGURE 21-9: AUTO-WAKE-UP BIT (WUE) TIMINGS DURING SLEEP

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
Bit set by user Auto-Cleared
WUE bit(2)

RXx/DTx Line
Note 1
RCxIF
Cleared due to user read of RCREGx
SLEEP Command Executed Sleep Ends

Note 1: If the wake-up event requires long oscillator warm-up time, the auto-clear of the WUE bit can occur before the
oscillator is ready. This sequence should not depend on the presence of Q clocks.
2: The EUSART remains in Idle while the WUE bit is set.

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21.2.5 BREAK CHARACTER SEQUENCE 21.2.5.1 Break and Sync Transmit Sequence
The EUSART module has the capability of sending the The following sequence will send a message frame
special Break character sequences that are required by header made up of a Break, followed by an Auto-Baud
the LIN/J2602 bus standard. The Break character Sync byte. This sequence is typical of a LIN/J2602 bus
transmit consists of a Start bit, followed by twelve ‘0’ master.
bits and a Stop bit. The Frame Break character is sent 1. Configure the EUSART for the desired mode.
whenever the SENDB and TXEN bits (TXSTAx<3> and
2. Set the TXEN and SENDB bits to set up the
TXSTAx<5>) are set while the Transmit Shift Register
Break character.
is loaded with data.
3. Load the TXREGx with a dummy character to
Note that the value of data written to TXREGx will be initiate transmission (the value is ignored).
ignored and all ‘0’s will be transmitted.
4. Write ‘55h’ to TXREGx to load the Sync
The SENDB bit is automatically reset by hardware after character into the transmit FIFO buffer.
the corresponding Stop bit is sent. This allows the user 5. After the Break has been sent, the SENDB bit is
to preload the transmit FIFO with the next transmit byte reset by hardware. The Sync character now
following the Break character (typically, the Sync transmits in the preconfigured mode.
character in the LIN/J2602 specification).
When the TXREGx becomes empty, as indicated by the
Note that the data value written to the TXREGx for the TXxIF, the next data byte can be written to TXREGx.
Break character is ignored. The write simply serves the
purpose of initiating the proper sequence. 21.2.6 RECEIVING A BREAK CHARACTER
The TRMT bit indicates when the transmit operation is The Enhanced USART module can receive a Break
active or Idle, just as it does during normal transmis- character in two ways.
sion. See Figure 21-10 for the timing of the Break
character sequence. The first method forces configuration of the baud rate
at a frequency of 9/13 of the typical speed. This allows
for the Stop bit transition to be at the correct sampling
location (13 bits for Break versus Start bit and 8 data
bits for typical data).
The second method uses the auto-wake-up feature
described in Section 21.2.4 “Auto-Wake-up on Sync
Break Character”. By enabling this feature, the
EUSART will sample the next two transitions on
RXx/DTx, cause an RCxIF interrupt and receive the
next data byte followed by another interrupt.
Note that following a Break character, the user will
typically want to enable the Auto-Baud Rate Detect
feature. For both methods, the user can set the ABDEN
bit once the TXxIF interrupt is observed.

FIGURE 21-10: SEND BREAK CHARACTER SEQUENCE

Write to TXREGx
Dummy Write

BRG Output
(Shift Clock)

TXx (pin) Start Bit Bit 0 Bit 1 Bit 11 Stop Bit

Break
TXxIF bit
(Transmit Buffer
Reg. Empty Flag)
TRMT bit
(Transmit Shift
Reg. Empty Flag)
SENDB sampled here Auto-Cleared
SENDB bit
(Transmit Shift
Reg. Empty Flag)

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21.3 EUSART Synchronous Master Once the TXREGx register transfers the data to the
Mode TSR register (occurs in one TCY), the TXREGx is empty
and the TXxIF flag bit is set. The interrupt can be
The Synchronous Master mode is entered by setting enabled or disabled by setting or clearing the interrupt
the CSRC bit (TXSTAx<7>). In this mode, the data is enable bit, TXxIE. TXxIF is set regardless of the state
transmitted in a half-duplex manner (i.e., transmission of enable bit, TXxIE; it cannot be cleared in software. It
and reception do not occur at the same time). When will reset only when new data is loaded into the
transmitting data, the reception is inhibited and vice TXREGx register.
versa. Synchronous mode is entered by setting bit,
While flag bit, TXxIF, indicates the status of the TXREGx
SYNC (TXSTAx<4>). In addition, enable bit, SPEN
register, another bit, TRMT (TXSTAx<1>), shows the
(RCSTAx<7>), is set in order to configure the TXx and
status of the TSR register. TRMT is a read-only bit which
RXx pins to CKx (clock) and DTx (data) lines,
is set when the TSR is empty. No interrupt logic is tied to
respectively.
this bit, so the user must poll this bit in order to determine
The Master mode indicates that the processor trans- if the TSR register is empty. The TSR is not mapped in
mits the master clock on the CKx line. Clock polarity is data memory so it is not available to the user.
selected with the TXCKP bit (BAUDCONx<4>). Setting
To set up a Synchronous Master Transmission:
TXCKP sets the Idle state on CKx as high, while clear-
ing the bit sets the Idle state as low. This option is 1. Initialize the SPBRGHx:SPBRGx registers for the
provided to support Microwire devices with this module. appropriate baud rate. Set or clear the BRG16
bit, as required, to achieve the required baud
21.3.1 EUSART SYNCHRONOUS MASTER rate.
TRANSMISSION 2. Enable the synchronous master serial port by
The EUSART transmitter block diagram is shown in setting bits, SYNC, SPEN and CSRC.
Figure 21-3. The heart of the transmitter is the Transmit 3. If interrupts are desired, set enable bit, TXxIE.
(Serial) Shift Register (TSR). The shift register obtains 4. If 9-bit transmission is required, set bit, TX9.
its data from the Read/Write Transmit Buffer register, 5. Enable the transmission by setting bit, TXEN.
TXREGx. The TXREGx register is loaded with data in 6. If 9-bit transmission is selected, the ninth bit
software. The TSR register is not loaded until the last should be loaded in bit, TX9D.
bit has been transmitted from the previous load. As
7. Start transmission by loading data to the
soon as the last bit is transmitted, the TSR is loaded
TXREGx register.
with new data from the TXREGx (if available).
8. If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.

FIGURE 21-11: SYNCHRONOUS TRANSMISSION

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

RC7/CCP10/PMA4/RX1/
DT1/SDO1/RP18 bit 0 bit 1 bit 2 bit 7 bit 0 bit 1 bit 7
Word 1 Word 2
RC6/CCP9/PMA5/TX1/CK1/
RP17 (TXCKP = 0)
RC6/CCP9/PMA5/TX1/CK1/
RP17 (TXCKP = 1)

Write to
TXREG1 Reg
Write Word 1 Write Word 2
TX1IF bit
(Interrupt Flag)

TRMT bit

TXEN bit ‘1’ ‘1’

Note: Sync Master mode, SPBRGx = 0; continuous transmission of two 8-bit words. This example is equally applicable to EUSART2
(RPn1/TX2/CK2 and RPn2/RX2/DT2).

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FIGURE 21-12: SYNCHRONOUS TRANSMISSION (THROUGH TXEN)

RC7/CCP10/PMA4/RX1/DT1/ bit 0 bit 1 bit 2 bit 6 bit 7

SDO1/RP18 Pin

RC6/CCP9/PMA5/TX1/CK1/
RP17 Pin
Write to
TXREG1 reg

TX1IF bit

TRMT bit

TXEN bit

Note: This example is equally applicable to EUSART2 (RPn1/TX2/CK2 and RPn2/RX2/DT2).

TABLE 21-7: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF
PIR1 PMPIF(1) ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF
PIE1 PMPIE(1) ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE
IPR1 PMPIP(1) ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP
PIR3 SSP2IF BCL2IF RC2IF TX2IF TMR4IF CTMUIF TMR3GIF RTCCIF
PIE3 SSP2IE BCL2IE RC2IE TX2IE TMR4IE CTMUIE TMR3GIE RTCCIE
IPR3 SSP2IP BCL2IP RC2IP TX2IP TMR4IP CTMUIP TMR3GIP RTCCIP
RCSTAx SPEN RX9 SREN CREN ADDEN FERR OERR RX9D
TXREGx EUSARTx Transmit Register
TXSTAx CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D
BAUDCONx ABDOVF RCIDL RXDTP TXCKP BRG16 — WUE ABDEN
SPBRGHx EUSARTx Baud Rate Generator High Byte
SPBRGx EUSARTx Baud Rate Generator Low Byte
ODCON2 — — — — CCP10OD CCP9OD U2OD U1OD
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master transmission.
Note 1: These pins are only available on 44-pin devices.

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 PIC18F47J53 FAMILY
21.3.2 EUSART SYNCHRONOUS MASTER 3. Ensure bits, CREN and SREN, are clear.
RECEPTION 4. If interrupts are desired, set enable bit, RCxIE.
Once Synchronous mode is selected, reception is 5. If 9-bit reception is desired, set bit, RX9.
enabled by setting either the Single Receive Enable bit, 6. If a single reception is required, set bit, SREN.
SREN (RCSTAx<5>) or the Continuous Receive For continuous reception, set bit, CREN.
Enable bit, CREN (RCSTAx<4>). Data is sampled on 7. Interrupt flag bit, RCxIF, will be set when
the RXx pin on the falling edge of the clock. reception is complete and an interrupt will be
If enable bit, SREN, is set, only a single word is generated if the enable bit, RCxIE, was set.
received. If enable bit, CREN, is set, the reception is 8. Read the RCSTAx register to get the ninth bit (if
continuous until CREN is cleared. If both bits are set, enabled) and determine if any error occurred
then CREN takes precedence. during reception.
To set up a Synchronous Master Reception: 9. Read the 8-bit received data by reading the
RCREGx register.
1. Initialize the SPBRGHx:SPBRGx registers for
the appropriate baud rate. Set or clear the 10. If any error occurred, clear the error by clearing
BRG16 bit, as required, to achieve the desired bit, CREN.
baud rate. 11. If using interrupts, ensure that the GIE and PEIE
2. Enable the synchronous master serial port by bits in the INTCON register (INTCON<7:6>) are
setting bits, SYNC, SPEN and CSRC. set.

FIGURE 21-13: SYNCHRONOUS RECEPTION (MASTER MODE, SREN)

Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

RC7/CCP10/PMA4/RX1/
DT1/SDO1/RP18 bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7

RC6/CCP9/PMA5/TX1/
CK1/RP17 (TXCKP = 0)

RC6/CCP9/PMA5/TX1/
CK1/RP17 (TXCKP = 1)

Write to
SREN bit

SREN bit
CREN bit ‘0’ ‘0’

RC1IF bit
(Interrupt)
Read
RCREG1

Note: Timing diagram demonstrates Sync Master mode with bit, SREN = 1, and bit, BRGH = 0. This example is equally applicable to EUSART2
(RPn1/TX2/CK2 and RPn2/RX2/DT2).

 2010 Microchip Technology Inc. Preliminary DS39964B-page 363

PIC18F47J53 FAMILY
TABLE 21-8: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF
PIR1 (1)
PMPIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF
(1)
PIE1 PMPIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE
IPR1 PMPIP(1) ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP
PIR3 SSP2IF BCL2IF RC2IF TX2IF TMR4IF CTMUIF TMR3GIF RTCCIF
PIE3 SSP2IE BCL2IE RC2IE TX2IE TMR4IE CTMUIE TMR3GIE RTCCIE
IPR3 SSP2IP BCL2IP RC2IP TX2IP TMR4IP CTMUIP TMR3GIP RTCCIP
RCSTAx SPEN RX9 SREN CREN ADDEN FERR OERR RX9D
RCREGx EUSARTx Receive Register
TXSTAx CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D
BAUDCONx ABDOVF RCIDL RXDTP TXCKP BRG16 — WUE ABDEN
SPBRGHx EUSARTx Baud Rate Generator High Byte
SPBRGx EUSARTx Baud Rate Generator Low Byte
ODCON2 — — — — CCP10OD CCP9OD U2OD U1OD
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master reception.
Note 1: These pins are only available on 44-pin devices.

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 PIC18F47J53 FAMILY
21.4 EUSART Synchronous Slave e) If enable bit, TXxIE, is set, the interrupt will wake
Mode the chip from Sleep. If the global interrupt is
enabled, the program will branch to the interrupt
Synchronous Slave mode is entered by clearing bit, vector.
CSRC (TXSTAx<7>). This mode differs from the
To set up a Synchronous Slave Transmission:
Synchronous Master mode in that the shift clock is sup-
plied externally at the CKx pin (instead of being supplied 1. Enable the synchronous slave serial port by
internally in Master mode). This allows the device to setting bits, SYNC and SPEN, and clearing bit,
transfer or receive data while in any low-power mode. CSRC.
2. Clear bits, CREN and SREN.
21.4.1 EUSART SYNCHRONOUS SLAVE 3. If interrupts are desired, set enable bit, TXxIE.
TRANSMISSION 4. If 9-bit transmission is desired, set bit, TX9.
The operation of the Synchronous Master and Slave 5. Enable the transmission by setting enable bit,
modes is identical, except in the case of Sleep mode. TXEN.
If two words are written to the TXREGx, and then the 6. If 9-bit transmission is selected, the ninth bit
SLEEP instruction is executed, the following will occur: should be loaded in bit, TX9D.
a) The first word will immediately transfer to the 7. Start transmission by loading data to the
TSR register and transmit. TXREGx register.
b) The second word will remain in the TXREGx 8. If using interrupts, ensure that the GIE and PEIE
register. bits in the INTCON register (INTCON<7:6>) are
c) Flag bit, TXxIF, will not be set. set.
d) When the first word has been shifted out of TSR,
the TXREGx register will transfer the second word
to the TSR and flag bit, TXxIF, will now be set.

TABLE 21-9: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF
PIR1 PMPIF(1) ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF
PIE1 PMPIE(1) ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE
IPR1 PMPIP(1) ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP
PIR3 SSP2IF BCL2IF RC2IF TX2IF TMR4IF CTMUIF TMR3GIF RTCCIF
PIE3 SSP2IE BCL2IE RC2IE TX2IE TMR4IE CTMUIE TMR3GIE RTCCIE
IPR3 SSP2IP BCL2IP RC2IP TX2IP TMR4IP CTMUIP TMR3GIP RTCCIP
RCSTAx SPEN RX9 SREN CREN ADDEN FERR OERR RX9D
TXREGx EUSARTx Transmit Register
TXSTAx CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D
BAUDCONx ABDOVF RCIDL RXDTP TXCKP BRG16 — WUE ABDEN
SPBRGHx EUSARTx Baud Rate Generator High Byte
SPBRGx EUSARTx Baud Rate Generator Low Byte
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave transmission.
Note 1: These pins are only available on 44-pin devices.

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PIC18F47J53 FAMILY
21.4.2 EUSART SYNCHRONOUS SLAVE To set up a Synchronous Slave Reception:
RECEPTION 1. Enable the synchronous master serial port by
The operation of the Synchronous Master and Slave setting bits, SYNC and SPEN, and clearing bit,
modes is identical, except in the case of Sleep, or any CSRC.
Idle mode and bit, SREN, which is a “don’t care” in 2. If interrupts are desired, set enable bit, RCxIE.
Slave mode. 3. If 9-bit reception is desired, set bit, RX9.
If receive is enabled by setting the CREN bit prior to 4. To enable reception, set enable bit, CREN.
entering Sleep or any Idle mode, then a word may be 5. Flag bit, RCxIF, will be set when reception is
received while in this low-power mode. Once the word complete. An interrupt will be generated if
is received, the RSR register will transfer the data to the enable bit, RCxIE, was set.
RCREGx register. If the RCxIE enable bit is set, the 6. Read the RCSTAx register to get the ninth bit (if
interrupt generated will wake the chip from the enabled) and determine if any error occurred
low-power mode. If the global interrupt is enabled, the during reception.
program will branch to the interrupt vector.
7. Read the 8-bit received data by reading the
RCREGx register.
8. If any error occurred, clear the error by clearing
bit, CREN.
9. If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.

TABLE 21-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF
PIR1 PMPIF(1) ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF
PIE1 PMPIE(1) ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE
IPR1 PMPIP(1) ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP
PIR3 SSP2IF BCL2IF RC2IF TX2IF TMR4IF CTMUIF TMR3GIF RTCCIF
PIE3 SSP2IE BCL2IE RC2IE TX2IE TMR4IE CTMUIE TMR3GIE RTCCIE
IPR3 SSP2IP BCL2IP RC2IP TX2IP TMR4IP CTMUIP TMR3GIP RTCCIP
RCSTAx SPEN RX9 SREN CREN ADDEN FERR OERR RX9D
RCREGx EUSARTx Receive Register
TXSTAx CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D
BAUDCONx ABDOVF RCIDL RXDTP TXCKP BRG16 — WUE ABDEN
SPBRGHx EUSARTx Baud Rate Generator High Byte
SPBRGx EUSARTx Baud Rate Generator Low Byte
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave reception.
Note 1: These pins are only available on 44-pin devices.

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 PIC18F47J53 FAMILY
22.0 10/12-BIT ANALOG-TO-DIGITAL The ADCON0 register, shown in Register 22-1,
controls the operation of the A/D module.
CONVERTER (A/D) MODULE
The ADCON1 register, shown in Register 22-1, config-
The Analog-to-Digital (A/D) Converter module in the ures the A/D clock source, programmed acquisition
PIC18F47J53 family of devices has 10 inputs for the time and justification. The ANCON0 and ANCON1
28-pin devices and 13 inputs for the 44-pin devices. registers, in Register 22-1 and Register 22-2, configure
This module allows conversion of an analog input the functions of the port pins.
signal to a corresponding 10 or 12-bit digital number.
The ADCSEL Configuration bit (CONFIG3H<1>) sets
The module has these registers: the module for 10 or 12-bit conversions. The 10-Bit
• A/D Control Register 0 (ADCON0) Conversion mode is useful for applications that favor
• A/D Control Register 1 (ADCON1) conversion speed over conversion resolution.
• A/D Port Configuration Register 0 (ANCON0)
• A/D Port Configuration Register 1 (ANCON1)
• A/D Result Registers (ADRESH and ADRESL)
• A/D Trigger Register (ADCTRIG)
• Configuration Register 3 High (ADCSEL,
CONFIG3H<1>)

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REGISTER 22-1: ADCON0: A/D CONTROL REGISTER 0 (ACCESS FC2h)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
(2) (2) (2) (2)
VCFG1 VCFG0 CHS3 CHS2 CHS1 CHS0 GO/DONE ADON
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 VCFG1: Voltage Reference Configuration bit (VREF- source)

1 = VREF- (AN2)
0 = AVSS(4)
bit 6 VCFG0: Voltage Reference Configuration bit (VREF+ source)
1 = VREF+ (AN3)
0 = AVDD(4)
bit 5-2 CHS<3:0>: Analog Channel Select bits(2)
0000 = Channel 00 (AN0)
0001 = Channel 01 (AN1)
0010 = Channel 02 (AN2)
0011 = Channel 03 (AN3)
0100 = Channel 04 (AN4)
0101 = Channel 05 (AN5)(1)
0110 = Channel 06 (AN6)(1)
0111 = Channel 07 (AN7)(1)
1000 = Channel 08 (AN8)
1001 = Channel 09 (AN9)
1010 = Channel 10 (AN10)
1011 = Channel 11 (AN11)
1100 = Channel 12 (AN12)
1101 = (Reserved)
1110 = VDDCORE
1111 = VBG Absolute Reference (~1.2V)(3)
bit 1 GO/DONE: A/D Conversion Status bit
When ADON = 1:
1 = A/D conversion is in progress
0 = A/D is Idle
bit 0 ADON: A/D On bit
1 = A/D Converter module is enabled
0 = A/D Converter module is disabled

Note 1: These channels are not implemented on 28-pin devices.

2: Performing a conversion on unimplemented channels will return random values.
3: For best accuracy, the band gap reference circuit should be enabled (ANCON1<7> = 1) at least 10 ms
before performing a conversion on this channel.
4: On 44-pin, QFN devices, AVDD and AVSS reference sources are intended to be externally connected to
VDD and VSS levels. Other package types tie AVDD and AVSS to VDD and VSS internally.

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 PIC18F47J53 FAMILY
REGISTER 22-2: ADCON1: A/D CONTROL REGISTER 1 (ACCESS FC1h)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
ADFM ADCAL ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 ADFM: A/D Result Format Select bit

1 = Right justified
0 = Left justified
bit 6 ADCAL: A/D Calibration bit
1 = Calibration is performed on the next A/D conversion
0 = Normal A/D Converter operation
bit 5-3 ACQT<2:0>: A/D Acquisition Time Select bits
111 = 20 TAD
110 = 16 TAD
101 = 12 TAD
100 = 8 TAD
011 = 6 TAD
010 = 4 TAD
001 = 2 TAD
000 = 0 TAD
bit 2-0 ADCS<2:0>: A/D Conversion Clock Select bits
110 = FOSC/64
101 = FOSC/16
100 = FOSC/4
011 = FRC (clock derived from A/D RC oscillator)(1)
010 = FOSC/32
001 = FOSC/8
000 = FOSC/2

Note 1: If the A/D FRC clock source is selected, a delay of one TCY (instruction cycle) is added before the A/D
clock starts. This allows the SLEEP instruction to be executed before starting a conversion.

 2010 Microchip Technology Inc. Preliminary DS39964B-page 369

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REGISTER 22-3: CONFIG3H: CONFIGURATION REGISTER 3 HIGH (BYTE ADDRESS 300005h)
U-1 U-1 U-1 U-1 R/WO-1 U-0 R/WO-1 R/WO-1
— — — — MSSPMSK — ADCSEL IOL1WAY
bit 7 bit 0

Legend:
R = Readable bit WO = Write-Once bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-4 Unimplemented: Program the corresponding Flash Configuration bit to ‘1’
bit 3 MSSPMSK: MSSP 7-Bit Address Masking Mode Enable bit
1 = 7-Bit Address Masking mode enabled
0 = 5-Bit Address Masking mode enabled
bit 2 Unimplemented: Read as ‘0’
bit 1 ADCSEL: A/D Converter Mode bit
1 = 10-Bit Conversion mode enabled
0 = 12-Bit Conversion mode enabled
bit 0 IOL1WAY: IOLOCK One Way Set Enable bit
1 = IOLOCK bit (PPSCON<0>) can be set once, provided the unlock sequence has been completed.
Once set, the Peripheral Pin Select registers cannot be written to a second time.
0 = IOLOCK bit (PPSCON<0>) can be set and cleared as needed, provided the unlock sequence has
been completed

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The ANCON0 and ANCON1 registers are used to request that the band gap reference circuit should be
configure the operation of the I/O pin associated with enabled. For best accuracy, firmware should allow a
each analog channel. Setting any one of the PCFG bits settling time of at least 10 ms prior to performing the first
configures the corresponding pin to operate as a digital acquisition on this channel after enabling the band gap
only I/O. Clearing a bit configures the pin to operate as reference.
an analog input for either the A/D Converter or the The reference circuit may already have been turned on
comparator module. All digital peripherals are disabled if some other hardware module (such as the on-chip
and digital inputs read as ‘0’. As a rule, I/O pins that are voltage regulator, comparators or HLVD) has already
multiplexed with analog inputs default to analog requested it. In this case, the initial turn-on settling time
operation on device Resets. may have already elapsed and firmware does not need
In order to correctly perform A/D conversions on the VBG to wait as long before measuring VBG. Once the acqui-
band gap reference (ADCON0<5:2> = 1111), the refer- sition is complete, firmware may clear the VBGEN bit,
ence circuit must be powered on first. The VBGEN bit in which will save a small amount of power if no other
the ANCON1 register allows the firmware to manually modules are still requesting the VBG reference.

REGISTER 22-4: ANCON0: A/D PORT CONFIGURATION REGISTER 0 (BANKED F48h)

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PCFG7(1) PCFG6(1) PCFG5(1) PCFG4 PCFG3 PCFG2 PCFG1 PCFG0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-0 PCFG<7:0>: Analog Port Configuration bits (AN7-AN0)

1 = Pin configured as a digital port
0 = Pin configured as an analog channel – digital input disabled and reads ‘0’

Note 1: These bits are only available only on 44-pin devices.

REGISTER 22-5: ANCON1: A/D PORT CONFIGURATION REGISTER 1 (BANKED F49h)

R/W-0 R U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
VBGEN r — PCFG12 PCFG11 PCFG10 PCFG9 PCFG8
bit 7 bit 0

Legend: r = Reserved bit

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 VBGEN: 1.2V Band Gap Reference Enable bit

1 = 1.2V band gap reference is powered on
0 = 1.2V band gap reference is turned off to save power (if no other modules are requesting it)
bit 6 Reserved: Always maintain as ‘0’ for lowest power consumption
bit 5 Unimplemented: Read as ‘0’
bit 4-0 PCFG<12:8>: Analog Port Configuration bits (AN12-AN8)
1 = Pin configured as a digital port
0 = Pin configured as an analog channel – digital input disabled and reads ‘0’

 2010 Microchip Technology Inc. Preliminary DS39964B-page 371

PIC18F47J53 FAMILY
The analog reference voltage is software select- Each port pin associated with the A/D Converter can be
able to either the device’s positive and negative configured as an analog input or as a digital I/O. The
supply voltage (AV DD and AV SS ), or the voltage ADRESH and ADRESL registers contain the result of
level on the RA3/AN3/C1INB/VREF + and the A/D conversion. When the A/D conversion is com-
RA2/AN2/C2INB/C1IND/C3INB/VREF -/CVREF pins. plete, the result is loaded into the ADRESH:ADRESL
register pair, the GO/DONE bit (ADCON0<1>) is
The A/D Converter has a unique feature of being able cleared and the A/D Interrupt Flag bit, ADIF, is set.
to operate while the device is in Sleep mode. To
operate in Sleep, the A/D conversion clock must be A device Reset forces all registers to their Reset state.
derived from the A/D’s internal RC oscillator. This forces the A/D module to be turned off and any
conversion in progress is aborted. The value in the
The output of the sample and hold is the input into the ADRESH:ADRESL register pair is not modified for a
Converter, which generates the result via successive Power-on Reset (POR). These registers will contain
approximation. unknown data after a POR.
Figure 22-1 provides the block diagram of the A/D
module.
FIGURE 22-1: A/D BLOCK DIAGRAM
CHS<3:0>

1111
VBG
1110
VDDCORE/VCAP
1100
AN12
1011
AN11
1010
AN10
1001
AN9
1000
AN8
0111
AN7(1)
0110
AN6(1)
VAIN
0101
10/12-Bit (Input Voltage) AN5(1)
A/D
Converter 0100
AN4
0011
AN3
0010
AN2
VCFG<1:0> 0001
Reference AN1
Voltage
VDD(2) 0000
AN0
VREF+

VREF-

VSS(2)
Note 1: Channels, AN5, AN6 and AN7, are not available on 28-pin devices.
2: I/O pins have diode protection to VDD and VSS.

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After the A/D module has been configured as desired, 2. Configure A/D interrupt (if desired):
the selected channel must be acquired before the • Clear ADIF bit
conversion is started. The analog input channels must • Set ADIE bit
have their corresponding TRIS bits selected as inputs.
• Set GIE bit
To determine acquisition time, see Section 22.1 “A/D
Acquisition Requirements”. After this acquisition 3. Wait the required acquisition time (if required).
time has elapsed, the A/D conversion can be started. 4. Start conversion:
An acquisition time can be programmed to occur • Set GO/DONE bit (ADCON0<1>)
between setting the GO/DONE bit and the actual start 5. Wait for A/D conversion to complete, by either:
of the conversion.
• Polling for the GO/DONE bit to be cleared
The following steps should be followed to do an A/D
OR
conversion:
• Waiting for the A/D interrupt
1. Configure the A/D module:
6. Read A/D Result registers (ADRESH:ADRESL);
• Configure the required ADC pins as analog
clear bit, ADIF, if required.
pins using ANCON0, ANCON1
7. For the next conversion, go to step 1 or step 2,
• Set voltage reference using ADCON0
as required. The A/D conversion time per bit is
• Select A/D input channel (ADCON0) defined as TAD. A minimum Wait of 2 TAD is
• Select A/D acquisition time (ADCON1) required before the next acquisition starts.
• Select A/D conversion clock (ADCON1)
• Turn on A/D module (ADCON0)

FIGURE 22-2: ANALOG INPUT MODEL

VDD
Sampling
Switch
VT = 0.6V
ANx RIC 1k SS RSS
RS

VAIN CPIN ILEAKAGE

VT = 0.6V CHOLD = 25 pF
5 pF ±100 nA

VSS

Legend: CPIN = Input Capacitance

VT = Threshold Voltage
ILEAKAGE = Leakage Current at the pin due to VDD
various junctions
RIC = Interconnect Resistance
SS = Sampling Switch
CHOLD = Sample/Hold Capacitance (from DAC)
RSS = Sampling Switch Resistance 1 2 3 4
Sampling Switch (k)

 2010 Microchip Technology Inc. Preliminary DS39964B-page 373

PIC18F47J53 FAMILY
22.1 A/D Acquisition Requirements To calculate the minimum acquisition time,
Equation 22-1 may be used. This equation assumes
For the A/D Converter to meet its specified accuracy, that 1/2 LSb error is used (1,024 steps for the 10-bit
the charge holding capacitor (CHOLD) must be allowed A/D). The 1/2 LSb error is the maximum error allowed
to fully charge to the input channel voltage level. The for the A/D to meet its specified resolution.
analog input model is illustrated in Figure 22-2. The
source impedance (RS) and the internal sampling Equation 22-3 provides the calculation of the minimum
switch (RSS) impedance directly affect the time required acquisition time, TACQ. This calculation is
required to charge the capacitor, CHOLD. The sampling based on the following application system
switch (RSS) impedance varies over the device voltage assumptions:
(VDD). The source impedance affects the offset voltage CHOLD = 25 pF
at the analog input (due to pin leakage current). The Rs = 2.5 k
maximum recommended impedance for analog Conversion Error  1/2 LSb
sources is 2.5 k for 10-bit conversions and 1 k VDD = 3V  Rss = 2 k
for 12-bit conversions. After the analog input channel Temperature = 85C (system max.)
is selected (changed), the channel must be sampled for
at least the minimum acquisition time before starting a
conversion.
Note: When the conversion is started, the
holding capacitor is disconnected from the
input pin.

EQUATION 22-1: ACQUISITION TIME

TACQ = Amplifier Settling Time + Holding Capacitor Charging Time + Temperature Coefficient
= TAMP + TC + TCOFF

EQUATION 22-2: A/D MINIMUM CHARGING TIME

VHOLD = (VREF – (VREF/2048)) • (1 – e(-TC/CHOLD(RIC + RSS + RS)))
or
TC = -(CHOLD)(RIC + RSS + RS) ln(1/2048)

EQUATION 22-3: CALCULATING THE MINIMUM REQUIRED ACQUISITION TIME

TACQ = TAMP + TC + TCOFF
TAMP = 0.2 s
TCOFF = (Temp – 25°C)(0.02 s/°C)
(85°C – 25°C)(0.02 s/°C)
1.2 s
Temperature coefficient is only required for temperatures > 25°C. Below 25°C, TCOFF = 0 s.
TC = -(CHOLD)(RIC + RSS + RS) ln(1/2048) s
-(25 pF) (1 k + 2 k + 2.5 k) ln(0.0004883) s
1.05 s
TACQ = 0.2 s + 1.05 s + 1.2 s
2.45 s

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22.2 Selecting and Configuring TABLE 22-1: TAD vs. DEVICE OPERATING
Automatic Acquisition Time FREQUENCIES
The ADCON1 register allows the user to select an AD Clock Source Maximum Device
acquisition time that occurs each time the GO/DONE (TAD) Frequency (MHz)(3)
bit is set. Operation ADCS<2:0> 10-Bit Mode 12-Bit Mode
When the GO/DONE bit is set, sampling is stopped and
2 TOSC 000 2.86 2.5
a conversion begins. The user is responsible for ensur-
ing the required acquisition time has passed between 4 TOSC 100 5.71 5
selecting the desired input channel and setting the 8 TOSC 001 11.43 10
GO/DONE bit. This occurs when the ACQT<2:0> bits 16 TOSC 101 22.86 20
(ADCON1<5:3>) remain in their Reset state (‘000’) and
is compatible with devices that do not offer 32 TOSC 010 45.71 40
programmable acquisition times. 64 TOSC 110 48 48
If desired, the ACQT bits can be set to select a pro- RC(2) 011 1 (1)
1(1)
grammable acquisition time for the A/D module. When Note 1: The RC source has a typical TAD time of
the GO/DONE bit is set, the A/D module continues to 4 s.
sample the input for the selected acquisition time, then 2: For device frequencies above 1 MHz, the
automatically begins a conversion. Since the acquisi- device must be in Sleep mode for the
tion time is programmed, there may be no need to wait entire conversion or the A/D accuracy may
for an acquisition time between selecting a channel and be out of specification.
setting the GO/DONE bit.
3: Maximum conversion speeds are
In either case, when the conversion is completed, the achieved at the bolded device frequencies.
GO/DONE bit is cleared, the ADIF flag is set and the
A/D begins sampling the currently selected channel 22.4 Configuring Analog Port Pins
again. If an acquisition time is programmed, there is
nothing to indicate if the acquisition time has ended or The ANCON0, ANCON1 and TRISA registers control
if the conversion has begun. the operation of the A/D port pins. The port pins needed
as analog inputs must have their corresponding TRIS
22.3 Selecting the A/D Conversion bits set (input). If the TRIS bit is cleared (output), the
Clock digital output level (VOH or VOL) will be converted.
The A/D operation is independent of the state of the
The A/D conversion time per bit is defined as TAD. The CHS<3:0> bits and the TRIS bits.
A/D conversion requires 11 TAD per 10-bit conversion
and 13 TAD per 12-bit conversion. The source of the Note 1: When reading the PORT register, all pins
A/D conversion clock is software selectable. configured as analog input channels will
read as cleared (a low level). Pins config-
There are seven possible options for TAD:
ured as digital inputs will convert an
• 2 TOSC analog input. Analog levels on a digitally
• 4 TOSC configured input will be accurately
• 8 TOSC converted.
• 16 TOSC 2: Analog levels on any pin defined as a
• 32 TOSC digital input may cause the digital input
• 64 TOSC buffer to consume current out of the
device’s specification limits.
• Internal RC Oscillator
For correct A/D conversions, the A/D conversion clock
(TAD) must be as short as possible but greater than the
minimum TAD (see parameter 130 in Table 31-30 for
more information).
Table 22-1 provides the resultant TAD times derived
from the device operating frequencies and the A/D
clock source selected.

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22.5 A/D Conversions 22.6 Use of the Special Event Triggers
Figure 22-3 displays the operation of the A/D Converter A/D conversion can be started by the Special Event
after the GO/DONE bit has been set and the Trigger of any of these modules:
ACQT<2:0> bits are cleared. A conversion is started • ECCP2 – Requires CCP2M<3:0> bits
after the following instruction to allow entry into Sleep (CCP2CON<3:0>) set at 1011
mode before the conversion begins.
• CTMU – Requires the setting of the CTTRIG bit
Figure 22-4 displays the operation of the A/D Converter (CTMUCONH<0>)
after the GO/DONE bit has been set, the ACQT<2:0> • Timer1 Overflow
bits are set to ‘010’ and selecting a 4 TAD acquisition
• RTCC Alarm
time before the conversion starts.
To start an A/D conversion:
Clearing the GO/DONE bit during a conversion will
abort the current conversion. The A/D Result register • The A/D module must be enabled (ADON = 1)
pair will NOT be updated with the partially completed • The appropriate analog input channel selected
A/D conversion sample. This means the • The minimum acquisition period is set in one of
ADRESH:ADRESL registers will continue to contain these ways:
the value of the last completed conversion (or the last
- Timing provided by the user
value written to the ADRESH:ADRESL registers).
- Selection made of an appropriate TACQ time
After the A/D conversion is completed or aborted, a
2 TAD Wait is required before the next acquisition can With these conditions met, the trigger sets the
be started. After this wait, acquisition on the selected GO/DONE bit and the A/D acquisition starts.
channel is automatically started. If the A/D module is not enabled (ADON = 0), the
module ignores the Special Event Trigger.
Note: The GO/DONE bit should NOT be set in
the same instruction that turns on the A/D. Note: With an ECCP2 trigger, Timer1 or Timer 3
is cleared. The timers reset to automati-
cally repeat the A/D acquisition period with
minimal software overhead (moving
ADRESH:ADRESL to the desired loca-
tion). If the A/D module is not enabled, the
Special Event Trigger is ignored by the
module, but the timer’s counter resets.

REGISTER 22-6: ADCTRIG: A/D TRIGGER REGISTER (BANKED EB8h)

U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0
— — — — — — TRIGSEL1 TRIGSEL0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-2 Unimplemented: Read as ‘0’

bit 1-0 TRIGSEL<1:0>: Special Trigger Select bits
11 = Selects the special trigger from the RTCC
10 = Selects the special trigger from the Timer1
01 = Selects the special trigger from the CTMU
00 = Selects the special trigger from the ECCP2

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FIGURE 22-3: A/D CONVERSION TAD CYCLES (ACQT<2:0> = 000, TACQ = 0)
TCY - TAD TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10 TAD11
b9 b8 b7 b6 b5 b4 b3 b2 b1 b0

Conversion starts
Holding capacitor is disconnected from analog input (typically 100 ns)

Set GO/DONE bit

Next Q4: ADRESH/ADRESL are loaded, GO/DONE bit is cleared,

ADIF bit is set, holding capacitor is connected to analog input.

FIGURE 22-4: A/D CONVERSION TAD CYCLES (ACQT<2:0> = 010, TACQ = 4 TAD)

TACQT Cycles TAD Cycles

1 2 3 4 1 2 3 4 5 6 7 8 9 10 11
b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
Automatic
Acquisition Conversion starts
Time (Holding capacitor is disconnected)

Set GO/DONE bit

(Holding capacitor continues
acquiring input) Next Q4: ADRESH:ADRESL are loaded, GO/DONE bit is cleared,
ADIF bit is set, holding capacitor is reconnected to analog input.

22.7 A/D Converter Calibration The calibration process assumes that the device is in a
relatively steady-state operating condition. If A/D
The A/D Converter in the PIC18F47J53 family of calibration is used, it should be performed after each
devices includes a self-calibration feature, which com- device Reset or if there are other major changes in
pensates for any offset generated within the module. operating conditions.
The calibration process is automated and is initiated by
setting the ADCAL bit (ADCON1<6>). The next time
the GO/DONE bit is set, the module will perform an off-
set calibration and store the result internally. Thus,
subsequent offsets will be compensated.
Example 22-1 provides an example of a calibration
routine.

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22.8 Operation in Power-Managed mode clock source until the conversion has been com-
Modes pleted. If desired, the device may be placed into the
corresponding power-managed Idle mode during the
The selection of the automatic acquisition time and A/D conversion.
conversion clock is determined in part by the clock
If the power-managed mode clock frequency is less
source and frequency while in a power-managed
than 1 MHz, the A/D RC clock source should be
mode.
selected.
If the A/D is expected to operate while the device is in
Operation in the Sleep mode requires the A/D RC clock
a power-managed mode, the ACQT<2:0> and
to be selected. If bits, ACQT<2:0>, are set to ‘000’ and
ADCS<2:0> bits in ADCON1 should be updated in
a conversion is started, the conversion will be delayed
accordance with the power-managed mode clock that
one instruction cycle to allow execution of the SLEEP
will be used. After the power-managed mode is entered
instruction and entry to Sleep mode. The IDLEN and
(either of the power-managed Run modes), an A/D
SCS bits in the OSCCON register must have already
acquisition or conversion may be started. Once an
been cleared prior to starting the conversion.
acquisition or conversion is started, the device should
continue to be clocked by the same power-managed

EXAMPLE 22-1: SAMPLE A/D CALIBRATION ROUTINE

BCF ANCON0,PCFG0 ;Make Channel 0 analog
BSF ADCON0,ADON ;Enable A/D module
BSF ADCON1,ADCAL ;Enable Calibration
BSF ADCON0,GO ;Start a dummy A/D conversion
CALIBRATION ;
BTFSC ADCON0,GO ;Wait for the dummy conversion to finish
BRA CALIBRATION ;
BCF ADCON1,ADCAL ;Calibration done, turn off calibration enable
;Proceed with the actual A/D conversion

TABLE 22-2: SUMMARY OF A/D REGISTERS

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF
PIR1 PMPIF(1) ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF
PIE1 PMPIE(1) ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE
IPR1 PMPIP(1) ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP
PIR2 OSCFIF CM2IF CM1IF USBIF BCL1IF HLVDIF TMR3IF CCP2IF
PIE2 OSCFIE CM2IE CM1IE USBIE BCL1IE HLVDIE TMR3IE CCP2IE
IPR2 OSCFIP CM2IP CM1IP USBIP BCL1IP HLVDIP TMR3IP CCP2IP
ADCTRIG — — — — — — TRIGSEL1 TRIGSEL0
ADRESH A/D Result Register High Byte
ADRESL A/D Result Register Low Byte
ADCON0 VCFG1 VCFG0 CHS3 CHS3 CHS1 CHS0 GO/DONE ADON
ANCON0 PCFG7(1) PCFG6(1) PCFG5(1) PCFG4 PCFG3 PCFG2 PCFG1 PCFG0
ADCON1 ADFM ADCAL ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0
ANCON1 VBGEN r — PCFG12 PCFG11 PCFG10 PCFG9 PCFG8
CCP2CON P2M1 P2M0 DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0
PORTA RA7 RA6 RA5 — RA3 RA2 RA1 RA0
TRISA TRISA7 TRISA6 TRISA5 — TRISA3 TRISA2 TRISA1 TRISA0
Legend: — = unimplemented, read as ‘0’, r = reserved. Shaded cells are not used for A/D conversion.
Note 1: These bits are only available on 44-pin devices.

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23.0 UNIVERSAL SERIAL BUS 23.1 Overview of the USB Peripheral
(USB) PIC18F47J53 family devices contain a full-speed and
This section describes the details of the USB peripheral. low-speed, compatible USB Serial Interface Engine
Because of the very specific nature of the module, (SIE) that allows fast communication between any USB
knowledge of USB is expected. Some high-level USB host and the PIC® MCU. The SIE can be interfaced
information is provided in Section 23.9 “Overview of directly to the USB, utilizing the internal transceiver.
USB” only for application design reference. Designers Some special hardware features have been included to
are encouraged to refer to the official specification improve performance. Dual access port memory in the
published by the USB Implementers Forum (USB-IF) for device’s data memory space (USB RAM) has been
the latest information. USB Specification Revision 2.0 is supplied to share direct memory access between the
the most current specification at the time of publication microcontroller core and the SIE. Buffer descriptors are
of this document. also provided, allowing users to freely program end-
point memory usage within the USB RAM space.
Figure 23-1 provides a general overview of the USB
peripheral and its features.

FIGURE 23-1: USB PERIPHERAL AND OPTIONS

PIC18F47J53 Family

External 3.3V
VUSB Supply

Optional
P External
Pull-ups(1)
FSEN P
UPUEN
Internal Pull-ups (Full (Low
UTRDIS Speed) Speed)
Transceiver
USB Bus
USB Clock from the FS
D+
Oscillator Module
D-

USB Control and

Configuration

USB
SIE

3.8-Kbyte
USB RAM

Note 1: The internal pull-up resistors should be disabled (UPUEN = 0) if external pull-up resistors are used.

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23.2 USB Status and Control monitored to determine whether the differential data
lines have come out of a single-ended zero condition.
The operation of the USB module is configured and This helps to differentiate the initial power-up state from
managed through three control registers. In addition, a the USB Reset signal.
total of 22 registers are used to manage the actual USB
transactions. The registers are: The overall operation of the USB module is controlled
by the USBEN bit (UCON<3>). Setting this bit activates
• USB Control register (UCON) the module and resets all of the PPBI bits in the Buffer
• USB Configuration register (UCFG) Descriptor Table (BDT) to ‘0’. This bit also activates the
• USB Transfer Status register (USTAT) internal pull-up resistors if they are enabled. Thus, this
• USB Device Address register (UADDR) bit can be used as a soft attach/detach to the USB.
• Frame Number registers (UFRMH:UFRML) Although all status and control bits are ignored when
• Endpoint Enable registers 0 through 15 (UEPn) this bit is clear, the module needs to be fully preconfig-
ured prior to setting this bit. The USB clock source
23.2.1 USB CONTROL REGISTER (UCON) should have been already configured for the correct
frequency and running. If the PLL is being used, it
The USB Control register (Register 23-1) contains bits
should be enabled at least 2 ms (enough time for the
needed to control the module behavior during transfers.
PLL to lock) before attempting to set the USBEN bit.
The register contains bits that control the following:
• Main USB Peripheral Enable Note: When disabling the USB module, make
• Ping-Pong Buffer Pointer Reset sure the SUSPND bit (UCON<1>) is clear
• Control of the Suspend mode prior to clearing the USBEN bit. Clearing
• Packet Transfer Disable the USBEN bit when the module is in the
suspended state may prevent the module
In addition, the USB Control register contains a status from fully powering down
bit, SE0 (UCON<5>), which is used to indicate the
occurrence of a single-ended zero on the bus. When
the USB module is enabled, this bit should be

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REGISTER 23-1: UCON: USB CONTROL REGISTER (ACCESS F65h)
U-0 R/W-0 R-x R/C-0 R/W-0 R/W-0 R/W-0 U-0
— PPBRST(2) SE0 PKTDIS USBEN(1) RESUME SUSPND —
bit 7 bit 0

Legend: C = Clearable bit

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 Unimplemented: Read as ‘0’

bit 6 PPBRST: Ping-Pong Buffers Reset bit(2)
1 = Reset all Ping-Pong Buffer Pointers to the Even Buffer Descriptor (BD) banks
0 = Ping-Pong Buffer Pointers are not being reset
bit 5 SE0: Live Single-Ended Zero Flag bit
1 = Single-ended zero is active on the USB bus
0 = No single-ended zero is detected
bit 4 PKTDIS: Packet Transfer Disable bit
1 = SIE token and packet processing are disabled, automatically set when a SETUP token is received
0 = SIE token and packet processing are enabled
bit 3 USBEN: USB Module Enable bit(1)
1 = USB module and supporting circuitry are enabled (device attached)
0 = USB module and supporting circuitry are disabled (device detached)
bit 2 RESUME: Resume Signaling Enable bit
1 = Resume signaling is activated
0 = Resume signaling is disabled
bit 1 SUSPND: Suspend USB bit
1 = USB module and supporting circuitry are in Power Conserve mode, SIE clock inactive
0 = USB module and supporting circuitry are in normal operation, SIE clocked at the configured rate
bit 0 Unimplemented: Read as ‘0’

Note 1: Make sure the USB clock source is correctly configured before setting this bit.
2: There should be at least four cycles of delay between the setting and PPBRST.

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The PPBRST bit (UCON<6>) controls the Reset status The UCFG register also contains two bits, which aid in
when Double-Buffering mode (ping-pong buffering) is module testing, debugging and USB certifications.
used. When the PPBRST bit is set, all Ping-Pong These bits control output enable state monitoring and
Buffer Pointers are set to the Even buffers. PPBRST eye pattern generation.
has to be cleared by firmware. This bit is ignored in
Note: The USB speed, transceiver and pull-up
buffering modes not using ping-pong buffering.
should only be configured during the
The PKTDIS bit (UCON<4>) is a flag indicating that the module setup phase. It is not recom-
SIE has disabled packet transmission and reception. mended to switch these settings while the
This bit is set by the SIE when a SETUP token is module is enabled.
received to allow setup processing. This bit cannot be
set by the microcontroller, only cleared; clearing it 23.2.2.1 Internal Transceiver
allows the SIE to continue transmission and/or
reception. Any pending events within the Buffer The USB peripheral has a built-in, USB 2.0, full-speed
Descriptor Table (BDT) will still be available, indicated and low-speed capable transceiver, internally con-
within the USTAT register’s FIFO buffer. nected to the SIE. This feature is useful for low-cost,
single chip applications. The UTRDIS bit (UCFG<3>)
The RESUME bit (UCON<2>) allows the peripheral to controls the transceiver; it is enabled by default
perform a remote wake-up by executing resume (UTRDIS = 0). The FSEN bit (UCFG<2>) controls the
signaling. To generate a valid remote wake-up, transceiver speed; setting the bit enables full-speed
firmware must set RESUME for 10 ms and then clear operation.
the bit. For more information on resume signaling, see
Sections 7.1.7.5, 11.4.4 and 11.9 in the USB The on-chip USB pull-up resistors are controlled by the
2.0 Specification. UPUEN bit (UCFG<4>). They can only be selected
when the on-chip transceiver is enabled.
The SUSPND bit (UCON<1>) places the module and
supporting circuitry in a low-power mode. The input The internal USB transceiver obtains power from the
clock to the SIE is also disabled. This bit should be set VUSB pin. In order to meet USB signalling level specifi-
by the software in response to an IDLEIF interrupt. It cations, VUSB must be supplied with a voltage source
should be reset by the microcontroller firmware after an between 3.0V and 3.6V. The best electrical signal
ACTVIF interrupt is observed. When this bit is active, quality is obtained when a 3.3V supply is used and
the device remains attached to the bus but the trans- locally bypassed with a high quality ceramic capacitor
ceiver outputs remain Idle. The voltage on the VUSB pin (ex: 0.1 F). The capacitor should be placed as close
may vary depending on the value of this bit. Setting this as possible to the VUSB and VSS pins.
bit before a IDLEIF request will result in unpredictable VUSB should always be maintained  VDD. If the USB
bus behavior. module is not used, but RC4 or RC5 are used as
general purpose inputs, VUSB should still be connected
Note: While in Suspend mode, a typical
to a power source (such as VDD). The input thresholds
bus-powered USB device is limited to
for the RC4 and RC5 pins are dependent upon the
2.5 mA of current. This is the complete
VUSB supply level.
current which may be drawn by the PIC
device and its supporting circuitry. Care The D+ and D- signal lines can be routed directly to
should be taken to assure minimum their respective pins on the USB connector or cable (for
current draw when the device enters hard-wired applications). No additional resistors,
Suspend mode. capacitors or magnetic components are required as the
D+ and D- drivers have controlled slew rate and output
23.2.2 USB CONFIGURATION REGISTER impedance intended to match with the
(UCFG) characteristic impedance of the USB cable.

Prior to communicating over USB, the module’s In order to achieve optimum USB signal quality, the D+
associated internal and/or external hardware must be and D- traces between the microcontroller and USB
configured. Most of the configuration is performed with connector (or cable) should be less than 19 cm long.
the UCFG register (Register 23-2).The UFCG register Both traces should be equal in length and they should
contains most of the bits that control the system level be routed parallel to each other. Ideally, these traces
behavior of the USB module. These include: should be designed to have a characteristic impedance
matching that of the USB cable.
• Bus Speed (full speed versus low speed)
• On-Chip Pull-up Resistor Enable
• On-Chip Transceiver Enable
• Ping-Pong Buffer Usage

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REGISTER 23-2: UCFG: USB CONFIGURATION REGISTER (BANKED F39h)
R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
UTEYE UOEMON (1,2) (1,3) (1)
— UPUEN UTRDIS FSEN PPB1 PPB0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 UTEYE: USB Eye Pattern Test Enable bit

1 = Eye pattern test is enabled
0 = Eye pattern test is disabled
bit 6 UOEMON: USB OE Monitor Enable bit
1 = UOE signal active, indicating intervals during which the D+/D- lines are driving
0 = UOE signal inactive
bit 5 Unimplemented: Read as ‘0’
bit 4 UPUEN: USB On-Chip Pull-up Enable bit(1,2)
1 = On-chip pull-up is enabled (pull-up on D+ with FSEN = 1 or D- with FSEN = 0)
0 = On-chip pull-up is disabled
bit 3 UTRDIS: On-Chip Transceiver Disable bit(1,3)
1 = On-chip transceiver is disabled
0 = On-chip transceiver is active
bit 2 FSEN: Full-Speed Enable bit(1)
1 = Full-speed device: controls transceiver edge rates; requires input clock at 48 MHz
0 = Low-speed device: controls transceiver edge rates; requires input clock at 6 MHz
bit 1-0 PPB<1:0>: Ping-Pong Buffers Configuration bits
11 = Even/Odd ping-pong buffers are enabled for Endpoints 1 to 15
10 = Even/Odd ping-pong buffers are enabled for all endpoints
01 = Even/Odd ping-pong buffer are enabled for OUT Endpoint 0
00 = Even/Odd ping-pong buffers are disabled

Note 1: The UPUEN, UTRDIS and FSEN bits should never be changed while the USB module is enabled. These
values must be preconfigured prior to enabling the module.
2: This bit is only valid when the on-chip transceiver is active (UTRDIS = 0); otherwise, it is ignored.
3: If UTRDIS is set, the UOE signal will be active – independent of the UOEMON bit setting.

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23.2.2.2 Internal Pull-up Resistors 23.2.2.4 Ping-Pong Buffer Configuration
The PIC18F47J53 family devices have built-in pull-up The usage of ping-pong buffers is configured using the
resistors designed to meet the requirements for PPB<1:0> bits. Refer to Section 23.4.4 “Ping-Pong
low-speed and full-speed USB. The UPUEN bit Buffering” for a complete explanation of the ping-pong
(UCFG<4>) enables the internal pull-ups. Figure 23-1 buffers.
shows the pull-ups and their control.
23.2.2.5 Eye Pattern Test Enable
Note: A compliant USB device should never
source any current onto the +5V VBUS line An automatic eye pattern test can be generated by the
of the USB cable. Additionally, USB module when the UCFG<7> bit is set. The eye pattern
devices should not source any current on output will be observable based on module settings,
the D+ and D- data lines whenever the meaning that the user is first responsible for configuring
+5V VBUS line is less than 1.17V. In order the SIE clock settings, pull-up resistor and Transceiver
to be USB compliant, applications which mode. In addition, the module has to be enabled.
are not purely bus-powered should moni- Once UTEYE is set, the module emulates a switch from
tor the VBUS line, and avoid turning on the a receive to transmit state and will start transmitting a
USB module and the D+ or D- pull-up J-K-J-K bit sequence (K-J-K-J for full speed). The
resistor until VBUS is greater than 1.17V. sequence will be repeated indefinitely while the Eye
VBUS can be connected to and monitored Pattern Test mode is enabled.
by a 5V tolerant I/O pin, or if a resistive
divider is used, by an analog capable pin. Note that this bit should never be set while the module
is connected to an actual USB system. This Test mode
is intended for board verification to aid with USB certi-
23.2.2.3 External Pull-up Resistors fication tests. It is intended to show a system developer
External pull-ups may also be used. The VUSB pin may the noise integrity of the USB signals which can be
be used to pull up D+ or D-. The pull-up resistor must be affected by board traces, impedance mismatches and
1.5 k (±5%) as required by the USB specifications. proximity to other system components. It does not
properly test the transition from a receive to a transmit
Figure 23-2 provides an example of external circuitry. state. Although the eye pattern is not meant to replace
the more complex USB certification test, it should aid
FIGURE 23-2: EXTERNAL CIRCUITRY during first order system debugging.
Host
PIC® MCU Controller/HUB

VUSB

1.5 k
D+

D-

Note: The above setting shows a typical connection

for a full-speed configuration using an on-chip
regulator and an external pull-up resistor.

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23.2.3 USB STATUS REGISTER (USTAT) Clearing the transfer complete flag bit, TRNIF, causes
the SIE to advance the FIFO. If the next data in the
The USB Status register reports the transaction status
FIFO holding register is valid, the SIE will reassert the
within the SIE. When the SIE issues a USB transfer
interrupt within 5 TCY of clearing TRNIF. If no additional
complete interrupt, USTAT should be read to determine
data is present, TRNIF will remain clear; USTAT data
the status of the transfer. USTAT contains the transfer
will no longer be reliable.
endpoint number, direction and Ping-Pong Buffer
Pointer value (if used). Note: If an endpoint request is received while the
USTAT FIFO is full, the SIE will
Note: The data in the USB Status register is valid
automatically issue a NAK back to the host.
only when the TRNIF interrupt flag is
asserted.
FIGURE 23-3: USTAT FIFO
The USTAT register is actually a read window into a
4-byte status FIFO, maintained by the SIE. It allows the USTAT from SIE
microcontroller to process one transfer while the SIE
processes additional endpoints (Figure 23-3). When
the SIE completes using a buffer for reading or writing
data, it updates the USTAT register. If another USB
transfer is performed before a transaction complete 4-Byte FIFO Clearing TRNIF
for USTAT Advances FIFO
interrupt is serviced, the SIE will store the status of the
next transfer into the status FIFO.

Data Bus

REGISTER 23-3: USTAT: USB STATUS REGISTER (ACCESS F64h)

U-0 R-x R-x R-x R-x R-x R-x U-0
— ENDP3 ENDP2 ENDP1 ENDP0 DIR PPBI(1) —
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 Unimplemented: Read as ‘0’

bit 6-3 ENDP<3:0>: Encoded Number of Last Endpoint Activity bits
(represents the number of the BDT updated by the last USB transfer)
1111 = Endpoint 15
1110 = Endpoint 14
.
.
.
0001 = Endpoint 1
0000 = Endpoint 0
bit 2 DIR: Last BD Direction Indicator bit
1 = The last transaction was an IN token
0 = The last transaction was an OUT or SETUP token
bit 1 PPBI: Ping-Pong BD Pointer Indicator bit(1)
1 = The last transaction was to the Odd BD bank
0 = The last transaction was to the Even BD bank
bit 0 Unimplemented: Read as ‘0’

Note 1: This bit is only valid for endpoints with available Even and Odd BD registers.

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23.2.4 USB ENDPOINT CONTROL transactions. For Endpoint 0, this bit should always be
cleared since the USB specifications identify
Each of the 16 possible bidirectional endpoints has its
Endpoint 0 as the default control endpoint.
own independent control register, UEPn (where ‘n’
represents the endpoint number). Each register has an The EPOUTEN bit (UEPn<2>) is used to enable or
identical complement of control bits. disable USB OUT transactions from the host. Setting
this bit enables OUT transactions. Similarly, the
Register 23-4 provides the prototype.
EPINEN bit (UEPn<1>) enables or disables USB IN
The EPHSHK bit (UEPn<4>) controls handshaking for transactions from the host.
the endpoint; setting this bit enables USB handshaking.
The EPSTALL bit (UEPn<0>) is used to indicate a
Typically, this bit is always set except when using
STALL condition for the endpoint. If a STALL is issued
isochronous endpoints.
on a particular endpoint, the EPSTALL bit for that end-
The EPCONDIS bit (UEPn<3>) is used to enable or point pair will be set by the SIE. This bit remains set
disable USB control operations (SETUP) through the until it is cleared through firmware, or until the SIE is
endpoint. Clearing this bit enables SETUP transac- reset.
tions. Note that the corresponding EPINEN and
EPOUTEN bits must be set to enable IN and OUT

REGISTER 23-4: UEPn: USB ENDPOINT n CONTROL REGISTER (UEP0 THROUGH UEP15)
(BANKED F26h-F35h)
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-5 Unimplemented: Read as ‘0’

bit 4 EPHSHK: Endpoint Handshake Enable bit
1 = Endpoint handshake enabled
0 = Endpoint handshake disabled (typically used for isochronous endpoints)
bit 3 EPCONDIS: Bidirectional Endpoint Control bit
If EPOUTEN = 1 and EPINEN = 1:
1 = Disable Endpoint n from control transfers; only IN and OUT transfers are allowed
0 = Enable Endpoint n for control (SETUP) transfers; IN and OUT transfers are also allowed
bit 2 EPOUTEN: Endpoint Output Enable bit
1 = Endpoint n output is enabled
0 = Endpoint n output is disabled
bit 1 EPINEN: Endpoint Input Enable bit
1 = Endpoint n input is enabled
0 = Endpoint n input is disabled
bit 0 EPSTALL: Endpoint Stall Indicator bit
1 = Endpoint n has issued one or more STALL packets
0 = Endpoint n has not issued any STALL packets

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23.2.5 USB ADDRESS REGISTER FIGURE 23-4: IMPLEMENTATION OF
(UADDR) USB RAM IN DATA
The USB Address register contains the unique USB MEMORY SPACE
address that the peripheral will decode when active.
UADDR is reset to 00h when a USB Reset is received, 000h
Access Ram
indicated by URSTIF, or when a Reset is received from 05Fh
the microcontroller. The USB address must be written 060h
by the microcontroller during the USB setup phase
(enumeration) as part of the Microchip USB firmware
support.

23.2.6 USB FRAME NUMBER REGISTERS

(UFRMH:UFRML)
The Frame Number registers contain the 11-bit frame
number. The low-order byte is contained in UFRML,
while the three high-order bits are contained in
UFRMH. The register pair is updated with the current
frame number whenever a SOF token is received. For Banks 0
the microcontroller, these registers are read-only. The to 14
Frame Number registers are primarily used for (USB RAM) USB Data or
isochronous transfers. The contents of the UFRMH and User Data
UFRML registers are only valid when the 48 MHz SIE
clock is active (i.e., contents are inaccurate when
SUSPND (UCON<1>) bit = 1).

23.3 USB RAM

USB data moves between the microcontroller core and CFFh
the SIE through a memory space known as the USB Buffer Descriptors, D00h
RAM. This is a special dual access memory that is USB Data or User Data DFFh
mapped into the normal data memory space in Banks, E00h
0 through 14 (00h to EBFh), for a total of 3.8 Kbytes EBFh
(Figure 23-4). EC0h

Bank 13 (D00h through DFFh) is used specifically for SFRs

endpoint buffer control, while Banks 0 through 12 and
Bank 14 are available for USB data. Depending on the FFFh
type of buffering being used, all but 8 bytes of Bank 13
may also be available for use as USB buffer space.
Although USB RAM is available to the microcontroller
as data memory, the sections that are being accessed
by the SIE should not be accessed by the
microcontroller. A semaphore mechanism is used to
determine the access to a particular buffer at any given
time. This is discussed in Section 23.4.1.1 “Buffer
Ownership”.

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23.4 Buffer Descriptors and the Buffer FIGURE 23-5: EXAMPLE OF A BUFFER
Descriptor Table DESCRIPTOR
Address Registers Contents
The registers in Bank 13 are used specifically for end-
point buffer control in a structure known as the Buffer 500h Starting
Address
Descriptor Table (BDT). This provides a flexible method
for users to construct and control endpoint buffers of
various lengths and configuration. Buffer USB Data Size of Block

The BDT is composed of Buffer Descriptors (BD) which

are used to define and control the actual buffers in the 53Fh
USB RAM space. Each BD, in turn, consists of four
registers, where n represents one of the 64 possible D00h BD0STAT (xxh)
BDs (range of 0 to 63): D01h BD0CNT 40h
Buffer
• BDnSTAT: BD Status register Descriptor D02h BD0ADRL 00h
• BDnCNT: BD Byte Count register D03h BD0ADRH 05h
• BDnADRL: BD Address Low register
Note: Memory regions are not to scale.
• BDnADRH: BD Address High register
BDs always occur as a four-byte block in the sequence, Unlike other control registers, the bit configuration for
BDnSTAT:BDnCNT:BDnADRL:BDnADRH. The address the BDnSTAT register is context-sensitive. There are
of BDnSTAT is always an offset of (4n – 1) (in hexa- two distinct configurations, depending on whether the
decimal) from D00h, with n being the buffer descriptor microcontroller or the USB module is modifying the BD
number. and buffer at a particular time. Only three bit definitions
Depending on the buffering configuration used are shared between the two.
(Section 23.4.4 “Ping-Pong Buffering”), there are up
to 32, 33 or 64 sets of buffer descriptors. At a minimum, 23.4.1.1 Buffer Ownership
the BDT must be at least 8 bytes long. This is because Because the buffers and their BDs are shared between
the USB Specification mandates that every device the CPU and the USB module, a simple semaphore
must have Endpoint 0 with both input and output for ini- mechanism is used to distinguish which is allowed to
tial setup. Depending on the endpoint and buffering update the BD and associated buffers in memory.
configuration, the BDT can be as long as 256 bytes.
This is done by using the UOWN bit (BDnSTAT<7>) as
Although they can be thought of as Special Function a semaphore to distinguish which is allowed to update
Registers, the Buffer Descriptor Status and Address the BD and associated buffers in memory. UOWN is the
registers are not hardware mapped, as conventional only bit that is shared between the two configurations
microcontroller SFRs in Bank 15 are. If the endpoint cor- of BDnSTAT.
responding to a particular BD is not enabled, its registers
When UOWN is clear, the BD entry is “owned” by the
are not used. Instead of appearing as unimplemented
microcontroller core. When the UOWN bit is set, the BD
addresses, however, they appear as available RAM.
entry and the buffer memory are “owned” by the USB
Only when an endpoint is enabled by setting the
peripheral. The core should not modify the BD or its
UEPn<1> bit does the memory at those addresses
corresponding data buffer during this time. Note that
become functional as BD registers. As with any address
the microcontroller core can still read BDnSTAT while
in the data memory space, the BD registers have an
the SIE owns the buffer and vice versa.
indeterminate value on any device Reset.
The buffer descriptors have a different meaning based
Figure 23-5 provides an example of a BD for a 64-byte
on the source of the register update. Prior to placing
buffer, starting at 500h. A particular set of BD registers
ownership with the USB peripheral, the user can
is only valid if the corresponding endpoint has been
configure the basic operation of the peripheral through
enabled using the UEPn register. All BD registers are
the BDnSTAT bits. During this time, the byte count and
available in USB RAM. The BD for each endpoint
buffer location registers can also be set.
should be set up prior to enabling the endpoint.
When UOWN is set, the user can no longer depend on
23.4.1 BD STATUS AND CONFIGURATION the values that were written to the BDs. From this point,
the SIE updates the BDs as necessary, overwriting the
Buffer descriptors not only define the size of an end-
original BD values. The BDnSTAT register is updated
point buffer, but also determine its configuration and
by the SIE with the token PID and the transfer count,
control. Most of the configuration is done with the BD
BDnCNT, is updated.
Status register, BDnSTAT. Each BD has its own unique
and correspondingly numbered BDnSTAT register.

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 PIC18F47J53 FAMILY
The BDnSTAT byte of the BDT should always be the The Buffer Stall bit, BSTALL (BDnSTAT<2>), provides
last byte updated when preparing to arm an endpoint. support for control transfers, usually one-time stalls on
The SIE will clear the UOWN bit when a transaction Endpoint 0. It also provides support for the
has completed. SET_FEATURE/CLEAR_FEATURE commands speci-
No hardware mechanism exists to block access when fied in Chapter 9 of the USB Specification; typically,
the UOWN bit is set. Thus, unexpected behavior can continuous STALLs to any endpoint other than the
occur if the microcontroller attempts to modify memory default control endpoint.
when the SIE owns it. Similarly, reading such memory The BSTALL bit enables buffer stalls. Setting BSTALL
may produce inaccurate data until the USB peripheral causes the SIE to return a STALL token to the host if a
returns ownership to the microcontroller. received token would use the BD in that location. The
EPSTALL bit in the corresponding UEPn Control
23.4.1.2 BDnSTAT Register (CPU Mode) register is set and a STALL interrupt is generated when
When UOWN = 0, the microcontroller core owns the a STALL is issued to the host. The UOWN bit remains
BD. At this point, the other seven bits of the register set and the BDs are not changed unless a SETUP
take on control functions. token is received. In this case, the STALL condition is
cleared and the ownership of the BD is returned to the
The Data Toggle Sync Enable bit, DTSEN microcontroller core.
(BDnSTAT<3>), controls data toggle parity checking.
Setting DTSEN enables data toggle synchronization by The BCx<9:8> bits (BDnSTAT<1:0>) store the two
the SIE. When enabled, it checks the data packet’s par- most significant digits of the SIE byte count. The lower
ity against the value of DTS (BDnSTAT<6>). If a packet 8 digits are stored in the corresponding BDnCNT regis-
arrives with an incorrect synchronization, the data will ter. See Section 23.4.2 “BD Byte Count” for more
essentially be ignored. It will not be written to the USB information.
RAM and the USB transfer complete interrupt flag will
not be set. The SIE will send an ACK token back to the
host to Acknowledge receipt, however. The effects of
the DTSEN bit on the SIE are summarized in
Table 23-1.

TABLE 23-1: EFFECT OF DTSEN BIT ON ODD/EVEN (DATA0/DATA1) PACKET RECEPTION

OUT Packet BDnSTAT Settings Device Response after Receiving Packet
from Host DTSEN DTS Handshake UOWN TRNIF BDnSTAT and USTAT Status
DATA0 1 0 ACK 0 1 Updated
DATA1 1 0 ACK 1 0 Not Updated
DATA0 1 1 ACK 1 0 Not Updated
DATA1 1 1 ACK 0 1 Updated
Either 0 x ACK 0 1 Updated
Either, with error x x NAK 1 0 Not Updated
Legend: x = don’t care

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PIC18F47J53 FAMILY
REGISTER 23-5: BDnSTAT: BUFFER DESCRIPTOR n STATUS REGISTER (BD0STAT THROUGH
BD63STAT), CPU MODE
R/W-x R/W-x U-0 U-0 R/W-x R/W-x R/W-x R/W-x
UOWN(1) DTS (2)
— (3)
— (3)
DTSEN BSTALL BC9 BC8
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 UOWN: USB Own bit(1)

0 = The microcontroller core owns the BD and its corresponding buffer
bit 6 DTS: Data Toggle Synchronization bit(2)
1 = Data 1 packet
0 = Data 0 packet
bit 5-4 Unimplemented: These bits should always be programmed to ‘0’(3)
bit 3 DTSEN: Data Toggle Synchronization Enable bit
1 = Data toggle synchronization is enabled; data packets with incorrect Sync value will be ignored
except for a SETUP transaction, which is accepted even if the data toggle bits do not match
0 = No data toggle synchronization is performed
bit 2 BSTALL: Buffer Stall Enable bit
1 = Buffer stall enabled; STALL handshake issued if a token is received that would use the BD in the
given location (UOWN bit remains set, BD value is unchanged)
0 = Buffer stall disabled
bit 1-0 BC<9:8>: Byte Count 9 and 8 bits
The byte count bits represent the number of bytes that will be transmitted for an IN token or received
during an OUT token. Together with BC<7:0>, the valid byte counts are 0-1023.

Note 1: This bit must be initialized by the user to the desired value prior to enabling the USB module.
2: This bit is ignored unless DTSEN = 1.
3: If these bits are set, USB communication may not work. Hence, these bits should always be maintained as
‘0’.

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23.4.1.3 BDnSTAT Register (SIE Mode) The 10-bit byte count is distributed over two registers.
The lower 8 bits of the count reside in the BDnCNT
When the BD and its buffer are owned by the SIE, most
register. The upper two bits reside in BDnSTAT<1:0>.
of the bits in BDnSTAT take on a different meaning. The
This represents a valid byte range of 0 to 1023.
configuration is shown in Register 23-6. Once UOWN
is set, any data or control settings previously written
23.4.3 BD ADDRESS VALIDATION
there by the user will be overwritten with data from the
SIE. The BD Address register pair contains the starting RAM
address location for the corresponding endpoint buffer.
The BDnSTAT register is updated by the SIE with the
No mechanism is available in hardware to validate the
token Packet Identifier (PID) which is stored in
BD address.
BDnSTAT<5:2>. The transfer count in the correspond-
ing BDnCNT register is updated. Values that overflow If the value of the BD address does not point to an
the 8-bit register carry over to the two most significant address in the USB RAM, or if it points to an address
digits of the count, stored in BDnSTAT<1:0>. within another endpoint’s buffer, data is likely to be lost
or overwritten. Similarly, overlapping a receive buffer
23.4.2 BD BYTE COUNT (OUT endpoint) with a BD location in use can yield
unexpected results. When developing USB
The byte count represents the total number of bytes
applications, the user may want to consider the
that will be transmitted during an IN transfer. After an IN
inclusion of software-based address validation in their
transfer, the SIE will return the number of bytes sent to
code.
the host.
For an OUT transfer, the byte count represents the
maximum number of bytes that can be received and
stored in USB RAM. After an OUT transfer, the SIE will
return the actual number of bytes received. If the
number of bytes received exceeds the corresponding
byte count, the data packet will be rejected and a NAK
handshake will be generated. When this happens, the
byte count will not be updated.

REGISTER 23-6: BDnSTAT: BUFFER DESCRIPTOR n STATUS REGISTER (BD0STAT THROUGH

BD63STAT), SIE MODE (DATA RETURNED BY THE SIE TO THE MCU)
R/W-x r-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
UOWN r PID3 PID2 PID1 PID0 BC9 BC8
bit 7 bit 0

Legend: r = Reserved bit

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 UOWN: USB Own bit

1 = The SIE owns the BD and its corresponding buffer
bit 6 Reserved: Not written by the SIE
bit 5-2 PID<3:0>: Packet Identifier bits
The received token PID value of the last transfer (IN, OUT or SETUP transactions only).
bit 1-0 BC<9:8>: Byte Count 9 and 8 bits
These bits are updated by the SIE to reflect the actual number of bytes received on an OUT transfer
and the actual number of bytes transmitted on an IN transfer.

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23.4.4 PING-PONG BUFFERING the completion of a transaction (UOWN cleared by the
SIE), the pointer is toggled to the Odd BD. After the
An endpoint is defined to have a ping-pong buffer when
completion of the next transaction, the pointer is
it has two sets of BD entries: one set for an Even
toggled back to the Even BD and so on.
transfer and one set for an Odd transfer. This allows the
CPU to process one BD while the SIE is processing the The Even/Odd status of the last transaction is stored in
other BD. Double-buffering BDs in this way allows for the PPBI bit of the USTAT register. The user can reset
maximum throughput to/from the USB. all Ping-Pong Pointers to Even using the PPBRST bit.
The USB module supports four modes of operation: Figure 23-6 shows the four different modes of
operation and how USB RAM is filled with the BDs.
• No ping-pong support
• Ping-pong buffer support for OUT Endpoint 0 only BDs have a fixed relationship to a particular endpoint,
depending on the buffering configuration. Table 23-2
• Ping-pong buffer support for all endpoints
provides the mapping of BDs to endpoints. This
• Ping-pong buffer support for all other endpoints relationship also means that gaps may occur in the
except Endpoint 0 BDT if endpoints are not enabled contiguously. This,
The ping-pong buffer settings are configured using the theoretically, means that the BDs for disabled
PPB<1:0> bits in the UCFG register. endpoints could be used as buffer space. In practice,
The USB module keeps track of the Ping-Pong Pointer users should avoid using such spaces in the BDT
individually for each endpoint. All pointers are initially unless a method of validating BD addresses is
reset to the Even BD when the module is enabled. After implemented.

FIGURE 23-6: BUFFER DESCRIPTOR TABLE MAPPING FOR BUFFERING MODES

PPB<1:0> = 00 PPB<1:0> = 01 PPB<1:0> = 10 PPB<1:0> = 11
No Ping-Pong Ping-Pong Buffer Ping-Pong Buffers Ping-Pong Buffers
Buffers on EP0 OUT on all EPs on all other EPs
except EP0
D00h D00h D00h D00h
EP0 OUT EP0 OUT Even EP0 OUT Even EP0 OUT
Descriptor Descriptor Descriptor Descriptor

EP0 IN EP0 OUT Odd EP0 OUT Odd EP0 IN

Descriptor Descriptor Descriptor Descriptor

EP1 OUT EP0 IN Even EP1 OUT Even

Descriptor EP0 IN Descriptor Descriptor
Descriptor
EP1 IN EP0 IN Odd EP1 OUT Odd
Descriptor EP1 OUT Descriptor Descriptor
Descriptor
EP1 OUT Even EP1 IN Even
EP1 IN Descriptor Descriptor
Descriptor
EP1 OUT Odd EP1 IN Odd
EP15 IN
Descriptor Descriptor
Descriptor
D7Fh
EP1 IN Even
EP15 IN Descriptor
D83h Descriptor
EP1 IN Odd
Descriptor
Available
as
Available
Data RAM EP15 IN Odd
as
Data RAM Descriptor
DF7h

Available
as
EP15 IN Odd Data RAM
Descriptor
DFFh DFFh DFFh DFFh
Maximum Memory Maximum Memory Maximum Memory Maximum Memory
Used: 128 bytes Used: 132 bytes Used: 256 bytes Used: 248 bytes
Maximum BDs: Maximum BDs: Maximum BDs: 6 Maximum BDs:
32 (BD0 to BD31) 33 (BD0 to BD32) 4 (BD0 to BD63) 62 (BD0 to BD61)

Note: Memory area is not shown to scale.

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TABLE 23-2: ASSIGNMENT OF BUFFER DESCRIPTORS FOR THE DIFFERENT
BUFFERING MODES
BDs Assigned to Endpoint

Mode 3
Mode 0 Mode 1 Mode 2
Endpoint (Ping-Pong on all other EPs,
(No Ping-Pong) (Ping-Pong on EP0 OUT) (Ping-Pong on all EPs)
except EP0)

Out In Out In Out In Out In

0 0 1 0 (E), 1 (O) 2 0 (E), 1 (O) 2 (E), 3 (O) 0 1

1 2 3 3 4 4 (E), 5 (O) 6 (E), 7 (O) 2 (E), 3 (O) 4 (E), 5 (O)
2 4 5 5 6 8 (E), 9 (O) 10 (E), 11 (O) 6 (E), 7 (O) 8 (E), 9 (O)
3 6 7 7 8 12 (E), 13 (O) 14 (E), 15 (O) 10 (E), 11 (O) 12 (E), 13 (O)
4 8 9 9 10 16 (E), 17 (O) 18 (E), 19 (O) 14 (E), 15 (O) 16 (E), 17 (O)
5 10 11 11 12 20 (E), 21 (O) 22 (E), 23 (O) 18 (E), 19 (O) 20 (E), 21 (O)
6 12 13 13 14 24 (E), 25 (O) 26 (E), 27 (O) 22 (E), 23 (O) 24 (E), 25 (O)
7 14 15 15 16 28 (E), 29 (O) 30 (E), 31 (O) 26 (E), 27 (O) 28 (E), 29 (O)
8 16 17 17 18 32 (E), 33 (O) 34 (E), 35 (O) 30 (E), 31 (O) 32 (E), 33 (O)
9 18 19 19 20 36 (E), 37 (O) 38 (E), 39 (O) 34 (E), 35 (O) 36 (E), 37 (O)
10 20 21 21 22 40 (E), 41 (O) 42 (E), 43 (O) 38 (E), 39 (O) 40 (E), 41 (O)
11 22 23 23 24 44 (E), 45 (O) 46 (E), 47 (O) 42 (E), 43 (O) 44 (E), 45 (O)
12 24 25 25 26 48 (E), 49 (O) 50 (E), 51 (O) 46 (E), 47 (O) 48 (E), 49 (O)
13 26 27 27 28 52 (E), 53 (O) 54 (E), 55 (O) 50 (E), 51 (O) 52 (E), 53 (O)
14 28 29 29 30 56 (E), 57 (O) 58 (E), 59 (O) 54 (E), 55 (O) 56 (E), 57 (O)
15 30 31 31 32 60 (E), 61 (O) 62 (E), 63 (O) 58 (E), 59 (O) 60 (E), 61 (O)
Legend: (E) = Even transaction buffer, (O) = Odd transaction buffer

TABLE 23-3: SUMMARY OF USB BUFFER DESCRIPTOR TABLE REGISTERS

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
BDnSTAT(1) UOWN DTS(4) PID3(2) PID2(2) PID1(2) PID0(2) BC9 BC8
DTSEN(3) BSTALL(3)
BDnCNT(1) Byte Count
BDnADRL(1) Buffer Address Low
BDnADRH(1) Buffer Address High
Note 1: For buffer descriptor registers, n may have a value of 0 to 63. For the sake of brevity, all 64 registers are
shown as one generic prototype. All registers have indeterminate Reset values (xxxx xxxx).
2: Bits, 5 through 2, of the BDnSTAT register are used by the SIE to return PID<3:0> values once the register
is turned over to the SIE (UOWN bit is set). Once the registers have been under SIE control, the values
written for DTSEN and BSTALL are no longer valid.
3: Prior to turning the buffer descriptor over to the SIE (UOWN bit is cleared), bits, 5 through 2, of the
BDnSTAT register are used to configure the DTSEN and BSTALL settings.
4: This bit is ignored unless DTSEN = 1.

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23.5 USB Interrupts Figure 23-7 provides the interrupt logic for the USB
module. There are two layers of interrupt registers in
The USB module can generate multiple interrupt con- the USB module. The top level consists of overall USB
ditions. To accommodate all of these interrupt sources, status interrupts; these are enabled and flagged in the
the module is provided with its own interrupt logic UIE and UIR registers, respectively. The second level
structure, similar to that of the microcontroller. USB consists of USB error conditions, which are enabled
interrupts are enabled with one set of control registers and flagged in the UEIR and UEIE registers. An
and trapped with a separate set of flag registers. All interrupt condition in any of these triggers a USB Error
sources are funneled into a single USB interrupt Interrupt Flag (UERRIF) in the top level.
request, USBIF (PIR2<4>), in the microcontroller’s
interrupt logic. Interrupts may be used to trap routine events in a USB
transaction. Figure 23-8 provides some common
events within a USB frame and its corresponding
interrupts.

FIGURE 23-7: USB INTERRUPT LOGIC FUNNEL

Second Level USB Interrupts Top Level USB Interrupts
(USB Error Conditions) (USB Status Interrupts)
UEIR (Flag) and UEIE (Enable) Registers UIR (Flag) and UIE (Enable) Registers

SOFIF
SOFIE
BTSEF
BTSEE TRNIF USBIF
TRNIE
BTOEF
BTOEE
IDLEIF
DFN8EF IDLEIE
DFN8EE UERRIF
CRC16EF UERRIE
CRC16EE

CRC5EF STALLIF
STALLIE
CRC5EE
PIDEF
PIDEE ACTVIF
ACTVIE

URSTIF
URSTIE

FIGURE 23-8: EXAMPLE OF A USB TRANSACTION AND INTERRUPT EVENTS

From Host From Host To Host
SETUP Token Data ACK Set TRNIF

From Host To Host From Host

IN Token Data ACK Set TRNIF
USB Reset
URSTIF
From Host From Host To Host
Start-of-Frame (SOF)
OUT Token Empty Data ACK Set TRNIF
SOFIF
Transaction
Transaction
Complete

RESET SOF SETUP DATA STATUS SOF

Differential Data

Control Transfer(1)
1 ms Frame

Note 1: The control transfer shown here is only an example showing events that can occur for every transaction. Typical
control transfers will spread across multiple frames.

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23.5.1 USB INTERRUPT STATUS When the USB module is in the Low-Power Suspend
REGISTER (UIR) mode (UCON<1> = 1), the SIE does not get clocked.
When in this state, the SIE cannot process packets,
The USB Interrupt Status register (Register 23-7) con-
and therefore, cannot detect new interrupt conditions
tains the flag bits for each of the USB status interrupt
other than the Activity Detect Interrupt, ACTVIF. The
sources. Each of these sources has a corresponding
ACTVIF bit is typically used by USB firmware to detect
interrupt enable bit in the UIE register. All of the USB
when the microcontroller should bring the USB module
status flags are ORed together to generate the USBIF
out of the Low-Power Suspend mode (UCON<1> = 0).
interrupt flag for the microcontroller’s interrupt funnel.
Once an interrupt bit has been set by the SIE, it must
be cleared in software by writing a ‘0’. The flag bits can
also be set in software, which can aid in firmware
debugging.

REGISTER 23-7: UIR: USB INTERRUPT STATUS REGISTER (ACCESS F62h)

U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R/W-0
— SOFIF STALLIF IDLEIF(1) TRNIF(2) ACTVIF(3) UERRIF(4) URSTIF
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 Unimplemented: Read as ‘0’

bit 6 SOFIF: Start-Of-Frame Token Interrupt bit
1 = A Start-Of-Frame token is received by the SIE
0 = No Start-Of-Frame token is received by the SIE
bit 5 STALLIF: A STALL Handshake Interrupt bit
1 = A STALL handshake was sent by the SIE
0 = A STALL handshake has not been sent
bit 4 IDLEIF: Idle Detect Interrupt bit(1)
1 = Idle condition is detected (constant Idle state of 3 ms or more)
0 = No Idle condition is detected
bit 3 TRNIF: Transaction Complete Interrupt bit(2)
1 = Processing of pending transaction is complete; read the USTAT register for endpoint information
0 = Processing of pending transaction is not complete or no transaction is pending
bit 2 ACTVIF: Bus Activity Detect Interrupt bit(3)
1 = Activity on the D+/D- lines was detected
0 = No activity detected on the D+/D- lines
bit 1 UERRIF: USB Error Condition Interrupt bit(4)
1 = An unmasked error condition has occurred
0 = No unmasked error condition has occurred.
bit 0 URSTIF: USB Reset Interrupt bit
1 = Valid USB Reset occurred; 00h is loaded into the UADDR register
0 = No USB Reset has occurred

Note 1: Once an Idle state is detected, the user may want to place the USB module in Suspend mode.
2: Clearing this bit will cause the USTAT FIFO to advance (valid only for IN, OUT and SETUP tokens).
3: This bit is typically unmasked only following the detection of a UIDLE interrupt event.
4: Only error conditions enabled through the UEIE register will set this bit. This bit is a status bit only and
cannot be set or cleared by the user.

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23.5.1.1 Bus Activity Detect Interrupt Bit may not be immediately operational while waiting for
(ACTVIF) the 96 MHz PLL to lock. The application code should
clear the ACTVIF flag as provided in Example 23-1.
The ACTVIF bit cannot be cleared immediately after
the USB module wakes up from Suspend mode or Note: Only one ACTVIF interrupt is generated
while the USB module is suspended. A few clock when resuming from the USB bus Idle con-
cycles are required to synchronize the internal hard- dition. If user firmware clears the ACTVIF
ware state machine before the ACTVIF bit can be bit, the bit will not immediately become set
cleared by firmware. Clearing the ACTVIF bit before again, even when there is continuous bus
the internal hardware is synchronized may not have an traffic. Bus traffic must cease long enough
effect on the value of ACTVIF. Additionally, if the USB to generate another IDLEIF condition
module uses the clock from the 96 MHz PLL source, before another ACTVIF interrupt can be
then after clearing the SUSPND bit, the USB module generated.

EXAMPLE 23-1: CLEARING ACTVIF BIT (UIR<2>)

Assembly:
BCF UCON, SUSPND
LOOP:
BTFSS UIR, ACTVIF
BRA DONE
BCF UIR, ACTVIF
BRA LOOP
DONE:

C:
UCONbits.SUSPND = 0;
while (UIRbits.ACTVIF) { UIRbits.ACTVIF = 0; }

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23.5.2 USB INTERRUPT ENABLE The values in this register only affect the propagation
REGISTER (UIE) of an interrupt condition to the microcontroller’s inter-
rupt logic. The flag bits are still set by their interrupt
The USB Interrupt Enable (UIE) register
conditions, allowing them to be polled and serviced
(Register 23-8) contains the enable bits for the USB
without actually generating an interrupt.
status interrupt sources. Setting any of these bits will
enable the respective interrupt source in the UIR
register.

REGISTER 23-8: UIE: USB INTERRUPT ENABLE REGISTER (BANKED F36h)

U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— SOFIE STALLIE IDLEIE TRNIE ACTVIE UERRIE URSTIE
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 Unimplemented: Read as ‘0’

bit 6 SOFIE: Start-Of-Frame Token Interrupt Enable bit
1 = Start-Of-Frame token interrupt is enabled
0 = Start-Of-Frame token interrupt is disabled
bit 5 STALLIE: STALL Handshake Interrupt Enable bit
1 = STALL interrupt is enabled
0 = STALL interrupt is disabled
bit 4 IDLEIE: Idle Detect Interrupt Enable bit
1 = Idle detect interrupt is enabled
0 = Idle detect interrupt is disabled
bit 3 TRNIE: Transaction Complete Interrupt Enable bit
1 = Transaction interrupt is enabled
0 = Transaction interrupt is disabled
bit 2 ACTVIE: Bus Activity Detect Interrupt Enable bit
1 = Bus activity detect interrupt is enabled
0 = Bus activity detect interrupt is disabled
bit 1 UERRIE: USB Error Interrupt Enable bit
1 = USB error interrupt is enabled
0 = USB error interrupt is disabled
bit 0 URSTIE: USB Reset Interrupt Enable bit
1 = USB Reset interrupt is enabled
0 = USB Reset interrupt is disabled

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23.5.3 USB ERROR INTERRUPT STATUS Each error bit is set as soon as the error condition is
REGISTER (UEIR) detected. Thus, the interrupt will typically not
correspond with the end of a token being processed.
The USB Error Interrupt Status register (Register 23-9)
contains the flag bits for each of the error sources Once an interrupt bit has been set by the SIE, it must
within the USB peripheral. Each of these sources is be cleared in software by writing a ‘0’.
controlled by a corresponding interrupt enable bit in
the UEIE register. All of the USB error flags are ORed
together to generate the USB Error Interrupt Flag
(UERRIF) at the top level of the interrupt logic.

REGISTER 23-9: UEIR: USB ERROR INTERRUPT STATUS REGISTER (ACCESS F63h)
R/C-0 U-0 U-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0
BTSEF — — BTOEF DFN8EF CRC16EF CRC5EF PIDEF
bit 7 bit 0

Legend:
R = Readable bit C = Clearable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 BTSEF: Bit Stuff Error Flag bit

1 = A bit stuff error has been detected
0 = No bit stuff error has been detected
bit 6-5 Unimplemented: Read as ‘0’
bit 4 BTOEF: Bus Turnaround Time-out Error Flag bit
1 = Bus turnaround time-out has occurred (more than 16 bit times of Idle from previous EOP elapsed)
0 = No bus turnaround time-out has occurred
bit 3 DFN8EF: Data Field Size Error Flag bit
1 = The data field was not an integral number of bytes
0 = The data field was an integral number of bytes
bit 2 CRC16EF: CRC16 Failure Flag bit
1 = The CRC16 failed
0 = The CRC16 passed
bit 1 CRC5EF: CRC5 Host Error Flag bit
1 = The token packet was rejected due to a CRC5 error
0 = The token packet was accepted
bit 0 PIDEF: PID Check Failure Flag bit
1 = PID check failed
0 = PID check passed

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23.5.4 USB ERROR INTERRUPT ENABLE As with the UIE register, the enable bits only affect the
REGISTER (UEIE) propagation of an interrupt condition to the micro-
controller’s interrupt logic. The flag bits are still set by
The USB Error Interrupt Enable register
their interrupt conditions, allowing them to be polled
(Register 23-10) contains the enable bits for each of
and serviced without actually generating an interrupt.
the USB error interrupt sources. Setting any of these
bits will enable the respective error interrupt source in
the UEIR register to propagate into the UERR bit at
the top level of the interrupt logic.

REGISTER 23-10: UEIE: USB ERROR INTERRUPT ENABLE REGISTER (BANKED F37h)
R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
BTSEE — — BTOEE DFN8EE CRC16EE CRC5EE PIDEE
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 BTSEE: Bit Stuff Error Interrupt Enable bit

1 = Bit stuff error interrupt is enabled
0 = Bit stuff error interrupt is disabled
bit 6-5 Unimplemented: Read as ‘0’
bit 4 BTOEE: Bus Turnaround Time-out Error Interrupt Enable bit
1 = Bus turnaround time-out error interrupt is enabled
0 = Bus turnaround time-out error interrupt is disabled
bit 3 DFN8EE: Data Field Size Error Interrupt Enable bit
1 = Data field size error interrupt is enabled
0 = Data field size error interrupt is disabled
bit 2 CRC16EE: CRC16 Failure Interrupt Enable bit
1 = CRC16 failure interrupt is enabled
0 = CRC16 failure interrupt is disabled
bit 1 CRC5EE: CRC5 Host Error Interrupt Enable bit
1 = CRC5 host error interrupt is enabled
0 = CRC5 host error interrupt is disabled
bit 0 PIDEE: PID Check Failure Interrupt Enable bit
1 = PID check failure interrupt is enabled
0 = PID check failure interrupt is disabled

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23.6 USB Power Modes The application should never source any current onto
Many USB applications will likely have several different the 5V VBUS pin of the USB cable.
sets of power requirements and configuration. The
most common power modes encountered are Bus FIGURE 23-10: SELF-POWER ONLY
Power Only, Self-Power Only and Dual Power with Attach Sense
Self-Power Dominance. The most common cases are VBUS 5.5V Tolerant
presented here. Also provided is a means of estimating ~5V I/O Pin
100 k
the current consumption of the USB transceiver. VSELF VDD
~3.3V
23.6.1 BUS POWER ONLY
In Bus Power Only mode, all power for the application 100 k VUSB
is drawn from the USB (Figure 23-9). This is effectively
the simplest power method for the device. VSS
In order to meet the inrush current requirements of the
USB 2.0 Specification, the total effective capacitance
appearing across VBUS and ground must be no more
than 10 µF. If not, some kind of inrush timing is
required. For more details, see Section 7.2.4 of the DIAGRAMS:OWER ONLY
USB 2.0 Specification.
23.6.3 DUAL POWER WITH SELF-POWER
According to the USB 2.0 Specification, all USB DOMINANCE
devices must also support a Low-Power Suspend
mode. In the USB Suspend mode, devices must Some applications may require a dual power option.
consume no more than 2.5 mA from the 5V VBUS line This allows the application to use internal power
of the USB cable. primarily, but switch to power from the USB when no
internal power is available. See Figure 23-11 for a
The host signals the USB device to enter the Suspend
simple Dual Power with Self-Power Dominance mode
mode by stopping all USB traffic to that device for more
example, which automatically switches between
than 3 ms. This condition will cause the IDLEIF bit in
Self-Power Only and USB Bus Power Only modes.
the UIR register to become set.
Dual power devices must also meet all of the special
During the USB Suspend mode, the D+ or D- pull-up
requirements for inrush current and Suspend mode
resistor must remain active, which will consume some
current, and must not enable the USB module until
of the allowed suspend current: 2.5 mA budget.
VBUS is driven high. See Section 23.6.1 “Bus Power
Only” and Section 23.6.2 “Self-Power Only” for
FIGURE 23-9: BUS POWER ONLY descriptions of those requirements. Additionally, dual
power devices must never source current onto the 5V
Low IQ Regulator
VBUS pin of the USB cable.
VBUS 3.3V
VDD
~5V
FIGURE 23-11: DUAL POWER EXAMPLE
100 k Attach Sense
VUSB Low IQ I/O Pin
Regulator
VSS 3.3V
VBUS VDD
~5V

100 k VUSB

23.6.2 SELF-POWER ONLY VSELF VSS

~3.3V
In Self-Power Only mode, the USB application provides
its own power, with very little power being pulled from
the USB. See Figure 23-10 for an example.
Note that an attach indication is added to indicate when
the USB has been connected and the host is actively Note: Users should keep in mind the limits for
powering VBUS. devices drawing power from the USB.
According to USB Specification 2.0, this
In order to meet compliance specifications, the USB
cannot exceed 100 mA per low-power
module (and the D+ or D- pull-up resistor) should not
device or 500 mA per high-power device.
be enabled until the host actively drives VBUS high.
One of the 5.5V tolerant I/O pins may be used for this
purpose.

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23.6.4 USB TRANSCEIVER CURRENT bits do not cause the output state of the transceiver to
CONSUMPTION change. Therefore, IN traffic consisting of data bits of
value, ‘0’, cause the most current consumption, as the
The USB transceiver consumes a variable amount of
transceiver must charge/discharge the USB cable in
current depending on the characteristic impedance of
order to change states.
the USB cable, the length of the cable, the VUSB supply
voltage and the actual data patterns moving across the More details about NRZI encoding and bit stuffing can
USB cable. Longer cables have larger capacitances be found in the USB 2.0 Specification’s Section 7.1,
and consume more total energy when switching output although knowledge of such details is not required to
states. make USB applications using the PIC18F47J53 family
of microcontrollers. Among other things, the SIE handles
Data patterns that consist of “IN” traffic consume far
bit stuffing/unstuffing, NRZI encoding/decoding and
more current than “OUT” traffic. IN traffic requires the
CRC generation/checking in hardware.
PIC® MCU to drive the USB cable, whereas OUT traffic
requires that the host drive the USB cable. The total transceiver current consumption will be
application-specific. However, to help estimate how
The data that is sent across the USB cable is NRZI
much current actually may be required in full-speed
encoded. In the NRZI encoding scheme, ‘0’ bits cause
applications, Equation 23-1 can be used.
a toggling of the output state of the transceiver (either
from a “J” state to a “K” state or vise versa). With the See Equation 23-2 to know how this equation can be
exception of the effects of bit stuffing, NRZI encoded ‘1’ used for a theoretical application.

EQUATION 23-1: ESTIMATING USB TRANSCEIVER CURRENT CONSUMPTION

(40 mA • VUSB • PZERO • PIN • LCABLE)
IXCVR = + IPULLUP
(3.3V • 5m)

Legend: VUSB – Voltage applied to the VUSB pin in volts (should be 3.0V to 3.6V).
PZERO – Percentage (in decimal) of the IN traffic bits sent by the PIC® MCU that are a value of ‘0’.
PIN – Percentage (in decimal) of total bus bandwidth that is used for IN traffic.
LCABLE – Length (in meters) of the USB cable. The USB 2.0 Specification requires that full-speed
applications use cables no longer than 5m.
IPULLUP – Current which the nominal, 1.5 k pull-up resistor (when enabled) must supply to the USB
cable. On the host or hub end of the USB cable, 15 k nominal resistors (14.25 k to 24.8 k) are
present which pull both the D+ and D- lines to ground. During bus Idle conditions (such as between
packets or during USB Suspend mode), this results in up to 218 A of quiescent current drawn at 3.3V.
IPULLUP is also dependant on bus traffic conditions and can be as high as 2.2 mA when the USB bandwidth
is fully utilized (either IN or OUT traffic) for data that drives the lines to the “K” state most of the time.

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EQUATION 23-2: CALCULATING USB TRANSCEIVER CURRENT†
For this example, the following assumptions are made about the application:
• 3.3V will be applied to VUSB and VDD, with the core voltage regulator enabled.
• This is a full-speed application that uses one interrupt IN endpoint that can send one packet of 64 bytes every
1 ms, with no restrictions on the values of the bytes being sent. The application may or may not have additional
traffic on OUT endpoints.
• A regular USB “B” or “mini-B” connector will be used on the application circuit board.
In this case, PZERO = 100% = 1, because there should be no restriction on the value of the data moving through the
IN endpoint. All 64 kbps of data could potentially be bytes of value, 00h. Since ‘0’ bits cause toggling of the output state
of the transceiver, they cause the USB transceiver to consume extra current charging/discharging the cable. In this
case, 100% of the data bits sent can be of value ‘0’. This should be considered the “max” value, as normal data will
consist of a fair mix of ones and zeros.
This application uses 64 kbps for IN traffic out of the total bus bandwidth of 1.5 Mbps (12 Mbps), therefore:
64 kbps
Pin = = 4.3% = 0.043
1.5 Mbps
Since a regular “B” or “mini-B” connector is used in this application, the end user may plug in any type of cable up to
the maximum allowed 5m length. Therefore, we use the worst-case length:
LCABLE = 5 meters
Assume IPULLUP = 2.2 mA. The actual value of IPULLUP will likely be closer to 218 A, but allowance for the worst-case.
USB bandwidth is shared between all the devices which are plugged into the root port (via hubs). If the application is
plugged into a USB 1.1 hub that has other devices plugged into it, your device may see host to device traffic on the
bus, even if it is not addressed to your device. Since any traffic, regardless of source, can increase the IPULLUP current
above the base 218 A, it is safest to allow for the worst-case of 2.2 mA.
Therefore:
(40 mA • 3.3V • 1 • 0.043 • 5m)
IXCVR = + 2.2 mA = 3.9 mA
(3.3V • 5m)
† The calculated value should be considered an approximation and additional guardband or
application-specific product testing is recommended. The transceiver current is “in addition to” the
rest of the current consumed by the PIC18F47J53 family device that is needed to run the core,
drive the other I/O lines, power the various modules, etc.

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23.7 Oscillator 23.8 USB Firmware and Drivers
The USB module has specific clock requirements. For Microchip provides a number of application-specific
full-speed operation, the clock source must be 48 MHz. resources, such as USB firmware and driver support.
Even so, the microcontroller core and other peripherals Refer to www.microchip.com for the latest firmware and
are not required to run at that clock speed. Available driver support.
clocking options are described in detail in Section 3.3
“Oscillator Settings for USB”.

TABLE 23-4: REGISTERS ASSOCIATED WITH USB MODULE OPERATION(1)

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF

IPR2 OSCFIP CM2IP CM1IP USBIP BCL1IP HLVDIP TMR3IP CCP2IP
PIR2 OSCFIF CM2IF CM1IF USBIF BCL1IF HLVDIF TMR3IF CCP2IF
PIE2 OSCFIE CM2IE CM1IE USBIE BCL1IE HLVDIE TMR3IE CCP2IE
UCON — PPBRST SE0 PKTDIS USBEN RESUME SUSPND —
UCFG UTEYE UOEMON — UPUEN UTRDIS FSEN PPB1 PPB0
USTAT — ENDP3 ENDP2 ENDP1 ENDP0 DIR PPBI —
UADDR — ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0
UFRML FRM7 FRM6 FRM5 FRM4 FRM3 FRM2 FRM1 FRM0
UFRMH — — — — — FRM10 FRM9 FRM8
UIR — SOFIF STALLIF IDLEIF TRNIF ACTVIF UERRIF URSTIF
UIE — SOFIE STALLIE IDLEIE TRNIE ACTVIE UERRIE URSTIE
UEIR BTSEF — — BTOEF DFN8EF CRC16EF CRC5EF PIDEF
UEIE BTSEE — — BTOEE DFN8EE CRC16EE CRC5EE PIDEE
UEP0 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL
UEP1 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL
UEP2 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL
UEP3 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL
UEP4 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL
UEP5 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL
UEP6 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL
UEP7 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL
UEP8 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL
UEP9 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL
UEP10 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL
UEP11 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL
UEP12 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL
UEP13 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL
UEP14 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL
UEP15 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the USB module.
Note 1: This table includes only those hardware mapped SFRs located in Bank 15 of the data memory space. The Buffer
Descriptor registers, which are mapped into Bank 4 and are not true SFRs, are listed separately in Table 23-3.

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23.9 Overview of USB 23.9.2 FRAMES
This section presents some of the basic USB concepts Information communicated on the bus is grouped into
and useful information necessary to design a USB 1 ms time slots, referred to as frames. Each frame can
device. Although much information is provided in this contain many transactions to various devices and
section, there is a plethora of information provided endpoints. See Figure 23-8 for an example of a
within the USB specifications and class specifications. transaction within a frame.
Thus, the reader is encouraged to refer to the USB
specifications for more information (www.usb.org). If 23.9.3 TRANSFERS
you are very familiar with the details of USB, then this There are four transfer types defined in the USB
section serves as a basic, high-level refresher of USB. specification.
• Isochronous: This type provides a transfer
23.9.1 LAYERED FRAMEWORK
method for large amounts of data (up to
USB device functionality is structured into a layered 1023 bytes) with timely delivery ensured;
framework, graphically illustrated in Figure 23-12. however, the data integrity is not ensured. This is
Each level is associated with a functional level within good for streaming applications where small data
the device. The highest layer, other than the device, is loss is not critical, such as audio.
the configuration. A device may have multiple configu- • Bulk: This type of transfer method allows for large
rations. For example, a particular device may have amounts of data to be transferred with ensured
multiple power requirements based on Self-Power Only data integrity; however, the delivery timeliness is
or Bus Power Only modes. not ensured.
For each configuration, there may be multiple • Interrupt: This type of transfer provides for
interfaces. Each interface could support a particular ensured timely delivery for small blocks of data,
mode of that configuration. plus data integrity is ensured.
Below the interface is the endpoint(s). Data is directly • Control: This type provides for device setup
moved at this level. There can be as many as control.
16 bidirectional endpoints. Endpoint 0 is always a While full-speed devices support all transfer types,
control endpoint, and by default, when the device is on low-speed devices are limited to interrupt and control
the bus, Endpoint 0 must be available to configure the transfers only.
device.
23.9.4 POWER
Power is available from the USB. The USB specifica-
tion defines the bus power requirements. Devices may
either be self-powered or bus-powered. Self-powered
devices draw power from an external source, while
bus-powered devices use power supplied from the bus.

FIGURE 23-12: USB LAYERS

Device

To Other Configurations (if any)

Configuration

To Other Interfaces (if any)

Interface Interface

Endpoint Endpoint Endpoint Endpoint Endpoint

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The USB Specification limits the power taken from the 23.9.6.2 Configuration Descriptor
bus. Each device is ensured 100 mA at approximately
The configuration descriptor provides information on
5V (one unit load). Additional power may be requested,
the power requirements of the device and how many
up to a maximum of 500 mA.
different interfaces are supported when in this configu-
Note that power above one unit load is a request and ration. There may be more than one configuration for a
the host or hub is not obligated to provide the extra cur- device (i.e., low-power and high-power configurations).
rent. Thus, a device capable of consuming more than
one unit load must be able to maintain a low-power 23.9.6.3 Interface Descriptor
configuration of a one unit load or less, if necessary. The interface descriptor details the number of end-
The USB Specification also defines a Suspend mode. points used in this interface, as well as the class of the
In this situation, current must be limited to 500 A, interface. There may be more than one interface for a
averaged over one second. A device must enter a configuration.
suspend state after 3 ms of inactivity (i.e., no SOF
tokens for 3 ms). A device entering Suspend mode 23.9.6.4 Endpoint Descriptor
must drop current consumption within 10 ms after The endpoint descriptor identifies the transfer type
suspend. Likewise, when signaling a wake-up, the (Section 23.9.3 “Transfers”) and direction, and some
device must signal a wake-up within 10 ms of drawing other specifics for the endpoint. There may be many
current above the suspend limit. endpoints in a device and endpoints may be shared in
different configurations.
23.9.5 ENUMERATION
When the device is initially attached to the bus, the host 23.9.6.5 String Descriptor
enters an enumeration process in an attempt to identify Many of the previous descriptors reference one or
the device. Essentially, the host interrogates the device, more string descriptors. String descriptors provide
gathering information, such as power consumption, data human readable information about the layer
rates and sizes, protocol and other descriptive (Section 23.9.1 “Layered Framework”) they
information; descriptors contain this information. A describe. Often these strings show up in the host to
typical enumeration process would be as follows: help the user identify the device. String descriptors are
1. USB Reset – Reset the device. Thus, the device generally optional to save memory and are encoded in
is not configured and does not have an address a unicode format.
(address 0).
2. Get Device Descriptor – The host requests a 23.9.7 BUS SPEED
small portion of the device descriptor. Each USB device must indicate its bus presence and
3. USB Reset – Reset the device again. speed to the host. This is accomplished through a
4. Set Address – The host assigns an address to 1.5 k resistor, which is connected to the bus at the
the device. time of the attachment event.
5. Get Device Descriptor – The host retrieves the Depending on the speed of the device, the resistor
device descriptor, gathering info, such as either pulls up the D+ or D- line to 3.3V. For a
manufacturer, type of device, maximum control low-speed device, the pull-up resistor is connected to
packet size. the D- line. For a full-speed device, the pull-up resistor
6. Get configuration descriptors. is connected to the D+ line.
7. Get any other descriptors. 23.9.8 CLASS SPECIFICATIONS AND
8. Set a configuration. DRIVERS
The exact enumeration process depends on the host. USB specifications include class specifications, which
operating system vendors optionally support.
23.9.6 DESCRIPTORS Examples of classes include Audio, Mass Storage,
There are eight different standard descriptor types, of Communications and Human Interface (HID). In most
which, five are most important for this device. cases, a driver is required at the host side to ‘talk’ to the
USB device. In custom applications, a driver may need
23.9.6.1 Device Descriptor to be developed. Fortunately, drivers are available for
The device descriptor provides general information, most common host systems for the most common
such as manufacturer, product number, serial number, classes of devices. Thus, these drivers can be reused.
the class of the device and the number of configurations.
There is only one device descriptor.

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24.0 COMPARATOR MODULE 24.1 Registers
The analog comparator module contains three compar- The CMxCON registers (Register 24-1) select the input
ators that can be independently configured in a variety of and output configuration for each comparator, as well
ways. The inputs can be selected from the analog inputs as the settings for interrupt generation.
and two internal voltage references. The digital outputs The CMSTAT register (Register 24-2) provides the out-
are available at the pin level and can also be read put results of the comparators. The bits in this register
through the control register. Multiple output and interrupt are read-only.
event generation is also available. Figure 24-1 provides
a generic single comparator from the module.
Key features of the module are:
• Independent comparator control
• Programmable input configuration
• Output to both pin and register levels
• Programmable output polarity
• Independent interrupt generation for each
comparator with configurable interrupt-on-change

FIGURE 24-1: COMPARATOR SIMPLIFIED BLOCK DIAGRAM

CCH<1:0> COUTx
(CMSTAT<2:0>)

CxINB 0

VIRV 3
Interrupt
CMxIF
CxINC 1 Logic

CxIND 2
EVPOL<1:0>
CREF COE
VIN- CxOUT
Polarity
CxINA 0 VIN+ Cx Logic
CVREF 1

CON CPOL

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REGISTER 24-1: CMxCON: COMPARATOR CONTROL 1/2/3 REGISTER (1, ACCESS FD2h; 2, FD1h;
3, BANKED F25h)
R/W-0 R/W-0 R/W-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
CON COE CPOL EVPOL1 EVPOL0 CREF CCH1 CCH0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 CON: Comparator Enable bit

1 = Comparator is enabled
0 = Comparator is disabled
bit 6 COE: Comparator Output Enable bit
1 = Comparator output is present on the CxOUT pin (assigned in the PPS module)
0 = Comparator output is internal only
bit 5 CPOL: Comparator Output Polarity Select bit
1 = Comparator output is inverted
0 = Comparator output is not inverted
bit 4-3 EVPOL<1:0>: Interrupt Polarity Select bits
11 = Interrupt generation on any change of the output(1)
10 = Interrupt generation only on high-to-low transition of the output
01 = Interrupt generation only on low-to-high transition of the output
00 = Interrupt generation is disabled
bit 2 CREF: Comparator Reference Select bit (non-inverting input)
1 = Non-inverting input connects to the internal CVREF voltage
0 = Non-inverting input connects to the CxINA pin
bit 1-0 CCH<1:0>: Comparator Channel Select bits
11 = Inverting input of comparator connects to VIRV (0.6V)
10 = Inverting input of comparator connects to the CxIND pin
01 = Inverting input of comparator connects to the CxINC pin
00 = Inverting input of comparator connects to the CxINB pin

Note 1: The CMxIF is automatically set any time this mode is selected and must be cleared by the application after
the initial configuration.

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REGISTER 24-2: CMSTAT: COMPARATOR STATUS REGISTER (ACCESS F70h)
U-0 U-0 U-0 U-0 U-0 R-1 R-1 R-1
— — — — — COUT3 COUT2 COUT1
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-3 Unimplemented: Read as ‘0’

bit 2-0 COUT<3:1>: Comparator x Status bits
(For example, COUT3 gives the status for Comparator 3.)
If CPOL (CMxCON<5>) = 0 non-inverted polarity):
1 = Comparator VIN+ > VIN-
0 = Comparator VIN+ < VIN-
If CPOL = 1 (inverted polarity):
1 = Comparator VIN+ < VIN-
0 = Comparator VIN+ > VIN-

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24.2 Comparator Operation 24.3 Comparator Response Time
A single comparator is shown in Figure 24-2, along with Response time is the minimum time, after selecting a
the relationship between the analog input levels and new reference voltage or input source, before the
the digital output. When the analog input at VIN+ is less comparator output has a valid level. The response time
than the analog input, VIN-, the output of the compara- of the comparator differs from the settling time of the
tor is a digital low level. When the analog input at VIN+ voltage reference. Therefore, both of these times must
is greater than the analog input, VIN-, the output of the be considered when determining the total response to
comparator is a digital high level. The shaded areas of a comparator input change. Otherwise, the maximum
the output of the comparator in Figure 24-2 represent delay of the comparators should be used (see
the uncertainty due to input offsets and response time. Section 31.0 “Electrical Characteristics”).

FIGURE 24-2: SINGLE COMPARATOR 24.4 Analog Input Connection

Considerations
VIN+ + Figure 24-3 provides a simplified circuit for an analog
Output
VIN- – input. Since the analog pins are connected to a digital
output, they have reverse biased diodes to VDD and
VSS. The analog input, therefore, must be between VSS
and VDD. If the input voltage deviates from this range
by more than 0.6V in either direction, one of the diodes
VIN- is forward biased and a latch-up condition may occur.
A maximum source impedance of 10 k is
VIN+ recommended for the analog sources. Any external
component connected to an analog input pin, such as
a capacitor or a Zener diode, should have very little
Output leakage current.

FIGURE 24-3: COMPARATOR ANALOG INPUT MODEL

VDD

VT = 0.6V RIC
RS < 10k
Comparator
AIN Input
CPIN ILEAKAGE
VA VT = 0.6V ±100 nA
5 pF

VSS

Legend: CPIN = Input Capacitance

VT = Threshold Voltage
ILEAKAGE = Leakage Current at the pin due to various junctions
RIC = Interconnect Resistance
RS = Source Impedance
VA = Analog Voltage

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24.5 Comparator Control and The external reference is used when CREF = 0
Configuration (CMxCON<2>) and VIN+ is connected to the CxINA
pin. When external voltage references are used, the
Each comparator has up to eight possible combina- comparator module can be configured to have the
tions of inputs: up to four external analog inputs and reference sources externally. The reference signal
one of two internal voltage references. must be between VSS and VDD, and can be applied to
Both comparators allow a selection of the signal from either pin of the comparator.
pin, CxINA, or the voltage from the comparator refer- The comparator module also allows the selection of an
ence (CVREF) on the non-inverting channel. This is internally generated voltage reference (CVREF) from
compared to either CxINB, CxINC, CxIND, CTMU or the comparator voltage reference module. This module
the microcontroller’s fixed internal reference voltage is described in more detail in Section 24.0 “Compara-
(VIRV, 0.6V nominal) on the inverting channel. tor Module”. The reference from the comparator
Table 24-1 provides the comparator inputs and outputs voltage reference module is only available when
tied to fixed I/O pins. CREF = 1. In this mode, the internal voltage reference
is applied to the comparator’s VIN+ pin.
TABLE 24-1: COMPARATOR INPUTS AND Note: The comparator input pin selected by
OUTPUTS CCH<1:0> must be configured as an input
by setting both the corresponding TRIS bits
Comparator Input or Output I/O Pin
and PCFG bits in the ANCON1 register.
C1INA (VIN+) RA0
C1INB (VIN-) RA3 24.5.2 COMPARATOR ENABLE AND
C1INC (VIN-) RA5 OUTPUT SELECTION
1
C1IND (VIN-) RA2 The comparator outputs are read through the CMSTAT
register. The CMSTAT<0> reads the Comparator 1 out-
Remapped
C1OUT put, CMSTAT<1> reads the Comparator 2 output and
RPn
CMSTAT<2> reads the Comparator 3 output. These
C2INA(VIN+) RA1 bits are read-only.
C2INB(VIN-) RA2 The comparator outputs may also be directly output to
C2INC (VIN-) RB2 the RPn I/O pins by setting the COE bit (CMxCON<6>).
2
C2IND (VIN-) RC2 When enabled, multiplexers in the output path of the
pins switch to the output of the comparator.
Remapped
C2OUT By default, the comparator’s output is at logic high
RPn
whenever the voltage on VIN+ is greater than on VIN-.
C3INA(VIN+) RB3
The polarity of the comparator outputs can be inverted
C3INB(VIN-) RA2 using the CPOL bit (CMxCON<5>).
C3INC (VIN-) RB1 The uncertainty of each of the comparators is related to
3
C3IND (VIN-) RB0 the input offset voltage and the response time given in
Remapped the specifications, as discussed in Section 24.2
C3OUT “Comparator Operation”.
RPn

24.5.1 COMPARATOR ENABLE AND

INPUT SELECTION
Setting the CON bit of the CMxCON register
(CMxCON<7>) enables the comparator for operation.
Clearing the CON bit disables the comparator,
minimizing current consumption.
The CCH<1:0> bits in the CMxCON register
(CMxCON<1:0>) direct either one of three analog input
pins, or the Internal Reference Voltage (VIRV), to the
comparator, VIN-. Depending on the comparator oper-
ating mode, either an external or internal voltage
reference may be used. The analog signal present at
VIN- is compared to the signal at VIN+ and the digital
output of the comparator is adjusted accordingly.

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24.6 Comparator Interrupts When EVPOL<1:0> = 11, the comparator interrupt flag
is set whenever there is a change in the output value of
The comparator interrupt flag is set whenever any of either comparator. Software will need to maintain
the following occurs: information about the status of the output bits, as read
• Low-to-high transition of the comparator output from CMSTAT<1:0>, to determine the actual change
• High-to-low transition of the comparator output that occurred. The CMxIF bits (PIR2<6:5>) are the
Comparator x Interrupt Flags. The CMxIF bits must be
• Any change in the comparator output
reset by clearing them. Since it is also possible to write
The comparator interrupt selection is done by the a ‘1’ to this register, a simulated interrupt may be
EVPOL<1:0> bits in the CMxCON register initiated.
(CMxCON<4:3>).
Table 24-2 provides the interrupt generation
In order to provide maximum flexibility, the output of the corresponding to comparator input voltages and
comparator may be inverted using the CPOL bit in the EVPOL bit settings.
CMxCON register (CMxCON<5>). This is functionally
Both the CMxIE bits (PIE2<6:5>) and the PEIE bit
identical to reversing the inverting and non-inverting
(INTCON<6>) must be set to enable the interrupt. In
inputs of the comparator for a particular mode.
addition, the GIE bit (INTCON<7>) must also be set.
An interrupt is generated on the low-to-high or high-to- If any of these bits are clear, the interrupt is not
low transition of the comparator output. This mode of enabled, though the CMxIF bits will still be set if an
interrupt generation is dependent on EVPOL<1:0> in interrupt condition occurs.
the CMxCON register. When EVPOL<1:0> = 01 or 10,
Figure 24-3 provides a simplified diagram of the
the interrupt is generated on a low-to-high or high-to-
interrupt section.
low transition of the comparator output. Once the
interrupt is generated, it is required to clear the interrupt
flag by software.

TABLE 24-2: COMPARATOR INTERRUPT GENERATION

Comparator Interrupt
CPOL EVPOL<1:0> COUTx Transition
Input Change Generated
VIN+ > VIN- Low-to-High No
00
VIN+ < VIN- High-to-Low No
VIN+ > VIN- Low-to-High Yes
01
VIN+ < VIN- High-to-Low No
0
VIN+ > VIN- Low-to-High No
10
VIN+ < VIN- High-to-Low Yes
VIN+ > VIN- Low-to-High Yes
11
VIN+ < VIN- High-to-Low Yes
VIN+ > VIN- High-to-Low No
00
VIN+ < VIN- Low-to-High No
VIN+ > VIN- High-to-Low No
01
VIN+ < VIN- Low-to-High Yes
1
VIN+ > VIN- High-to-Low Yes
10
VIN+ < VIN- Low-to-High No
VIN+ > VIN- High-to-Low Yes
11
VIN+ < VIN- Low-to-High Yes

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24.7 Comparator Operation During 24.8 Effects of a Reset
Sleep A device Reset forces the CMxCON registers to their
When a comparator is active and the device is placed Reset state. This forces both comparators and the
in Sleep mode, the comparator remains active and the voltage reference to the OFF state.
interrupt is functional, if enabled. This interrupt will
wake-up the device from Sleep mode when enabled.
Each operational comparator will consume additional
current. To minimize power consumption while in Sleep
mode, turn off the comparators (CON = 0) before
entering Sleep. If the device wakes up from Sleep, the
contents of the CMxCON register are not affected.

TABLE 24-3: REGISTERS ASSOCIATED WITH COMPARATOR MODULE

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF
PIR2 OSCFIF CM2IF CM1IF USBIF BCL1IF HLVDIF TMR3IF CCP2IF
PIR5 — — CM3IF TMR8IF TMR6IF TMR5IF TMR5GIF TMR1GIF
PIE2 OSCFIE CM2IE CM1IE USBIE BCL1IE HLVDIE TMR3IE CCP2IE
PIE5 — — CM3IE TMR8IE TMR6IE TMR5IE TMR5GIE TMR1GIE
IPR2 OSCFIP CM2IP CM1IP USBIP BCL1IP HLVDIP TMR3IP CCP2IP
IPR5 — — CM3IP TMR8IP TMR6IP TMR5IP TMR5GIP TMR1GIP
CMxCON CON COE CPOL EVPOL1 EVPOL0 CREF CCH1 CCH0
CVRCON CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0
CMSTAT — — — — — COUT3 COUT2 COUT1
ANCON0 PCFG7(Leg PCFG6(Leg- PCFG5(Le PCFG4 PCFG3 PCFG2 PCFG1 PCFG0
end:) end:) gend:)

ANCON1 VBGEN — — PCFG12 PCFG11 PCFG10 PCFG9 PCFG8

TRISA TRISA7 TRISA6 TRISA5 — TRISA3 TRISA2 TRISA1 TRISA0
Legend: — = unimplemented, read as ‘0’. Shaded cells are not related to comparator operation.

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25.0 COMPARATOR VOLTAGE Figure 25-1 provides a block diagram of the module.
The resistor ladder is segmented to provide two ranges
REFERENCE MODULE
of CVREF values and has a power-down function to
The comparator voltage reference is a 16-tap resistor conserve power when the reference is not being used.
ladder network that provides a selectable reference The module’s supply reference can be provided from
voltage. Although its primary purpose is to provide a either device VDD/VSS or an external voltage reference.
reference for the analog comparators, it may also be
used independently of them.

FIGURE 25-1: COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM

CVRSS = 1
VREF+

VDD
CVRSS = 0 8R
CVR<3:0>

CVREN R

16-to-1 MUX
16 Steps
CVREF

R
R

CVRR 8R
CVRSS = 1
VREF-

CVRSS = 0

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25.1 Configuring the Comparator The comparator reference supply voltage can come
Voltage Reference from either VDD and VSS, or the external VREF+ and
VREF- that are multiplexed with RA2 and RA3. The
The comparator voltage reference module is controlled voltage source is selected by the CVRSS bit
through the CVRCON register (Register 25-1). The (CVRCON<4>).
comparator voltage reference provides two ranges of
The settling time of the comparator voltage reference
output voltage, each with 16 distinct levels. The range
must be considered when changing the CVREF
to be used is selected by the CVRR bit (CVRCON<5>).
output (see Table 31-2 in Section 31.0 “Electrical
The primary difference between the ranges is the size
Characteristics”).
of the steps selected by the CVREF Selection bits
(CVR<3:0>), with one range offering finer resolution.
The equations used to calculate the output of the
comparator voltage reference are as follows:

EQUATION 25-1: CALCULATING OUTPUT

OF THE COMPARATOR
VOLTAGE REFERENCE
When CVRR = 1 and CVRSS = 0:
CVREF = ((CVR<3:0>)/24) x (CVRSRC)
When CVRR = 0 and CVRSS = 0:
CVREF = (CVRSRC/4) + ((CVR<3:0>)/32) x (CVRSRC)
When CVRR = 1 and CVRSS = 1:
CVREF = ((CVR<3:0>)/24) x (CVRSRC) + VREF-
When CVRR = 0 and CVRSS = 1:
CVREF = (CVRSRC/4) + ((CVR<3:0>)/32) x (CVRSRC) +VREF-)

REGISTER 25-1: CVRCON: COMPARATOR VOLTAGE REFERENCE CONTROL REGISTER (F53h)

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CVREN CVROE(1) CVRR CVRSS CVR3 CVR2 CVR1 CVR0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 CVREN: Comparator Voltage Reference Enable bit

1 = CVREF circuit is powered on
0 = CVREF circuit is powered down
bit 6 CVROE: Comparator VREF Output Enable bit(1)
1 = CVREF voltage level is also output on the RA2/AN2//C2INB/C1IND/C3INB/VREF-/CVREF pin
0 = CVREF voltage is disconnected from the RA2/AN2//C2INB/C1IND/C3INB/VREF-/CVREF pin
bit 5 CVRR: Comparator VREF Range Selection bit
1 = 0 to 0.667 CVRSRC with CVRSRC/24 step size (low range)
0 = 0.25 CVRSRC to 0.75 CVRSRC with CVRSRC/32 step size (high range)
bit 4 CVRSS: Comparator VREF Source Selection bit
1 = Comparator reference source, CVRSRC = (VREF+) – (VREF-)
0 = Comparator reference source, CVRSRC = AVDD – AVSS
bit 3-0 CVR<3:0>: Comparator VREF Value Selection bits (0  (CVR<3:0>)  15)
When CVRR = 1:
CVREF = ((CVR<3:0>)/24)  (CVRSRC)
When CVRR = 0:
CVREF = (CVRSRC/4) + ((CVR<3:0>)/32)  (CVRSRC)

Note 1: CVROE overrides the TRIS bit setting.

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25.2 Voltage Reference Accuracy/Error The RA2 pin can be used as a simple D/A output with
limited drive capability. Due to the limited current drive
The full range of voltage reference cannot be realized capability, a buffer must be used on the voltage
due to the construction of the module. The transistors reference output for external connections to VREF. See
on the top and bottom of the resistor ladder network Figure 25-2 for an example buffering technique.
(see Figure 25-1) keep CVREF from approaching the
reference source rails. The voltage reference is derived
25.4 Operation During Sleep
from the reference source; therefore, the CVREF output
changes with fluctuations in that source. The tested When the device wakes up from Sleep through an
absolute accuracy of the voltage reference can be interrupt or a Watchdog Timer time-out, the contents of
found in Section 31.0 “Electrical Characteristics”. the CVRCON register are not affected. To minimize
current consumption in Sleep mode, the voltage
25.3 Connection Considerations reference should be disabled.

The voltage reference module operates independently

25.5 Effects of a Reset
of the comparator module. The output of the reference
generator may be connected to the RA2 pin if the A device Reset disables the voltage reference by
CVROE bit is set. Enabling the voltage reference out- clearing bit, CVREN (CVRCON<7>). This Reset also
put onto RA2 when it is configured as a digital input will disconnects the reference from the RA2 pin by clearing
increase current consumption. Connecting RA2 as a bit, CVROE (CVRCON<6>) and selects the high-voltage
digital output with CVRSS enabled will also increase range by clearing bit, CVRR (CVRCON<5>). The CVR
current consumption. value select bits are also cleared.

FIGURE 25-2: COMPARATOR VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE

PIC18F47J53

CVREF
R(1)
Module
+
Voltage RA2 CVREF Output
–
Reference
Output
Impedance

Note 1: R is dependent upon the Comparator Voltage Reference Configuration bits, CVRCON<5> and CVRCON<3:0>.

TABLE 25-1: REGISTERS ASSOCIATED WITH COMPARATOR VOLTAGE REFERENCE

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
CVRCON CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0
CM1CON CON COE CPOL EVPOL1 EVPOL0 CREF CCH1 CCH0
CM2CON CON COE CPOL EVPOL1 EVPOL0 CREF CCH1 CCH0
CM3CON CON COE CPOL EVPOL1 EVPOL0 CREF CCH1 CCH0
TRISA TRISA7 TRISA6 TRISA5 — TRISA3 TRISA2 TRISA1 TRISA0
ANCON0 PCFG7(1) PCFG6(1) PCFG5(1) PCFG4 PCFG3 PCFG2 PCFG1 PCFG0
Legend: — = unimplemented, read as ‘0’, r = reserved. Shaded cells are not used with the comparator voltage
reference.
Note 1: These bits are only available on 44-pin devices.

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26.0 HIGH/LOW VOLTAGE DETECT The High/Low-Voltage Detect Control register
(Register 26-1) completely controls the operation of the
(HLVD)
HLVD module. This allows the circuitry to be “turned
The High/Low-Voltage Detect (HLVD) module can be off” by the user under software control, which
used to monitor the absolute voltage on VDD or the minimizes the current consumption for the device.
HLVDIN pin. This is a programmable circuit that allows Figure 26-1 provides a block diagram for the HLVD
the user to specify both a device voltage trip point and module.
the direction of change from that point.
If the module detects an excursion past the trip point in
that direction, an interrupt flag is set. If the interrupt is
enabled, the program execution will branch to the inter-
rupt vector address and the software can then respond
to the interrupt.

REGISTER 26-1: HLVDCON: HIGH/LOW-VOLTAGE DETECT CONTROL REGISTER (ACCESS F85h)

R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
VDIRMAG BGVST IRVST HLVDEN HLVDL3(1) HLVDL2(1) HLVDL1(1) HLVDL0(1)
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 VDIRMAG: Voltage Direction Magnitude Select bit

1 = Event occurs when the voltage equals or exceeds the trip point (HLVDL<3:0>)
0 = Event occurs when the voltage equals or falls below the trip point (HLVDL<3:0>)
bit 6 BGVST: Band Gap Reference Voltages Stable Status Flag bit
1 = Indicates internal band gap voltage references is stable
0 = Indicates internal band gap voltage reference is not stable
bit 5 IRVST: Internal Reference Voltage Stable Flag bit
1 = Indicates that the voltage detect logic will generate the interrupt flag at the specified voltage range
0 = Indicates that the voltage detect logic will not generate the interrupt flag at the specified voltage
range and the HLVD interrupt should not be enabled
bit 4 HLVDEN: High/Low-Voltage Detect Power Enable bit
1 = HLVD is enabled
0 = HLVD is disabled
bit 3-0 HLVDL<3:0>: Voltage Detection Limit bits(1)
1111 = External analog input is used (input comes from the HLVDIN pin)
1110 = Maximum setting
.
.
.
0000 = Minimum setting

Note 1: See Table 31-8 in Section 31.0 “Electrical Characteristics” for specifications.

The module is enabled by setting the HLVDEN bit. The VDIRMAG bit determines the overall operation of
Each time the module is enabled, the circuitry requires the module. When VDIRMAG is cleared, the module
some time to stabilize. The IRVST bit is a read-only bit monitors for drops in VDD below a predetermined set
that indicates when the circuit is stable. The module point. When the bit is set, the module monitors for rises
can generate an interrupt only after the circuit is stable in VDD above the set point.
and IRVST is set.

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26.1 Operation The trip point voltage is software programmable to any
one of 16 values. The trip point is selected by
When the HLVD module is enabled, a comparator uses programming the HLVDL<3:0> bits (HLVDCON<3:0>).
an internally generated reference voltage as the set
point. The set point is compared with the trip point, Additionally, the HLVD module allows the user to
where each node in the resistor divider represents a supply the trip voltage to the module from an external
trip point voltage. The “trip point” voltage is the voltage source. This mode is enabled when bits, HLVDL<3:0>,
level at which the device detects a high or low-voltage are set to ‘1111’. In this state, the comparator input is
event, depending on the configuration of the module. multiplexed from the external input pin, HLVDIN. This
gives users flexibility because it allows them to
When the supply voltage is equal to the trip point, the configure the HLVD interrupt to occur at any voltage in
voltage tapped off of the resistor array is equal to the the valid operating range.
internal reference voltage generated by the voltage
reference module. The comparator then generates an
interrupt signal by setting the HLVDIF bit.

FIGURE 26-1: HLVD MODULE BLOCK DIAGRAM (WITH EXTERNAL INPUT)

Externally Generated
Trip Point
VDD

VDD
HLVDL<3:0> HLVDCON
Register

HLVDEN VDIRMAG
HLVDIN
16-to-1 MUX

Set
HLVDIF

Internal Voltage
Reference
1.2V Typical

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26.2 HLVD Setup 26.4 HLVD Start-up Time
To set up the HLVD module: The internal reference voltage of the HLVD module,
1. Disable the module by clearing the HLVDEN bit specified in electrical specification parameter D420
(HLVDCON<4>). (see Table 31-8 in Section 31.0 “Electrical Charac-
teristics”), may be used by other internal circuitry,
2. Write the value to the HLVDL<3:0> bits that
such as the Programmable Brown-out Reset (BOR).
select the desired HLVD trip point.
3. Set the VDIRMAG bit to detect one of the If the HLVD or other circuits using the voltage reference
following: are disabled to lower the device’s current consumption,
the reference voltage circuit will require time to become
• High voltage (VDIRMAG = 1)
stable before a low or high-voltage condition can be
• Low voltage (VDIRMAG = 0) reliably detected. This start-up time, TIRVST, is an
4. Enable the HLVD module by setting the interval that is independent of device clock speed. It is
HLVDEN bit. specified in electrical specification, parameter 36
5. Clear the HLVD Interrupt Flag, HLVDIF (Table 31-14).
(PIR2<2>), which may have been set from a The HLVD interrupt flag is not enabled until TIRVST has
previous interrupt. expired and a stable reference voltage is reached. For
6. If interrupts are desired, enable the HLVD inter- this reason, brief excursions beyond the set point may
rupt by setting the HLVDIE and GIE/GIEH bits not be detected during this interval. Refer to Figure 26-2
(PIE2<2> and INTCON<7>). or Figure 26-3.
An interrupt will not be generated until the
IRVST bit is set.

26.3 Current Consumption

When the module is enabled, the HLVD comparator
and voltage divider are enabled, and will consume
static current. The total current consumption, when
enabled, is specified in electrical specification
parameter, D022B (IHLVD) (Section 31.2 “DC Char-
acteristics: Power-Down and Supply Current
PIC18F47J53 Family (Industrial)”).
Depending on the application, the HLVD module does
not need to operate constantly. To decrease the current
requirements, the HLVD circuitry may only need to be
enabled for short periods where the voltage is checked.
After doing the check, the HLVD module may be
disabled.

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FIGURE 26-2: LOW-VOLTAGE DETECT OPERATION (VDIRMAG = 0)
CASE 1:
HLVDIF may not be set

VDD

VHLVD

HLVDIF

Enable HLVD

TIRVST
IRVST
HLVDIF cleared in software
Internal Reference is stable

CASE 2:

VDD
VHLVD

HLVDIF

Enable HLVD

TIRVST
IRVST
Internal Reference is stable
HLVDIF cleared in software

HLVDIF cleared in software,

HLVDIF remains set since HLVD condition still exists

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FIGURE 26-3: HIGH-VOLTAGE DETECT OPERATION (VDIRMAG = 1)
CASE 1:
HLVDIF may not be set

VHLVD
VDD

HLVDIF

Enable HLVD

IRVST TIRVST

HLVDIF cleared in software

Internal Reference is stable

CASE 2:

VHLVD
VDD

HLVDIF

Enable HLVD

IRVST TIRVST

Internal Reference is stable

HLVDIF cleared in software

HLVDIF cleared in software,

HLVDIF remains set since HLVD condition still exists

26.5 Applications FIGURE 26-4: TYPICAL HIGH/

LOW-VOLTAGE DETECT
In many applications, it is desirable to have the ability to
APPLICATION
detect a drop below, or rise above, a particular threshold.
For example, the HLVD module could be enabled
periodically to detect Universal Serial Bus (USB) attach
or detach.
For general battery applications, Figure 26-4 provides
VA
a possible voltage curve.
VB
Over time, the device voltage decreases. When the
Voltage

device voltage reaches voltage, VA, the HLVD logic

generates an interrupt at time, TA. The interrupt could
cause the execution of an ISR, which would allow the
application to perform “housekeeping tasks” and
perform a controlled shutdown before the device
voltage exits the valid operating range at TB.
The HLVD, thus, would give the application a time TA TB
window, represented by the difference between TA and Time
TB, to safely exit. Legend: VA = HLVD trip point
VB = Minimum valid device
operating voltage

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26.6 Operation During Sleep 26.7 Effects of a Reset
When enabled, the HLVD circuitry continues to operate A device Reset forces all registers to their Reset state.
during Sleep. If the device voltage crosses the trip This forces the HLVD module to be turned off.
point, the HLVDIF bit will be set and the device will
wake-up from Sleep. Device execution will continue
from the interrupt vector address if interrupts have
been globally enabled.

TABLE 26-1: REGISTERS ASSOCIATED WITH HIGH/LOW-VOLTAGE DETECT MODULE

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
HLVDCON VDIRMAG BGVST IRVST HLVDEN HLVDL3 HLVDL2 HLVDL1 HLVDL0
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF
PIR2 OSCFIF CM2IF CM1IF USBIF BCL1IF HLVDIF TMR3IF CCP2IF
PIE2 OSCFIE CM2IE CM1IE USBIE BCL1IE HLVDIE TMR3IE CCP2IE
IPR2 OSCFIP CM2IP CM1IP USBIP BCL1IP HLVDIP TMR3IP CCP2IP
Legend: — = unimplemented, read as ‘0’. Shaded cells are unused by the HLVD module.

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27.0 CHARGE TIME • Control of edge sequence
MEASUREMENT UNIT (CTMU) • Control of response to edges
• Time measurement resolution of 1 nanosecond
The Charge Time Measurement Unit (CTMU) is a
• High precision time measurement
flexible analog module that provides accurate differen-
tial time measurement between pulse sources, as well • Time delay of external or internal signal
as asynchronous pulse generation. By working with asynchronous to system clock
other on-chip analog modules, the CTMU can be used • Accurate current source suitable for capacitive
to precisely measure time, measure capacitance, measurement
measure relative changes in capacitance or generate The CTMU works in conjunction with the A/D Converter
output pulses with a specific time delay. The CTMU is to provide up to 13 channels for time or charge
ideal for interfacing with capacitive-based sensors. measurement, depending on the specific device and
The module includes the following key features: the number of A/D channels available. When config-
ured for time delay, the CTMU is connected to one of
• Up to 13 channels available for capacitive or time
the analog comparators. The level-sensitive input edge
measurement input
sources can be selected from four sources: two
• On-chip precision current source external inputs, Timer1 or Output Compare Module 1.
• Four-edge input trigger sources
Figure 27-1 provides a block diagram of the CTMU.
• Polarity control for each edge source

FIGURE 27-1: CTMU BLOCK DIAGRAM

CTMUCON

EDGEN CTMUICON
EDGSEQEN
ITRIM<5:0> TGEN
EDG1SELx
EDG1POL IRNG<1:0> IDISSEN
EDG2SELx EDG1STAT
EDG2POL EDG2STAT Current Source

CTED1 Edge
CTMU
Control Control
CTED2 Logic Current Logic
Control

Timer1
Pulse CTPLS
ECCP1 Generator
A/D Converter Comparator 2
Input

Comparator 2 Output

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27.1 CTMU Operation Current trim is provided by the ITRIM<5:0> bits
(CTMUICON<7:2>). These six bits allow trimming of
The CTMU works by using a fixed current source to the current source in steps of approximately 2% per
charge a circuit. The type of circuit depends on the type step. Note that half of the range adjusts the current
of measurement being made. In the case of charge source positively and the other half reduces the current
measurement, the current is fixed and the amount of source. A value of ‘000000’ is the neutral position (no
time the current is applied to the circuit is fixed. The change). A value of ‘100000’ is the maximum negative
amount of voltage read by the A/D is then a measure- adjustment (approximately -62%) and ‘011111’ is the
ment of the capacitance of the circuit. In the case of maximum positive adjustment (approximately +62%).
time measurement, the current, as well as the capaci-
tance of the circuit, is fixed. In this case, the voltage 27.1.3 EDGE SELECTION AND CONTROL
read by the A/D is then representative of the amount of
CTMU measurements are controlled by edge events
time elapsed from the time the current source starts
occurring on the module’s two input channels. Each
and stops charging the circuit.
channel, referred to as Edge 1 and Edge 2, can be con-
If the CTMU is being used as a time delay, both capaci- figured to receive input pulses from one of the edge
tance and current source are fixed, as well as the voltage input pins (CTED1 and CTED2), Timer1 or Output
supplied to the comparator circuit. The delay of a signal Compare Module 1. The input channels are level-
is determined by the amount of time it takes the voltage sensitive, responding to the instantaneous level on the
to charge to the comparator threshold voltage. channel rather than a transition between levels. The
inputs are selected using the EDG1SEL and EDG2SEL
27.1.1 THEORY OF OPERATION bit pairs (CTMUCONL<3:2 and 6:5>).
The operation of the CTMU is based on the following In addition to source, each channel can be configured for
equation for charge: event polarity using the EDGE2POL and EDGE1POL
dV bits (CTMUCONL<7,4>). The input channels can also
C = I  -------
dT be filtered for an edge event sequence (Edge 1 occur-
ring before Edge 2) by setting the EDGSEQEN bit
More simply, the amount of charge measured in (CTMUCONH<2>).
coulombs in a circuit is defined as current in amperes
(I) multiplied by the amount of time in seconds that the 27.1.4 EDGE STATUS
current flows (t). Charge is also defined as the
The CTMUCON register also contains two status bits:
capacitance in farads (C) multiplied by the voltage of
EDG2STAT and EDG1STAT (CTMUCONL<1:0>).
the circuit (V). It follows that:
Their primary function is to show if an edge response
I  t = C  V. has occurred on the corresponding channel. The
CTMU automatically sets a particular bit when an edge
The CTMU module provides a constant, known current response is detected on its channel. The level-sensitive
source. The A/D Converter is used to measure (V) in nature of the input channels also means that the status
the equation, leaving two unknowns: capacitance (C) bits become set immediately if the channel’s configura-
and time (t). The above equation can be used to calcu- tion is changed and is the same as the channel’s
late capacitance or time, by either the relationship current state.
using the known fixed capacitance of the circuit:
The module uses the edge status bits to control the cur-
t = C  V  I rent source output to external analog modules (such as
the A/D Converter). Current is only supplied to external
or by:
modules when only one (but not both) of the status bits
C = I  t  V is set, and shuts current off when both bits are either
set or cleared. This allows the CTMU to measure cur-
using a fixed time that the current source is applied to rent only during the interval between edges. After both
the circuit. status bits are set, it is necessary to clear them before
another measurement is taken. Both bits should be
27.1.2 CURRENT SOURCE
cleared simultaneously, if possible, to avoid re-enabling
At the heart of the CTMU is a precision current source, the CTMU current source.
designed to provide a constant reference for measure-
In addition to being set by the CTMU hardware, the
ments. The level of current is user-selectable across
edge status bits can also be set by software. This is
three ranges or a total of two orders of magnitude, with
also the user’s application to manually enable or
the ability to trim the output in ±2% increments
disable the current source. Setting either one (but not
(nominal). The current range is selected by the
both) of the bits enables the current source. Setting or
IRNG<1:0> bits (CTMUICON<1:0>), with a value of
clearing both bits at once disables the source.
‘00’ representing the lowest range.

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27.1.5 INTERRUPTS Depending on the type of measurement or pulse
generation being performed, one or more additional
The CTMU sets its interrupt flag (PIR3<2>) whenever
modules may also need to be initialized and configured
the current source is enabled, then disabled. An inter-
with the CTMU module:
rupt is generated only if the corresponding interrupt
enable bit (PIE3<2>) is also set. If edge sequencing is • Edge Source Generation: In addition to the
not enabled (i.e., Edge 1 must occur before Edge 2), it external edge input pins, both Timer1 and the
is necessary to monitor the edge status bits and Output Compare/PWM1 module can be used as
determine which edge occurred last and caused the edge sources for the CTMU.
interrupt. • Capacitance or Time Measurement: The CTMU
module uses the A/D Converter to measure the
27.2 CTMU Module Initialization voltage across a capacitor that is connected to one
of the analog input channels.
The following sequence is a general guideline used to
• Pulse Generation: When generating system
initialize the CTMU module:
clock, independent output pulses, the CTMU
1. Select the current source range using the IRNG module uses Comparator 2 and the associated
bits (CTMUICON<1:0>). comparator voltage reference.
2. Adjust the current source trim using the ITRIM
bits (CTMUICON<7:2>). 27.3 Calibrating the CTMU Module
3. Configure the edge input sources for Edge 1 and
The CTMU requires calibration for precise measure-
Edge 2 by setting the EDG1SEL and EDG2SEL
ments of capacitance and time, as well as for accurate
bits (CTMUCONL<3:2> and <6:5>).
time delay. If the application only requires measurement
4. Configure the input polarities for the edge inputs of a relative change in capacitance or time, calibration is
using the EDG1POL and EDG2POL bits usually not necessary. An example of this type of appli-
(CTMUCONL<7,4>). The default configuration cation would include a capacitive touch switch, in which
is for negative edge polarity (high-to-low the touch circuit has a baseline capacitance, and the
transitions). added capacitance of the human body changes the
5. Enable edge sequencing using the EDGSEQEN overall capacitance of a circuit.
bit (CTMUCONH<2>). By default, edge
If actual capacitance or time measurement is required,
sequencing is disabled.
two hardware calibrations must take place: the current
6. Select the operating mode (Measurement or source needs calibration to set it to a precise current,
Time Delay) with the TGEN bit. The default and the circuit being measured needs calibration to
mode is Time/Capacitance Measurement. measure and/or nullify all other capacitance other than
7. Discharge the connected circuit by setting the that to be measured.
IDISSEN bit (CTMUCONH<1>). After waiting a
sufficient time for the circuit to discharge, clear 27.3.1 CURRENT SOURCE CALIBRATION
IDISSEN.
The current source on board the CTMU module has a
8. Disable the module by clearing the CTMUEN bit range of ±60% nominal for each of three current
(CTMUCONH<7>). ranges. Therefore, for precise measurements, it is pos-
9. Enable the module by setting the CTMUEN bit. sible to measure and adjust this current source by
10. Clear the Edge Status bits: EDG2STAT and placing a high-precision resistor, RCAL, onto an unused
EDG1STAT (CTMUCONL<1:0>). analog channel. An example circuit is shown in
11. Enable both edge inputs by setting the EDGEN Figure 27-2. The current source measurement is
bit (CTMUCONH<3>). performed using the following steps:
1. Initialize the A/D Converter.
2. Initialize the CTMU.
3. Enable the current source by setting EDG1STAT
(CTMUCONL<0>).
4. Issue settling time delay.
5. Perform A/D conversion.
6. Calculate the present source current using
I = V/ RCAL, where RCAL is a high-precision
resistance and V is measured by performing an
A/D conversion.

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The CTMU current source may be trimmed with the A value of 70% of full-scale voltage is chosen to make
trim bits in CTMUICON using an iterative process to get sure that the A/D Converter was in a range that is well
an exact desired current. Alternatively, the nominal above the noise floor. Keep in mind that if an exact cur-
value without adjustment may be used; it may be rent is chosen that is to incorporate the trimming bits
stored by the software for use in all subsequent from CTMUICON, the resistor value of RCAL may need
capacitive or time measurements. to be adjusted accordingly. RCAL may also be adjusted
To calculate the value for RCAL, the nominal current to allow for available resistor values. RCAL should be of
must be chosen and then the resistance can be the highest precision available, keeping in mind the
calculated. For example, if the A/D Converter reference amount of precision needed for the circuit that the
voltage is 3.3V, use 70% of full scale or 2.31V as the CTMU will be used to measure. A recommended
desired approximate voltage to be read by the A/D minimum would be 0.1% tolerance.
Converter. If the range of the CTMU current source is The following examples show one typical method for
selected to be 0.55 A, the resistor value needed is cal- performing a CTMU current calibration. Example 27-1
culated as RCAL = 2.31V/0.55 A, for a value of 4.2 MΩ. demonstrates how to initialize the A/D Converter and
Similarly, if the current source is chosen to be 5.5 A, the CTMU. This routine is typical for applications using
RCAL would be 420,000Ω, and 42,000Ω if the current both modules. Example 27-2 demonstrates one
source is set to 55 A. method for the actual calibration routine.

FIGURE 27-2: CTMU CURRENT SOURCE

CALIBRATION CIRCUIT

PIC18F47J53
CTMU
Current Source

A/D Converter

ANx
A/D

RCAL MUX

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 PIC18F47J53 FAMILY
EXAMPLE 27-1: SETUP FOR CTMU CALIBRATION ROUTINES
#include <p18cxxx.h>
/**************************************************************************/
/*Setup CTMU *****************************************************************/
/**************************************************************************/
void setup(void)

{ //CTMUCON - CTMU Control register

CTMUCONH = 0x00; //make sure CTMU is disabled

CTMUCONL = 0x90;
//CTMU continues to run when emulator is stopped,CTMU continues
//to run in idle mode,Time Generation mode disabled, Edges are blocked
//No edge sequence order, Analog current source not grounded, trigger
//output disabled, Edge2 polarity = positive level, Edge2 source =
//source 0, Edge1 polarity = positive level, Edge1 source = source 0,

//CTMUICON - CTMU Current Control Register

CTMUICON = 0x01; //0.55uA, Nominal - No Adjustment

/**************************************************************************/
//Setup AD converter;
/**************************************************************************/

TRISA=0x04; //set channel 2 as an input

// Configured AN2 as an analog channel

// ANCON0
ANCON0 = 0XFB;
// ANCON1
ANCON1 = 0X1F;

// ADCON1
ADCON1bits.ADFM=1; // Resulst format 1= Right justified
ADCON1bits.ADCAL=0; // Normal A/D conversion operation
ADCON1bits.ACQT=1; // Acquition time 7 = 20TAD 2 = 4TAD 1=2TAD
ADCON1bits.ADCS=2; // Clock conversion bits 6= FOSC/64 2=FOSC/32

// ADCON0
ADCON0bits.VCFG0 =0; // Vref+ = AVdd
ADCON0bits.VCFG1 =0; // Vref- = AVss
ADCON0bits.CHS=2; // Select ADC channel

ADCON0bits.ADON=1; // Turn on ADC

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EXAMPLE 27-2: CURRENT CALIBRATION ROUTINE
#include "p18cxxx.h"

#define COUNT 500 //@ 8MHz = 125uS.

#define DELAY for(i=0;i<COUNT;i++)
#define RCAL .027 //R value is 4200000 (4.2M)
//scaled so that result is in
//1/100th of uA
#define ADSCALE 1023 //for unsigned conversion 10 sig bits
#define ADREF 3.3 //Vdd connected to A/D Vr+

int main(void)
{
int i;
int j = 0; //index for loop
unsigned int Vread = 0;
double VTot = 0;
float Vavg=0, Vcal=0, CTMUISrc = 0; //float values stored for calcs

//assume CTMU and A/D have been setup correctly

//see Example 25-1 for CTMU & A/D setup
setup();

CTMUCONHbits.CTMUEN = 1; //Enable the CTMU

CTMUCONLbits.EDG1STAT = 0; // Set Edge status bits to zero
CTMUCONLbits.EDG2STAT = 0;
for(j=0;j<10;j++)
{
CTMUCONHbits.IDISSEN = 1; //drain charge on the circuit
DELAY; //wait 125us
CTMUCONHbits.IDISSEN = 0; //end drain of circuit

CTMUCONLbits.EDG1STAT = 1; //Begin charging the circuit

//using CTMU current source
DELAY; //wait for 125us
CTMUCONLbits.EDG1STAT = 0; //Stop charging circuit

PIR1bits.ADIF = 0; //make sure A/D Int not set

ADCON0bits.GO=1; //and begin A/D conv.
while(!PIR1bits.ADIF); //Wait for A/D convert complete

Vread = ADRES; //Get the value from the A/D

PIR1bits.ADIF = 0; //Clear A/D Interrupt Flag
VTot += Vread; //Add the reading to the total
}

Vavg = (float)(VTot/10.000); //Average of 10 readings

Vcal = (float)(Vavg/ADSCALE*ADREF);
CTMUISrc = Vcal/RCAL; //CTMUISrc is in 1/100ths of uA

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27.3.2 CAPACITANCE CALIBRATION This measured value is then stored and used for
calculations of time measurement or subtracted for
There is a small amount of capacitance from the inter-
capacitance measurement. For calibration, it is
nal A/D Converter sample capacitor as well as stray
expected that the capacitance of CSTRAY + CAD is
capacitance from the circuit board traces and pads that
approximately known. CAD is approximately 4 pF.
affect the precision of capacitance measurements. A
measurement of the stray capacitance can be taken by An iterative process may need to be used to adjust the
making sure the desired capacitance to be measured time, t, that the circuit is charged to obtain a reasonable
has been removed. The measurement is then voltage reading from the A/D Converter. The value of t
performed using the following steps: may be determined by setting COFFSET to a theoretical
value, then solving for t. For example, if CSTRAY is
1. Initialize the A/D Converter and the CTMU.
theoretically calculated to be 11 pF, and V is expected
2. Set EDG1STAT (= 1). to be 70% of VDD or 2.31V, then t would be:
3. Wait for a fixed delay of time, t.
4. Clear EDG1STAT. (4 pF + 11 pF) • 2.31V/0.55 A
5. Perform an A/D conversion.
6. Calculate the stray and A/D sample capacitances: or 63 s.
C OFFSET = C STRAY + CAD =  I  t   V See Example 27-3 for a typical routine for CTMU
capacitance calibration.
where I is known from the current source measurement
step, t is a fixed delay and V is measured by performing
an A/D conversion.

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EXAMPLE 27-3: CAPACITANCE CALIBRATION ROUTINE
#include "p18cxxx.h"

#define COUNT 25 //@ 8MHz INTFRC = 62.5 us.

#define ETIME COUNT*2.5 //time in uS
#define DELAY for(i=0;i<COUNT;i++)
#define ADSCALE 1023 //for unsigned conversion 10 sig bits
#define ADREF 3.3 //Vdd connected to A/D Vr+
#define RCAL .027 //R value is 4200000 (4.2M)
//scaled so that result is in
//1/100th of uA

int main(void)
{
int i;
int j = 0; //index for loop
unsigned int Vread = 0;
float CTMUISrc, CTMUCap, Vavg, VTot, Vcal;

//assume CTMU and A/D have been setup correctly

//see Example 25-1 for CTMU & A/D setup
setup();

CTMUCONHbits.CTMUEN = 1; // Enable the CTMU

CTMUCONLbits.EDG1STAT = 0; // Set Edge status bits to zero
CTMUCONLbits.EDG2STAT = 0;
for(j=0;j<10;j++)
{
CTMUCONHbits.IDISSEN = 1; //drain charge on the circuit
DELAY; //wait 125us
CTMUCONHbits.IDISSEN = 0; //end drain of circuit

CTMUCONLbits.EDG1STAT = 1; //Begin charging the circuit

//using CTMU current source
DELAY; //wait for 125us
CTMUCONLbits.EDG1STAT = 0; //Stop charging circuit

PIR1bits.ADIF = 0; //make sure A/D Int not set

ADCON0bits.GO=1; //and begin A/D conv.
while(!PIR1bits.ADIF); //Wait for A/D convert complete

Vread = ADRES; //Get the value from the A/D

PIR1bits.ADIF = 0; //Clear A/D Interrupt Flag
VTot += Vread; //Add the reading to the total
}

Vavg = (float)(VTot/10.000); //Average of 10 readings

Vcal = (float)(Vavg/ADSCALE*ADREF);
CTMUISrc = Vcal/RCAL; //CTMUISrc is in 1/100ths of uA
CTMUCap = (CTMUISrc*ETIME/Vcal)/100;
}

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27.4 Measuring Capacitance with the 27.4.2 RELATIVE CHARGE
CTMU MEASUREMENT
There are two separate methods of measuring capaci- An application may not require precise capacitance
tance with the CTMU. The first is the absolute method, measurements. For example, when detecting a valid
in which the actual capacitance value is desired. The press of a capacitance-based switch, detecting a rela-
second is the relative method, in which the actual tive change of capacitance is of interest. In this type of
capacitance is not needed, rather an indication of a application, when the switch is open (or not touched),
change in capacitance is required. the total capacitance is the capacitance of the combina-
tion of the board traces, the A/D Converter, etc. A larger
27.4.1 ABSOLUTE CAPACITANCE voltage will be measured by the A/D Converter. When
MEASUREMENT the switch is closed (or is touched), the total
capacitance is larger due to the addition of the
For absolute capacitance measurements, both the capacitance of the human body to the above listed
current and capacitance calibration steps found in capacitances and a smaller voltage will be measured
Section 27.3 “Calibrating the CTMU Module” by the A/D Converter.
should be followed. Capacitance measurements are
then performed using the following steps: Detecting capacitance changes is easily accomplished
with the CTMU using these steps:
1. Initialize the A/D Converter.
1. Initialize the A/D Converter and the CTMU.
2. Initialize the CTMU.
2. Set EDG1STAT.
3. Set EDG1STAT.
3. Wait for a fixed delay.
4. Wait for a fixed delay, T.
4. Clear EDG1STAT.
5. Clear EDG1STAT.
5. Perform an A/D conversion.
6. Perform an A/D conversion.
7. Calculate the total capacitance, CTOTAL = (I * T)/V, The voltage measured by performing the A/D conver-
where I is known from the current source sion is an indication of the relative capacitance. Note
measurement step (see Section 27.3.1 “Current that in this case, no calibration of the current source or
Source Calibration”), T is a fixed delay and V is circuit capacitance measurement is needed. See
measured by performing an A/D conversion. Example 27-4 for a sample software routine for a
capacitive touch switch.
8. Subtract the stray and A/D capacitance
(COFFSET from Section 27.3.2 “Capacitance
Calibration”) from CTOTAL to determine the
measured capacitance.

 2010 Microchip Technology Inc. Preliminary DS39964B-page 433

PIC18F47J53 FAMILY
EXAMPLE 27-4: ROUTINE FOR CAPACITIVE TOUCH SWITCH
#include "p18cxxx.h"

#define COUNT 500 //@ 8MHz = 125uS.

#define DELAY for(i=0;i<COUNT;i++)
#define OPENSW 1000 //Un-pressed switch value
#define TRIP 300 //Difference between pressed
//and un-pressed switch
#define HYST 65 //amount to change
//from pressed to un-pressed
#define PRESSED 1
#define UNPRESSED 0

int main(void)
{
unsigned int Vread; //storage for reading
unsigned int switchState;
int i;

//assume CTMU and A/D have been setup correctly

//see Example 25-1 for CTMU & A/D setup
setup();

CTMUCONHbits.CTMUEN = 1; // Enable the CTMU

CTMUCONLbits.EDG1STAT = 0; // Set Edge status bits to zero
CTMUCONLbits.EDG2STAT = 0;

CTMUCONHbits.IDISSEN = 1; //drain charge on the circuit

DELAY; //wait 125us
CTMUCONHbits.IDISSEN = 0; //end drain of circuit

CTMUCONLbits.EDG1STAT = 1; //Begin charging the circuit

//using CTMU current source
DELAY; //wait for 125us
CTMUCONLbits.EDG1STAT = 0; //Stop charging circuit

PIR1bits.ADIF = 0; //make sure A/D Int not set

ADCON0bits.GO=1; //and begin A/D conv.
while(!PIR1bits.ADIF); //Wait for A/D convert complete

Vread = ADRES; //Get the value from the A/D

if(Vread < OPENSW - TRIP)

{
switchState = PRESSED;
}
else if(Vread > OPENSW - TRIP + HYST)
{
switchState = UNPRESSED;
}
}

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27.5 Measuring Time with the CTMU It is assumed that the time measured is small enough
Module that the capacitance, COFFSET, provides a valid voltage
to the A/D Converter. For the smallest time measure-
Time can be precisely measured after the ratio (C/I) is ment, always set the A/D Channel Select register
measured from the current and capacitance calibration (AD1CHS) to an unused A/D channel; the correspond-
step by following these steps: ing pin for which is not connected to any circuit board
1. Initialize the A/D Converter and the CTMU. trace. This minimizes added stray capacitance,
keeping the total circuit capacitance close to that of the
2. Set EDG1STAT.
A/D Converter itself (4-5 pF). To measure longer time
3. Set EDG2STAT. intervals, an external capacitor may be connected to an
4. Perform an A/D conversion. A/D channel and this channel selected when making a
5. Calculate the time between edges as T = (C/I) * V, time measurement.
where I is calculated in the current calibration step
(Section 27.3.1 “Current Source Calibration”),
C is calculated in the capacitance calibration step
(Section 27.3.2 “Capacitance Calibration”) and
V is measured by performing the A/D conversion.

FIGURE 27-3: TYPICAL CONNECTIONS AND INTERNAL CONFIGURATION FOR TIME

MEASUREMENT
PIC18F47J53

CTMU
CTED1 EDG1
Current Source
CTED2 EDG2

Output Pulse

A/D Converter
ANX
CAD

RPR

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27.6 Creating a Delay with the CTMU An example use of this feature is for interfacing with
Module variable capacitive-based sensors, such as a humidity
sensor. As the humidity varies, the pulse width output
A unique feature on board the CTMU module is its on CTPLS will vary. The CTPLS output pin can be
ability to generate system clock, independent output connected to an input capture pin and the varying pulse
pulses based on an external capacitor value. This is width is measured to determine the humidity in the
accomplished using the internal comparator voltage application.
reference module, Comparator 2 input pin and an
Follow these steps to use this feature:
external capacitor. The pulse is output onto the CTPLS
pin. To enable this mode, set the TGEN bit. 1. Set the CPOL bit (CMxCON<5>).
See Figure 27-4 for an example circuit. CPULSE is 2. Initialize the comparator voltage reference.
chosen by the user to determine the output pulse width 3. Initialize the CTMU and enable time delay
on CTPLS. The pulse width is calculated by generation by setting the TGEN bit.
T = (CPULSE /I)*V, where I is known from the current 4. Set EDG1STAT.
source measurement step (Section 27.3.1 “Current 5. When CPULSE charges to the value of the voltage
Source Calibration”) and V is the internal reference reference trip point, an output pulse is generated
voltage (CVREF). on CTPLS.

FIGURE 27-4: TYPICAL CONNECTIONS AND INTERNAL CONFIGURATION FOR PULSE

DELAY GENERATION

PIC18F47J53

CTMU
CTED1 EDG1 CTPLS

Current Source

Comparator
C2INB
C2

CPULSE CVREF

27.7 Operation During Sleep/Idle case, if the module is performing an operation when
Modes Idle mode is invoked, the results will be similar to those
with Sleep mode.
27.7.1 SLEEP MODE AND DEEP SLEEP
MODES 27.8 Effects of a Reset on CTMU
When the device enters any Sleep mode, the CTMU Upon Reset, all registers of the CTMU are cleared. This
module current source is always disabled. If the CTMU leaves the CTMU module disabled; its current source is
is performing an operation that depends on the current turned off and all configuration options return to their
source when Sleep mode is invoked, the operation may default settings. The module needs to be re-initialized
not terminate correctly. Capacitance and time following any Reset.
measurements may return erroneous values.
If the CTMU is in the process of taking a measurement at
the time of Reset, the measurement will be lost. A partial
27.7.2 IDLE MODE
charge may exist on the circuit that was being measured,
The behavior of the CTMU in Idle mode is determined and should be properly discharged before the CTMU
by the CTMUSIDL bit (CTMUCONH<5>). If CTMUSIDL makes subsequent attempts to make a measurement.
is cleared, the module will continue to operate in Idle The circuit is discharged by setting and then clearing the
mode. If CTMUSIDL is set, the module’s current source IDISSEN bit (CTMUCONH<1>) while the A/D Converter
is disabled when the device enters Idle mode. In this is connected to the appropriate channel.

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27.9 Registers The CTMUCONH and CTMUCONL registers
(Register 27-1 and Register 27-2) contain control bits
There are three control registers for the CTMU: for configuring the CTMU module edge source selec-
• CTMUCONH tion, edge source polarity selection, edge sequencing,
• CTMUCONL A/D trigger, analog circuit capacitor discharge and
enables. The CTMUICON register (Register 27-3) has
• CTMUICON
bits for selecting the current source range and current
source trim.

REGISTER 27-1: CTMUCONH: CTMU CONTROL REGISTER HIGH (ACCESS FB3h)

R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CTMUEN — CTMUSIDL TGEN EDGEN EDGSEQEN IDISSEN CTTRIG
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 CTMUEN: CTMU Enable bit

1 = Module is enabled
0 = Module is disabled
bit 6 Unimplemented: Read as ‘0’
bit 5 CTMUSIDL: Stop in Idle Mode bit
1 = Discontinue module operation when device enters Idle mode
0 = Continue module operation in Idle mode
bit 4 TGEN: Time Generation Enable bit
1 = Enables edge delay generation
0 = Disables edge delay generation
bit 3 EDGEN: Edge Enable bit
1 = Edges are not blocked
0 = Edges are blocked
bit 2 EDGSEQEN: Edge Sequence Enable bit
1 = Edge 1 event must occur before Edge 2 event can occur
0 = No edge sequence is needed
bit 1 IDISSEN: Analog Current Source Control bit
1 = Analog current source output is grounded
0 = Analog current source output is not grounded
bit 0 CTTRIG: CTMU Special Event Trigger bit
1 = CTMU Special Event Trigger is enabled
0 = CTMU Special Event Trigger is disabled

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REGISTER 27-2: CTMUCONL: CTMU CONTROL REGISTER LOW (ACCESS FB2h)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x R/W-x
EDG2POL EDG2SEL1 EDG2SEL0 EDG1POL EDG1SEL1 EDG1SEL0 EDG2STAT EDG1STAT
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 EDG2POL: Edge 2 Polarity Select bit

1 = Edge 2 is programmed for a positive edge response
0 = Edge 2 is programmed for a negative edge response
bit 6-5 EDG2SEL<1:0>: Edge 2 Source Select bits
11 = CTED1 pin
10 = CTED2 pin
01 = ECCP1 output compare module
00 = Timer1 module
bit 4 EDG1POL: Edge 1 Polarity Select bit
1 = Edge 1 programmed for a positive edge response
0 = Edge 1 programmed for a negative edge response
bit 3-2 EDG1SEL<1:0>: Edge 1 Source Select bits
11 = CTED1 pin
10 = CTED2 pin
01 = ECCP1 output compare module
00 = Timer1 module
bit 1 EDG2STAT: Edge 2 Status bit
1 = Edge 2 event has occurred
0 = Edge 2 event has not occurred
bit 0 EDG1STAT: Edge 1 Status bit
1 = Edge 1 event has occurred
0 = Edge 1 event has not occurred

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REGISTER 27-3: CTMUICON: CTMU CURRENT CONTROL REGISTER (ACCESS FB1h)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
ITRIM5 ITRIM4 ITRIM3 ITRIM2 ITRIM1 ITRIM0 IRNG1 IRNG0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-2 ITRIM<5:0>: Current Source Trim bits

011111 = Maximum positive change from nominal current
011110
.
.
.
000001 = Minimum positive change from nominal current
000000 = Nominal current output specified by IRNG<1:0>
111111 = Minimum negative change from nominal current
.
.
.
100010
100001 = Maximum negative change from nominal current
bit 1-0 IRNG<1:0>: Current Source Range Select bits
11 = 100  Base current
10 = 10  Base current
01 = Base current level (0.55 A nominal)
00 = Current source disabled

TABLE 27-1: REGISTERS ASSOCIATED WITH CTMU MODULE

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

CTMUCONH CTMUEN — CTMUSIDL TGEN EDGEN EDGSEQEN IDISSEN CTTRIG

CTMUCONL EDG2POL EDG2SEL1 EDG2SEL0 EDG1POL EDG1SEL1 EDG1SEL0 EDG2STAT EDG1STAT
CTMUICON ITRIM5 ITRIM4 ITRIM3 ITRIM2 ITRIM1 ITRIM0 IRNG1 IRNG0
PIR3 SSP2IF BCL2IF RC2IF TX2IF TMR4IF CTMUIF TMR3GIF RTCCIF
PIE3 SSP2IE BCL2IE RC2IE TX2IE TMR4IE CTMUIE TMR3GIE RTCCIE
IPR3 SSP2IP BCL2IP RC2IP TX2IP TMR4IP CTMUIP TMR3GIP RTCCIP
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during CTMU module.

 2010 Microchip Technology Inc. Preliminary DS39964B-page 439

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NOTES:

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28.0 SPECIAL FEATURES OF THE 28.1.1 CONSIDERATIONS FOR
CPU CONFIGURING THE PIC18F47J53
FAMILY DEVICES
PIC18F47J53 family devices include several features
Unlike some previous PIC18 microcontrollers, devices
intended to maximize reliability and minimize cost
through elimination of external components. These are: of the PIC18F47J53 family do not use persistent mem-
ory registers to store configuration information. The
• Oscillator Selection Configuration registers, CONFIG1L through
• Resets: CONFIG4H, are implemented as volatile memory.
- Power-on Reset (POR) Immediately after power-up, or after a device Reset,
- Power-up Timer (PWRT) the microcontroller hardware automatically loads the
- Oscillator Start-up Timer (OST) CONFIG1L through CONFIG4L registers with configu-
- Brown-out Reset (BOR) ration data stored in nonvolatile Flash program
• Interrupts memory. The last four words of Flash program memory,
known as the Flash Configuration Words (FCW), are
• Watchdog Timer (WDT)
used to store the configuration data.
• Fail-Safe Clock Monitor (FSCM)
Table 28-1 provides the Flash program memory, which
• Two-Speed Start-up
will be loaded into the corresponding Configuration
• Code Protection register.
• In-Circuit Serial Programming (ICSP)
When creating applications for these devices, users
The oscillator can be configured for the application should always specifically allocate the location of the
depending on frequency, power, accuracy and cost. All FCW for configuration data. This is to make certain that
of the options are discussed in detail in Section 3.0 program code is not stored in this address when the
“Oscillator Configurations”. code is compiled.
A complete discussion of device Resets and interrupts The four Most Significant bits (MSb) of the FCW, corre-
is available in previous sections of this data sheet. In sponding to CONFIG1H, CONFIG2H, CONFIG3H and
addition to their Power-up and Oscillator Start-up CONFIG4H, should always be programmed to ‘1111’.
Timers provided for Resets, the PIC18F47J53 family of
This makes these FCWs appear to be NOP instructions
devices has a configurable Watchdog Timer (WDT),
in the remote event that their locations are ever
which is controlled in software.
executed by accident.
The inclusion of an internal RC oscillator also provides
The four MSbs of the CONFIG1H, CONFIG2H,
the additional benefits of a Fail-Safe Clock Monitor
CONFIG3H and CONFIG4H registers are not imple-
(FSCM) and Two-Speed Start-up. FSCM provides for
mented, so writing ‘1’s to their corresponding FCW has
background monitoring of the peripheral clock and
no effect on device operation.
automatic switchover in the event of its failure.
Two-Speed Start-up enables code to be executed To prevent inadvertent configuration changes during
almost immediately on start-up, while the primary clock code execution, the Configuration registers,
source completes its start-up delays. CONFIG1L through CONFIG4L, are loaded only once
All of these features are enabled and configured by per power-up or Reset cycle. User’s firmware can still
setting the appropriate Configuration register bits. change the configuration by using self-reprogramming
to modify the contents of the FCW.
28.1 Configuration Bits Modifying the FCW will not change the active contents
being used in the CONFIG1L through CONFIG4H
The Configuration bits can be programmed to select registers until after the device is reset.
various device configurations. The configuration data is
stored in the last four words of Flash program memory;
Figure 6-1 depicts this. The configuration data gets
loaded into the volatile Configuration registers,
CONFIG1L through CONFIG4H, which are readable
and mapped to program memory, starting at location
300000h.
Table 28-2 provides a complete list. A detailed explana-
tion of the various bit functions is provided in
Register 28-1 through Register 28-6.

 2010 Microchip Technology Inc. Preliminary DS39964B-page 441

PIC18F47J53 FAMILY
TABLE 28-1: MAPPING OF THE FLASH CONFIGURATION WORDS TO THE CONFIGURATION
REGISTERS
Configuration Register Configuration Register
Flash Configuration Byte Address
(Volatile) Address
CONFIG1L 300000h XXXF8h
CONFIG1H 300001h XXXF9h
CONFIG2L 300002h XXXFAh
CONFIG2H 300003h XXXFBh
CONFIG3L 300004h XXXFCh
CONFIG3H 300005h XXXFDh
CONFIG4L 300006h XXXFEh
CONFIG4H 300007h XXXFFh

TABLE 28-2: CONFIGURATION BITS AND DEVICE IDs

Default/
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Unprog.
Value(1)

300000h CONFIG1L DEBUG XINST STVREN CFGPLLEN PLLDIV2 PLLDIV1 PLLDIV0 WDTEN 1111 1111
300001h CONFIG1H —(2) —(2) —(2) —(2) — CP0 CPDIV1 CPDIV0 1111 -111
300002h CONFIG2L IESO FCMEN CLKOEC SOSCSEL1 SOSCSEL0 FOSC2 FOSC1 FOSC0 1111 1111
300003h CONFIG2H —(2) —(2) —(2) —(2) WDTPS3 WDTPS2 WDTPS1 WDTPS0 1111 1111
300004h CONFIG3L DSWDTPS3 DSWDTPS2 DSWDTPS1 DSWDTPS0 DSWDTEN DSBOREN RTCOSC DSWDTOSC 1111 1111
300005h CONFIG3H —(2) —(2) —(2) —(2) MSSPMSK — ADCSEL IOL1WAY 1111 1-11
300006h CONFIG4L WPCFG WPFP6 WPFP5 WPFP4 WPFP3 WPFP2 WPFP1 WPFP0 1111 1111
300007h CONFIG4H —(2) —(2) —(2) —(2) LS48MHZ — WPEND WPDIS 1111 1-11
3FFFFEh DEVID1 DEV2 DEV1 DEV0 REV4 REV3 REV2 REV1 REV0 xxx0 0000(3)
3FFFFFh DEVID2 DEV10 DEV9 DEV8 DEV7 DEV6 DEV5 DEV4 DEV3 0100 00xx(3)
Legend: x = unknown, u = unchanged, - = unimplemented. Shaded cells are unimplemented, read as ‘0’.
Note 1: Values reflect the unprogrammed state as received from the factory and following Power-on Resets. In all other Reset states, the
configuration bytes maintain their previously programmed states.
2: The value of these bits in program memory should always be programmed to ‘1’. This ensures that the location is executed as a NOP if it
is accidentally executed.
3: See Register 28-9 and Register 28-10 for DEVID values. These registers are read-only and cannot be programmed by the user.

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REGISTER 28-1: CONFIG1L: CONFIGURATION REGISTER 1 LOW (BYTE ADDRESS 300000h)
R/WO-1 R/WO-1 R/WO-1 R/WO-1 R/WO-1 R/WO-1 R/WO-1 R/WO-1
DEBUG XINST STVREN CFGPLLEN PLLDIV2 PLLDIV1 PLLDIV0 WDTEN
bit 7 bit 0

Legend:
R = Readable bit WO = Write-Once bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 DEBUG: Background Debugger Enable bit

1 = Background debugger is disabled; RB6 and RB7 configured as general purpose I/O pins
0 = Background debugger is enabled; RB6 and RB7 are dedicated to In-Circuit Debug
bit 6 XINST: Extended Instruction Set Enable bit
1 = Instruction set extension and Indexed Addressing mode are enabled
0 = Instruction set extension and Indexed Addressing mode are disabled
bit 5 STVREN: Stack Overflow/Underflow Reset Enable bit
1 = Reset on stack overflow/underflow is enabled
0 = Reset on stack overflow/underflow is disabled
bit 4 CFGPLLEN: PLL Enable bit
1 = 96 MHz PLL is disabled
0 = 96 MHz PLL is enabled
bit 3-1 PLLDIV<2:0>: Oscillator Selection bits
Divider must be selected to provide a 4 MHz input into the 96 MHz PLL.
111 = No divide – oscillator used directly (4 MHz input)
110 = Oscillator divided by 2 (8 MHz input)
101 = Oscillator divided by 3 (12 MHz input)
100 = Oscillator divided by 4 (16 MHz input)
011 = Oscillator divided by 5 (20 MHz input)
010 = Oscillator divided by 6 (24 MHz input)
001 = Oscillator divided by 10 (40 MHz input)
000 = Oscillator divided by 12 (48 MHz input)
bit 0 WDTEN: Watchdog Timer Enable bit
1 = WDT is enabled
0 = WDT is disabled (control is placed on the SWDTEN bit)

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REGISTER 28-2: CONFIG1H: CONFIGURATION REGISTER 1 HIGH (BYTE ADDRESS 300001h)
U-1 U-1 U-1 U-1 U-0 R/WO-1 R/WO-1 R/WO-1
— — — — — CP0 CPDIV1 CPDIV0
bit 7 bit 0

Legend:
R = Readable bit WO = Write-Once bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-4 Unimplemented: Program the corresponding Flash Configuration bit to ‘1’
bit 3 Unimplemented: Maintain as ‘0’
bit 2 CP0: Code Protection bit
1 = Program memory is not code-protected
0 = Program memory is code-protected
bit 1-0 CPDIV<1:0>: CPU System Clock Selection bits
11 = No CPU system clock divide
10 = CPU system clock is divided by 2
01 = CPU system clock is divided by 3
00 = CPU system clock is divided by 6

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REGISTER 28-3: CONFIG2L: CONFIGURATION REGISTER 2 LOW (BYTE ADDRESS 300002h)
R/WO-1 R/WO-1 R/WO-1 R/WO-1 R/WO-1 R/WO-1 R/WO-1 R/WO-1
IESO FCMEN CLKOEC SOSCSEL1 SOSCSEL0 FOSC2 FOSC1 FOSC0
bit 7 bit 0

Legend:
R = Readable bit WO = Write-Once bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 IESO: Two-Speed Start-up (Internal/External Oscillator Switchover) Control bit

1 = Two-Speed Start-up is enabled
0 = Two-Speed Start-up is disabled
bit 6 FCMEN: Fail-Safe Clock Monitor Enable bit
1 = Fail-Safe Clock Monitor is enabled
0 = Fail-Safe Clock Monitor is disabled
bit 5 CLKOEC: CLKO Enable Configuration bit
(Applicable only when the FOSC<2:1> bits are configured for EC or ECPLL mode.)
1 = CLKO output signal active on the RA6 pin
0 = CLKO output is disabled
bit 4-3 SOSCSEL<1:0>: T1OSC/SOSC Power Selection Configuration bits
11 = High-power T1OSC/SOSC circuit is selected
10 = Digital (SCLKI) mode is enabled
01 = Low-power T1OSC/SOSC circuit is selected
00 = Reserved
bit 2-0 FOSC<2:0>: Oscillator Selection bits
111 = ECPLL oscillator with PLL software controlled, CLKO on RA6
110 = EC oscillator with CLKO on RA6
101 = HSPLL oscillator with PLL software controlled
100 = HS oscillator
011 = INTOSCPLLO, internal oscillator with PLL software controlled, CLKO on RA6, port function on
RA7
010 = INTOSCPLL, internal oscillator with PLL software controlled, port function on RA6 and RA7
001 = INTOSCO internal oscillator block (INTRC/INTOSC) with CLKO on RA6, port function on RA7
000 = INTOSC internal oscillator block (INTRC/INTOSC), port function on RA6 and RA7

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REGISTER 28-4: CONFIG2H: CONFIGURATION REGISTER 2 HIGH (BYTE ADDRESS 300003h)
U-1 U-1 U-1 U-1 R/WO-1 R/WO-1 R/WO-1 R/WO-1
— — — — WDTPS3 WDTPS2 WDTPS1 WDTPS0
bit 7 bit 0

Legend:
R = Readable bit WO = Write-Once bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-4 Unimplemented: Program the corresponding Flash Configuration bit to ‘1’
bit 3-0 WDTPS<3:0>: Watchdog Timer Postscale Select bits
1111 = 1:32,768
1110 = 1:16,384
1101 = 1:8,192
1100 = 1:4,096
1011 = 1:2,048
1010 = 1:1,024
1001 = 1:512
1000 = 1:256
0111 = 1:128
0110 = 1:64
0101 = 1:32
0100 = 1:16
0011 = 1:8
0010 = 1:4
0001 = 1:2
0000 = 1:1

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REGISTER 28-5: CONFIG3L: CONFIGURATION REGISTER 3 LOW (BYTE ADDRESS 300004h)
R/WO-1 R/WO-1 R/WO-1 R/WO-1 R/WO-1 R/WO-1 R/WO-1 R/WO-1
(1)
DSWDTPS3 DSWDTPS2(1) DSWDTPS1(1) DSWDTPS0(1) DSWDTEN(1) DSBOREN RTCOSC DSWDTOSC(1)
bit 7 bit 0

Legend:
R = Readable bit WO = Write-Once bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-4 DSWDTPS<3:0>: Deep Sleep Watchdog Timer Postscale Select bits(1)
The DSWDT prescaler is 32. This creates an approximate base time unit of 1 ms.
1111 = 1:2,147,483,648 (25.7 days)
1110 = 1:536,870,912 (6.4 days)
1101 = 1:134,217,728 (38.5 hours)
1100 = 1:33,554,432 (9.6 hours)
1011 = 1:8,388,608 (2.4 hours)
1010 = 1:2,097,152 (36 minutes)
1001 = 1:524,288 (9 minutes)
1000 = 1:131,072 (135 seconds)
0111 = 1:32,768 (34 seconds)
0110 = 1:8,192 (8.5 seconds)
0101 = 1:2,048 (2.1 seconds)
0100 = 1:512 (528 ms)
0011 = 1:128 (132 ms)
0010 = 1:32 (33 ms)
0001 = 1:8 (8.3 ms)
0000 = 1:2 (2.1 ms)
bit 3 DSWDTEN: Deep Sleep Watchdog Timer Enable bit(1)
1 = DSWDT is enabled
0 = DSWDT is disabled
bit 2 DSBOREN: “F” Device Deep Sleep BOR Enable bit, “LF” Device VDD BOR Enable bit
For “F” Devices:
1 = VDD sensing BOR is enabled in Deep Sleep
0 = VDD sensing BOR circuit is always disabled
For “LF” Devices:
1 = VDD sensing BOR circuit is always enabled
0 = VDD sensing BOR circuit is always disabled
bit 1 RTCOSC: RTCC Reference Clock Select bit
1 = RTCC uses T1OSC/T1CKI as reference clock
0 = RTCC uses INTRC as the reference clock
bit 0 DSWDTOSC: DSWDT Reference Clock Select bit(1)
1 = DSWDT uses INTRC as the reference clock
0 = DSWDT uses T1OSC/T1CKI as reference clock

Note 1: Functions are not available on “LF” devices.

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REGISTER 28-6: CONFIG3H: CONFIGURATION REGISTER 3 HIGH (BYTE ADDRESS 300005h)
U-1 U-1 U-1 U-1 R/WO-1 U-0 R/WO-1 R/WO-1
— — — — MSSPMSK — ADCSEL IOL1WAY
bit 7 bit 0

Legend:
R = Readable bit WO = Write-Once bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-4 Unimplemented: Program the corresponding Flash Configuration bit to ‘1’
bit 3 MSSPMSK: MSSP 7-Bit Address Masking Mode Enable bit
1 = 7-Bit Address Masking mode is enabled
0 = 5-Bit Address Masking mode is enabled
bit 2 Unimplemented: Read as ‘0’
bit 1 ADCSEL: A/D Converter Mode
1 = 10-bit conversion mode is enabled
0 = 12-bit conversion mode is enabled
bit 0 IOL1WAY: IOLOCK One-Way Set Enable bit
1 = IOLOCK bit (PPSCON<0>) can be set once, provided the unlock sequence has been completed.
Once set, the Peripheral Pin Select registers cannot be written to a second time.
0 = IOLOCK bit (PPSCON<0>) can be set and cleared as needed, provided the unlock sequence has
been completed

REGISTER 28-7: CONFIG4L: CONFIGURATION REGISTER 4 LOW (BYTE ADDRESS 300006h)

R/WO-1 R/WO-1 R/WO-1 R/WO-1 R/WO-1 R/WO-1 R/WO-1 R/WO-1
WPCFG WPFP6 WPFP5 WPFP4 WPFP3 WPFP2 WPFP1 WPFP0
bit 7 bit 0

Legend:
R = Readable bit WO = Write-Once bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 WPCFG: Write/Erase Protect Configuration Region Select bit (valid when WPDIS = 0)
1 = Configuration Words page is not erase/write-protected unless WPEND and WPFP<5:0> settings
include the Configuration Words page(1)
0 = Configuration Words page is erase/write-protected, regardless of WPEND and WPFP<5:0>(1)
bit 6-0 WPFP<6:0>: Write/Erase Protect Page Start/End Location bits
Used with WPEND bit to define which pages in Flash will be write/erase protected.

Note 1: The “Configuration Words page” contains the FCWs and is the last page of implemented Flash memory on
a given device. Each page consists of 1,024 bytes. For example, on a device with 64 Kbytes of Flash, the
first page is 0 and the last page (Configuration Words page) is 63 (3Fh).

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 PIC18F47J53 FAMILY
REGISTER 28-8: CONFIG4H: CONFIGURATION REGISTER 4 HIGH (BYTE ADDRESS 300007h)
U-1 U-1 U-1 U-1 R/WO-1 U-0 R/WO-1 R/WO-1
— — — — LS48MHZ — WPEND WPDIS
bit 7 bit 0

Legend:
R = Readable bit WO = Write-Once bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-4 Unimplemented: Program the corresponding Flash Configuration bit to ‘1’
bit 3 LS48MHZ: Low-Speed USB Clock Selection
1 = 48-MHz system clock is expected; divide-by-8 generates low-speed USB clock
0 = 24-MHz system clock is expected; divide-by-4 generates low-speed USB clock
bit 2 Unimplemented: Read as ‘0’
bit 1 WPEND: Write-Protect Disable bit
1 = Flash pages, WPFP<6:0> to (Configuration Words page), are write/erase protected
0 = Flash pages 0 to WPFP<6:0> are write/erase-protected
bit 0 WPDIS: Write-Protect Disable bit
1 = WPFP<5:0>, WPEND and WPCFG bits are ignored; all Flash memory may be erased or written
0 = WPFP<5:0>, WPEND and WPCFG bits enabled; erase/write-protect is active for the selected
region(s)

REGISTER 28-9: DEVID1: DEVICE ID REGISTER 1 FOR PIC18F47J53 FAMILY DEVICES

(BYTE ADDRESS 3FFFFEh)
R R R R R R R R
DEV2 DEV1 DEV0 REV4 REV3 REV2 REV1 REV0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-5 DEV<2:0>: Device ID bits

These bits are used with DEV<10:3> bits in Device ID Register 2 to identify the part number. See
Register 28-10.
bit 4-0 REV<4:0>: Revision ID bits
These bits are used to indicate the device revision.

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PIC18F47J53 FAMILY
REGISTER 28-10: DEVID2: DEVICE ID REGISTER 2 FOR PIC18F47J53 FAMILY DEVICES
(BYTE ADDRESS 3FFFFFh)
R R R R R R R R
DEV10 DEV9 DEV8 DEV7 DEV6 DEV5 DEV4 DEV3
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-0 DEV<10:3>: Device ID bits

These bits are used with the DEV<2:0> bits in the Device ID Register 1 to identify the part number.

DEV<10:3> DEV<2:0>
Device
(DEVID2<7:0>) (DEVID2<7:5>)
0101 1000 111 PIC18F47J53
0101 1000 101 PIC18F46J53
0101 1000 011 PIC18F27J53
0101 1000 001 PIC18F26J53
0101 1010 111 PIC18LF47J53
0101 1010 101 PIC18LF46J53
0101 1010 011 PIC18LF27J53
0101 1010 001 PIC18LF26J53

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28.2 Watchdog Timer (WDT) whenever a SLEEP or CLRWDT instruction is executed,
or a clock failure (primary or Timer1 oscillator) has
PIC18F47J53 family devices have both a conventional occurred.
WDT circuit and a dedicated, Deep Sleep capable
Watchdog Timer. When enabled, the conventional Note 1: The CLRWDT and SLEEP instructions
WDT operates in normal Run, Idle and Sleep modes. clear the WDT and postscaler counts
This data sheet section describes the conventional when executed.
WDT circuit. 2: When a CLRWDT instruction is executed,
The dedicated, Deep Sleep capable WDT can only be the postscaler count will be cleared.
enabled in Deep Sleep mode. This timer is described in
Section 4.6.4 “Deep Sleep Watchdog Timer 28.2.1 CONTROL REGISTER
(DSWDT)”.
The WDTCON register (Register 28-11) is a readable
The conventional WDT is driven by the INTRC oscilla-
and writable register. The SWDTEN bit enables or dis-
tor. When the WDT is enabled, the clock source is also
ables WDT operation. This allows software to override
enabled. The nominal WDT period is 4 ms and has the
the WDTEN Configuration bit and enable the WDT only
same stability as the INTRC oscillator.
if it has been disabled by the Configuration bit.
The 4 ms period of the WDT is multiplied by a 16-bit
LVDSTAT is a read-only status bit that is continuously
postscaler. Any output of the WDT postscaler is
updated and provides information about the current
selected by a multiplexer, controlled by the WDTPS bits
level of VDDCORE. This bit is only valid when the on-chip
in Configuration Register 2H. Available periods range
voltage regulator is enabled.
from about 4 ms to 135 seconds (2.25 minutes
depending on voltage, temperature and WDT
postscaler). The WDT and postscaler are cleared

FIGURE 28-1: WDT BLOCK DIAGRAM

Enable WDT
SWDTEN INTRC Control
WDT Counter

INTRC Oscillator 128 Wake-up from

Power-Managed
Modes

CLRWDT Programmable Postscaler Reset WDT

All Device Resets Reset
1:1 to 1:32,768
WDT
WDTPS<3:0> 4

Sleep

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PIC18F47J53 FAMILY
REGISTER 28-11: WDTCON: WATCHDOG TIMER CONTROL REGISTER (ACCESS FC0h)
R/W-1 R-x R-x R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
REGSLP LVDSTAT(2) ULPLVL VBGOE DS(2) ULPEN ULPSINK SWDTEN(1)
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 REGSLP: Voltage Regulator Low-Power Operation Enable bit

1 = On-chip regulator enters low-power operation when device enters Sleep mode
0 = On-chip regulator is active even in Sleep mode
bit 6 LVDSTAT: Low-Voltage Detect Status bit(2)
1 = VDDCORE > 2.45V nominal
0 = VDDCORE < 2.45V nominal
bit 5 ULPLVL: Ultra Low-Power Wake-up Output bit (not valid unless ULPEN = 1)
1 = Voltage on RA0 > ~0.5V
0 = Voltage on RA0 < ~0.5V
bit 4 VBGOE: Band Gap Reference Voltage (VBG) Output Enable bit
1 = Band gap reference output is enabled on pin RA1
0 = Band gap reference output is disabled
bit 3 DS: Deep Sleep Wake-up Status bit (used in conjunction with RCON, POR and BOR bits to determine
Reset source)(2)
1 = If the last exit from Reset was caused by a normal wake-up from Deep Sleep
0 = If the last exit from Reset was not due to a wake-up from Deep Sleep
bit 2 ULPEN: Ultra Low-Power Wake-up Module Enable bit
1 = Ultra low-power wake-up module is enabled; ULPLVL bit indicates the comparator output
0 = Ultra low-power wake-up module is disabled
bit 1 ULPSINK: Ultra Low-Power Wake-up Current Sink Enable bit
1 = Ultra low-power wake-up current sink is enabled (if ULPEN = 1)
0 = Ultra low-power wake-up current sink is disabled
bit 0 SWDTEN: Software Controlled Watchdog Timer Enable bit(1)
1 = Watchdog Timer is on
0 = Watchdog Timer is off

Note 1: This bit has no effect if the Configuration bit, WDTEN, is enabled.
2: Not available on devices where the on-chip voltage regulator is disabled (“LF” devices).

TABLE 28-3: SUMMARY OF WATCHDOG TIMER REGISTERS

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

RCON IPEN — CM RI TO PD POR BOR

WDTCON REGSLP LVDSTAT ULPLVL VBGOE DS ULPEN ULPSINK SWDTEN
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Watchdog Timer.

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 PIC18F47J53 FAMILY
28.3 On-Chip Voltage Regulator I/O pins may still optionally be supplied with a voltage
between 2.0V to 3.6V, provided that VDD is always
Note 1: The on-chip voltage regulator is only greater than, or equal to, VDDCORE/VCAP. For example
available in parts designated with an “F”, connections for PIC18F and PIC18LF devices, see
such as PIC18F26J53. The on-chip Figure 28-2.
regulator is disabled on devices with “LF”
in their part number. Note: In parts designated with an “LF”, such as
PIC18LF47J53, VDDCORE must never
2: The VDDCORE/VCAP pin must never be left exceed VDD.
floating. On “F” devices, it must be con-
nected to a capacitor, of size CEFC, to The specifications for core voltage and capacitance are
ground. On “LF” devices, VDDCORE/VCAP listed in Section 31.3 “DC Characteristics:
must be connected to a power supply PIC18F47J53 Family (Industrial)”.
source between 2.0V and 2.7V.
28.3.1 VOLTAGE REGULATOR TRACKING
The digital core logic of the PIC18F47J53 family MODE AND LOW-VOLTAGE
devices is designed on an advanced manufacturing DETECTION
process, which requires 2.0V to 2.7V. The digital core
On “F” devices, the on-chip regulator provides a con-
logic obtains power from the VDDCORE/VCAP power
stant voltage of 2.5V nominal to the digital core logic.
supply pin.
The regulator can provide this level from a VDD of about
However, in many applications it may be inconvenient 2.5V, all the way up to the device’s VDDMAX. It does not
to run the I/O pins at the same core logic voltage, as it have the capability to boost VDD levels below 2.5V.
would restrict the ability of the device to interface with When the VDD supply input voltage drops too low to
other, higher voltage devices, such as those run at a regulate 2.5V, the regulator enters Tracking mode. In
nominal 3.3V. Therefore, all PIC18F47J53 family Tracking mode, the regulator output follows VDD, with a
devices implement a dual power supply rail topology. typical voltage drop of 100 mV or less.
The core logic obtains power from the VDDCORE/VCAP
The on-chip regulator includes a simple Low-Voltage
pin, while the general purpose I/O pins obtain power
Detect (LVD) circuit. This circuit is separate and
from the VDD pin of the microcontroller, which may be
independent of the High/Low-Voltage Detect (HLVD)
supplied with a voltage between 2.15V to 3.6V (“F”
module described in Section 26.0 “High/Low Voltage
device) or 2.0V to 3.6V (“LF” device).
Detect (HLVD)”. The on-chip regulator LVD circuit con-
This dual supply topology allows the microcontroller to tinuously monitors the VDDCORE voltage level and
interface with standard 3.3V logic devices, while updates the LVDSTAT bit in the WDTCON register. The
running the core logic at a lower voltage of nominally LVD detect threshold is set slightly below the normal
2.5V. regulation set point of the on-chip regulator.
In order to make the microcontroller more convenient to Application firmware may optionally poll the LVDSTAT
use, an integrated 2.5V low dropout, low quiescent bit to determine when it is safe to run at maximum rated
current linear regulator has been integrated on the die frequency, so as not to inadvertently violate the voltage
inside PIC18F47J53 family devices. This regulator is versus frequency requirements provided by
designed specifically to supply the core logic of the Figure 31-1.
device. It allows PIC18F47J53 family devices to
The VDDCORE monitoring LVD circuit is only active
effectively run from a single power supply rail, without
when the on-chip regulator is enabled. On “LF”
the need for external regulators.
devices, the Analog-to-Digital Converter and the HLVD
The on-chip voltage regulator is always enabled on “F” module can still be used to provide firmware with VDD
devices. The VDDCORE/VCAP pin simultaneously serves and VDDCORE voltage level information.
as the regulator output pin and the core logic supply
power input pin. A capacitor should be connected to the
VDDCORE/VCAP pin to ground and is necessary for regu-
lator stability. For example connections for PIC18F and
PIC18LF devices, see Figure 28-2.
On “LF” devices, the on-chip regulator is always
disabled. This allows the device to save a small amount
of quiescent current consumption, which may be
advantageous in some types of applications, such as
those which will entirely be running at a nominal 2.5V.
On “LF” devices, the VDDCORE/VCAP pin still serves as
the core logic power supply input pin, and therefore,
must be connected to a 2.0V to 2.7V supply rail at the
application circuit board level. On these devices, the

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PIC18F47J53 FAMILY
FIGURE 28-2: CONNECTIONS FOR THE 28.3.2 ON-CHIP REGULATOR AND BOR
ON-CHIP REGULATOR When the on-chip regulator is enabled, PIC18F47J53
PIC18FXXJ53 Devices (Regulator Enabled): family devices also have a simple brown-out capability.
3.3V If the voltage supplied to the regulator is inadequate to
PIC18FXXJ53
maintain a minimum output level, the regulator Reset
circuitry will generate a Brown-out Reset (BOR). This
event is captured by the BOR flag bit (RCON<0>).
VDD
The operation of the BOR is described in more detail in
VDDCORE/VCAP Section 5.4 “Brown-out Reset (BOR)” and
CF Section 5.4.1 “Detecting BOR”. The brown-out voltage
VSS levels are specific in Section 31.1 “DC Characteristics:
Supply Voltage PIC18F47J53 Family (Industrial)”.

PIC18LFXXJ53 Devices (Regulator Disabled): 28.3.3 POWER-UP REQUIREMENTS

2.5V The on-chip regulator is designed to meet the power-up
PIC18LFXXJ53 requirements for the device. If the application does not
use the regulator, then strict power-up conditions must
VDD
be adhered to. While powering up, VDDCORE should not
exceed VDD by 0.3 volts.
VDDCORE/VCAP
28.3.4 OPERATION IN SLEEP MODE
VSS
When enabled, the on-chip regulator always consumes
a small incremental amount of current over IDD. This
OR includes when the device is in Sleep mode, even
2.5V 3.3V though the core digital logic does not require much
PIC18LFXXJ53 power. To provide additional savings in applications
where power resources are critical, the regulator can
be configured to automatically enter a lower quiescent
VDD
draw Standby mode whenever the device goes into
Sleep mode. This feature is controlled by the REGSLP
VDDCORE/VCAP
bit (WDTCON<7>, Register 28-11). If this bit is set
VSS upon entry into Sleep mode, the regulator will transition
into a lower power state. In this state, the regulator still
provides a regulated output voltage necessary to
maintain SRAM state information, but consumes less
quiescent current.
Substantial Sleep mode power savings can be
obtained by setting the REGSLP bit, but device
wake-up time will increase in order to insure the
regulator has enough time to stabilize.

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28.4 Two-Speed Start-up When enabled, Resets and wake-ups from Sleep mode
cause the device to configure itself to run from the inter-
The Two-Speed Start-up feature helps to minimize the nal oscillator block as the clock source, following the
latency period, from oscillator start-up to code execu- time-out of the Power-up Timer after a Power-on Reset
tion, by allowing the microcontroller to use the INTRC is enabled. This allows almost immediate code
oscillator as a clock source until the primary clock execution while the primary oscillator starts and the
source is available. It is enabled by setting the IESO OST is running. Once the OST times out, the device
Configuration bit. automatically switches to PRI_RUN mode.
Two-Speed Start-up should be enabled only if the In all other power-managed modes, Two-Speed
primary oscillator mode is HS or HSPLL Start-up is not used. The device will be clocked by the
(Crystal-Based) modes. Since the EC and ECPLL currently selected clock source until the primary clock
modes do not require an Oscillator Start-up Timer source becomes available. The setting of the IESO bit
(OST) delay, Two-Speed Start-up should be disabled. is ignored.

FIGURE 28-3: TIMING TRANSITION FOR TWO-SPEED START-UP (INTRC TO HSPLL)

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3
INTRC

OSC1
TOST(1) TPLL(1)
1 2 n-1 n
PLL Clock
Output
Clock
Transition
CPU Clock

Peripheral
Clock

Program PC PC + 2 PC + 4 PC + 6
Counter

Wake from Interrupt Event OSTS bit Set

Note1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.

28.4.1 SPECIAL CONSIDERATIONS FOR 28.5 Fail-Safe Clock Monitor

USING TWO-SPEED START-UP
The Fail-Safe Clock Monitor (FSCM) allows the
While using the INTRC oscillator in Two-Speed microcontroller to continue operation in the event of an
Start-up, the device still obeys the normal command external oscillator failure by automatically switching the
sequences for entering power-managed modes, device clock to the internal oscillator block. The FSCM
including serial SLEEP instructions (refer to function is enabled by setting the FCMEN Configuration
Section 4.1.4 “Multiple Sleep Commands”). In bit.
practice, this means that user code can change the
When FSCM is enabled, the INTRC oscillator runs at
SCS<1:0> bit settings or issue SLEEP instructions
all times to monitor clocks to peripherals and provide a
before the OST times out. This would allow an applica-
backup clock in the event of a clock failure. Clock
tion to briefly wake-up, perform routine “housekeeping”
monitoring (shown in Figure 28-4) is accomplished by
tasks and return to Sleep before the device starts to
creating a sample clock signal, which is the INTRC out-
operate from the primary oscillator.
put divided by 64. This allows ample time between
User code can also check if the primary clock source is FSCM sample clocks for a peripheral clock edge to
currently providing the device clocking by checking the occur. The peripheral device clock and the sample
status of the OSTS bit (OSCCON<3>). If the bit is set, clock are presented as inputs to the clock monitor latch.
the primary oscillator is providing the clock. Otherwise, The clock monitor is set on the falling edge of the
the internal oscillator block is providing the clock during device clock source but cleared on the rising edge of
wake-up from Reset or Sleep mode. the sample clock.

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FIGURE 28-4: FSCM BLOCK DIAGRAM be desirable to select another clock configuration and
Clock Monitor enter an alternate power-managed mode. This can be
Latch done to attempt a partial recovery or execute a
(edge-triggered) controlled shutdown. See Section 4.1.4 “Multiple
Peripheral Sleep Commands” and Section 28.4.1 “Special
S Q
Clock Considerations For Using Two-speed Start-up” for
more details.
INTRC The FSCM will detect failures of the primary or secondary
÷ 64 C Q clock sources only. If the internal oscillator block fails, no
Source
failure would be detected, nor would any action be
(32 s) 488 Hz possible.
(2.048 ms)
28.5.1 FSCM AND THE WATCHDOG TIMER
Clock
Failure Both the FSCM and the WDT are clocked by the
Detected INTRC oscillator. Since the WDT operates with a
separate divider and counter, disabling the WDT has
Clock failure is tested for on the falling edge of the no effect on the operation of the INTRC oscillator when
sample clock. If a sample clock falling edge occurs the FSCM is enabled.
while the clock monitor is still set, and a clock failure
As already noted, the clock source is switched to the
has been detected (Figure 28-5), the following results:
INTRC clock when a clock failure is detected; this may
• The FSCM generates an oscillator fail interrupt by mean a substantial change in the speed of code execu-
setting bit, OSCFIF (PIR2<7>); tion. If the WDT is enabled with a small prescale value,
• The device clock source is switched to the internal a decrease in clock speed allows a WDT time-out to
oscillator block (OSCCON is not updated to show occur and a subsequent device Reset. For this reason,
the current clock source – this is the Fail-safe Fail-Safe Clock Monitor events also reset the WDT and
condition); and postscaler, allowing it to start timing from when execu-
• The WDT is reset. tion speed was changed and decreasing the likelihood
of an erroneous time-out.
During switchover, the postscaler frequency from the
internal oscillator block may not be sufficiently stable
for timing-sensitive applications. In these cases, it may

FIGURE 28-5: FSCM TIMING DIAGRAM

Sample Clock

Device Oscillator
Clock Failure
Output

Clock Monitor
Output (Q)
Failure
Detected
OSCFIF

Clock Monitor Test Clock Monitor Test Clock Monitor Test

Note: The device clock is normally at a much higher frequency than the sample clock. The relative frequencies in
this example have been chosen for clarity.

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 PIC18F47J53 FAMILY
28.5.2 EXITING FAIL-SAFE OPERATION out). This is identical to Two-Speed Start-up mode.
Once the primary clock is stable, the INTRC returns to
The Fail-Safe Clock Monitor condition is terminated by
its role as the FSCM source.
either a device Reset or by entering a power-managed
mode. On Reset, the controller starts the primary clock Note: The same logic that prevents false
source specified in Configuration Register 2H (with any oscillator failure interrupts on POR, or
required start-up delays that are required for the oscil- wake-up from Sleep, will also prevent the
lator mode, such as the OST or PLL timer). The INTRC detection of the oscillator’s failure to start
oscillator provides the device clock until the primary at all following these events. This can be
clock source becomes ready (similar to a Two-Speed avoided by monitoring the OSTS bit and
Start-up). The clock source is then switched to the using a timing routine to determine if the
primary clock (indicated by the OSTS bit in the oscillator is taking too long to start. Even
OSCCON register becoming set). The FSCM then so, no oscillator failure interrupt will be
resumes monitoring the peripheral clock. flagged.
The primary clock source may never become ready
As noted in Section 28.4.1 “Special Considerations
during start-up. In this case, operation is clocked by the
For Using Two-speed Start-up”, it is also possible to
INTRC oscillator. The OSCCON register will remain in
select another clock configuration and enter an alternate
its Reset state until a power-managed mode is entered.
power-managed mode while waiting for the primary
clock to become stable. When the new power-managed
28.5.3 FSCM INTERRUPTS IN
mode is selected, the primary clock is disabled.
POWER-MANAGED MODES
By entering a power-managed mode, the clock 28.6 Program Verification and Code
multiplexer selects the clock source selected by the
Protection
OSCCON register. FSCM of the power-managed clock
source resumes in the power-managed mode. For all devices in the PIC18F47J53 family of devices,
If an oscillator failure occurs during power-managed the on-chip program memory space is treated as a
operation, the subsequent events depend on whether single block. Code protection for this block is controlled
or not the oscillator failure interrupt is enabled. If by one Configuration bit, CP0. This bit inhibits external
enabled (OSCFIF = 1), code execution will be clocked reads and writes to the program memory space. It has
by the INTRC multiplexer. An automatic transition back no direct effect in normal execution mode.
to the failed clock source will not occur.
28.6.1 CONFIGURATION REGISTER
If the interrupt is disabled, subsequent interrupts while PROTECTION
in Idle mode, will cause the CPU to begin executing
instructions while being clocked by the INTRC source. The Configuration registers are protected against
untoward changes or reads in two ways. The primary
28.5.4 POR OR WAKE-UP FROM SLEEP protection is the write-once feature of the Configuration
bits, which prevents reconfiguration once the bit has
The FSCM is designed to detect oscillator failure at any
been programmed during a power cycle. To safeguard
point after the device has exited Power-on Reset (POR)
against unpredictable events, Configuration bit
or low-power Sleep mode. When the primary device
changes resulting from individual cell level disruptions
clock is either the EC or INTRC modes, monitoring can
(such as ESD events) will cause a parity error and
begin immediately following these events.
trigger a device Reset. This is seen by the user as a
For HS or HSPLL modes, the situation is somewhat Configuration Mismatch (CM) Reset.
different. Since the oscillator may require a start-up
The data for the Configuration registers is derived from
time considerably longer than the FSCM sample clock
the FCW in program memory. When the CP0 bit is set,
time, a false clock failure may be detected. To prevent
the source data for device configuration is also
this, the internal oscillator block is automatically config-
protected as a consequence.
ured as the device clock and functions until the primary
clock is stable (the OST and PLL timers have timed

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28.7 In-Circuit Serial Programming™ 28.8 In-Circuit Debugger
(ICSP™) When the DEBUG Configuration bit is programmed to
PIC18F47J53 family microcontrollers can be serially a ‘0’, the In-Circuit Debugger functionality is enabled.
programmed while in the end application circuit. This is This function allows simple debugging functions when
simply done with two lines for clock and data, and three used with MPLAB® IDE. When the microcontroller has
other lines for power, ground and the programming this feature enabled, some resources are not available
voltage. This allows customers to manufacture boards for general use.
with unprogrammed devices and then program the Table 28-4 lists the resources required by the
microcontroller just before shipping the product. This background debugger.
also allows the most recent firmware or a custom
firmware to be programmed. TABLE 28-4: DEBUGGER RESOURCES
I/O pins: RB6, RB7
Stack: 2 levels
Program Memory: 512 bytes
Data Memory: 10 bytes

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29.0 INSTRUCTION SET SUMMARY The literal instructions may use some of the following
operands:
The PIC18F47J53 family of devices incorporate the
• A literal value to be loaded into a file register
standard set of 75 PIC18 core instructions, as well as
(specified by ‘k’)
an extended set of 8 new instructions for the optimiza-
tion of code that is recursive or that utilizes a software • The desired FSR register to load the literal value
stack. The extended set is discussed later in this into (specified by ‘f’)
section. • No operand required
(specified by ‘—’)
29.1 Standard Instruction Set The control instructions may use some of the following
operands:
The standard PIC18 MCU instruction set adds many
enhancements to the previous PIC® MCU instruction • A program memory address (specified by ‘n’)
sets, while maintaining an easy migration from these • The mode of the CALL or RETURN instructions
PIC MCU instruction sets. Most instructions are a (specified by ‘s’)
single program memory word (16 bits), but there are • The mode of the table read and table write
four instructions that require two program memory instructions (specified by ‘m’)
locations. • No operand required
Each single-word instruction is a 16-bit word divided (specified by ‘—’)
into an opcode, which specifies the instruction type and All instructions are a single word, except for four
one or more operands, which further specify the double-word instructions. These instructions were
operation of the instruction. made double-word to contain the required information
The instruction set is highly orthogonal and is grouped in 32 bits. In the second word, the 4 MSbs are ‘1’s. If
into four basic categories: this second word is executed as an instruction (by
• Byte-oriented operations itself), it will execute as a NOP.
• Bit-oriented operations All single-word instructions are executed in a single
• Literal operations instruction cycle, unless a conditional test is true or the
program counter is changed as a result of the instruc-
• Control operations
tion. In these cases, the execution takes two instruction
The PIC18 instruction set summary in Table 29-2 lists cycles with the additional instruction cycle(s) executed
byte-oriented, bit-oriented, literal and control as a NOP.
operations. Table 29-1 shows the opcode field
The double-word instructions execute in two instruction
descriptions.
cycles.
Most byte-oriented instructions have three operands:
One instruction cycle consists of four oscillator periods.
1. The file register (specified by ‘f’) Thus, for an oscillator frequency of 4 MHz, the normal
2. The destination of the result (specified by ‘d’) instruction execution time is 1 s. If a conditional test is
3. The accessed memory (specified by ‘a’) true, or the program counter is changed as a result of
an instruction, the instruction execution time is 2 s.
The file register designator, ‘f’, specifies which file reg- Two-word branch instructions (if true) would take 3 s.
ister is to be used by the instruction. The destination
designator, ‘d’, specifies where the result of the Figure 29-1 shows the general formats that the instruc-
operation is to be placed. If ‘d’ is zero, the result is tions can have. All examples use the convention ‘nnh’
placed in the WREG register. If ‘d’ is one, the result is to represent a hexadecimal number.
placed in the file register specified in the instruction. The Instruction Set Summary, shown in Table 29-2,
All bit-oriented instructions have three operands: lists the standard instructions recognized by the
Microchip MPASMTM Assembler.
1. The file register (specified by ‘f’)
Section 29.1.1 “Standard Instruction Set” provides
2. The bit in the file register (specified by ‘b’)
a description of each instruction.
3. The accessed memory (specified by ‘a’)
The bit field designator, ‘b’, selects the number of the bit
affected by the operation, while the file register desig-
nator, ‘f’, represents the number of the file in which the
bit is located.

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TABLE 29-1: OPCODE FIELD DESCRIPTIONS

Field Description
a RAM access bit:
a = 0: RAM location in Access RAM (BSR register is ignored)
a = 1: RAM bank is specified by BSR register
bbb Bit address within an 8-bit file register (0 to 7).
BSR Bank Select Register. Used to select the current RAM bank.
C, DC, Z, OV, N ALU Status bits: Carry, Digit Carry, Zero, Overflow, Negative.
d Destination select bit:
d = 0: store result in WREG
d = 1: store result in file register f
dest Destination: either the WREG register or the specified register file location.
f 8-bit Register file address (00h to FFh), or 2-bit FSR designator (0h to 3h).
fs 12-bit Register file address (000h to FFFh). This is the source address.
fd 12-bit Register file address (000h to FFFh). This is the destination address.
GIE Global Interrupt Enable bit.
k Literal field, constant data or label (may be either an 8-bit, 12-bit or a 20-bit value).
label Label name.
mm The mode of the TBLPTR register for the table read and table write instructions.
Only used with table read and table write instructions:
* No Change to register (such as TBLPTR with table reads and writes)
*+ Post-Increment register (such as TBLPTR with table reads and writes)
*- Post-Decrement register (such as TBLPTR with table reads and writes)
+* Pre-Increment register (such as TBLPTR with table reads and writes)
n The relative address (2’s complement number) for relative branch instructions or the direct address for
Call/Branch and Return instructions.
PC Program Counter.
PCL Program Counter Low Byte.
PCH Program Counter High Byte.
PCLATH Program Counter High Byte Latch.
PCLATU Program Counter Upper Byte Latch.
PD Power-Down bit.
PRODH Product of Multiply High Byte.
PRODL Product of Multiply Low Byte.
s Fast Call/Return mode select bit:
s = 0: do not update into/from shadow registers
s = 1: certain registers loaded into/from shadow registers (Fast mode)
TBLPTR 21-bit Table Pointer (points to a Program Memory location).
TABLAT 8-bit Table Latch.
TO Time-out bit.
TOS Top-of-Stack.
u Unused or Unchanged.
WDT Watchdog Timer.
WREG Working register (accumulator).
x Don’t care (‘0’ or ‘1’). The assembler will generate code with x = 0. It is the recommended form of use for
compatibility with all Microchip software tools.
zs 7-bit offset value for Indirect Addressing of register files (source).
zd 7-bit offset value for Indirect Addressing of register files (destination).
{ } Optional argument.
[text] Indicates an Indexed Address.
(text) The contents of text.

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 PIC18F47J53 FAMILY
TABLE 29-1: OPCODE FIELD DESCRIPTIONS (CONTINUED)

Field Description
[expr]<n> Specifies bit n of the register indicated by the pointer expr.
 Assigned to.
< > Register bit field.
 In the set of.
italics User-defined term (font is Courier New).

FIGURE 29-1: GENERAL FORMAT FOR INSTRUCTIONS

Byte-oriented file register operations Example Instruction
15 10 9 8 7 0
OPCODE d a f (FILE #) ADDWF MYREG, W, B
d = 0 for result destination to be WREG register
d = 1 for result destination to be file register (f)
a = 0 to force Access Bank
a = 1 for BSR to select bank
f = 8-bit file register address

Byte to Byte move operations (2-word)

15 12 11 0
OPCODE f (Source FILE #) MOVFF MYREG1, MYREG2
15 12 11 0
1111 f (Destination FILE #)

f = 12-bit file register address

Bit-oriented file register operations

15 12 11 9 8 7 0
OPCODE b (BIT #) a f (FILE #) BSF MYREG, bit, B

b = 3-bit position of bit in file register (f)

a = 0 to force Access Bank
a = 1 for BSR to select bank
f = 8-bit file register address

Literal operations
15 8 7 0
OPCODE k (literal) MOVLW 7Fh

k = 8-bit immediate value

Control operations
CALL, GOTO and Branch operations
15 8 7 0
OPCODE n<7:0> (literal) GOTO Label
15 12 11 0
1111 n<19:8> (literal)

n = 20-bit immediate value

15 8 7 0
OPCODE S n<7:0> (literal) CALL MYFUNC

15 12 11 0
1111 n<19:8> (literal)
S = Fast bit

15 11 10 0

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TABLE 29-2: PIC18F47J53 FAMILY INSTRUCTION SET

Mnemonic, 16-Bit Instruction Word Status
Description Cycles Notes
Operands MSb LSb Affected

BYTE-ORIENTED OPERATIONS
ADDWF f, d, a Add WREG and f 1 0010 01da ffff ffff C, DC, Z, OV, N 1, 2
ADDWFC f, d, a Add WREG and Carry bit to f 1 0010 00da ffff ffff C, DC, Z, OV, N 1, 2
ANDWF f, d, a AND WREG with f 1 0001 01da ffff ffff Z, N 1,2
CLRF f, a Clear f 1 0110 101a ffff ffff Z 2
COMF f, d, a Complement f 1 0001 11da ffff ffff Z, N 1, 2
CPFSEQ f, a Compare f with WREG, Skip = 1 (2 or 3) 0110 001a ffff ffff None 4
CPFSGT f, a Compare f with WREG, Skip > 1 (2 or 3) 0110 010a ffff ffff None 4
CPFSLT f, a Compare f with WREG, Skip < 1 (2 or 3) 0110 000a ffff ffff None 1, 2
DECF f, d, a Decrement f 1 0000 01da ffff ffff C, DC, Z, OV, N 1, 2, 3, 4
DECFSZ f, d, a Decrement f, Skip if 0 1 (2 or 3) 0010 11da ffff ffff None 1, 2, 3, 4
DCFSNZ f, d, a Decrement f, Skip if Not 0 1 (2 or 3) 0100 11da ffff ffff None 1, 2
INCF f, d, a Increment f 1 0010 10da ffff ffff C, DC, Z, OV, N 1, 2, 3, 4
INCFSZ f, d, a Increment f, Skip if 0 1 (2 or 3) 0011 11da ffff ffff None 4
INFSNZ f, d, a Increment f, Skip if Not 0 1 (2 or 3) 0100 10da ffff ffff None 1, 2
IORWF f, d, a Inclusive OR WREG with f 1 0001 00da ffff ffff Z, N 1, 2
MOVF f, d, a Move f 1 0101 00da ffff ffff Z, N 1
MOVFF fs, fd Move fs (source) to 1st word 2 1100 ffff ffff ffff None
fd (destination) 2nd word 1111 ffff ffff ffff
MOVWF f, a Move WREG to f 1 0110 111a ffff ffff None
MULWF f, a Multiply WREG with f 1 0000 001a ffff ffff None 1, 2
NEGF f, a Negate f 1 0110 110a ffff ffff C, DC, Z, OV, N
RLCF f, d, a Rotate Left f through Carry 1 0011 01da ffff ffff C, Z, N 1, 2
RLNCF f, d, a Rotate Left f (No Carry) 1 0100 01da ffff ffff Z, N
RRCF f, d, a Rotate Right f through Carry 1 0011 00da ffff ffff C, Z, N
RRNCF f, d, a Rotate Right f (No Carry) 1 0100 00da ffff ffff Z, N
SETF f, a Set f 1 0110 100a ffff ffff None 1, 2
SUBFWB f, d, a Subtract f from WREG with 1 0101 01da ffff ffff C, DC, Z, OV, N
Borrow
SUBWF f, d, a Subtract WREG from f 1 0101 11da ffff ffff C, DC, Z, OV, N 1, 2
SUBWFB f, d, a Subtract WREG from f with 1 0101 10da ffff ffff C, DC, Z, OV, N
Borrow
SWAPF f, d, a Swap Nibbles in f 1 0011 10da ffff ffff None 4
TSTFSZ f, a Test f, Skip if 0 1 (2 or 3) 0110 011a ffff ffff None 1, 2
XORWF f, d, a Exclusive OR WREG with f 1 0001 10da ffff ffff Z, N
Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that
value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is
driven low by an external device, the data will be written back with a ‘0’.
2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared
if assigned.
3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second
cycle is executed as a NOP.
4: Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP
unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all
program memory locations have a valid instruction.

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TABLE 29-2: PIC18F47J53 FAMILY INSTRUCTION SET (CONTINUED)
Mnemonic, 16-Bit Instruction Word Status
Description Cycles Notes
Operands MSb LSb Affected

BIT-ORIENTED OPERATIONS
BCF f, b, a Bit Clear f 1 1001 bbba ffff ffff None 1, 2
BSF f, b, a Bit Set f 1 1000 bbba ffff ffff None 1, 2
BTFSC f, b, a Bit Test f, Skip if Clear 1 (2 or 3) 1011 bbba ffff ffff None 3, 4
BTFSS f, b, a Bit Test f, Skip if Set 1 (2 or 3) 1010 bbba ffff ffff None 3, 4
BTG f, b, a Bit Toggle f 1 0111 bbba ffff ffff None 1, 2
CONTROL OPERATIONS
BC n Branch if Carry 1 (2) 1110 0010 nnnn nnnn None
BN n Branch if Negative 1 (2) 1110 0110 nnnn nnnn None
BNC n Branch if Not Carry 1 (2) 1110 0011 nnnn nnnn None
BNN n Branch if Not Negative 1 (2) 1110 0111 nnnn nnnn None
BNOV n Branch if Not Overflow 1 (2) 1110 0101 nnnn nnnn None
BNZ n Branch if Not Zero 1 (2) 1110 0001 nnnn nnnn None
BOV n Branch if Overflow 1 (2) 1110 0100 nnnn nnnn None
BRA n Branch Unconditionally 2 1101 0nnn nnnn nnnn None
BZ n Branch if Zero 1 (2) 1110 0000 nnnn nnnn None
CALL n, s Call Subroutine 1st word 2 1110 110s kkkk kkkk None
2nd word 1111 kkkk kkkk kkkk
CLRWDT — Clear Watchdog Timer 1 0000 0000 0000 0100 TO, PD
DAW — Decimal Adjust WREG 1 0000 0000 0000 0111 C
GOTO n Go to Address 1st word 2 1110 1111 kkkk kkkk None
2nd word 1111 kkkk kkkk kkkk
NOP — No Operation 1 0000 0000 0000 0000 None
NOP — No Operation 1 1111 xxxx xxxx xxxx None 4
POP — Pop Top of Return Stack (TOS) 1 0000 0000 0000 0110 None
PUSH — Push Top of Return Stack (TOS) 1 0000 0000 0000 0101 None
RCALL n Relative Call 2 1101 1nnn nnnn nnnn None
RESET Software Device Reset 1 0000 0000 1111 1111 All
RETFIE s Return from Interrupt Enable 2 0000 0000 0001 000s GIE/GIEH,
PEIE/GIEL
RETLW k Return with Literal in WREG 2 0000 1100 kkkk kkkk None
RETURN s Return from Subroutine 2 0000 0000 0001 001s None
SLEEP — Go into Standby mode 1 0000 0000 0000 0011 TO, PD
Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that
value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is
driven low by an external device, the data will be written back with a ‘0’.
2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared
if assigned.
3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second
cycle is executed as a NOP.
4: Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP
unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all
program memory locations have a valid instruction.

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TABLE 29-2: PIC18F47J53 FAMILY INSTRUCTION SET (CONTINUED)
Mnemonic, 16-Bit Instruction Word Status
Description Cycles Notes
Operands MSb LSb Affected

LITERAL OPERATIONS
ADDLW k Add Literal and WREG 1 0000 1111 kkkk kkkk C, DC, Z, OV, N
ANDLW k AND Literal with WREG 1 0000 1011 kkkk kkkk Z, N
IORLW k Inclusive OR Literal with WREG 1 0000 1001 kkkk kkkk Z, N
LFSR f, k Move literal (12-bit) 2nd word 2 1110 1110 00ff kkkk None
to FSR(f) 1st word 1111 0000 kkkk kkkk
MOVLB k Move Literal to BSR<3:0> 1 0000 0001 0000 kkkk None
MOVLW k Move Literal to WREG 1 0000 1110 kkkk kkkk None
MULLW k Multiply Literal with WREG 1 0000 1101 kkkk kkkk None
RETLW k Return with Literal in WREG 2 0000 1100 kkkk kkkk None
SUBLW k Subtract WREG from Literal 1 0000 1000 kkkk kkkk C, DC, Z, OV, N
XORLW k Exclusive OR Literal with WREG 1 0000 1010 kkkk kkkk Z, N
DATA MEMORY  PROGRAM MEMORY OPERATIONS
TBLRD* Table Read 2 0000 0000 0000 1000 None
TBLRD*+ Table Read with Post-Increment 0000 0000 0000 1001 None
TBLRD*- Table Read with Post-Decrement 0000 0000 0000 1010 None
TBLRD+* Table Read with Pre-Increment 0000 0000 0000 1011 None
TBLWT* Table Write 2 0000 0000 0000 1100 None
TBLWT*+ Table Write with Post-Increment 0000 0000 0000 1101 None
TBLWT*- Table Write with Post-Decrement 0000 0000 0000 1110 None
TBLWT+* Table Write with Pre-Increment 0000 0000 0000 1111 None
Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that
value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is
driven low by an external device, the data will be written back with a ‘0’.
2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared
if assigned.
3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second
cycle is executed as a NOP.
4: Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP
unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all
program memory locations have a valid instruction.

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29.1.1 STANDARD INSTRUCTION SET

ADDLW ADD Literal to W ADDWF ADD W to f

Syntax: ADDLW k Syntax: ADDWF f {,d {,a}}

Operands: 0  k  255 Operands: 0  f  255
Operation: (W) + k  W d  [0,1]
a  [0,1]
Status Affected: N, OV, C, DC, Z
Operation: (W) + (f)  dest
Encoding: 0000 1111 kkkk kkkk
Status Affected: N, OV, C, DC, Z
Description: The contents of W are added to the
Encoding: 0010 01da ffff ffff
8-bit literal ‘k’ and the result is placed in
W. Description: Add W to register ‘f’. If ‘d’ is ‘0’, the
result is stored in W. If ‘d’ is ‘1’, the
Words: 1
result is stored back in register ‘f’
Cycles: 1 (default).
Q Cycle Activity: If ‘a’ is ‘0’, the Access Bank is selected.
Q1 Q2 Q3 Q4 If ‘a’ is ‘1’, the BSR is used to select the
Decode Read Process Write to GPR bank (default).
literal ‘k’ Data W If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
Example: ADDLW 15h
mode whenever f 95 (5Fh). See
Before Instruction Section 29.2.3 “Byte-Oriented and
W = 10h Bit-Oriented Instructions in Indexed
After Instruction Literal Offset Mode” for details.
W = 25h
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read Process Write to
register ‘f’ Data destination

Example: ADDWF REG, 0, 0

Before Instruction
W = 17h
REG = 0C2h
After Instruction
W = 0D9h
REG = 0C2h

Note: All PIC18 instructions may take an optional label argument preceding the instruction mnemonic for use in
symbolic addressing. If a label is used, the instruction format then becomes: {label} instruction argument(s).

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ADDWFC ADD W and Carry bit to f ANDLW AND Literal with W

Syntax: ADDWFC f {,d {,a}} Syntax: ANDLW k

Operands: 0  f  255 Operands: 0  k  255
d [0,1] Operation: (W) .AND. k  W
a [0,1]
Status Affected: N, Z
Operation: (W) + (f) + (C)  dest
Encoding: 0000 1011 kkkk kkkk
Status Affected: N,OV, C, DC, Z
Description: The contents of W are ANDed with the
Encoding: 0010 00da ffff ffff
8-bit literal ‘k’. The result is placed in W.
Description: Add W, the Carry flag and data memory
Words: 1
location ‘f’. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is Cycles: 1
placed in data memory location ‘f’. Q Cycle Activity:
If ‘a’ is ‘0’, the Access Bank is selected. Q1 Q2 Q3 Q4
If ‘a’ is ‘1’, the BSR is used to select the Decode Read literal Process Write to
GPR bank (default). ‘k’ Data W
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates Example: ANDLW 05Fh
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See Before Instruction
Section 29.2.3 “Byte-Oriented and W = A3h
Bit-Oriented Instructions in Indexed After Instruction
Literal Offset Mode” for details. W = 03h

Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read Process Write to
register ‘f’ Data destination

Example: ADDWFC REG, 0, 1

Before Instruction
Carry bit = 1
REG = 02h
W = 4Dh
After Instruction
Carry bit = 0
REG = 02h
W = 50h

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ANDWF AND W with f BC Branch if Carry

Syntax: ANDWF f {,d {,a}} Syntax: BC n

Operands: 0  f  255 Operands: -128  n  127
d [0,1] Operation: if Carry bit is ‘1’,
a [0,1]
(PC) + 2 + 2n  PC
Operation: (W) .AND. (f)  dest
Status Affected: None
Status Affected: N, Z Encoding: 1110 0010 nnnn nnnn
Encoding: 0001 01da ffff ffff
Description: If the Carry bit is ’1’, then the program
Description: The contents of W are ANDed with will branch.
register ‘f’. If ‘d’ is ‘0’, the result is stored
The 2’s complement number ‘2n’ is
in W. If ‘d’ is ‘1’, the result is stored back added to the PC. Since the PC will have
in register ‘f’ (default). incremented to fetch the next
If ‘a’ is ‘0’, the Access Bank is selected. instruction, the new address will be
If ‘a’ is ‘1’, the BSR is used to select the PC + 2 + 2n. This instruction is then a
GPR bank (default). two-cycle instruction.
If ‘a’ is ‘0’ and the extended instruction Words: 1
set is enabled, this instruction operates
Cycles: 1(2)
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See Q Cycle Activity:
Section 29.2.3 “Byte-Oriented and If Jump:
Bit-Oriented Instructions in Indexed Q1 Q2 Q3 Q4
Literal Offset Mode” for details. Decode Read literal Process Write to
Words: 1 ‘n’ Data PC

Cycles: 1 No No No No
operation operation operation operation
Q Cycle Activity:
If No Jump:
Q1 Q2 Q3 Q4
Q1 Q2 Q3 Q4
Decode Read Process Write to
Decode Read literal Process No
register ‘f’ Data destination
‘n’ Data operation

Example: ANDWF REG, 0, 0

Example: HERE BC 5
Before Instruction
Before Instruction
W = 17h PC = address (HERE)
REG = C2h
After Instruction
After Instruction
If Carry = 1;
W = 02h PC = address (HERE + 12)
REG = C2h If Carry = 0;
PC = address (HERE + 2)

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BCF Bit Clear f BN Branch if Negative

Syntax: BCF f, b {,a} Syntax: BN n

Operands: 0  f  255 Operands: -128  n  127
0b7 Operation: if Negative bit is ‘1’,
a [0,1]
(PC) + 2 + 2n  PC
Operation: 0  f<b>
Status Affected: None
Status Affected: None Encoding: 1110 0110 nnnn nnnn
Encoding: 1001 bbba ffff ffff
Description: If the Negative bit is ‘1’, then the
Description: Bit ‘b’ in register ‘f’ is cleared. program will branch.
If ‘a’ is ‘0’, the Access Bank is selected. The 2’s complement number ‘2n’ is
If ‘a’ is ‘1’, the BSR is used to select the added to the PC. Since the PC will have
GPR bank (default). incremented to fetch the next
instruction, the new address will be
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates PC + 2 + 2n. This instruction is then a
two-cycle instruction.
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See Words: 1
Section 29.2.3 “Byte-Oriented and
Cycles: 1(2)
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details. Q Cycle Activity:
If Jump:
Words: 1
Q1 Q2 Q3 Q4
Cycles: 1
Decode Read literal Process Write to
Q Cycle Activity: ‘n’ Data PC
Q1 Q2 Q3 Q4 No No No No
Decode Read Process Write operation operation operation operation
register ‘f’ Data register ‘f’ If No Jump:
Q1 Q2 Q3 Q4
Example: BCF FLAG_REG, 7, 0 Decode Read literal Process No
‘n’ Data operation
Before Instruction
FLAG_REG = C7h
After Instruction Example: HERE BN Jump
FLAG_REG = 47h
Before Instruction
PC = address (HERE)
After Instruction
If Negative = 1;
PC = address (Jump)
If Negative = 0;
PC = address (HERE + 2)

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BNC Branch if Not Carry BNN Branch if Not Negative

Syntax: BNC n Syntax: BNN n

Operands: -128  n  127 Operands: -128  n  127
Operation: if Carry bit is ‘0’, Operation: if Negative bit is ‘0’,
(PC) + 2 + 2n  PC (PC) + 2 + 2n  PC
Status Affected: None Status Affected: None
Encoding: 1110 0011 nnnn nnnn Encoding: 1110 0111 nnnn nnnn
Description: If the Carry bit is ‘0’, then the program Description: If the Negative bit is ‘0’, then the
will branch. program will branch.
The 2’s complement number ‘2n’ is The 2’s complement number ‘2n’ is
added to the PC. Since the PC will have added to the PC. Since the PC will have
incremented to fetch the next incremented to fetch the next
instruction, the new address will be instruction, the new address will be
PC + 2 + 2n. This instruction is then a PC + 2 + 2n. This instruction is then a
two-cycle instruction. two-cycle instruction.
Words: 1 Words: 1
Cycles: 1(2) Cycles: 1(2)
Q Cycle Activity: Q Cycle Activity:
If Jump: If Jump:
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Decode Read literal Process Write to Decode Read literal Process Write to
‘n’ Data PC ‘n’ Data PC
No No No No No No No No
operation operation operation operation operation operation operation operation
If No Jump: If No Jump:
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Decode Read literal Process No Decode Read literal Process No
‘n’ Data operation ‘n’ Data operation

Example: HERE BNC Jump Example: HERE BNN Jump

Before Instruction Before Instruction
PC = address (HERE) PC = address (HERE)
After Instruction After Instruction
If Carry = 0; If Negative = 0;
PC = address (Jump) PC = address (Jump)
If Carry = 1; If Negative = 1;
PC = address (HERE + 2) PC = address (HERE + 2)

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BNOV Branch if Not Overflow BNZ Branch if Not Zero

Syntax: BNOV n Syntax: BNZ n

Operands: -128  n  127 Operands: -128  n  127
Operation: if Overflow bit is ‘0’, Operation: if Zero bit is ‘0’,
(PC) + 2 + 2n  PC (PC) + 2 + 2n  PC
Status Affected: None Status Affected: None
Encoding: 1110 0101 nnnn nnnn Encoding: 1110 0001 nnnn nnnn
Description: If the Overflow bit is ‘0’, then the Description: If the Zero bit is ‘0’, then the program
program will branch. will branch.
The 2’s complement number ‘2n’ is The 2’s complement number ‘2n’ is
added to the PC. Since the PC will have added to the PC. Since the PC will have
incremented to fetch the next incremented to fetch the next
instruction, the new address will be instruction, the new address will be
PC + 2 + 2n. This instruction is then a PC + 2 + 2n. This instruction is then a
two-cycle instruction. two-cycle instruction.
Words: 1 Words: 1
Cycles: 1(2) Cycles: 1(2)
Q Cycle Activity: Q Cycle Activity:
If Jump: If Jump:
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Decode Read literal Process Write to Decode Read literal Process Write to
‘n’ Data PC ‘n’ Data PC
No No No No No No No No
operation operation operation operation operation operation operation operation
If No Jump: If No Jump:
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Decode Read literal Process No Decode Read literal Process No
‘n’ Data operation ‘n’ Data operation

Example: HERE BNOV Jump Example: HERE BNZ Jump

Before Instruction Before Instruction
PC = address (HERE) PC = address (HERE)
After Instruction After Instruction
If Overflow = 0; If Zero = 0;
PC = address (Jump) PC = address (Jump)
If Overflow = 1; If Zero = 1;
PC = address (HERE + 2) PC = address (HERE + 2)

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BRA Unconditional Branch BSF Bit Set f

Syntax: BRA n Syntax: BSF f, b {,a}

Operands: -1024  n  1023 Operands: 0  f  255
Operation: (PC) + 2 + 2n  PC 0b7
a [0,1]
Status Affected: None
Operation: 1  f<b>
Encoding: 1101 0nnn nnnn nnnn
Status Affected: None
Description: Add the 2’s complement number ‘2n’ to
Encoding: 1000 bbba ffff ffff
the PC. Since the PC will have
incremented to fetch the next Description: Bit ‘b’ in register ‘f’ is set.
instruction, the new address will be
If ‘a’ is ‘0’, the Access Bank is selected.
PC + 2 + 2n. This instruction is a If ‘a’ is ‘1’, the BSR is used to select the
two-cycle instruction. GPR bank (default).
Words: 1
If ‘a’ is ‘0’ and the extended instruction
Cycles: 2 set is enabled, this instruction operates
in Indexed Literal Offset Addressing
Q Cycle Activity:
mode whenever f 95 (5Fh). See
Q1 Q2 Q3 Q4 Section 29.2.3 “Byte-Oriented and
Decode Read literal Process Write to Bit-Oriented Instructions in Indexed
‘n’ Data PC Literal Offset Mode” for details.
No No No No
Words: 1
operation operation operation operation
Cycles: 1
Q Cycle Activity:
Example: HERE BRA Jump
Q1 Q2 Q3 Q4
Before Instruction Decode Read Process Write
PC = address (HERE) register ‘f’ Data register ‘f’
After Instruction
PC = address (Jump)
Example: BSF FLAG_REG, 7, 1
Before Instruction
FLAG_REG = 0Ah
After Instruction
FLAG_REG = 8Ah

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BTFSC Bit Test File, Skip if Clear BTFSS Bit Test File, Skip if Set

Syntax: BTFSC f, b {,a} Syntax: BTFSS f, b {,a}

Operands: 0  f  255 Operands: 0  f  255
0b7 0b<7
a [0,1] a [0,1]
Operation: skip if (f<b>) = 0 Operation: skip if (f<b>) = 1
Status Affected: None Status Affected: None
Encoding: 1011 bbba ffff ffff Encoding: 1010 bbba ffff ffff
Description: If bit ‘b’ in register ‘f’ is ‘0’, then the next Description: If bit ‘b’ in register ‘f’ is ‘1’, then the next
instruction is skipped. If bit ‘b’ is ‘0’, then instruction is skipped. If bit ‘b’ is ‘1’, then
the next instruction fetched during the the next instruction fetched during the
current instruction execution is discarded current instruction execution is discarded
and a NOP is executed instead, making and a NOP is executed instead, making
this a two-cycle instruction. this a two-cycle instruction.
If ‘a’ is ‘0’, the Access Bank is selected. If If ‘a’ is ‘0’, the Access Bank is selected. If
‘a’ is ‘1’, the BSR is used to select the ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default). GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction set If ‘a’ is ‘0’ and the extended instruction
is enabled, this instruction operates in set is enabled, this instruction operates in
Indexed Literal Offset Addressing mode Indexed Literal Offset Addressing mode
whenever f 95 (5Fh). See whenever f 95 (5Fh). See
Section 29.2.3 “Byte-Oriented and Section 29.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details. Literal Offset Mode” for details.
Words: 1 Words: 1
Cycles: 1(2) Cycles: 1(2)
Note: 3 cycles if skip and followed Note: 3 cycles if skip and followed
by a 2-word instruction. by a 2-word instruction.
Q Cycle Activity: Q Cycle Activity:
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Decode Read Process No Decode Read Process No
register ‘f’ Data operation register ‘f’ Data operation
If skip: If skip:
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
No No No No No No No No
operation operation operation operation operation operation operation operation
If skip and followed by 2-word instruction: If skip and followed by 2-word instruction:
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
No No No No No No No No
operation operation operation operation operation operation operation operation
No No No No No No No No
operation operation operation operation operation operation operation operation

Example: HERE BTFSC FLAG, 1, 0 Example: HERE BTFSS FLAG, 1, 0

FALSE : FALSE :
TRUE : TRUE :
Before Instruction Before Instruction
PC = address (HERE) PC = address (HERE)
After Instruction After Instruction
If FLAG<1> = 0; If FLAG<1> = 0;
PC = address (TRUE) PC = address (FALSE)
If FLAG<1> = 1; If FLAG<1> = 1;
PC = address (FALSE) PC = address (TRUE)

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BTG Bit Toggle f BOV Branch if Overflow

Syntax: BTG f, b {,a} Syntax: BOV n

Operands: 0  f  255 Operands: -128  n  127
0b<7 Operation: if Overflow bit is ‘1’,
a [0,1]
(PC) + 2 + 2n  PC
Operation: (f<b>)  f<b>
Status Affected: None
Status Affected: None
Encoding: 1110 0100 nnnn nnnn
Encoding: 0111 bbba ffff ffff
Description: If the Overflow bit is ‘1’, then the
Description: Bit ‘b’ in data memory location ‘f’ is program will branch.
inverted.
The 2’s complement number ‘2n’ is
If ‘a’ is ‘0’, the Access Bank is selected. added to the PC. Since the PC will have
If ‘a’ is ‘1’, the BSR is used to select the incremented to fetch the next
GPR bank (default). instruction, the new address will be
If ‘a’ is ‘0’ and the extended instruction PC + 2 + 2n. This instruction is then a
two-cycle instruction.
set is enabled, this instruction operates
in Indexed Literal Offset Addressing Words: 1
mode whenever f 95 (5Fh). See
Cycles: 1(2)
Section 29.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed Q Cycle Activity:
Literal Offset Mode” for details. If Jump:

Words: 1 Q1 Q2 Q3 Q4
Decode Read literal Process Write to PC
Cycles: 1
‘n’ Data
Q Cycle Activity: No No No No
Q1 Q2 Q3 Q4 operation operation operation operation
Decode Read Process Write If No Jump:
register ‘f’ Data register ‘f’ Q1 Q2 Q3 Q4
Decode Read literal Process No
Example: BTG PORTC, 4, 0 ‘n’ Data operation
Before Instruction:
PORTC = 0111 0101 [75h] Example: HERE BOV Jump
After Instruction:
Before Instruction
PORTC = 0110 0101 [65h]
PC = address (HERE)
After Instruction
If Overflow = 1;
PC = address (Jump)
If Overflow = 0;
PC = address (HERE + 2)

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BZ Branch if Zero CALL Subroutine Call

Syntax: BZ n Syntax: CALL k {,s}

Operands: -128  n  127 Operands: 0  k  1048575
Operation: if Zero bit is ‘1’, s [0,1]
(PC) + 2 + 2n  PC Operation: (PC) + 4  TOS,
k  PC<20:1>;
Status Affected: None
if s = 1
Encoding: 1110 0000 nnnn nnnn (W)  WS,
Description: If the Zero bit is ‘1’, then the program (STATUS)  STATUSS,
will branch. (BSR)  BSRS

The 2’s complement number ‘2n’ is Status Affected: None

added to the PC. Since the PC will have Encoding:
incremented to fetch the next 1st word (k<7:0>) 1110 110s k7kkk kkkk0
instruction, the new address will be 2nd word(k<19:8>) 1111 k19kkk kkkk kkkk8
PC + 2 + 2n. This instruction is then a
Description: Subroutine call of entire 2-Mbyte
two-cycle instruction.
memory range. First, return address
Words: 1 (PC+ 4) is pushed onto the return stack.
Cycles: 1(2) If ‘s’ = 1, the W, STATUS and BSR
registers are also pushed into their
Q Cycle Activity:
respective shadow registers, WS,
If Jump:
STATUSS and BSRS. If ‘s’ = 0, no
Q1 Q2 Q3 Q4 update occurs (default). Then, the
Decode Read literal Process Write to 20-bit value ‘k’ is loaded into PC<20:1>.
‘n’ Data PC CALL is a two-cycle instruction.
No No No No Words: 2
operation operation operation operation
Cycles: 2
If No Jump:
Q Cycle Activity:
Q1 Q2 Q3 Q4
Q1 Q2 Q3 Q4
Decode Read literal Process No
‘n’ Data operation Decode Read literal Push PC to Read literal
‘k’<7:0>, stack ’k’<19:8>,
Write to PC
Example: HERE BZ Jump
No No No No
Before Instruction operation operation operation operation
PC = address (HERE)
After Instruction
Example: HERE CALL THERE,1
If Zero = 1;
PC = address (Jump) Before Instruction
If Zero = 0; PC = address (HERE)
PC = address (HERE + 2)
After Instruction
PC = address (THERE)
TOS = address (HERE + 4)
WS = W
BSRS = BSR
STATUSS = STATUS

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CLRF Clear f CLRWDT Clear Watchdog Timer

Syntax: CLRF f {,a} Syntax: CLRWDT

Operands: 0  f  255 Operands: None
a [0,1] Operation: 000h  WDT,
Operation: 000h  f, 000h  WDT postscaler,
1Z 1  TO,
1  PD
Status Affected: Z
Status Affected: TO, PD
Encoding: 0110 101a ffff ffff
Encoding: 0000 0000 0000 0100
Description: Clears the contents of the specified
register. Description: CLRWDT instruction resets the
Watchdog Timer. It also resets the post-
If ‘a’ is ‘0’, the Access Bank is selected.
scaler of the WDT. Status bits, TO and
If ‘a’ is ‘1’, the BSR is used to select the
PD, are set.
GPR bank (default).
Words: 1
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates Cycles: 1
in Indexed Literal Offset Addressing Q Cycle Activity:
mode whenever f 95 (5Fh). See
Q1 Q2 Q3 Q4
Section 29.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed Decode No Process No
Literal Offset Mode” for details. operation Data operation

Words: 1
Example: CLRWDT
Cycles: 1
Before Instruction
Q Cycle Activity:
WDT Counter = ?
Q1 Q2 Q3 Q4 After Instruction
Decode Read Process Write WDT Counter = 00h
register ‘f’ Data register ‘f’ WDT Postscaler = 0
TO = 1
PD = 1
Example: CLRF FLAG_REG,1
Before Instruction
FLAG_REG = 5Ah
After Instruction
FLAG_REG = 00h

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COMF Complement f CPFSEQ Compare f with W, Skip if f = W

Syntax: COMF f {,d {,a}} Syntax: CPFSEQ f {,a}

Operands: 0  f  255 Operands: 0  f  255

d  [0,1] a  [0,1]
a  [0,1] Operation: (f) – (W),
skip if (f) = (W)
Operation: f  dest
(unsigned comparison)
Status Affected: N, Z
Status Affected: None
Encoding: 0001 11da ffff ffff
Encoding: 0110 001a ffff ffff
Description: The contents of register ‘f’ are Description: Compares the contents of data memory
complemented. If ‘d’ is ‘0’, the result is location ‘f’ to the contents of W by
stored in W. If ‘d’ is ‘1’, the result is performing an unsigned subtraction.
stored back in register ‘f’ (default).
If ‘f’ = W, then the fetched instruction is
If ‘a’ is ‘0’, the Access Bank is selected. discarded and a NOP is executed
If ‘a’ is ‘1’, the BSR is used to select the instead, making this a two-cycle
GPR bank (default). instruction.
If ‘a’ is ‘0’ and the extended instruction If ‘a’ is ‘0’, the Access Bank is selected.
set is enabled, this instruction operates If ‘a’ is ‘1’, the BSR is used to select the
in Indexed Literal Offset Addressing GPR bank (default).
mode whenever f 95 (5Fh). See
Section 29.2.3 “Byte-Oriented and If ‘a’ is ‘0’ and the extended instruction
Bit-Oriented Instructions in Indexed set is enabled, this instruction operates
Literal Offset Mode” for details. in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Words: 1 Section 29.2.3 “Byte-Oriented and
Cycles: 1 Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Q Cycle Activity:
Q1 Q2 Q3 Q4 Words: 1

Decode Read Process Write to Cycles: 1(2)

register ‘f’ Data destination Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Example: COMF REG, 0, 0
Q1 Q2 Q3 Q4
Before Instruction Decode Read Process No
REG = 13h register ‘f’ Data operation
After Instruction
If skip:
REG = 13h
W = ECh Q1 Q2 Q3 Q4
No No No No
operation operation operation operation
If skip and followed by 2-word instruction:
Q1 Q2 Q3 Q4
No No No No
operation operation operation operation
No No No No
operation operation operation operation

Example: HERE CPFSEQ REG, 0

NEQUAL :
EQUAL :
Before Instruction
PC Address = HERE
W = ?
REG = ?
After Instruction
If REG = W;
PC = Address (EQUAL)
If REG  W;
PC = Address (NEQUAL)

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CPFSGT Compare f with W, Skip if f > W CPFSLT Compare f with W, Skip if f < W
Syntax: CPFSGT f {,a} Syntax: CPFSLT f {,a}
Operands: 0  f  255 Operands: 0  f  255
a  [0,1] a  [0,1]
Operation: (f) –W),
Operation: (f) –W),
skip if (f) > (W)
skip if (f) < (W)
(unsigned comparison)
(unsigned comparison)
Status Affected: None
Status Affected: None
Encoding: 0110 010a ffff ffff
Encoding: 0110 000a ffff ffff
Description: Compares the contents of data memory
location ‘f’ to the contents of the W by Description: Compares the contents of data memory
performing an unsigned subtraction. location ‘f’ to the contents of W by
performing an unsigned subtraction.
If the contents of ‘f’ are greater than the
contents of WREG, then the fetched If the contents of ‘f’ are less than the
instruction is discarded and a NOP is contents of W, then the fetched
executed instead, making this a instruction is discarded and a NOP is
two-cycle instruction. executed instead, making this a
two-cycle instruction.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the If ‘a’ is ‘0’, the Access Bank is selected.
GPR bank (default). If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates Words: 1
in Indexed Literal Offset Addressing Cycles: 1(2)
mode whenever f 95 (5Fh). See Note: 3 cycles if skip and followed
Section 29.2.3 “Byte-Oriented and by a 2-word instruction.
Bit-Oriented Instructions in Indexed
Q Cycle Activity:
Literal Offset Mode” for details.
Q1 Q2 Q3 Q4
Words: 1
Decode Read Process No
Cycles: 1(2) register ‘f’ Data operation
Note: 3 cycles if skip and followed
If skip:
by a 2-word instruction.
Q1 Q2 Q3 Q4
Q Cycle Activity:
No No No No
Q1 Q2 Q3 Q4
operation operation operation operation
Decode Read Process No
register ‘f’ Data operation If skip and followed by 2-word instruction:
If skip: Q1 Q2 Q3 Q4
Q1 Q2 Q3 Q4 No No No No
No No No No operation operation operation operation
operation operation operation operation No No No No
If skip and followed by 2-word instruction: operation operation operation operation
Q1 Q2 Q3 Q4
No No No No Example: HERE CPFSLT REG, 1
operation operation operation operation NLESS :
No No No No LESS :
operation operation operation operation
Before Instruction
PC = Address (HERE)
Example: HERE CPFSGT REG, 0 W = ?
NGREATER : After Instruction
GREATER : If REG < W;
Before Instruction PC = Address (LESS)
If REG  W;
PC = Address (HERE) PC = Address (NLESS)
W = ?
After Instruction
If REG  W;
PC = Address (GREATER)
If REG  W;
PC = Address (NGREATER)

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DAW Decimal Adjust W Register DECF Decrement f

Syntax: DAW Syntax: DECF f {,d {,a}}

Operands: None Operands: 0  f  255
Operation: If [W<3:0> > 9] or [DC = 1], then d  [0,1]
a  [0,1]
(W<3:0>) + 6  W<3:0>;
else Operation: (f) – 1  dest
(W<3:0>)  W<3:0>
Status Affected: C, DC, N, OV, Z

If [W<7:4> > 9] or [C = 1], then Encoding: 0000 01da ffff ffff

(W<7:4>) + 6  W<7:4>; Description: Decrement register ‘f’. If ‘d’ is ‘0’, the
C =1; result is stored in W. If ‘d’ is ‘1’, the
else result is stored back in register ‘f’
(W<7:4>)  W<7:4> (default).
Status Affected: C If ‘a’ is ‘0’, the Access Bank is selected.
Encoding: 0000 0000 0000 0111 If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
Description: DAW adjusts the eight-bit value in W,
resulting from the earlier addition of two If ‘a’ is ‘0’ and the extended instruction
variables (each in packed BCD format) set is enabled, this instruction operates
and produces a correct packed BCD in Indexed Literal Offset Addressing
result. mode whenever f 95 (5Fh). See
Section 29.2.3 “Byte-Oriented and
Words: 1
Bit-Oriented Instructions in Indexed
Cycles: 1 Literal Offset Mode” for details.
Q Cycle Activity: Words: 1
Q1 Q2 Q3 Q4 Cycles: 1
Decode Read Process Write Q Cycle Activity:
register W Data W
Q1 Q2 Q3 Q4

Example 1: DAW Decode Read Process Write to

register ‘f’ Data destination
Before Instruction
W = A5h
C = 0 Example: DECF CNT, 1, 0
DC = 0
Before Instruction
After Instruction
CNT = 01h
W = 05h Z = 0
C = 1
DC = 0 After Instruction
CNT = 00h
Example 2: Z = 1
Before Instruction
W = CEh
C = 0
DC = 0
After Instruction
W = 34h
C = 1
DC = 0

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DECFSZ Decrement f, Skip if 0 DCFSNZ Decrement f, Skip if Not 0

Syntax: DECFSZ f {,d {,a}} Syntax: DCFSNZ f {,d {,a}}

Operands: 0  f  255 Operands: 0  f  255
d  [0,1] d  [0,1]
a  [0,1] a  [0,1]
Operation: (f) – 1  dest, Operation: (f) – 1  dest,
skip if result = 0 skip if result  0
Status Affected: None Status Affected: None
Encoding: 0010 11da ffff ffff Encoding: 0100 11da ffff ffff
Description: The contents of register ‘f’ are Description: The contents of register ‘f’ are
decremented. If ‘d’ is ‘0’, the result is decremented. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’ (default). placed back in register ‘f’ (default).
If the result is ‘0’, the next instruction If the result is not ‘0’, the next
which is already fetched is discarded instruction which is already fetched is
and a NOP is executed instead, making discarded and a NOP is executed
it a two-cycle instruction. instead, making it a two-cycle
instruction.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the If ‘a’ is ‘0’, the Access Bank is selected.
GPR bank (default). If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates If ‘a’ is ‘0’ and the extended instruction
in Indexed Literal Offset Addressing set is enabled, this instruction operates
mode whenever f 95 (5Fh). See in Indexed Literal Offset Addressing
Section 29.2.3 “Byte-Oriented and mode whenever f 95 (5Fh). See
Bit-Oriented Instructions in Indexed Section 29.2.3 “Byte-Oriented and
Literal Offset Mode” for details. Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words: 1
Words: 1
Cycles: 1(2)
Note: 3 cycles if skip and followed Cycles: 1(2)
by a 2-word instruction. Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1 Q2 Q3 Q4 Q Cycle Activity:
Decode Read Process Write to Q1 Q2 Q3 Q4
register ‘f’ Data destination Decode Read Process Write to
If skip: register ‘f’ Data destination
Q1 Q2 Q3 Q4 If skip:
No No No No Q1 Q2 Q3 Q4
operation operation operation operation No No No No
If skip and followed by 2-word instruction: operation operation operation operation
Q1 Q2 Q3 Q4 If skip and followed by 2-word instruction:
No No No No Q1 Q2 Q3 Q4
operation operation operation operation No No No No
No No No No operation operation operation operation
operation operation operation operation No No No No
operation operation operation operation
Example: HERE DECFSZ CNT, 1, 1
GOTO LOOP Example: HERE DCFSNZ TEMP, 1, 0
CONTINUE ZERO :
NZERO :
Before Instruction
PC = Address (HERE) Before Instruction
After Instruction TEMP = ?
CNT = CNT – 1 After Instruction
If CNT = 0; TEMP = TEMP – 1,
PC = Address (CONTINUE) If TEMP = 0;
If CNT  0; PC = Address (ZERO)
PC = Address (HERE + 2) If TEMP  0;
PC = Address (NZERO)

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GOTO Unconditional Branch INCF Increment f

Syntax: GOTO k Syntax: INCF f {,d {,a}}

Operands: 0  k  1048575 Operands: 0  f  255
Operation: k  PC<20:1> d  [0,1]
a  [0,1]
Status Affected: None
Operation: (f) + 1  dest
Encoding:
1st word (k<7:0>) 1110 1111 k7kkk kkkk0 Status Affected: C, DC, N, OV, Z
2nd word(k<19:8>) 1111 k19kkk kkkk kkkk8 Encoding: 0010 10da ffff ffff
Description: GOTO allows an unconditional branch Description: The contents of register ‘f’ are
anywhere within entire 2-Mbyte memory incremented. If ‘d’ is ‘0’, the result is
range. The 20-bit value ‘k’ is loaded into placed in W. If ‘d’ is ‘1’, the result is
PC<20:1>. GOTO is always a two-cycle placed back in register ‘f’ (default).
instruction.
If ‘a’ is ‘0’, the Access Bank is selected.
Words: 2 If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
Cycles: 2
Q Cycle Activity: If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
Q1 Q2 Q3 Q4
in Indexed Literal Offset Addressing
Decode Read literal No Read literal mode whenever f 95 (5Fh). See
‘k’<7:0>, operation ‘k’<19:8>, Section 29.2.3 “Byte-Oriented and
Write to PC Bit-Oriented Instructions in Indexed
No No No No Literal Offset Mode” for details.
operation operation operation operation
Words: 1
Cycles: 1
Example: GOTO THERE
Q Cycle Activity:
After Instruction
Q1 Q2 Q3 Q4
PC = Address (THERE)
Decode Read Process Write to
register ‘f’ Data destination

Example: INCF CNT, 1, 0

Before Instruction
CNT = FFh
Z = 0
C = ?
DC = ?
After Instruction
CNT = 00h
Z = 1
C = 1
DC = 1

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INCFSZ Increment f, Skip if 0 INFSNZ Increment f, Skip if Not 0

Syntax: INCFSZ f {,d {,a}} Syntax: INFSNZ f {,d {,a}}

Operands: 0  f  255 Operands: 0  f  255

d  [0,1] d  [0,1]
a  [0,1] a  [0,1]
Operation: (f) + 1  dest,
Operation: (f) + 1  dest,
skip if result  0
skip if result = 0
Status Affected: None
Status Affected: None
Encoding: 0100 10da ffff ffff
Encoding: 0011 11da ffff ffff
Description: The contents of register ‘f’ are
Description: The contents of register ‘f’ are incremented. If ‘d’ is ‘0’, the result is
incremented. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is
placed in W. If ‘d’ is ‘1’, the result is placed back in register ‘f’ (default).
placed back in register ‘f’. (default)
If the result is not ‘0’, the next
If the result is ‘0’, the next instruction instruction which is already fetched is
which is already fetched is discarded discarded and a NOP is executed
and a NOP is executed instead, making instead, making it a two-cycle
it a two-cycle instruction. instruction.
If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default). GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates set is enabled, this instruction operates
in Indexed Literal Offset Addressing in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See mode whenever f 95 (5Fh). See
Section 29.2.3 “Byte-Oriented and Section 29.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details. Literal Offset Mode” for details.
Words: 1 Words: 1
Cycles: 1(2) Cycles: 1(2)
Note: 3 cycles if skip and followed Note: 3 cycles if skip and followed
by a 2-word instruction. by a 2-word instruction.
Q Cycle Activity: Q Cycle Activity:
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Decode Read Process Write to Decode Read Process Write to
register ‘f’ Data destination register ‘f’ Data destination
If skip: If skip:
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
No No No No No No No No
operation operation operation operation operation operation operation operation
If skip and followed by 2-word instruction: If skip and followed by 2-word instruction:
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
No No No No No No No No
operation operation operation operation operation operation operation operation
No No No No No No No No
operation operation operation operation operation operation operation operation

Example: HERE INCFSZ CNT, 1, 0 Example: HERE INFSNZ REG, 1, 0

NZERO : ZERO
ZERO : NZERO
Before Instruction Before Instruction
PC = Address (HERE) PC = Address (HERE)
After Instruction After Instruction
CNT = CNT + 1 REG = REG + 1
If CNT = 0; If REG  0;
PC = Address (ZERO) PC = Address (NZERO)
If CNT  0; If REG = 0;
PC = Address (NZERO) PC = Address (ZERO)

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IORLW Inclusive OR Literal with W IORWF Inclusive OR W with f

Syntax: IORLW k Syntax: IORWF f {,d {,a}}

Operands: 0  k  255 Operands: 0  f  255
Operation: (W) .OR. k  W d  [0,1]
a  [0,1]
Status Affected: N, Z
Operation: (W) .OR. (f)  dest
Encoding: 0000 1001 kkkk kkkk
Status Affected: N, Z
Description: The contents of W are ORed with the
Encoding: 0001 00da ffff ffff
eight-bit literal ‘k’. The result is placed
in W. Description: Inclusive OR W with register ‘f’. If ‘d’ is
‘0’, the result is placed in W. If ‘d’ is ‘1’,
Words: 1
the result is placed back in register ‘f’
Cycles: 1 (default).
Q Cycle Activity: If ‘a’ is ‘0’, the Access Bank is selected.
Q1 Q2 Q3 Q4 If ‘a’ is ‘1’, the BSR is used to select the
Decode Read Process Write to GPR bank (default).
literal ‘k’ Data W If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
Example: IORLW 35h in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Before Instruction Section 29.2.3 “Byte-Oriented and
W = 9Ah Bit-Oriented Instructions in Indexed
After Instruction Literal Offset Mode” for details.
W = BFh
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read Process Write to
register ‘f’ Data destination

Example: IORWF RESULT, 0, 1

Before Instruction
RESULT = 13h
W = 91h
After Instruction
RESULT = 13h
W = 93h

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LFSR Load FSR MOVF Move f

Syntax: LFSR f, k Syntax: MOVF f {,d {,a}}

Operands: 0f2 Operands: 0  f  255
0  k  4095 d  [0,1]
a  [0,1]
Operation: k  FSRf
Operation: f  dest
Status Affected: None
Encoding: 1110 1110 00ff k11kkk Status Affected: N, Z
1111 0000 k7kkk kkkk Encoding: 0101 00da ffff ffff
Description: The 12-bit literal ‘k’ is loaded into the Description: The contents of register ‘f’ are moved to
file select register pointed to by ‘f’. a destination dependent upon the
Words: 2 status of ‘d’. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
Cycles: 2 placed back in register ‘f’ (default).
Q Cycle Activity: Location ‘f’ can be anywhere in the
Q1 Q2 Q3 Q4 256-byte bank.

Decode Read literal Process Write If ‘a’ is ‘0’, the Access Bank is selected.
‘k’ MSB Data literal ‘k’ If ‘a’ is ‘1’, the BSR is used to select the
MSB to GPR bank (default).
FSRfH If ‘a’ is ‘0’ and the extended instruction
Decode Read literal Process Write literal set is enabled, this instruction operates
‘k’ LSB Data ‘k’ to FSRfL in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 29.2.3 “Byte-Oriented and
Example: LFSR 2, 3ABh
Bit-Oriented Instructions in Indexed
After Instruction Literal Offset Mode” for details.
FSR2H = 03h
FSR2L = ABh Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read Process Write
register ‘f’ Data W

Example: MOVF REG, 0, 0

Before Instruction
REG = 22h
W = FFh
After Instruction
REG = 22h
W = 22h

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MOVFF Move f to f MOVLB Move Literal to Low Nibble in BSR

Syntax: MOVFF fs,fd Syntax: MOVLW k

Operands: 0  fs  4095 Operands: 0  k  255
0  fd  4095
Operation: k  BSR
Operation: (fs)  fd
Status Affected: None
Status Affected: None
Encoding: 0000 0001 kkkk kkkk
Encoding:
Description: The eight-bit literal ‘k’ is loaded into the
1st word (source) 1100 ffff ffff ffffs
Bank Select Register (BSR). The value
2nd word (destin.) 1111 ffff ffff ffffd
of BSR<7:4> always remains ‘0’
Description: The contents of source register ‘fs’ are regardless of the value of k7:k4.
moved to destination register ‘fd’.
Words: 1
Location of source ‘fs’ can be anywhere
in the 4096-byte data space (000h to Cycles: 1
FFFh) and location of destination ‘fd’ Q Cycle Activity:
can also be anywhere from 000h to Q1 Q2 Q3 Q4
FFFh.
Decode Read Process Write literal
Either source or destination can be W literal ‘k’ Data ‘k’ to BSR
(a useful special situation).
MOVFF is particularly useful for Example: MOVLB 5
transferring a data memory location to a
peripheral register (such as the transmit Before Instruction
buffer or an I/O port). BSR Register = 02h
After Instruction
The MOVFF instruction cannot use the BSR Register = 05h
PCL, TOSU, TOSH or TOSL as the
destination register
Words: 2
Cycles: 2
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read Process No
register ‘f’ Data operation
(src)
Decode No No Write
operation operation register ‘f’
No dummy (dest)
read

Example: MOVFF REG1, REG2

Before Instruction
REG1 = 33h
REG2 = 11h
After Instruction
REG1 = 33h
REG2 = 33h

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MOVLW Move Literal to W MOVWF Move W to f

Syntax: MOVLW k Syntax: MOVWF f {,a}

Operands: 0  k  255 Operands: 0  f  255
Operation: kW a  [0,1]
Operation: (W)  f
Status Affected: None
Status Affected: None
Encoding: 0000 1110 kkkk kkkk
Encoding: 0110 111a ffff ffff
Description: The eight-bit literal ‘k’ is loaded into W.
Description: Move data from W to register ‘f’.
Words: 1
Location ‘f’ can be anywhere in the
Cycles: 1 256-byte bank.
Q Cycle Activity: If ‘a’ is ‘0’, the Access Bank is selected.
Q1 Q2 Q3 Q4 If ‘a’ is ‘1’, the BSR is used to select the
Decode Read Process Write to GPR bank (default).
literal ‘k’ Data W If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
Example: MOVLW 5Ah in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
After Instruction Section 29.2.3 “Byte-Oriented and
W = 5Ah Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read Process Write
register ‘f’ Data register ‘f’

Example: MOVWF REG, 0

Before Instruction
W = 4Fh
REG = FFh
After Instruction
W = 4Fh
REG = 4Fh

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MULLW Multiply Literal with W MULWF Multiply W with f

Syntax: MULLW k Syntax: MULWF f {,a}

Operands: 0  k  255 Operands: 0  f  255
Operation: (W) x k  PRODH:PRODL a  [0,1]
Operation: (W) x (f)  PRODH:PRODL
Status Affected: None
Status Affected: None
Encoding: 0000 1101 kkkk kkkk
Encoding: 0000 001a ffff ffff
Description: An unsigned multiplication is carried
out between the contents of W and the Description: An unsigned multiplication is carried out
8-bit literal ‘k’. The 16-bit result is between the contents of W and the
placed in the PRODH:PRODL register register file location ‘f’. The 16-bit result is
pair. PRODH contains the high byte. stored in the PRODH:PRODL register
W is unchanged. pair. PRODH contains the high byte. Both
W and ‘f’ are unchanged.
None of the Status flags are affected.
None of the Status flags are affected.
Note that neither Overflow nor Carry is
possible in this operation. A Zero result Note that neither Overflow nor Carry is
is possible but not detected. possible in this operation. A Zero result is
possible but not detected.
Words: 1
If ‘a’ is ‘0’, the Access Bank is selected. If
Cycles: 1 ‘a’ is ‘1’, the BSR is used to select the
Q Cycle Activity: GPR bank (default).
Q1 Q2 Q3 Q4 If ‘a’ is ‘0’ and the extended instruction set
Decode Read Process Write is enabled, this instruction operates in
literal ‘k’ Data registers Indexed Literal Offset Addressing mode
PRODH: whenever f 95 (5Fh). See
PRODL Section 29.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Example: MULLW 0C4h
Words: 1
Before Instruction
W = E2h Cycles: 1
PRODH = ? Q Cycle Activity:
PRODL = ?
After Instruction Q1 Q2 Q3 Q4
W = E2h Decode Read Process Write
PRODH = ADh register ‘f’ Data registers
PRODL = 08h PRODH:
PRODL

Example: MULWF REG, 1

Before Instruction
W = C4h
REG = B5h
PRODH = ?
PRODL = ?
After Instruction
W = C4h
REG = B5h
PRODH = 8Ah
PRODL = 94h

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NEGF Negate f NOP No Operation

Syntax: NEGF f {,a} Syntax: NOP

Operands: 0  f  255 Operands: None
a  [0,1] Operation: No operation
Operation: (f) + 1  f
Status Affected: None
Status Affected: N, OV, C, DC, Z
Encoding: 0000 0000 0000 0000
Encoding: 0110 110a ffff ffff 1111 xxxx xxxx xxxx
Description: Location ‘f’ is negated using two’s Description: No operation.
complement. The result is placed in the
Words: 1
data memory location ‘f’.
Cycles: 1
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the Q Cycle Activity:
GPR bank (default). Q1 Q2 Q3 Q4
If ‘a’ is ‘0’ and the extended instruction Decode No No No
set is enabled, this instruction operates operation operation operation
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See Example:
Section 29.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed None.
Literal Offset Mode” for details.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read Process Write
register ‘f’ Data register ‘f’

Example: NEGF REG, 1

Before Instruction
REG = 0011 1010 [3Ah]
After Instruction
REG = 1100 0110 [C6h]

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POP Pop Top of Return Stack PUSH Push Top of Return Stack

Syntax: POP Syntax: PUSH

Operands: None Operands: None
Operation: (TOS)  bit bucket Operation: (PC + 2)  TOS
Status Affected: None Status Affected: None
Encoding: 0000 0000 0000 0110 Encoding: 0000 0000 0000 0101
Description: The TOS value is pulled off the return Description: The PC + 2 is pushed onto the top of
stack and is discarded. The TOS value the return stack. The previous TOS
then becomes the previous value that value is pushed down on the stack.
was pushed onto the return stack. This instruction allows implementing a
This instruction is provided to enable software stack by modifying TOS and
the user to properly manage the return then pushing it onto the return stack.
stack to incorporate a software stack.
Words: 1
Words: 1 Cycles: 1
Cycles: 1
Q Cycle Activity:
Q Cycle Activity: Q1 Q2 Q3 Q4
Q1 Q2 Q3 Q4 Decode PUSH No No
Decode No POP TOS No PC + 2 onto operation operation
operation value operation return stack

Example: POP Example: PUSH

GOTO NEW Before Instruction
Before Instruction TOS = 345Ah
TOS = 0031A2h PC = 0124h
Stack (1 level down) = 014332h
After Instruction
After Instruction PC = 0126h
TOS = 014332h TOS = 0126h
PC = NEW Stack (1 level down) = 345Ah

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RCALL Relative Call RESET Reset

Syntax: RCALL n Syntax: RESET

Operands: -1024  n  1023 Operands: None
Operation: (PC) + 2  TOS, Operation: Reset all registers and flags that are
(PC) + 2 + 2n  PC affected by a MCLR Reset.
Status Affected: None Status Affected: All
Encoding: 1101 1nnn nnnn nnnn Encoding: 0000 0000 1111 1111
Description: Subroutine call with a jump up to 1K Description: This instruction provides a way to
from the current location. First, return execute a MCLR Reset in software.
address (PC + 2) is pushed onto the
Words: 1
stack. Then, add the 2’s complement
number ‘2n’ to the PC. Since the PC will Cycles: 1
have incremented to fetch the next Q Cycle Activity:
instruction, the new address will be Q1 Q2 Q3 Q4
PC + 2 + 2n. This instruction is a
Decode Start No No
two-cycle instruction.
reset operation operation
Words: 1
Cycles: 2 Example: RESET
Q Cycle Activity: After Instruction
Q1 Q2 Q3 Q4 Registers = Reset Value
Decode Read literal Process Write to PC Flags* = Reset Value
‘n’ Data
PUSH PC
to stack
No No No No
operation operation operation operation

Example: HERE RCALL Jump

Before Instruction
PC = Address (HERE)
After Instruction
PC = Address (Jump)
TOS = Address (HERE + 2)

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RETFIE Return from Interrupt RETLW Return Literal to W

Syntax: RETFIE {s} Syntax: RETLW k

Operands: s  [0,1] Operands: 0  k  255
Operation: (TOS)  PC, Operation: k  W,
1  GIE/GIEH or PEIE/GIEL; (TOS)  PC,
if s = 1, PCLATU, PCLATH are unchanged
(WS)  W,
Status Affected: None
(STATUSS)  STATUS,
(BSRS)  BSR, Encoding: 0000 1100 kkkk kkkk
PCLATU, PCLATH are unchanged Description: W is loaded with the eight-bit literal ‘k’.
Status Affected: GIE/GIEH, PEIE/GIEL. The program counter is loaded from the
top of the stack (the return address).
Encoding: 0000 0000 0001 000s
The high address latch (PCLATH)
Description: Return from interrupt. Stack is popped remains unchanged.
and Top-of-Stack (TOS) is loaded into
Words: 1
the PC. Interrupts are enabled by
setting either the high or low-priority Cycles: 2
global interrupt enable bit. If ‘s’ = 1, the Q Cycle Activity:
contents of the shadow registers WS,
Q1 Q2 Q3 Q4
STATUSS and BSRS are loaded into
Decode Read Process POP PC
their corresponding registers W,
literal ‘k’ Data from stack,
STATUS and BSR. If ‘s’ = 0, no update
write to W
of these registers occurs (default).
No No No No
Words: 1
operation operation operation operation
Cycles: 2
Q Cycle Activity: Example:
Q1 Q2 Q3 Q4
Decode No No POP PC CALL TABLE ; W contains table
operation operation from stack ; offset value
; W now has
Set GIEH or
; table value
GIEL
:
No No No No TABLE
operation operation operation operation ADDWF PCL ; W = offset
RETLW k0 ; Begin table
Example: RETFIE 1 RETLW k1 ;
:
After Interrupt
:
PC = TOS
W = WS RETLW kn ; End of table
BSR = BSRS
STATUS = STATUSS
GIE/GIEH, PEIE/GIEL = 1 Before Instruction
W = 07h
After Instruction
W = value of kn

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RETURN Return from Subroutine RLCF Rotate Left f through Carry

Syntax: RETURN {s} Syntax: RLCF f {,d {,a}}

Operands: s  [0,1] Operands: 0  f  255
Operation: (TOS)  PC; d  [0,1]
a  [0,1]
if s = 1,
(WS)  W, Operation: (f<n>)  dest<n + 1>,
(STATUSS)  STATUS, (f<7>)  C,
(BSRS)  BSR, (C)  dest<0>
PCLATU, PCLATH are unchanged Status Affected: C, N, Z
Status Affected: None
Encoding: 0011 01da ffff ffff
Encoding: 0000 0000 0001 001s
Description: The contents of register ‘f’ are rotated
Description: Return from subroutine. The stack is one bit to the left through the Carry flag.
popped and the top of the stack (TOS) If ‘d’ is ‘0’, the result is placed in W. If ‘d’
is loaded into the program counter. If is ‘1’, the result is stored back in register
‘s’= 1, the contents of the shadow ‘f’ (default).
registers WS, STATUSS and BSRS are
If ‘a’ is ‘0’, the Access Bank is selected.
loaded into their corresponding
If ‘a’ is ‘1’, the BSR is used to select the
registers W, STATUS and BSR. If
GPR bank (default).
‘s’ = 0, no update of these registers
occurs (default). If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
Words: 1
in Indexed Literal Offset Addressing
Cycles: 2 mode whenever f 95 (5Fh). See
Section 29.2.3 “Byte-Oriented and
Q Cycle Activity:
Bit-Oriented Instructions in Indexed
Q1 Q2 Q3 Q4
Literal Offset Mode” for details.
Decode No Process POP PC
operation Data from stack C register f
No No No No
operation operation operation operation Words: 1
Cycles: 1
Q Cycle Activity:
Example: RETURN Q1 Q2 Q3 Q4
After Instruction: Decode Read Process Write to
PC = TOS register ‘f’ Data destination

Example: RLCF REG, 0, 0

Before Instruction
REG = 1110 0110
C = 0
After Instruction
REG = 1110 0110
W = 1100 1100
C = 1

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RLNCF Rotate Left f (No Carry) RRCF Rotate Right f through Carry

Syntax: RLNCF f {,d {,a}} Syntax: RRCF f {,d {,a}}

Operands: 0  f  255 Operands: 0  f  255
d  [0,1] d  [0,1]
a  [0,1] a  [0,1]
Operation: (f<n>)  dest<n + 1>, Operation: (f<n>)  dest<n – 1>,
(f<7>)  dest<0> (f<0>)  C,
(C)  dest<7>
Status Affected: N, Z
Status Affected: C, N, Z
Encoding: 0100 01da ffff ffff
Encoding: 0011 00da ffff ffff
Description: The contents of register ‘f’ are rotated
one bit to the left. If ‘d’ is ‘0’, the result Description: The contents of register ‘f’ are rotated
is placed in W. If ‘d’ is ‘1’, the result is one bit to the right through the Carry
stored back in register ‘f’ (default). flag. If ‘d’ is ‘0’, the result is placed in W.
If ‘d’ is ‘1’, the result is placed back in
If ‘a’ is ‘0’, the Access Bank is selected.
register ‘f’ (default).
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default). If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘0’ and the extended instruction If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
set is enabled, this instruction operates
in Indexed Literal Offset Addressing If ‘a’ is ‘0’ and the extended instruction
mode whenever f 95 (5Fh). See set is enabled, this instruction operates
Section 29.2.3 “Byte-Oriented and in Indexed Literal Offset Addressing
Bit-Oriented Instructions in Indexed mode whenever f 95 (5Fh). See
Literal Offset Mode” for details. Section 29.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
register f
Literal Offset Mode” for details.

Words: 1 C register f
Cycles: 1
Words: 1
Q Cycle Activity:
Cycles: 1
Q1 Q2 Q3 Q4
Decode Read Process Write to Q Cycle Activity:
register ‘f’ Data destination Q1 Q2 Q3 Q4
Decode Read Process Write to
Example: RLNCF REG, 1, 0 register ‘f’ Data destination

Before Instruction
REG = 1010 1011 Example: RRCF REG, 0, 0
After Instruction Before Instruction
REG = 0101 0111 REG = 1110 0110
C = 0
After Instruction
REG = 1110 0110
W = 0111 0011
C = 0

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RRNCF Rotate Right f (No Carry) SETF Set f

Syntax: RRNCF f {,d {,a}} Syntax: SETF f {,a}

Operands: 0  f  255 Operands: 0  f  255
d  [0,1] a [0,1]
a  [0,1]
Operation: FFh  f
Operation: (f<n>)  dest<n – 1>,
Status Affected: None
(f<0>)  dest<7>
Encoding: 0110 100a ffff ffff
Status Affected: N, Z
Description: The contents of the specified register
Encoding: 0100 00da ffff ffff
are set to FFh.
Description: The contents of register ‘f’ are rotated
If ‘a’ is ‘0’, the Access Bank is selected.
one bit to the right. If ‘d’ is ‘0’, the result
If ‘a’ is ‘1’, the BSR is used to select the
is placed in W. If ‘d’ is ‘1’, the result is GPR bank (default).
placed back in register ‘f’ (default).
If ‘a’ is ‘0’ and the extended instruction
If ‘a’ is ‘0’, the Access Bank will be
set is enabled, this instruction operates
selected, overriding the BSR value. If ‘a’
in Indexed Literal Offset Addressing
is ‘1’, then the bank will be selected as
mode whenever f 95 (5Fh). See
per the BSR value (default).
Section 29.2.3 “Byte-Oriented and
If ‘a’ is ‘0’ and the extended instruction Bit-Oriented Instructions in Indexed
set is enabled, this instruction operates Literal Offset Mode” for details.
in Indexed Literal Offset Addressing
Words: 1
mode whenever f 95 (5Fh). See
Section 29.2.3 “Byte-Oriented and Cycles: 1
Bit-Oriented Instructions in Indexed Q Cycle Activity:
Literal Offset Mode” for details.
Q1 Q2 Q3 Q4
register f Decode Read Process Write
register ‘f’ Data register ‘f’
Words: 1
Cycles: 1 Example: SETF REG,1
Q Cycle Activity: Before Instruction
Q1 Q2 Q3 Q4 REG = 5Ah
After Instruction
Decode Read Process Write to
REG = FFh
register ‘f’ Data destination

Example 1: RRNCF REG, 1, 0

Before Instruction
REG = 1101 0111
After Instruction
REG = 1110 1011

Example 2: RRNCF REG, 0, 0

Before Instruction
W = ?
REG = 1101 0111
After Instruction
W = 1110 1011
REG = 1101 0111

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SLEEP Enter Sleep Mode SUBFWB Subtract f from W with Borrow

Syntax: SLEEP Syntax: SUBFWB f {,d {,a}}

Operands: None Operands: 0 f 255
Operation: 00h  WDT, d  [0,1]
a  [0,1]
0  WDT postscaler,
1  TO, Operation: (W) – (f) – (C) dest
0  PD
Status Affected: N, OV, C, DC, Z
Status Affected: TO, PD Encoding: 0101 01da ffff ffff
Encoding: 0000 0000 0000 0011 Description: Subtract register ‘f’ and Carry flag
Description: The Power-Down status bit (PD) is (borrow) from W (2’s complement
cleared. The Time-out status bit (TO) method). If ‘d’ is ‘0’, the result is stored in
is set. The Watchdog Timer and its W. If ‘d’ is ‘1’, the result is stored in
postscaler are cleared. register ‘f’ (default).
The processor is put into Sleep mode If ‘a’ is ‘0’, the Access Bank is selected. If
with the oscillator stopped. ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
Words: 1
If ‘a’ is ‘0’ and the extended instruction
Cycles: 1
set is enabled, this instruction operates in
Q Cycle Activity: Indexed Literal Offset Addressing mode
Q1 Q2 Q3 Q4 whenever f 95 (5Fh). See
Decode No Process Go to Section 29.2.3 “Byte-Oriented and
operation Data Sleep Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.

Example: SLEEP Words: 1

Before Instruction Cycles: 1

TO = ? Q Cycle Activity:
PD = ? Q1 Q2 Q3 Q4
After Instruction Decode Read Process Write to
TO = 1† register ‘f’ Data destination
PD = 0
Example 1: SUBFWB REG, 1, 0
† If WDT causes wake-up, this bit is cleared. Before Instruction
REG = 3
W = 2
C = 1
After Instruction
REG = FF
W = 2
C = 0
Z = 0
N = 1 ; result is negative
Example 2: SUBFWB REG, 0, 0
Before Instruction
REG = 2
W = 5
C = 1
After Instruction
REG = 2
W = 3
C = 1
Z = 0
N = 0 ; result is positive
Example 3: SUBFWB REG, 1, 0
Before Instruction
REG = 1
W = 2
C = 0
After Instruction
REG = 0
W = 2
C = 1
Z = 1 ; result is zero
N = 0

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SUBLW Subtract W from Literal SUBWF Subtract W from f

Syntax: SUBLW k Syntax: SUBWF f {,d {,a}}

Operands: 0 k 255 Operands: 0 f 255
Operation: k – (W) W d  [0,1]
a  [0,1]
Status Affected: N, OV, C, DC, Z
Operation: (f) – (W) dest
Encoding: 0000 1000 kkkk kkkk
Status Affected: N, OV, C, DC, Z
Description: W is subtracted from the eight-bit
Encoding: 0101 11da ffff ffff
literal ‘k’. The result is placed in W.
Description: Subtract W from register ‘f’ (2’s
Words: 1
complement method). If ‘d’ is ‘0’, the
Cycles: 1 result is stored in W. If ‘d’ is ‘1’, the result
Q Cycle Activity: is stored back in register ‘f’ (default).
Q1 Q2 Q3 Q4 If ‘a’ is ‘0’, the Access Bank is selected.
Decode Read Process Write to If ‘a’ is ‘1’, the BSR is used to select the
literal ‘k’ Data W GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
Example 1: SUBLW 02h
set is enabled, this instruction operates
Before Instruction in Indexed Literal Offset Addressing
W = 01h mode whenever f 95 (5Fh). See
C = ? Section 29.2.3 “Byte-Oriented and
After Instruction Bit-Oriented Instructions in Indexed
W = 01h Literal Offset Mode” for details.
C = 1 ; result is positive
Z = 0 Words: 1
N = 0
Cycles: 1
Example 2: SUBLW 02h
Q Cycle Activity:
Before Instruction
Q1 Q2 Q3 Q4
W = 02h
C = ? Decode Read Process Write to
After Instruction register ‘f’ Data destination
W = 00h
C = 1 ; result is zero Example 1: SUBWF REG, 1, 0
Z = 1 Before Instruction
N = 0 REG = 3
Example 3: SUBLW 02h W = 2
C = ?
Before Instruction After Instruction
W = 03h REG = 1
C = ? W = 2
After Instruction C = 1 ; result is positive
W = FFh ; (2’s complement) Z = 0
C = 0 ; result is negative N = 0
Z = 0 Example 2: SUBWF REG, 0, 0
N = 1
Before Instruction
REG = 2
W = 2
C = ?
After Instruction
REG = 2
W = 0
C = 1 ; result is zero
Z = 1
N = 0
Example 3: SUBWF REG, 1, 0
Before Instruction
REG = 1
W = 2
C = ?
After Instruction
REG = FFh ;(2’s complement)
W = 2
C = 0 ; result is negative
Z = 0
N = 1

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SUBWFB Subtract W from f with Borrow SWAPF Swap f

Syntax: SUBWFB f {,d {,a}} Syntax: SWAPF f {,d {,a}}
Operands: 0  f  255 Operands: 0  f  255
d  [0,1] d  [0,1]
a  [0,1] a  [0,1]
Operation: (f) – (W) – (C) dest
Operation: (f<3:0>)  dest<7:4>,
Status Affected: N, OV, C, DC, Z (f<7:4>)  dest<3:0>
Encoding: 0101 10da ffff ffff Status Affected: None
Description: Subtract W and the Carry flag (borrow) Encoding: 0011 10da ffff ffff
from register ‘f’ (2’s complement
method). If ‘d’ is ‘0’, the result is stored Description: The upper and lower nibbles of register
in W. If ‘d’ is ‘1’, the result is stored back ‘f’ are exchanged. If ‘d’ is ‘0’, the result
in register ‘f’ (default). is placed in W. If ‘d’ is ‘1’, the result is
placed in register ‘f’ (default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the If ‘a’ is ‘0’, the Access Bank is selected.
GPR bank (default). If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates If ‘a’ is ‘0’ and the extended instruction
in Indexed Literal Offset Addressing set is enabled, this instruction operates
mode whenever f 95 (5Fh). See in Indexed Literal Offset Addressing
Section 29.2.3 “Byte-Oriented and mode whenever f 95 (5Fh). See
Bit-Oriented Instructions in Indexed Section 29.2.3 “Byte-Oriented and
Literal Offset Mode” for details. Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words: 1
Words: 1
Cycles: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4 Q Cycle Activity:
Decode Read Process Write to Q1 Q2 Q3 Q4
register ‘f’ Data destination Decode Read Process Write to
Example 1: SUBWFB REG, 1, 0 register ‘f’ Data destination
Before Instruction
REG = 19h (0001 1001) Example: SWAPF REG, 1, 0
W = 0Dh (0000 1101)
C = 1 Before Instruction
After Instruction REG = 53h
REG = 0Ch (0000 1011) After Instruction
W = 0Dh (0000 1101) REG = 35h
C = 1
Z = 0
N = 0 ; result is positive
Example 2: SUBWFB REG, 0, 0
Before Instruction
REG = 1Bh (0001 1011)
W = 1Ah (0001 1010)
C = 0
After Instruction
REG = 1Bh (0001 1011)
W = 00h
C = 1
Z = 1 ; result is zero
N = 0
Example 3: SUBWFB REG, 1, 0
Before Instruction
REG = 03h (0000 0011)
W = 0Eh (0000 1101)
C = 1
After Instruction
REG = F5h (1111 0100)
; [2’s comp]
W = 0Eh (0000 1101)
C = 0
Z = 0
N = 1 ; result is negative

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TBLRD Table Read TBLRD Table Read (Continued)

Syntax: TBLRD ( *; *+; *-; +*) Example 1: TBLRD *+ ;

Operands: None Before Instruction
TABLAT = 55h
Operation: if TBLRD *,
TBLPTR = 00A356h
(Prog Mem (TBLPTR))  TABLAT; MEMORY(00A356h) = 34h
TBLPTR – No Change After Instruction
if TBLRD *+, TABLAT = 34h
(Prog Mem (TBLPTR))  TABLAT; TBLPTR = 00A357h
(TBLPTR) + 1  TBLPTR Example 2: TBLRD +* ;
if TBLRD *-,
(Prog Mem (TBLPTR))  TABLAT; Before Instruction
(TBLPTR) – 1  TBLPTR TABLAT = AAh
TBLPTR = 01A357h
if TBLRD +*,
MEMORY(01A357h) = 12h
(TBLPTR) + 1  TBLPTR; MEMORY(01A358h) = 34h
(Prog Mem (TBLPTR))  TABLAT After Instruction
Status Affected: None TABLAT = 34h
TBLPTR = 01A358h
Encoding: 0000 0000 0000 10nn
nn=0 *
=1 *+
=2 *-
=3 +*
Description: This instruction is used to read the contents
of Program Memory (P.M.). To address the
program memory, a pointer called Table
Pointer (TBLPTR) is used.
The TBLPTR (a 21-bit pointer) points to
each byte in the program memory. TBLPTR
has a 2-Mbyte address range.
TBLPTR[0] = 0: Least Significant Byte of
Program Memory Word
TBLPTR[0] = 1: Most Significant Byte of
Program Memory Word
The TBLRD instruction can modify the value
of TBLPTR as follows:
• no change
• post-increment
• post-decrement
• pre-increment
Words: 1
Cycles: 2
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode No No No
operation operation operation
No No operation No No operation
operation (Read Program operation (Write
Memory) TABLAT)

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TBLWT Table Write TBLWT Table Write (Continued)

Syntax: TBLWT ( *; *+; *-; +*) Example 1: TBLWT *+;
Operands: None Before Instruction
Operation: if TBLWT*, TABLAT = 55h
(TABLAT)  Holding Register; TBLPTR = 00A356h
HOLDING REGISTER
TBLPTR – No Change
(00A356h) = FFh
if TBLWT*+,
After Instructions (table write completion)
(TABLAT)  Holding Register;
TABLAT = 55h
(TBLPTR) + 1  TBLPTR TBLPTR = 00A357h
if TBLWT*-, HOLDING REGISTER
(TABLAT)  Holding Register; (00A356h) = 55h
(TBLPTR) – 1  TBLPTR Example 2: TBLWT +*;
if TBLWT+*,
Before Instruction
(TBLPTR) + 1  TBLPTR;
TABLAT = 34h
(TABLAT)  Holding Register TBLPTR = 01389Ah
Status Affected: None HOLDING REGISTER
(01389Ah) = FFh
Encoding: 0000 0000 0000 11nn HOLDING REGISTER
nn=0 * (01389Bh) = FFh
=1 *+ After Instruction (table write completion)
=2 *- TABLAT = 34h
=3 +* TBLPTR = 01389Bh
HOLDING REGISTER
Description: This instruction uses the 3 LSBs of (01389Ah) = FFh
TBLPTR to determine which of the HOLDING REGISTER
8 holding registers the TABLAT is written (01389Bh) = 34h
to. The holding registers are used to
program the contents of Program Memory
(P.M.). (Refer to Section 6.0 “Memory
Organization” for additional details on
programming Flash memory.)
The TBLPTR (a 21-bit pointer) points to
each byte in the program memory.
TBLPTR has a 2-Mbyte address range.
The LSb of the TBLPTR selects which
byte of the program memory location to
access.
TBLPTR[0] = 0: Least Significant Byte
of Program Memory
Word
TBLPTR[0] = 1: Most Significant Byte
of Program Memory
Word
The TBLWT instruction can modify the
value of TBLPTR as follows:
• no change
• post-increment
• post-decrement
• pre-increment
Words: 1
Cycles: 2
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode No No No
operation operation operation
No No No No
operation operation operation operation
(Read (Write to
TABLAT) Holding
Register)

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TSTFSZ Test f, Skip if 0 XORLW Exclusive OR Literal with W

Syntax: TSTFSZ f {,a} Syntax: XORLW k

Operands: 0  f  255 Operands: 0 k 255
a  [0,1] Operation: (W) .XOR. k W
Operation: skip if f = 0
Status Affected: N, Z
Status Affected: None
Encoding: 0000 1010 kkkk kkkk
Encoding: 0110 011a ffff ffff
Description: The contents of W are XORed with
Description: If ‘f’ = 0, the next instruction fetched the 8-bit literal ‘k’. The result is placed
during the current instruction execution in W.
is discarded and a NOP is executed,
Words: 1
making this a two-cycle instruction.
Cycles: 1
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the Q Cycle Activity:
GPR bank (default). Q1 Q2 Q3 Q4
If ‘a’ is ‘0’ and the extended instruction Decode Read Process Write to
set is enabled, this instruction operates literal ‘k’ Data W
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See Example: XORLW 0AFh
Section 29.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed Before Instruction
Literal Offset Mode” for details. W = B5h
After Instruction
Words: 1 W = 1Ah
Cycles: 1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read Process No
register ‘f’ Data operation
If skip:
Q1 Q2 Q3 Q4
No No No No
operation operation operation operation
If skip and followed by 2-word instruction:
Q1 Q2 Q3 Q4
No No No No
operation operation operation operation
No No No No
operation operation operation operation

Example: HERE TSTFSZ CNT, 1

NZERO :
ZERO :
Before Instruction
PC = Address (HERE)
After Instruction
If CNT = 00h,
PC = Address (ZERO)
If CNT  00h,
PC = Address (NZERO)

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XORWF Exclusive OR W with f

Syntax: XORWF f {,d {,a}}

Operands: 0  f  255
d  [0,1]
a  [0,1]
Operation: (W) .XOR. (f) dest
Status Affected: N, Z
Encoding: 0001 10da ffff ffff
Description: Exclusive OR the contents of W with
register ‘f’. If ‘d’ is ‘0’, the result is stored
in W. If ‘d’ is ‘1’, the result is stored back
in the register ‘f’ (default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 29.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read Process Write to
register ‘f’ Data destination

Example: XORWF REG, 1, 0

Before Instruction
REG = AFh
W = B5h
After Instruction
REG = 1Ah
W = B5h

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29.2 Extended Instruction Set A summary of the instructions in the extended instruc-
tion set is provided in Table 29-3. Detailed descriptions
In addition to the standard 75 instructions of the PIC18 are provided in Section 29.2.2 “Extended Instruction
instruction set, the PIC18F47J53 family of devices also Set”. The opcode field descriptions in Table 29-1
provide an optional extension to the core CPU function- (page 460) apply to both the standard and extended
ality. The added features include eight additional PIC18 instruction sets.
instructions that augment Indirect and Indexed
Addressing operations and the implementation of Note: The instruction set extension and the
Indexed Literal Offset Addressing for many of the Indexed Literal Offset Addressing mode
standard PIC18 instructions. were designed for optimizing applications
written in C; the user may likely never use
The additional features of the extended instruction set
these instructions directly in assembler.
are enabled by default on unprogrammed devices.
The syntax for these commands is
Users must properly set or clear the XINST Configura-
provided as a reference for users who may
tion bit during programming to enable or disable these
be reviewing code that has been
features.
generated by a compiler.
The instructions in the extended set can all be
classified as literal operations, which either manipulate 29.2.1 EXTENDED INSTRUCTION SYNTAX
the File Select Registers, or use them for Indexed
Most of the extended instructions use indexed argu-
Addressing. Two of the instructions, ADDFSR and
ments, using one of the File Select Registers and some
SUBFSR, each have an additional special instantiation
offset to specify a source or destination register. When
for using FSR2. These versions (ADDULNK and
an argument for an instruction serves as part of
SUBULNK) allow for automatic return after execution.
Indexed Addressing, it is enclosed in square brackets
The extended instructions are specifically implemented (“[ ]”). This is done to indicate that the argument is used
to optimize re-entrant program code (that is, code that as an index or offset. The MPASM™ Assembler will
is recursive or that uses a software stack) written in flag an error if it determines that an index or offset value
high-level languages, particularly C. Among other is not bracketed.
things, they allow users working in high-level
When the extended instruction set is enabled, brackets
languages to perform certain operations on data
are also used to indicate index arguments in
structures more efficiently. These include:
byte-oriented and bit-oriented instructions. This is in
• Dynamic allocation and deallocation of software addition to other changes in their syntax. For more
stack space when entering and leaving details, see Section 29.2.3.1 “Extended Instruction
subroutines Syntax with Standard PIC18 Commands”.
• Function Pointer invocation
Note: In the past, square brackets have been
• Software Stack Pointer manipulation used to denote optional arguments in the
• Manipulation of variables located in a software PIC18 and earlier instruction sets. In this
stack text and going forward, optional
arguments are denoted by braces (“{ }”).

TABLE 29-3: EXTENSIONS TO THE PIC18 INSTRUCTION SET

Mnemonic, 16-Bit Instruction Word Status
Description Cycles
Operands MSb LSb Affected

ADDFSR f, k Add Literal to FSR 1 1110 1000 ffkk kkkk None

ADDULNK k Add Literal to FSR2 and Return 2 1110 1000 11kk kkkk None
CALLW Call Subroutine using WREG 2 0000 0000 0001 0100 None
MOVSF zs, fd Move zs (source) to 1st word 2 1110 1011 0zzz zzzz None
fd (destination) 2nd word 1111 ffff ffff ffff
MOVSS zs, zd Move zs (source) to 1st word 2 1110 1011 1zzz zzzz None
zd (destination) 2nd word 1111 xxxx xzzz zzzz
PUSHL k Store Literal at FSR2, 1 1110 1010 kkkk kkkk None
Decrement FSR2
SUBFSR f, k Subtract Literal from FSR 1 1110 1001 ffkk kkkk None
SUBULNK k Subtract Literal from FSR2 and 2 1110 1001 11kk kkkk None
return

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29.2.2 EXTENDED INSTRUCTION SET

ADDFSR Add Literal to FSR ADDULNK Add Literal to FSR2 and Return
Syntax: ADDFSR f, k Syntax: ADDULNK k
Operands: 0  k  63 Operands: 0  k  63
f  [ 0, 1, 2 ] Operation: FSR2 + k  FSR2,
Operation: FSR(f) + k  FSR(f) (TOS) PC
Status Affected: None Status Affected: None
Encoding: 1110 1000 ffkk kkkk Encoding: 1110 1000 11kk kkkk
Description: The 6-bit literal ‘k’ is added to the Description: The 6-bit literal ‘k’ is added to the
contents of the FSR specified by ‘f’. contents of FSR2. A RETURN is then
Words: 1 executed by loading the PC with the
TOS.
Cycles: 1
Q Cycle Activity: The instruction takes two cycles to
execute; a NOP is performed during
Q1 Q2 Q3 Q4
the second cycle.
Decode Read Process Write to
literal ‘k’ Data FSR This may be thought of as a special
case of the ADDFSR instruction,
where f = 3 (binary ‘11’); it operates
Example: ADDFSR 2, 23h only on FSR2.
Words: 1
Before Instruction
FSR2 = 03FFh Cycles: 2
After Instruction Q Cycle Activity:
FSR2 = 0422h Q1 Q2 Q3 Q4
Decode Read Process Write to
literal ‘k’ Data FSR
No No No No
Operation Operation Operation Operation

Example: ADDULNK 23h

Before Instruction
FSR2 = 03FFh
PC = 0100h
After Instruction
FSR2 = 0422h
PC = (TOS)

Note: All PIC18 instructions may take an optional label argument preceding the instruction mnemonic for use in
symbolic addressing. If a label is used, the instruction format then becomes: {label} instruction argument(s).

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CALLW Subroutine Call Using WREG MOVSF Move Indexed to f

Syntax: CALLW Syntax: MOVSF [zs], fd

Operands: None Operands: 0  zs  127
0  fd  4095
Operation: (PC + 2)  TOS,
(W)  PCL, Operation: ((FSR2) + zs)  fd
(PCLATH)  PCH, Status Affected: None
(PCLATU)  PCU
Encoding:
Status Affected: None 1st word (source) 1110 1011 0zzz zzzzs
Encoding: 0000 0000 0001 0100 2nd word (destin.) 1111 ffff ffff ffffd
Description First, the return address (PC + 2) is Description: The contents of the source register are
pushed onto the return stack. Next, the moved to destination register ‘fd’. The
contents of W are written to PCL; the actual address of the source register is
existing value is discarded. Then, the determined by adding the 7-bit literal
contents of PCLATH and PCLATU are offset ‘zs’, in the first word, to the value
latched into PCH and PCU, of FSR2. The address of the destination
respectively. The second cycle is register is specified by the 12-bit literal
executed as a NOP instruction while the ‘fd’ in the second word. Both addresses
new next instruction is fetched. can be anywhere in the 4096-byte data
space (000h to FFFh).
Unlike CALL, there is no option to
update W, STATUS or BSR. The MOVSF instruction cannot use the
PCL, TOSU, TOSH or TOSL as the
Words: 1
destination register.
Cycles: 2
If the resultant source address points to
Q Cycle Activity: an Indirect Addressing register, the
Q1 Q2 Q3 Q4 value returned will be 00h.
Decode Read Push PC to No Words: 2
WREG stack operation
Cycles: 2
No No No No
operation operation operation operation Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Determine Determine Read
Example: HERE CALLW source addr source addr source reg
Before Instruction Decode No No Write
PC = address (HERE) operation operation register ‘f’
PCLATH = 10h (dest)
PCLATU = 00h No dummy
W = 06h read
After Instruction
PC = 001006h
TOS = address (HERE + 2) Example: MOVSF [05h], REG2
PCLATH = 10h
PCLATU = 00h Before Instruction
W = 06h FSR2 = 80h
Contents
of 85h = 33h
REG2 = 11h
After Instruction
FSR2 = 80h
Contents
of 85h = 33h
REG2 = 33h

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MOVSS Move Indexed to Indexed PUSHL Store Literal at FSR2, Decrement FSR2
Syntax: MOVSS [zs], [zd] Syntax: PUSHL k
Operands: 0  zs  127 Operands: 0k  255
0  zd  127
Operation: k  (FSR2),
Operation: ((FSR2) + zs)  ((FSR2) + zd) FSR2 – 1  FSR2
Status Affected: None
Status Affected: None
Encoding:
Encoding: 1111 1010 kkkk kkkk
1st word (source) 1110 1011 1zzz zzzzs
2nd word (dest.) 1111 xxxx xzzz zzzzd Description: The 8-bit literal ‘k’ is written to the data
Description The contents of the source register are memory address specified by FSR2.
FSR2 is decremented by 1 after the
moved to the destination register. The
addresses of the source and destination operation.
registers are determined by adding the This instruction allows users to push
7-bit literal offsets, ‘zs’ or ‘zd’, values onto a software stack.
respectively, to the value of FSR2. Both
Words: 1
registers can be located anywhere in
the 4096-byte data memory space Cycles: 1
(000h to FFFh). Q Cycle Activity:
The MOVSS instruction cannot use the Q1 Q2 Q3 Q4
PCL, TOSU, TOSH or TOSL as the Decode Read ‘k’ Process Write to
destination register. data destination
If the resultant source address points to
an Indirect Addressing register, the
value returned will be 00h. If the Example: PUSHL 08h
resultant destination address points to Before Instruction
an Indirect Addressing register, the FSR2H:FSR2L = 01ECh
instruction will execute as a NOP. Memory (01ECh) = 00h
Words: 2
After Instruction
Cycles: 2 FSR2H:FSR2L = 01EBh
Q Cycle Activity: Memory (01ECh) = 08h
Q1 Q2 Q3 Q4
Decode Determine Determine Read
source addr source addr source reg
Decode Determine Determine Write
dest addr dest addr to dest reg

Example: MOVSS [05h], [06h]

Before Instruction
FSR2 = 80h
Contents
of 85h = 33h
Contents
of 86h = 11h
After Instruction
FSR2 = 80h
Contents
of 85h = 33h
Contents
of 86h = 33h

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 PIC18F47J53 FAMILY

SUBFSR Subtract Literal from FSR SUBULNK Subtract Literal from FSR2 and Return
Syntax: SUBFSR f, k Syntax: SUBULNK k
Operands: 0  k  63 Operands: 0  k  63
f  [ 0, 1, 2 ] Operation: FSR2 – k  FSR2,
Operation: FSRf – k  FSRf (TOS) PC
Status Affected: None Status Affected: None
Encoding: 1110 1001 ffkk kkkk Encoding: 1110 1001 11kk kkkk
Description: The 6-bit literal ‘k’ is subtracted from Description: The 6-bit literal ‘k’ is subtracted from the
the contents of the FSR specified contents of the FSR2. A RETURN is then
by ‘f’. executed by loading the PC with the
TOS.
Words: 1
Cycles: 1 The instruction takes two cycles to
execute; a NOP is performed during the
Q Cycle Activity:
second cycle.
Q1 Q2 Q3 Q4
This may be thought of as a special case
Decode Read Process Write to
of the SUBFSR instruction, where f = 3
register ‘f’ Data destination
(binary ‘11’); it operates only on FSR2.
Words: 1
Example: SUBFSR 2, 23h Cycles: 2
Before Instruction Q Cycle Activity:
FSR2 = 03FFh Q1 Q2 Q3 Q4
After Instruction Decode Read Process Write to
FSR2 = 03DCh register ‘f’ Data destination
No No No No
Operation Operation Operation Operation

Example: SUBULNK 23h

Before Instruction
FSR2 = 03FFh
PC = 0100h
After Instruction
FSR2 = 03DCh
PC = (TOS)

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29.2.3 BYTE-ORIENTED AND 29.2.3.1 Extended Instruction Syntax with
BIT-ORIENTED INSTRUCTIONS IN Standard PIC18 Commands
INDEXED LITERAL OFFSET MODE When the extended instruction set is enabled, the file
Note: Enabling the PIC18 instruction set exten- register argument ‘f’ in the standard byte-oriented and
sion may cause legacy applications to bit-oriented commands is replaced with the literal offset
behave erratically or fail entirely. value ‘k’. As already noted, this occurs only when ‘f’ is
less than or equal to 5Fh. When an offset value is used,
In addition to eight new commands in the extended set, it must be indicated by square brackets (“[ ]”). As with
enabling the extended instruction set also enables the extended instructions, the use of brackets indicates
Indexed Literal Offset Addressing (Section 6.6.1 to the compiler that the value is to be interpreted as an
“Indexed Addressing with Literal Offset”). This has index or an offset. Omitting the brackets, or using a
a significant impact on the way that many commands of value greater than 5Fh within the brackets, will
the standard PIC18 instruction set are interpreted. generate an error in the MPASM Assembler.
When the extended set is disabled, addresses embed- If the index argument is properly bracketed for Indexed
ded in opcodes are treated as literal memory locations: Literal Offset Addressing, the Access RAM argument is
either as a location in the Access Bank (a = 0) or in a never specified; it will automatically be assumed to be
GPR bank designated by the BSR (a = 1). When the ‘0’. This is in contrast to standard operation (extended
extended instruction set is enabled and a = 0, however, instruction set disabled), when ‘a’ is set on the basis of
a file register argument of 5Fh or less is interpreted as the target address. Declaring the Access RAM bit in
an offset from the pointer value in FSR2 and not as a this mode will also generate an error in the MPASM
literal address. For practical purposes, this means that Assembler.
all instructions that use the Access RAM bit as an
argument – that is, all byte-oriented and bit-oriented The destination argument ‘d’ functions as before.
instructions, or almost half of the core PIC18 instruc- In the latest versions of the MPASM Assembler,
tions – may behave differently when the extended language support for the extended instruction set must
instruction set is enabled. be explicitly invoked. This is done with either the
When the content of FSR2 is 00h, the boundaries of the command line option, /y, or the PE directive in the
Access RAM are essentially remapped to their original source listing.
values. This may be useful in creating
backward-compatible code. If this technique is used, it 29.2.4 CONSIDERATIONS WHEN
may be necessary to save the value of FSR2 and ENABLING THE EXTENDED
restore it when moving back and forth between C and INSTRUCTION SET
assembly routines in order to preserve the Stack It is important to note that the extensions to the instruc-
Pointer. Users must also keep in mind the syntax tion set may not be beneficial to all users. In particular,
requirements of the extended instruction set (see users who are not writing code that uses a software
Section 29.2.3.1 “Extended Instruction Syntax with stack may not benefit from using the extensions to the
Standard PIC18 Commands”). instruction set.
Although the Indexed Literal Offset mode can be very Additionally, the Indexed Literal Offset Addressing
useful for dynamic stack and pointer manipulation, it mode may create issues with legacy applications
can also be very annoying if a simple arithmetic opera- written to the PIC18 assembler. This is because
tion is carried out on the wrong register. Users who are instructions in the legacy code may attempt to address
accustomed to the PIC18 programming must keep in registers in the Access Bank below 5Fh. Since these
mind that, when the extended instruction set is addresses are interpreted as literal offsets to FSR2
enabled, register addresses of 5Fh or less are used for when the instruction set extension is enabled, the
Indexed Literal Offset Addressing. application may read or write to the wrong data
Representative examples of typical byte-oriented and addresses.
bit-oriented instructions in the Indexed Literal Offset When porting an application to the PIC18F47J53 fam-
mode are provided on the following page to show how ily, it is very important to consider the type of code. A
execution is affected. The operand conditions shown in large, re-entrant application that is written in C and
the examples are applicable to all instructions of these would benefit from efficient compilation will do well
types. when using the instruction set extensions. Legacy
applications that heavily use the Access Bank will most
likely not benefit from using the extended instruction
set.

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 PIC18F47J53 FAMILY

ADD W to Indexed Bit Set Indexed

ADDWF BSF
(Indexed Literal Offset mode) (Indexed Literal Offset mode)

Syntax: ADDWF [k] {,d} Syntax: BSF [k], b

Operands: 0  k  95 Operands: 0  f  95
d  [0,1] 0b7
Operation: (W) + ((FSR2) + k)  dest Operation: 1  ((FSR2) + k)<b>
Status Affected: N, OV, C, DC, Z Status Affected: None
Encoding: 0010 01d0 kkkk kkkk Encoding: 1000 bbb0 kkkk kkkk
Description: The contents of W are added to the Description: Bit ‘b’ of the register indicated by FSR2,
contents of the register indicated by offset by the value ‘k’, is set.
FSR2, offset by the value ‘k’.
Words: 1
If ‘d’ is ‘0’, the result is stored in W. If ‘d’
Cycles: 1
is ‘1’, the result is stored back in
register ‘f’ (default). Q Cycle Activity:
Q1 Q2 Q3 Q4
Words: 1
Decode Read Process Write to
Cycles: 1
register ‘f’ Data destination
Q Cycle Activity:
Q1 Q2 Q3 Q4 Example: BSF [FLAG_OFST], 7
Decode Read ‘k’ Process Write to Before Instruction
Data destination FLAG_OFST = 0Ah
FSR2 = 0A00h
Example: ADDWF [OFST] ,0 Contents
of 0A0Ah = 55h
Before Instruction After Instruction
W = 17h Contents
OFST = 2Ch of 0A0Ah = D5h
FSR2 = 0A00h
Contents
of 0A2Ch = 20h
After Instruction Set Indexed
SETF
W = 37h (Indexed Literal Offset mode)
Contents
of 0A2Ch = 20h Syntax: SETF [k]
Operands: 0  k  95
Operation: FFh  ((FSR2) + k)
Status Affected: None
Encoding: 0110 1000 kkkk kkkk
Description: The contents of the register indicated by
FSR2, offset by ‘k’, are set to FFh.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read ‘k’ Process Write
Data register

Example: SETF [OFST]

Before Instruction
OFST = 2Ch
FSR2 = 0A00h
Contents
of 0A2Ch = 00h
After Instruction
Contents
of 0A2Ch = FFh

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29.2.5 SPECIAL CONSIDERATIONS WITH To develop software for the extended instruction set,
MICROCHIP MPLAB® IDE TOOLS the user must enable support for the instructions and
the Indexed Addressing mode in their language tool(s).
The latest versions of Microchip’s software tools have Depending on the environment being used, this may be
been designed to fully support the extended instruction done in several ways:
set for the PIC18F47J53 family. This includes the
MPLAB C18 C Compiler, MPASM assembly language • A menu option or dialog box within the
and MPLAB Integrated Development Environment environment that allows the user to configure the
(IDE). language tool and its settings for the project
• A command line option
When selecting a target device for software
development, MPLAB IDE will automatically set default • A directive in the source code
Configuration bits for that device. The default setting for These options vary between different compilers,
the XINST Configuration bit is ‘0’, disabling the assemblers and development environments. Users are
extended instruction set and Indexed Literal Offset encouraged to review the documentation accompany-
Addressing. For proper execution of applications ing their development systems for the appropriate
developed to take advantage of the extended information.
instruction set, XINST must be set during
programming.

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 PIC18F47J53 FAMILY
30.0 DEVELOPMENT SUPPORT 30.1 MPLAB Integrated Development
Environment Software
The PIC® microcontrollers and dsPIC® digital signal
controllers are supported with a full range of software The MPLAB IDE software brings an ease of software
and hardware development tools: development previously unseen in the 8/16/32-bit
• Integrated Development Environment microcontroller market. The MPLAB IDE is a Windows®
operating system-based application that contains:
- MPLAB® IDE Software
• Compilers/Assemblers/Linkers • A single graphical interface to all debugging tools
- MPLAB C Compiler for Various Device - Simulator
Families - Programmer (sold separately)
- HI-TECH C for Various Device Families - In-Circuit Emulator (sold separately)
- MPASMTM Assembler - In-Circuit Debugger (sold separately)
- MPLINKTM Object Linker/ • A full-featured editor with color-coded context
MPLIBTM Object Librarian • A multiple project manager
- MPLAB Assembler/Linker/Librarian for • Customizable data windows with direct edit of
Various Device Families contents
• Simulators • High-level source code debugging
- MPLAB SIM Software Simulator • Mouse over variable inspection
• Emulators • Drag and drop variables from source to watch
- MPLAB REAL ICE™ In-Circuit Emulator windows
• In-Circuit Debuggers • Extensive on-line help
- MPLAB ICD 3 • Integration of select third party tools, such as
- PICkit™ 3 Debug Express IAR C Compilers
• Device Programmers The MPLAB IDE allows you to:
- PICkit™ 2 Programmer • Edit your source files (either C or assembly)
- MPLAB PM3 Device Programmer • One-touch compile or assemble, and download to
• Low-Cost Demonstration/Development Boards, emulator and simulator tools (automatically
Evaluation Kits, and Starter Kits updates all project information)
• Debug using:
- Source files (C or assembly)
- Mixed C and assembly
- Machine code
MPLAB IDE supports multiple debugging tools in a
single development paradigm, from the cost-effective
simulators, through low-cost in-circuit debuggers, to
full-featured emulators. This eliminates the learning
curve when upgrading to tools with increased flexibility
and power.

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30.2 MPLAB C Compilers for Various 30.5 MPLINK Object Linker/
Device Families MPLIB Object Librarian
The MPLAB C Compiler code development systems The MPLINK Object Linker combines relocatable
are complete ANSI C compilers for Microchip’s PIC18, objects created by the MPASM Assembler and the
PIC24 and PIC32 families of microcontrollers and the MPLAB C18 C Compiler. It can link relocatable objects
dsPIC30 and dsPIC33 families of digital signal control- from precompiled libraries, using directives from a
lers. These compilers provide powerful integration linker script.
capabilities, superior code optimization and ease of The MPLIB Object Librarian manages the creation and
use. modification of library files of precompiled code. When
For easy source level debugging, the compilers provide a routine from a library is called from a source file, only
symbol information that is optimized to the MPLAB IDE the modules that contain that routine will be linked in
debugger. with the application. This allows large libraries to be
used efficiently in many different applications.
30.3 HI-TECH C for Various Device The object linker/library features include:
Families • Efficient linking of single libraries instead of many
The HI-TECH C Compiler code development systems smaller files
are complete ANSI C compilers for Microchip’s PIC • Enhanced code maintainability by grouping
family of microcontrollers and the dsPIC family of digital related modules together
signal controllers. These compilers provide powerful • Flexible creation of libraries with easy module
integration capabilities, omniscient code generation listing, replacement, deletion and extraction
and ease of use.
For easy source level debugging, the compilers provide 30.6 MPLAB Assembler, Linker and
symbol information that is optimized to the MPLAB IDE Librarian for Various Device
debugger. Families
The compilers include a macro assembler, linker, pre-
MPLAB Assembler produces relocatable machine
processor, and one-step driver, and can run on multiple
code from symbolic assembly language for PIC24,
platforms.
PIC32 and dsPIC devices. MPLAB C Compiler uses
the assembler to produce its object file. The assembler
30.4 MPASM Assembler generates relocatable object files that can then be
The MPASM Assembler is a full-featured, universal archived or linked with other relocatable object files and
macro assembler for PIC10/12/16/18 MCUs. archives to create an executable file. Notable features
of the assembler include:
The MPASM Assembler generates relocatable object
files for the MPLINK Object Linker, Intel® standard HEX • Support for the entire device instruction set
files, MAP files to detail memory usage and symbol • Support for fixed-point and floating-point data
reference, absolute LST files that contain source lines • Command line interface
and generated machine code and COFF files for • Rich directive set
debugging.
• Flexible macro language
The MPASM Assembler features include: • MPLAB IDE compatibility
• Integration into MPLAB IDE projects
• User-defined macros to streamline
assembly code
• Conditional assembly for multi-purpose
source files
• Directives that allow complete control over the
assembly process

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 PIC18F47J53 FAMILY
30.7 MPLAB SIM Software Simulator 30.9 MPLAB ICD 3 In-Circuit Debugger
The MPLAB SIM Software Simulator allows code
System
development in a PC-hosted environment by simulat- MPLAB ICD 3 In-Circuit Debugger System is Micro-
ing the PIC MCUs and dsPIC® DSCs on an instruction chip's most cost effective high-speed hardware
level. On any given instruction, the data areas can be debugger/programmer for Microchip Flash Digital Sig-
examined or modified and stimuli can be applied from nal Controller (DSC) and microcontroller (MCU)
a comprehensive stimulus controller. Registers can be devices. It debugs and programs PIC® Flash microcon-
logged to files for further run-time analysis. The trace trollers and dsPIC® DSCs with the powerful, yet easy-
buffer and logic analyzer display extend the power of to-use graphical user interface of MPLAB Integrated
the simulator to record and track program execution, Development Environment (IDE).
actions on I/O, most peripherals and internal registers.
The MPLAB ICD 3 In-Circuit Debugger probe is con-
The MPLAB SIM Software Simulator fully supports nected to the design engineer's PC using a high-speed
symbolic debugging using the MPLAB C Compilers, USB 2.0 interface and is connected to the target with a
and the MPASM and MPLAB Assemblers. The soft- connector compatible with the MPLAB ICD 2 or MPLAB
ware simulator offers the flexibility to develop and REAL ICE systems (RJ-11). MPLAB ICD 3 supports all
debug code outside of the hardware laboratory envi- MPLAB ICD 2 headers.
ronment, making it an excellent, economical software
development tool. 30.10 PICkit 3 In-Circuit Debugger/
Programmer and
30.8 MPLAB REAL ICE In-Circuit
PICkit 3 Debug Express
Emulator System
The MPLAB PICkit 3 allows debugging and program-
MPLAB REAL ICE In-Circuit Emulator System is ming of PIC® and dsPIC® Flash microcontrollers at a
Microchip’s next generation high-speed emulator for most affordable price point using the powerful graphical
Microchip Flash DSC and MCU devices. It debugs and user interface of the MPLAB Integrated Development
programs PIC® Flash MCUs and dsPIC® Flash DSCs Environment (IDE). The MPLAB PICkit 3 is connected
with the easy-to-use, powerful graphical user interface of to the design engineer's PC using a full speed USB
the MPLAB Integrated Development Environment (IDE), interface and can be connected to the target via an
included with each kit. Microchip debug (RJ-11) connector (compatible with
The emulator is connected to the design engineer’s PC MPLAB ICD 3 and MPLAB REAL ICE). The connector
using a high-speed USB 2.0 interface and is connected uses two device I/O pins and the reset line to imple-
to the target with either a connector compatible with in- ment in-circuit debugging and In-Circuit Serial Pro-
circuit debugger systems (RJ11) or with the new high- gramming™.
speed, noise tolerant, Low-Voltage Differential Signal The PICkit 3 Debug Express include the PICkit 3, demo
(LVDS) interconnection (CAT5). board and microcontroller, hookup cables and CDROM
The emulator is field upgradable through future firmware with user’s guide, lessons, tutorial, compiler and
downloads in MPLAB IDE. In upcoming releases of MPLAB IDE software.
MPLAB IDE, new devices will be supported, and new
features will be added. MPLAB REAL ICE offers signifi-
cant advantages over competitive emulators including
low-cost, full-speed emulation, run-time variable
watches, trace analysis, complex breakpoints, a rugge-
dized probe interface and long (up to three meters) inter-
connection cables.

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30.11 PICkit 2 Development 30.13 Demonstration/Development
Programmer/Debugger and Boards, Evaluation Kits, and
PICkit 2 Debug Express Starter Kits
The PICkit™ 2 Development Programmer/Debugger is A wide variety of demonstration, development and
a low-cost development tool with an easy to use inter- evaluation boards for various PIC MCUs and dsPIC
face for programming and debugging Microchip’s Flash DSCs allows quick application development on fully func-
families of microcontrollers. The full featured tional systems. Most boards include prototyping areas for
Windows® programming interface supports baseline adding custom circuitry and provide application firmware
(PIC10F, PIC12F5xx, PIC16F5xx), midrange and source code for examination and modification.
(PIC12F6xx, PIC16F), PIC18F, PIC24, dsPIC30, The boards support a variety of features, including LEDs,
dsPIC33, and PIC32 families of 8-bit, 16-bit, and 32-bit temperature sensors, switches, speakers, RS-232
microcontrollers, and many Microchip Serial EEPROM interfaces, LCD displays, potentiometers and additional
products. With Microchip’s powerful MPLAB Integrated EEPROM memory.
Development Environment (IDE) the PICkit™ 2
enables in-circuit debugging on most PIC® microcon- The demonstration and development boards can be
trollers. In-Circuit-Debugging runs, halts and single used in teaching environments, for prototyping custom
steps the program while the PIC microcontroller is circuits and for learning about various microcontroller
embedded in the application. When halted at a break- applications.
point, the file registers can be examined and modified. In addition to the PICDEM™ and dsPICDEM™ demon-
The PICkit 2 Debug Express include the PICkit 2, demo stration/development board series of circuits, Microchip
board and microcontroller, hookup cables and CDROM has a line of evaluation kits and demonstration software
with user’s guide, lessons, tutorial, compiler and for analog filter design, KEELOQ® security ICs, CAN,
MPLAB IDE software. IrDA®, PowerSmart battery management, SEEVAL®
evaluation system, Sigma-Delta ADC, flow rate
sensing, plus many more.
30.12 MPLAB PM3 Device Programmer
Also available are starter kits that contain everything
The MPLAB PM3 Device Programmer is a universal, needed to experience the specified device. This usually
CE compliant device programmer with programmable includes a single application and debug capability, all
voltage verification at VDDMIN and VDDMAX for on one board.
maximum reliability. It features a large LCD display
(128 x 64) for menus and error messages and a modu- Check the Microchip web page (www.microchip.com)
lar, detachable socket assembly to support various for the complete list of demonstration, development
package types. The ICSP™ cable assembly is included and evaluation kits.
as a standard item. In Stand-Alone mode, the MPLAB
PM3 Device Programmer can read, verify and program
PIC devices without a PC connection. It can also set
code protection in this mode. The MPLAB PM3
connects to the host PC via an RS-232 or USB cable.
The MPLAB PM3 has high-speed communications and
optimized algorithms for quick programming of large
memory devices and incorporates an MMC card for file
storage and data applications.

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 PIC18F47J53 FAMILY
31.0 ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings(†)

Ambient temperature under bias.............................................................................................................-40°C to +125°C
Storage temperature .............................................................................................................................. -65°C to +150°C
Voltage on any digital only I/O pin or MCLR with respect to VSS (except VDD) ........................................... -0.3V to 6.0V
Voltage on any combined digital and analog pin with respect to VSS (except VDD)........................ -0.3V to (VDD + 0.3V)
Voltage on VDDCORE with respect to VSS ................................................................................................... -0.3V to 2.75V
Voltage on VDD with respect to VSS ........................................................................................................... -0.3V to 4.0V
Voltage on VUSB with respect to VSS................................................................................................ (VDD – 0.3V) to 4.0V
Total power dissipation (Note 1) ...............................................................................................................................1.0W
Maximum current out of VSS pin ...........................................................................................................................300 mA
Maximum current into VDD pin ..............................................................................................................................250 mA
Maximum output current sunk by any PORTB, PORTC and RA6 I/O pin...............................................................25 mA
Maximum output current sunk by any PORTA (except RA6), PORTD and PORTE I/O pin......................................8 mA
Maximum output current sourced by any PORTB, PORTC and RA6 I/O pin .........................................................25 mA
Maximum output current sourced by any PORTA (except RA6), PORTD and PORTE I/O pin ................................8 mA
Maximum current sunk byall ports .......................................................................................................................200 mA
Maximum current sourced by all ports ..................................................................................................................200 mA
Note 1: Power dissipation is calculated as follows:
PDIS = VDD x {IDD –  IOH} +  {(VDD – VOH) x IOH} +  (VOL x IOL)

† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.

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PIC18F47J53 FAMILY
FIGURE 31-1: PIC18F47J53 FAMILY VDD FREQUENCY GRAPH (INDUSTRIAL)

4.0V
3.6V
3.5V

3.0V Valid Operating Range

Voltage (VDD)

2.5V
2.35V(1)
2.15V

8 MHz 48 MHz
0
Frequency

Note 1: When the USB module is enabled, VUSB should be provided 3.0V-3.6V while VDD must be 2.35V. When the USB
module is not enabled, the wider limits shaded in grey apply. VUSB should be maintained  VDD, but may optionally
be high-impedance when the USB module is not in use.

FIGURE 31-2: PIC18LF47J53 FAMILY VDDCORE FREQUENCY GRAPH (INDUSTRIAL)(1)

3.00V

2.75V 2.75V
Valid Operating Range
2.50V
Voltage (VDDCORE)

2.35V(2)
2.25V

2.00V

8 MHz 48 MHz
0 Frequency

Note 1: VDD and VDDCORE must be maintained so that VDDCORE  VDD.

2: When the USB module is enabled, VUSB should be provided 3.0V-3.6V while VDDCORE must be 2.35V. When
the USB module is not enabled, the wider limits shaded in grey apply. VUSB should be maintained  VDD, but
may optionally be high-impedance when the USB module is not in use.

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 PIC18F47J53 FAMILY
31.1 DC Characteristics: Supply Voltage PIC18F47J53 Family (Industrial)
Standard Operating Conditions (unless otherwise stated)
PIC18F47J53 Family
Operating temperature -40°C  TA  +85°C for industrial

Param
Symbol Characteristic Min Typ Max Units Conditions
No.
D001 VDD Supply Voltage 2.15 — 3.6 V PIC18F4XJ53, PIC18F2XJ53
D001A VDD Supply Voltage 2.0 — 3.6 V PIC18LF4XJ53, PIC18LF2XJ53
D001B VDDCORE External Supply 2.0 — 2.75 V PIC18LF4XJ53, PIC18LF2XJ53
for Microcontroller Core
D001C AVDD Analog Supply Voltage VDD – 0.3 — VDD + 0.3 V
D001D AVSS Analog Ground Potential VSS – 0.3 — VSS + 0.3 V
D001E VUSB USB Supply Voltage 3.0 3.3 3.6 V USB module enabled(2)
D002 VDR RAM Data Retention 1.5 — — V
Voltage(1)
D003 VPOR VDD Start Voltage — — 0.7 V See Section 5.3 “Power-on
to Ensure Internal Reset (POR)” for details
Power-on Reset Signal
D004 SVDD VDD Rise Rate 0.05 — — V/ms See Section 5.3 “Power-on
to Ensure Internal Reset (POR)” for details
Power-on Reset Signal
D005 VBOR VDDCORE Brown-out Reset — 2.0 — V PIC18F4XJ53, PIC18F2XJ53
Voltage only
D006 VDSBOR VDD Brown-out Reset — 1.8 — V DSBOREN = 1 on “LF” device or
Voltage “F” device in Deep Sleep
Note 1: This is the limit to which VDDCORE can be lowered in Sleep mode, or during a device Reset, without losing RAM
data.
2: VUSB should always be maintained  VDD, but may be left floating when the USB module is disabled and
RC4/RC5 will not be used as general purpose inputs.

 2010 Microchip Technology Inc. Preliminary DS39964B-page 515

PIC18F47J53 FAMILY
31.2 DC Characteristics: Power-Down and Supply Current
PIC18F47J53 Family (Industrial)
Standard Operating Conditions (unless otherwise stated)
PIC18LF47J53 Family
Operating temperature -40°C  TA  +85°C for industrial

Standard Operating Conditions (unless otherwise stated)

PIC18F47J53 Family
Operating temperature -40°C  TA  +85°C for industrial

Param
Device Typ Max Units Conditions
No.
Power-Down Current (IPD)(1) – Sleep mode
PIC18LFXXJ53 0.1 1.6 A -40°C
0.2 1.6 A +25°C VDD = 2.0V,
0.8 7.0 A +60°C VDDCORE = 2.0V
2.1 11.5 A +85°C
PIC18LFXXJ53 0.2 2.0 A -40°C
0.5 2.0 A +25°C VDD = 2.5V,
1.4 9.0 A +60°C VDDCORE = 2.5V
3.2 15.0 A +85°C Sleep mode,
PIC18FXXJ53 3.0 6.0 A -40°C REGSLP = 1
3.8 6.0 A +25°C VDD = 2.15V
Vddcore = 10 F
4.7 9.0 A +60°C Capacitor
6.4 18.5 A +85°C
PIC18FXXJ53 3.3 9.0 A -40°C
4.2 9.0 A +25°C VDD = 3.3V
Vddcore = 10 F
5.5 12.0 A +60°C Capacitor
7.8 22.0 A +85°C
Power-Down Current (IPD)(1) – Deep Sleep mode
PIC18FXXJ53 2 25 nA -40°C
9 100 nA +25°C VDD = 2.15V,
VDDCORE = 10 F
72 250 nA +60°C
Capacitor
0.26 1.0 A +85°C
Deep Sleep mode
PIC18FXXJ53 17 50 nA -40°C
53 150 nA +25°C VDD = 3.3V,
VDDCORE = 10 F
186 400 nA +60°C Capacitor
0.50 2.0 A +85°C
Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured
with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that
add delta current disabled (such as WDT, Timer1 oscillator, BOR, etc.).
2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as
I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature,
also have an impact on the current consumption. All features that add delta current are disabled (USB module,
WDT, etc.). The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD/VSS;
MCLR = VDD; WDT disabled unless otherwise specified.
3: Low-power Timer1 with standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to
+70°C. Extended temperature crystals are available at a much higher cost.
4: This is the module differential current when the USB module is enabled and clocked at 48 MHz, but with no USB
cable attached. When the USB cable is attached or data is being transmitted, the current consumption may be
much higher (see Section 23.6.4 “USB Transceiver Current Consumption”). During USB Suspend mode
(USBEN = 1, SUSPND = 1, bus in Idle state), the USB module current will be dominated by the D+ or D- pull-up
resistor. The integrated pull-up resistors use “resistor switching” according to the resistor_ecn supplement to
the USB 2.0 Specifications, and therefore, may be as low as 900 during Idle conditions.

DS39964B-page 516 Preliminary  2010 Microchip Technology Inc.

 PIC18F47J53 FAMILY
31.2 DC Characteristics: Power-Down and Supply Current
PIC18F47J53 Family (Industrial) (Continued)
Standard Operating Conditions (unless otherwise stated)
PIC18LF47J53 Family
Operating temperature -40°C  TA  +85°C for industrial

Standard Operating Conditions (unless otherwise stated)

PIC18F47J53 Family
Operating temperature -40°C  TA  +85°C for industrial

Param
Device Typ Max Units Conditions
No.
Supply Current (IDD)(2)
PIC18LFXXJ53 5.5 14.2 A -40°C
VDD = 2.0V,
5.8 14.2 A +25°C
VDDCORE = 2.0V
7.9 19.0 A +85°C
PIC18LFXXJ53 8.4 16.5 A -40°C
VDD = 2.5V,
8.5 16.5 A +25°C
VDDCORE = 2.5V FOSC = 31 kHz
11.3 25.0 A +85°C (RC_RUN mode,
PIC18FXXJ53 23.7 60.0 A -40°C Internal RC Oscillator,
VDD = 2.15V
INTSRC = 0)
27.8 60.0 A +25°C VDDCORE = 10 F
34.0 70.0 A +85°C Capacitor
PIC18FXXJ53 26.1 70.0 A -40°C VDD = 3.3V
29.6 70.0 A +25°C VDDCORE = 10 F
36.2 96.0 A +85°C Capacitor
PIC18LFXXJ53 0.87 1.5 mA -40°C
VDD = 2.0V,
0.91 1.5 mA +25°C
VDDCORE = 2.0
0.95 1.6 mA +85°C
PIC18LFXXJ53 1.23 2.0 mA -40°C
VDD = 2.5V,
1.24 2.0 mA +25°C
VDDCORE = 2.5V
1.25 2.0 mA +85°C FOSC = 4 MHz,
RC_RUN mode,
PIC18FXXJ53 0.99 2.4 mA -40°C VDD = 2.15V, Internal RC Oscillator
1.02 2.4 mA +25°C VDDCORE = 10 F
1.06 2.6 mA +85°C capacitor
PIC18FXXJ53 1.31 2.6 mA -40°C VDD = 3.3V,
1.25 2.6 mA +25°C VDDCORE = 10 F
1.26 2.7 mA +85°C capacitor
Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured
with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that
add delta current disabled (such as WDT, Timer1 oscillator, BOR, etc.).
2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as
I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature,
also have an impact on the current consumption. All features that add delta current are disabled (USB module,
WDT, etc.). The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD/VSS;
MCLR = VDD; WDT disabled unless otherwise specified.
3: Low-power Timer1 with standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to
+70°C. Extended temperature crystals are available at a much higher cost.
4: This is the module differential current when the USB module is enabled and clocked at 48 MHz, but with no USB
cable attached. When the USB cable is attached or data is being transmitted, the current consumption may be
much higher (see Section 23.6.4 “USB Transceiver Current Consumption”). During USB Suspend mode
(USBEN = 1, SUSPND = 1, bus in Idle state), the USB module current will be dominated by the D+ or D- pull-up
resistor. The integrated pull-up resistors use “resistor switching” according to the resistor_ecn supplement to
the USB 2.0 Specifications, and therefore, may be as low as 900 during Idle conditions.

 2010 Microchip Technology Inc. Preliminary DS39964B-page 517

PIC18F47J53 FAMILY
31.2 DC Characteristics: Power-Down and Supply Current
PIC18F47J53 Family (Industrial) (Continued)
Standard Operating Conditions (unless otherwise stated)
PIC18LF47J53 Family
Operating temperature -40°C  TA  +85°C for industrial

Standard Operating Conditions (unless otherwise stated)

PIC18F47J53 Family
Operating temperature -40°C  TA  +85°C for industrial

Param
Device Typ Max Units Conditions
No.
Supply Current (IDD)(2)
PIC18LFXXJ53 1.45 3.0 mA -40°C
VDD = 2.0V,
1.48 3.0 mA +25°C
VDDCORE = 2.0V
1.52 3.0 mA +85°C
PIC18LFXXJ53 2.12 3.8 mA -40°C
VDD = 2.5V,
2.10 3.8 mA +25°C
VDDCORE = 2.5V
2.10 3.9 mA +85°C FOSC = 8 MHz,
RC_RUN mode,
PIC18FXXJ53 1.65 3.6 mA -40°C
VDD = 2.15V, Internal RC Oscillator
1.68 3.6 mA +25°C
VDDCORE = 10 F
1.71 3.9 mA +85°C
PIC18FXXJ53 2.26 4.3 mA -40°C
VDD = 3.3V,
2.13 4.3 mA +25°C
VDDCORE = 10 F
2.10 4.6 mA +85°C
PIC18LFXXJ53 1.5 11 A -40°C
VDD = 2.0V,
1.7 11 A +25°C
VDDCORE = 2.0V
3.9 20 A +85°C
PIC18LFXXJ53 2.0 12 A -40°C
VDD = 2.5V,
2.4 13 A +25°C
VDDCORE = 2.5V FOSC = 31 kHz,
5.4 23 A +85°C RC_IDLE mode,
PIC18FXXJ53 19.0 60 A -40°C Internal RC Oscillator,
VDD = 2.15V, INTSRC = 0
23.2 60 A +25°C
VDDCORE = 10 F
29.9 75 A +85°C
PIC18FXXJ53 19.7 65 A -40°C
VDD = 3.3V,
24.0 65 A +25°C
VDDCORE = 10 F
31.4 90 A +85°C
Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured
with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that
add delta current disabled (such as WDT, Timer1 oscillator, BOR, etc.).
2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as
I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature,
also have an impact on the current consumption. All features that add delta current are disabled (USB module,
WDT, etc.). The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD/VSS;
MCLR = VDD; WDT disabled unless otherwise specified.
3: Low-power Timer1 with standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to
+70°C. Extended temperature crystals are available at a much higher cost.
4: This is the module differential current when the USB module is enabled and clocked at 48 MHz, but with no USB
cable attached. When the USB cable is attached or data is being transmitted, the current consumption may be
much higher (see Section 23.6.4 “USB Transceiver Current Consumption”). During USB Suspend mode
(USBEN = 1, SUSPND = 1, bus in Idle state), the USB module current will be dominated by the D+ or D- pull-up
resistor. The integrated pull-up resistors use “resistor switching” according to the resistor_ecn supplement to
the USB 2.0 Specifications, and therefore, may be as low as 900 during Idle conditions.

DS39964B-page 518 Preliminary  2010 Microchip Technology Inc.

 PIC18F47J53 FAMILY
31.2 DC Characteristics: Power-Down and Supply Current
PIC18F47J53 Family (Industrial) (Continued)
Standard Operating Conditions (unless otherwise stated)
PIC18LF47J53 Family
Operating temperature -40°C  TA  +85°C for industrial

Standard Operating Conditions (unless otherwise stated)

PIC18F47J53 Family
Operating temperature -40°C  TA  +85°C for industrial

Param
Device Typ Max Units Conditions
No.
Supply Current (IDD)(2)
PIC18LFXXJ53 0.41 0.98 mA -40°C
VDD = 2.0V,
0.44 0.98 mA +25°C
VDDCORE = 2.0V
0.48 1.12 mA +85°C
PIC18LFXXJ53 0.48 1.14 mA -40°C
VDD = 2.5V,
0.51 1.14 mA +25°C
VDDCORE = 2.5V
0.55 1.25 mA +85°C FOSC = 4 MHz,
RC_IDLE mode,
PIC18FXXJ53 0.45 1.21 mA -40°C
VDD = 2.15V, Internal RC Oscillator
0.48 1.21 mA +25°C
VDDCORE = 10 F
0.52 1.30 mA +85°C
PIC18FXXJ53 0.52 1.20 mA -40°C
VDD = 3.3V,
0.54 1.20 mA +25°C
VDDCORE = 10 F
0.58 1.35 mA +85°C
PIC18LFXXJ53 0.53 1.4 mA -40°C
VDD = 2.0V,
0.56 1.5 mA +25°C
VDDCORE = 2.0V
0.60 1.6 mA +85°C
PIC18LFXXJ53 0.63 2.0 mA -40°C
VDD = 2.5V,
0.67 2.0 mA +25°C
VDDCORE = 2.5V
0.72 2.2 mA +85°C FOSC = 8 MHz,
RC_IDLE mode,
PIC18FXXJ53 0.58 1.8 mA -40°C
VDD = 2.15V, Internal RC Oscillator
0.62 1.8 mA +25°C
VDDCORE = 10 F
0.66 2.0 mA +85°C
PIC18FXXJ53 0.69 2.2 mA -40°C
VDD = 3.3V,
0.70 2.2 mA +25°C
VDDCORE = 10 F
0.74 2.3 mA +85°C
Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured
with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that
add delta current disabled (such as WDT, Timer1 oscillator, BOR, etc.).
2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as
I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature,
also have an impact on the current consumption. All features that add delta current are disabled (USB module,
WDT, etc.). The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD/VSS;
MCLR = VDD; WDT disabled unless otherwise specified.
3: Low-power Timer1 with standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to
+70°C. Extended temperature crystals are available at a much higher cost.
4: This is the module differential current when the USB module is enabled and clocked at 48 MHz, but with no USB
cable attached. When the USB cable is attached or data is being transmitted, the current consumption may be
much higher (see Section 23.6.4 “USB Transceiver Current Consumption”). During USB Suspend mode
(USBEN = 1, SUSPND = 1, bus in Idle state), the USB module current will be dominated by the D+ or D- pull-up
resistor. The integrated pull-up resistors use “resistor switching” according to the resistor_ecn supplement to
the USB 2.0 Specifications, and therefore, may be as low as 900 during Idle conditions.

 2010 Microchip Technology Inc. Preliminary DS39964B-page 519

PIC18F47J53 FAMILY
31.2 DC Characteristics: Power-Down and Supply Current
PIC18F47J53 Family (Industrial) (Continued)
Standard Operating Conditions (unless otherwise stated)
PIC18LF47J53 Family
Operating temperature -40°C  TA  +85°C for industrial

Standard Operating Conditions (unless otherwise stated)

PIC18F47J53 Family
Operating temperature -40°C  TA  +85°C for industrial

Param
Device Typ Max Units Conditions
No.
Supply Current (IDD)(2)
PIC18LFXXJ53 0.61 1.25 mA -40°C
VDD = 2.0V,
0.62 1.25 mA +25°C
VDDCORE = 2.0V
0.64 1.35 mA +85°C
PIC18LFXXJ53 0.99 1.70 mA -40°C
VDD = 2.5V,
0.96 1.70 mA +25°C
VDDCORE = 2.5V
0.94 1.82 mA +85°C FOSC = 4 MHz,
PRI_RUN mode,
PIC18FXXJ53 0.78 1.60 mA -40°C EC Oscillator
VDD = 2.15V,
0.78 1.60 mA +25°C
VDDCORE = 10 F
0.78 1.70 mA +85°C
PIC18FXXJ53 1.10 1.95 mA -40°C
VDD = 3.3V,
1.02 1.90 mA +25°C
VDDCORE = 10 F
1.00 2.00 mA +85°C
PIC18LFXXJ53 9.8 14.8 mA -40°C
VDD = 2.5V,
9.5 14.8 mA +25°C
VDDCORE = 2.5V
9.4 15.1 mA +85°C FOSC = 48 MHz,
PRI_RUN mode,
PIC18FXXJ53 10.9 19.5 mA -40°C EC Oscillator
VDD = 3.3V,
10.2 19.5 mA +25°C
VDDCORE = 10 F
9.9 19.5 mA +85°C
Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured
with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that
add delta current disabled (such as WDT, Timer1 oscillator, BOR, etc.).
2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as
I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature,
also have an impact on the current consumption. All features that add delta current are disabled (USB module,
WDT, etc.). The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD/VSS;
MCLR = VDD; WDT disabled unless otherwise specified.
3: Low-power Timer1 with standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to
+70°C. Extended temperature crystals are available at a much higher cost.
4: This is the module differential current when the USB module is enabled and clocked at 48 MHz, but with no USB
cable attached. When the USB cable is attached or data is being transmitted, the current consumption may be
much higher (see Section 23.6.4 “USB Transceiver Current Consumption”). During USB Suspend mode
(USBEN = 1, SUSPND = 1, bus in Idle state), the USB module current will be dominated by the D+ or D- pull-up
resistor. The integrated pull-up resistors use “resistor switching” according to the resistor_ecn supplement to
the USB 2.0 Specifications, and therefore, may be as low as 900 during Idle conditions.

DS39964B-page 520 Preliminary  2010 Microchip Technology Inc.

 PIC18F47J53 FAMILY
31.2 DC Characteristics: Power-Down and Supply Current
PIC18F47J53 Family (Industrial) (Continued)
Standard Operating Conditions (unless otherwise stated)
PIC18LF47J53 Family
Operating temperature -40°C  TA  +85°C for industrial

Standard Operating Conditions (unless otherwise stated)

PIC18F47J53 Family
Operating temperature -40°C  TA  +85°C for industrial

Param
Device Typ Max Units Conditions
No.
PIC18LFXXJ53 0.18 0.70 mA -40°C
VDD = 2.0V,
0.18 0.70 mA +25°C
VDDCORE = 2.0V
0.19 0.75 mA +85°C
PIC18LFXXJ53 0.23 0.90 mA -40°C
VDD = 2.5V,
0.23 0.90 mA +25°C
VDDCORE = 2.5V
0.24 1.00 mA +85°C FOSC = 4 MHz
PRI_IDLE mode,
PIC18FXXJ53 0.23 0.80 mA -40°C VDD = 2.15V, EC Oscillator
0.24 0.80 mA +25°C VDDCORE = 10 F
0.25 0.85 mA +85°C Capacitor
PIC18FXXJ53 0.32 1.00 mA -40°C VDD = 3.3V,
0.31 1.00 mA +25°C VDDCORE = 10 F
0.32 1.00 mA +85°C Capacitor
PIC18LFXXJ53 2.74 7.00 mA -40°C
VDD = 2.5V,
2.77 6.50 mA +25°C
VDDCORE = 2.5V
2.80 6.50 mA +85°C FOSC = 48 MHz
PRI_IDLE mode,
PIC18FXXJ53 3.48 11.00 mA -40°C VDD = 3.3V, EC Oscillator
3.42 10.00 mA +25°C VDDCORE = 10 F
3.44 10.00 mA +85°C Capacitor
Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured
with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that
add delta current disabled (such as WDT, Timer1 oscillator, BOR, etc.).
2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as
I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature,
also have an impact on the current consumption. All features that add delta current are disabled (USB module,
WDT, etc.). The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD/VSS;
MCLR = VDD; WDT disabled unless otherwise specified.
3: Low-power Timer1 with standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to
+70°C. Extended temperature crystals are available at a much higher cost.
4: This is the module differential current when the USB module is enabled and clocked at 48 MHz, but with no USB
cable attached. When the USB cable is attached or data is being transmitted, the current consumption may be
much higher (see Section 23.6.4 “USB Transceiver Current Consumption”). During USB Suspend mode
(USBEN = 1, SUSPND = 1, bus in Idle state), the USB module current will be dominated by the D+ or D- pull-up
resistor. The integrated pull-up resistors use “resistor switching” according to the resistor_ecn supplement to
the USB 2.0 Specifications, and therefore, may be as low as 900 during Idle conditions.

 2010 Microchip Technology Inc. Preliminary DS39964B-page 521

PIC18F47J53 FAMILY
31.2 DC Characteristics: Power-Down and Supply Current
PIC18F47J53 Family (Industrial) (Continued)
Standard Operating Conditions (unless otherwise stated)
PIC18LF47J53 Family
Operating temperature -40°C  TA  +85°C for industrial

Standard Operating Conditions (unless otherwise stated)

PIC18F47J53 Family
Operating temperature -40°C  TA  +85°C for industrial

Param
Device Typ Max Units Conditions
No.
PIC18LFXXJ53 6.9 11.0 mA -40°C
VDD = 2.5V,
6.7 11.0 mA +25°C
VDDCORE = 2.5V FOSC = 24 MHz
6.4 10.0 mA +85°C PRI_RUN mode,
PIC18FXXJ53 7.0 15.0 mA -40°C ECPLL Oscillator
VDD = 3.3V,
(4 MHz Input)
6.8 14.0 mA +25°C VDDCORE = 10 F
6.6 14.0 mA +85°C Capacitor
PIC18LFXXJ53 9.9 14.0 mA -40°C
VDD = 2.5V,
9.7 14.0 mA +25°C
VDDCORE = 2.5V FOSC = 48 MHz
9.5 14.0 mA +85°C PRI_RUN mode,
PIC18FXXJ53 10.3 21.5 mA -40°C VDD = 3.3V, ECPLL Oscillator
10.0 20.5 mA +25°C VDDCORE = 10 F (4 MHz Input)

9.7 20.5 mA +85°C Capacitor

Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured
with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that
add delta current disabled (such as WDT, Timer1 oscillator, BOR, etc.).
2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as
I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature,
also have an impact on the current consumption. All features that add delta current are disabled (USB module,
WDT, etc.). The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD/VSS;
MCLR = VDD; WDT disabled unless otherwise specified.
3: Low-power Timer1 with standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to
+70°C. Extended temperature crystals are available at a much higher cost.
4: This is the module differential current when the USB module is enabled and clocked at 48 MHz, but with no USB
cable attached. When the USB cable is attached or data is being transmitted, the current consumption may be
much higher (see Section 23.6.4 “USB Transceiver Current Consumption”). During USB Suspend mode
(USBEN = 1, SUSPND = 1, bus in Idle state), the USB module current will be dominated by the D+ or D- pull-up
resistor. The integrated pull-up resistors use “resistor switching” according to the resistor_ecn supplement to
the USB 2.0 Specifications, and therefore, may be as low as 900 during Idle conditions.

DS39964B-page 522 Preliminary  2010 Microchip Technology Inc.

 PIC18F47J53 FAMILY
31.2 DC Characteristics: Power-Down and Supply Current
PIC18F47J53 Family (Industrial) (Continued)
Standard Operating Conditions (unless otherwise stated)
PIC18LF47J53 Family
Operating temperature -40°C  TA  +85°C for industrial

Standard Operating Conditions (unless otherwise stated)

PIC18F47J53 Family
Operating temperature -40°C  TA  +85°C for industrial

Param
Device Typ Max Units Conditions
No.
PIC18LFXXJ53 9 45 A -40°C
VDD = 2.5V,
9 45 A +25°C
VDDCORE = 2.5V
12 61 A +85°C
PIC18FXXJ53 24 95 A -40°C VDD = 2.15V, FOSC = 32 kHz(3)
28 95 A +25°C VDDCORE = 10 F SEC_RUN mode,
35 105 A +85°C Capacitor (SOSCSEL<1:0> = 01)
PIC18FXXJ53 27 110 A -40°C VDD = 3.3V,
31 110 A +25°C VDDCORE = 10 F
35 150 A +85°C Capacitor
PIC18LFXXJ53 2.5 31 A -40°C
VDD = 2.5V,
3.0 31 A +25°C
VDDCORE = 2.5V
6.1 50 A +85°C
PIC18FXXJ53 19 87 A -40°C VDD = 2.15V, FOSC = 32 kHz(3)
24 89 A +25°C VDDCORE = 10 F SEC_IDLE mode,
31 97 A +85°C Capacitor (SOSCSEL<1:0> = 01)
PIC18FXXJ53 21 100 A -40°C VDD = 3.3V,
25 100 A +25°C VDDCORE = 10 F
31 140 A +85°C Capacitor
Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured
with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that
add delta current disabled (such as WDT, Timer1 oscillator, BOR, etc.).
2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as
I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature,
also have an impact on the current consumption. All features that add delta current are disabled (USB module,
WDT, etc.). The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD/VSS;
MCLR = VDD; WDT disabled unless otherwise specified.
3: Low-power Timer1 with standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to
+70°C. Extended temperature crystals are available at a much higher cost.
4: This is the module differential current when the USB module is enabled and clocked at 48 MHz, but with no USB
cable attached. When the USB cable is attached or data is being transmitted, the current consumption may be
much higher (see Section 23.6.4 “USB Transceiver Current Consumption”). During USB Suspend mode
(USBEN = 1, SUSPND = 1, bus in Idle state), the USB module current will be dominated by the D+ or D- pull-up
resistor. The integrated pull-up resistors use “resistor switching” according to the resistor_ecn supplement to
the USB 2.0 Specifications, and therefore, may be as low as 900 during Idle conditions.

 2010 Microchip Technology Inc. Preliminary DS39964B-page 523

PIC18F47J53 FAMILY
31.2 DC Characteristics: Power-Down and Supply Current
PIC18F47J53 Family (Industrial) (Continued)
Standard Operating Conditions (unless otherwise stated)
PIC18LF47J53 Family
Operating temperature -40°C  TA  +85°C for industrial

Standard Operating Conditions (unless otherwise stated)

PIC18F47J53 Family
Operating temperature -40°C  TA  +85°C for industrial

Param
Device Typ Max Units Conditions
No.
Module Differential Currents (IWDT, IHLVD, IOSCB, IAD, IUSB)
D022
(IWDT) Watchdog Timer 0.38 4.0 A -40°C
VDD = 2.5V,
0.41 4.0 A +25°C PIC18LFXXJ53
VDDCORE = 2.5V
0.44 5.2 A +85°C
0.33 4.0 A -40°C VDD = 2.15V,
0.33 4.0 A +25°C VDDCORE = 10 F
0.39 6.0 A +85°C Capacitor
PIC18FXXJ53
0.49 8.0 A -40°C VDD = 3.3V,
0.48 8.0 A +25°C VDDCORE = 10 F
0.45 9.0 A +85°C Capacitor
D022B High/Low-Voltage Detect 4.1 8.0 A -40°C
(IHLVD) VDD = 2.5V,
4.9 8.0 A +25°C PIC18LFXXJ53
VDDCORE = 2.5V
5.8 9.0 A +85°C
2.6 6.0 A -40°C VDD = 2.15V,
3.0 6.0 A +25°C VDDCORE = 10 F
3.5 8.0 A +85°C Capacitor
PIC18FXXJ53
3.4 9.0 A -40°C VDD = 3.3V,
3.9 9.0 A +25°C VDDCORE = 10 F
4.2 12.0 A +85°C Capacitor
Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured
with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that
add delta current disabled (such as WDT, Timer1 oscillator, BOR, etc.).
2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as
I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature,
also have an impact on the current consumption. All features that add delta current are disabled (USB module,
WDT, etc.). The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD/VSS;
MCLR = VDD; WDT disabled unless otherwise specified.
3: Low-power Timer1 with standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to
+70°C. Extended temperature crystals are available at a much higher cost.
4: This is the module differential current when the USB module is enabled and clocked at 48 MHz, but with no USB
cable attached. When the USB cable is attached or data is being transmitted, the current consumption may be
much higher (see Section 23.6.4 “USB Transceiver Current Consumption”). During USB Suspend mode
(USBEN = 1, SUSPND = 1, bus in Idle state), the USB module current will be dominated by the D+ or D- pull-up
resistor. The integrated pull-up resistors use “resistor switching” according to the resistor_ecn supplement to
the USB 2.0 Specifications, and therefore, may be as low as 900 during Idle conditions.

DS39964B-page 524 Preliminary  2010 Microchip Technology Inc.

 PIC18F47J53 FAMILY
31.2 DC Characteristics: Power-Down and Supply Current
PIC18F47J53 Family (Industrial) (Continued)
Standard Operating Conditions (unless otherwise stated)
PIC18LF47J53 Family
Operating temperature -40°C  TA  +85°C for industrial

Standard Operating Conditions (unless otherwise stated)

PIC18F47J53 Family
Operating temperature -40°C  TA  +85°C for industrial

Param
Device Typ Max Units Conditions
No.
D025 Module Differential Currents (IWDT, IHLVD, IOSCB, IAD, IUSB)
(IOSCB)
Real-Time Clock/Calendar 0.5 4.0 A -40°C
with Low-Power Timer1 0.7 4.5 A +25°C VDD = 2.15V,
Oscillator VDDCORE = 10 F
0.8 4.5 A +60°C Capacitor
0.9 4.5 A +85°C
0.6 4.5 A -40°C
0.8 5.0 A +25°C VDD = 2.5V, PIC18FXXJ53
VDDCORE = 10 F 32.768 kHz(3), T1OSCEN = 1,
0.9 5.0 A +60°C Capacitor (SOSCSEL<1:0> = 01)
1.0 5.0 A +85°C
0.8 6.5 A -40°C
1.0 6.5 A +25°C VDD = 3.3V,
VDDCORE = 10 F
1.1 8.0 A +60°C Capacitor
1.3 8.0 A +85°C
Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured
with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that
add delta current disabled (such as WDT, Timer1 oscillator, BOR, etc.).
2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as
I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature,
also have an impact on the current consumption. All features that add delta current are disabled (USB module,
WDT, etc.). The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD/VSS;
MCLR = VDD; WDT disabled unless otherwise specified.
3: Low-power Timer1 with standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to
+70°C. Extended temperature crystals are available at a much higher cost.
4: This is the module differential current when the USB module is enabled and clocked at 48 MHz, but with no USB
cable attached. When the USB cable is attached or data is being transmitted, the current consumption may be
much higher (see Section 23.6.4 “USB Transceiver Current Consumption”). During USB Suspend mode
(USBEN = 1, SUSPND = 1, bus in Idle state), the USB module current will be dominated by the D+ or D- pull-up
resistor. The integrated pull-up resistors use “resistor switching” according to the resistor_ecn supplement to
the USB 2.0 Specifications, and therefore, may be as low as 900 during Idle conditions.

 2010 Microchip Technology Inc. Preliminary DS39964B-page 525

PIC18F47J53 FAMILY
31.2 DC Characteristics: Power-Down and Supply Current
PIC18F47J53 Family (Industrial) (Continued)
Standard Operating Conditions (unless otherwise stated)
PIC18LF47J53 Family
Operating temperature -40°C  TA  +85°C for industrial

Standard Operating Conditions (unless otherwise stated)

PIC18F47J53 Family
Operating temperature -40°C  TA  +85°C for industrial

Param
Device Typ Max Units Conditions
No.
Module Differential Currents (IWDT, IHLVD, IOSCB, IAD, IUSB)
D026 A/D Converter 0.5 4.0 A -40°C
(IAD) VDD = 2.5V, PIC18LFXXJ53
0.5 4.0 A +25°C
VDDCORE = 2.5V A/D on, not converting
0.5 4.0 A +85°C
1.1 5.0 A -40°C VDD = 2.15V,
1.1 5.0 A +25°C VDDCORE = 10 F
1.1 5.0 A +85°C Capacitor
PIC18FXXJ53
3.2 11 A -40°C A/D on, not converting
VDD = 3.3V,
3.2 11 A +25°C VDDCORE = 10 F
3.2 11 A +85°C Capacitor

D027 USB Module 1.7 3.2 mA -40°C PIC18FXXJ53

VDD and USB enabled, no cable
(IUSB) 1.7 3.2 mA +25°C VUSB = 3.3V, connected.(4) Traffic makes a
1.6 3.2 mA +85°C VDDCORE = 10 F difference, see Section 23.6.4
Capacitor “USB Transceiver Current
Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured
with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that
add delta current disabled (such as WDT, Timer1 oscillator, BOR, etc.).
2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as
I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature,
also have an impact on the current consumption. All features that add delta current are disabled (USB module,
WDT, etc.). The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD/VSS;
MCLR = VDD; WDT disabled unless otherwise specified.
3: Low-power Timer1 with standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to
+70°C. Extended temperature crystals are available at a much higher cost.
4: This is the module differential current when the USB module is enabled and clocked at 48 MHz, but with no USB
cable attached. When the USB cable is attached or data is being transmitted, the current consumption may be
much higher (see Section 23.6.4 “USB Transceiver Current Consumption”). During USB Suspend mode
(USBEN = 1, SUSPND = 1, bus in Idle state), the USB module current will be dominated by the D+ or D- pull-up
resistor. The integrated pull-up resistors use “resistor switching” according to the resistor_ecn supplement to
the USB 2.0 Specifications, and therefore, may be as low as 900 during Idle conditions.

DS39964B-page 526 Preliminary  2010 Microchip Technology Inc.

 PIC18F47J53 FAMILY
31.3 DC Characteristics:PIC18F47J53 Family (Industrial)
Standard Operating Conditions (unless otherwise stated)
DC CHARACTERISTICS
Operating temperature -40°C TA  +85°C for industrial

Param
Symbol Characteristic Min Max Units Conditions
No.
VIL Input Low Voltage
All I/O ports:
D030 with TTL Buffer(4) VSS 0.15 VDD V VDD < 3.3V
(4)
D030A with TTL Buffer VSS 0.8 V 3.3V < VDD <3.6V
D031 with Schmitt Trigger Buffer VSS 0.2 VDD V
D031A SCLx/SDAx — 0.3 VDD V I2C™ enabled
D031B SCLx/SDAx — 0.8 V SMBus enabled
D032 MCLR VSS 0.2 VDD V
D033 OSC1 VSS 0.3 VDD V HS, HSPLL modes
D033A OSC1 VSS 0.2 VDD V EC, ECPLL modes
D034 T1OSI VSS 0.3 V T1OSCEN = 1
VIH Input High Voltage
I/O Ports without 5.5V
Tolerance:
D040 with TTL Buffer(4) 0.25 VDD + 0.8V VDD V VDD < 3.3V
D040A with TTL Buffer(4) 2.0 VDD V 3.3V < VDD <3.6V
D041 with Schmitt Trigger Buffer 0.8 VDD VDD V
I/O Ports with 5.5V Tolerance:(5)
Dxxx with TTL Buffer 0.25 VDD + 0.8V 5.5 V VDD < 3.3V
DxxxA 2.0 5.5 V 3.3V  VDD 3.6V
Dxxx with Schmitt Trigger Buffer 0.8 VDD 5.5 V
D041A SCLx/SDAx 0.7 VDD — V I2C™ enabled
D041B SCLx/SDAx 2.1 — V SMBus enabled; VDD > 3V
D042 MCLR 0.8 VDD 5.5 V
D043 OSC1 0.7 VDD VDD V HS, HSPLL modes
D043A OSC1 0.8 VDD VDD V EC, ECPLL modes
D044 T1OSI 1.6 VDD V T1OSCEN = 1
IIL (1,2)
Input Leakage Current
D060 I/O Ports ±5 ±200 nA VSS VPIN VDD,
Pin at high-impedance
D061 MCLR ±5 ±200 nA Vss VPIN VDD
D062 D+/D- ±75 typical ±500 nA Vss VPIN VDD
D063 OSC1 ±5 ±200 nA Vss VPIN VDD
IPU Weak Pull-up Current
D070 IPURB PORTB, PORTD(3) and 80 400 A VDD = 3.3V, VPIN = VSS
PORTE(3) Weak Pull-up Current
Note 1: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent
normal operating conditions. Higher leakage current may be measured at different input voltages.
2: Negative current is defined as current sourced by the pin.
3: Only available in 44-pin devices.
4: When used as general purpose inputs, the RC4 and RC5 thresholds are referenced to VUSB instead of VDD.
5: Refer to Table 10-2 for pin tolerance levels.

 2010 Microchip Technology Inc. Preliminary DS39964B-page 527

PIC18F47J53 FAMILY
31.3 DC Characteristics:PIC18F47J53 Family (Industrial) (Continued)
Standard Operating Conditions (unless otherwise stated)
DC CHARACTERISTICS
Operating temperature -40°C TA  +85°C for industrial

Param
Symbol Characteristic Min Max Units Conditions
No.
VOL Output Low Voltage
D080 I/O Ports:
PORTA (except RA6), — 0.4 V IOL = 4 mA, VDD = 3.3V,
PORTD(3), PORTE(3) -40C to +85C
PORTB, PORTC, RA6 — 0.4 V IOL = 8.5 mA, VDD = 3.3V,
-40C to +85C
VOH Output High Voltage
D090 I/O Ports: V
PORTA (except RA6), 2.4 — V IOH = -3 mA, VDD = 3.3V,
PORTD(3), PORTE(3) -40C to +85C
PORTB, PORTC, RA6 2.4 — V IOH = -6 mA, VDD = 3.3V,
-40C to +85C
Capacitive Loading Specs
on Output Pins
D101 CIO All I/O Pins and OSC2 — 50 pF To meet the AC Timing
Specifications
D102 CB SCLx, SDAx — 400 pF I2C™ Specification
Note 1: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent
normal operating conditions. Higher leakage current may be measured at different input voltages.
2: Negative current is defined as current sourced by the pin.
3: Only available in 44-pin devices.
4: When used as general purpose inputs, the RC4 and RC5 thresholds are referenced to VUSB instead of VDD.
5: Refer to Table 10-2 for pin tolerance levels.

DS39964B-page 528 Preliminary  2010 Microchip Technology Inc.

 PIC18F47J53 FAMILY
TABLE 31-1: MEMORY PROGRAMMING REQUIREMENTS
Standard Operating Conditions (unless otherwise stated)
DC CHARACTERISTICS
Operating temperature -40°C  TA  +85°C for industrial
Param
Sym Characteristic Min Typ† Max Units Conditions
No.
Program Flash Memory
D130 EP Cell Endurance 10K — — E/W -40C to +85C
D131 VPR VDDcore for Read VMIN — 2.75 V VMIN = Minimum operating
voltage
D132B VPEW VDDCORE for Self-Timed Erase or 2.25 — 2.75 V
Write
D133A TIW Self-Timed Write Cycle Time — 2.8 — ms 64 bytes
D133B TIE Self-Timed Block Erase Cycle — 33.0 — ms
Time
D134 TRETD Characteristic Retention 20 — — Year Provided no other
specifications are violated
D135 IDDP Supply Current during — 3 — mA
Programming
† Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.

TABLE 31-2: COMPARATOR SPECIFICATIONS

Operating Conditions: 3.0V < VDD < 3.6V, -40°C < TA < +85°C (unless otherwise stated)

Param
Sym Characteristics Min Typ Max Units Comments
No.
D300 VIOFF Input Offset Voltage — +5 +25 mV
D301 VICM Input Common Mode Voltage 0 — VDD V
VIRV Internal Reference Voltage 0.57 0.60 0.63 V
D302 CMRR Common Mode Rejection Ratio 55 — — dB
300 TRESP Response Time(1) — 150 400 ns
301 TMC2OV Comparator Mode Change to — — 10 s
Output Valid
Note 1: Response time measured with one comparator input at VDD/2, while the other input transitions from VSS to
VDD.

TABLE 31-3: VOLTAGE REFERENCE SPECIFICATIONS

Operating Conditions: 3.0V < VDD < 3.6V, -40°C < TA < +85°C (unless otherwise stated)
Param
Sym Characteristics Min Typ Max Units Comments
No.
D310 VRES Resolution VDD/24 — VDD/32 LSb
D311 VRAA Absolute Accuracy — — 1/2 LSb
D312 VRUR Unit Resistor Value (R) — 2k — 
310 TSET Settling Time(1) — — 10 s
Note 1: Settling time measured while CVRR = 1 and CVR<3:0> bits transition from ‘0000’ to ‘1111’.

 2010 Microchip Technology Inc. Preliminary DS39964B-page 529

PIC18F47J53 FAMILY
TABLE 31-4: INTERNAL VOLTAGE REGULATOR SPECIFICATIONS
Operating Conditions: -40°C < TA < +85°C (unless otherwise stated)

Param
Sym Characteristics Min Typ Max Units Comments
No.
VRGOUT Regulator Output Voltage 2.35 2.5 2.7 V Regulator enabled, VDD = 3.0V
CEFC External Filter Capacitor 5.4 10 18 F ESR < 3 recommended
Value(1) ESR < 5 required
Note 1: CEFC applies for PIC18F devices in the family. For PIC18LF devices in the family, there is no specific
minimum or maximum capacitance for VDDCORE, although proper supply rail bypassing should still be
used.

TABLE 31-5: ULPWU SPECIFICATIONS

Standard Operating Conditions (unless otherwise stated)
DC CHARACTERISTICS
Operating temperature -40°C  TA  +85°C for industrial
Param
Sym Characteristic Min Typ† Max Units Conditions
No.
D100 IULP Ultra Low-Power Wake-up Current — 60 — nA Net of I/O leakage and current
sink at 1.6V on pin,
VDD = 3.3V
See Application Note AN879,
“Using the Microchip Ultra
Low-Power Wake-up Module”
(DS00879)
† Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.

TABLE 31-6: CTMU CURRENT SOURCE SPECIFICATIONS

Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated)
DC CHARACTERISTICS
Operating temperature -40°C  TA  +85°C for Industrial
Param
Sym Characteristic Min Typ(1) Max Units Conditions
No.

IOUT1 CTMU Current Source, Base Range — 550 — nA CTMUICON<1:0> = 01

IOUT2 CTMU Current Source, 10x Range — 5.5 — A CTMUICON<1:0> = 10
IOUT3 CTMU Current Source, 100x Range — 55 — A CTMUICON<1:0> = 11
Note 1: Nominal value at center point of current trim range (CTMUICON<7:2> = 000000).

DS39964B-page 530 Preliminary  2010 Microchip Technology Inc.

 PIC18F47J53 FAMILY
TABLE 31-7: USB MODULE SPECIFICATIONS
Operating Conditions: -40°C < TA < +85°C (unless otherwise stated)

Param
Sym Characteristics Min Typ Max Units Comments
No.
D313 VUSB USB Voltage 3.0 — 3.6 V Voltage on VUSB pin must
be in this range for proper
USB operation
D314 IIL Input Leakage on D+ or D- — — +0.2 A VSS < VPIN < VUSB
D315 VILUSB Input Low Voltage for — — 0.8 V For VUSB range
USB Buffer
D316 VIHUSB Input High Voltage for 2.0 — — V For VUSB range
USB Buffer
D318 VDIFS Differential Input Sensitivity — — 0.2 V The difference between D+
and D- must exceed this
value while VCM is met
D319 VCM Differential Common Mode 0.8 — 2.5 V
Range
D320 ZOUT Driver Output Impedance(1) 28 — 44 
D321 VOL Voltage Output Low 0.0 — 0.3 V 1.5 kload connected to
3.6V
D322 VOH Voltage Output High 2.8 — 3.6 V 1.5 kload connected to
ground
Note 1: The D+ and D- signal lines have built-in impedance matching resistors. No external resistors, capacitors or
magnetic components are necessary on the D+/D- signal paths between the PIC18F47J53 family device
and a USB cable.

 2010 Microchip Technology Inc. Preliminary DS39964B-page 531

PIC18F47J53 FAMILY
FIGURE 31-3: HIGH/LOW-VOLTAGE DETECT CHARACTERISTICS

For VDIRMAG = 1: VDD

VHLVD

(HLVDIF set by hardware) (HLVDIF can be

cleared in software)

VHLVD

For VDIRMAG = 0: VDD

HLVDIF

TABLE 31-8: HIGH/LOW-VOLTAGE DETECT CHARACTERISTICS

Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C  TA  +85°C for industrial

Param
Symbol Characteristic Min Typ Max Units Conditions
No.
D420 HLVD Voltage on VDD HLVDL<3:0> = 1000 2.33 2.45 2.57 V
Transition High-to-Low HLVDL<3:0> = 1001 2.47 2.60 2.73 V
HLVDL<3:0> = 1010 2.66 2.80 2.94 V
HLVDL<3:0> = 1011 2.76 2.90 3.05 V
HLVDL<3:0> = 1100 2.85 3.00 3.15 V
HLVDL<3:0> = 1101 2.97 3.13 3.29 V
HLVDL<3:0> = 1110 3.23 3.40 3.57 V
D421 TIRVST Time for Internal Reference Voltage to — 50 — s
become Stable
D422 TLVD High/Low-Voltage Detect Pulse Width 200 — — s

DS39964B-page 532 Preliminary  2010 Microchip Technology Inc.

 PIC18F47J53 FAMILY
31.4 AC (Timing) Characteristics
31.4.1 TIMING PARAMETER SYMBOLOGY
The timing parameter symbols have been created
following one of the following formats:

1. TppS2ppS 3. TCC:ST (I2C specifications only)

2. TppS 4. Ts (I2C specifications only)
T
F Frequency T Time
Lowercase letters (pp) and their meanings:
pp
cc CCP1 osc OSC1
ck CLKO rd RD
cs CS rw RD or WR
di SDI sc SCK
do SDO ss SS
dt Data in t0 T0CKI
io I/O port t1 T13CKI
mc MCLR wr WR
Uppercase letters and their meanings:
S
F Fall P Period
H High R Rise
I Invalid (High-impedance) V Valid
L Low Z High-impedance
I2C only
AA output access High High
BUF Bus free Low Low
TCC:ST (I2C specifications only)
CC
HD Hold SU Setup
ST
DAT DATA input hold STO Stop condition
STA Start condition

 2010 Microchip Technology Inc. Preliminary DS39964B-page 533

PIC18F47J53 FAMILY
31.4.2 TIMING CONDITIONS
The temperature and voltages specified in Table 31-9
apply to all timing specifications unless otherwise
noted. Figure 31-4 specifies the load conditions for the
timing specifications.

TABLE 31-9: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC

Standard Operating Conditions (unless otherwise stated)
AC CHARACTERISTICS Operating temperature -40°C  TA +85°C for industrial
Operating voltage VDD range as described in Section 31.1 and Section 31.3.

FIGURE 31-4: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS

Load Condition 1 Load Condition 2

VDD/2

RL Pin CL

VSS
CL
Pin
RL = 464
VSS CL = 50 pF for all pins except OSC2/CLKO/RA6
and including D and E outputs as ports
CL = 15 pF for OSC2/CLKO/RA6

31.4.3 TIMING DIAGRAMS AND SPECIFICATIONS

FIGURE 31-5: EXTERNAL CLOCK TIMING

Q4 Q1 Q2 Q3 Q4 Q1

OSC1
1 3 3 4 4
2
CLKO

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TABLE 31-10: EXTERNAL CLOCK TIMING REQUIREMENTS
Param.
Symbol Characteristic Min Max Units Conditions
No.
1A FOSC External CLKI Frequency(1) DC 48 MHz EC Oscillator mode
DC 48 ECPLL Oscillator mode(2)
(1)
Oscillator Frequency 4 16 MHz HS Oscillator mode
4 16(4) HSPLL Oscillator mode(3)
(1)
1 TOSC External CLKI Period 20.8 — ns EC Oscillator mode
20.8 — ECPLL Oscillator mode(2)
(1)
Oscillator Period 62.5 250 ns HS Oscillator mode
(4)
62.5 250 HSPLL Oscillator mode(3)
(1)
2 TCY Instruction Cycle Time 83.3 DC ns TCY = 4/FOSC, Industrial
3 TOSL, External Clock in (OSC1) 10 — ns EC Oscillator mode
TOSH High or Low Time
4 TOSR, External Clock in (OSC1) — 7.5 ns EC Oscillator mode
TOSF Rise or Fall Time
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period for all configurations
except PLL. All specified values are based on characterization data for that particular oscillator type under
standard operating conditions with the device executing code. Exceeding these specified limits may result
in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested
to operate at “min.” values with an external clock applied to the OSC1/CLKI pin. When an external clock
input is used, the “max.” cycle time limit is “DC” (no clock) for all devices.
2: In order to use the PLL, the external clock frequency must be either 4, 8, 12, 16, 20, 24, 40 or 48 MHz.
3: In order to use the PLL, the crystal/resonator must produce a frequency of either 4, 8, 12 or 16 MHz.
4: This is the maximum crystal/resonator driver frequency. The internal FOSC frequency when running from
the PLL can be up to 48 MHz.

TABLE 31-11: PLL CLOCK TIMING SPECIFICATIONS (VDDCORE = 2.35V TO 2.75V)

Param
Sym Characteristic Min Typ† Max Units Conditions
No.
F10 FOSC Oscillator Frequency Range 4 — 48 MHz
F11 FSYS On-Chip VCO System Frequency — 96 — MHz
F12 trc PLL Start-up Time (lock time) — — 2 ms

TABLE 31-12: INTERNAL RC ACCURACY (INTOSC AND INTRC SOURCES)

Param
Device Min Typ Max Units Conditions
No.
INTOSC Accuracy @ Freq = 8 MHz, 4 MHz, 2 MHz, 1 MHz, 500 kHz, 250 kHz, 125 kHz, 31 kHz(1)
All Devices -1 +0.15 +1 % 0°C to +85°C VDD = 2.4V-3.6V
VDDCORE = 2.3V-2.7V
-1 +0.25 +1 % -40°C to +85°C VDD = 2.0V-3.6V
VDDCORE = 2.0V-2.7V
INTRC Accuracy @ Freq = 31 kHz(1)
All Devices 20.3 — 42.2 kHz -40°C to +85°C VDD = 2.0V-3.6V
VDDCORE = 2.0V-2.7V
Note 1: The accuracy specification of the 31 kHz clock is determined by which source is providing it at a given time.
When INTSRC (OSCTUNE<7>) is ‘1’, use the INTOSC accuracy specification. When INTSRC is ‘0’, use
the INTRC accuracy specification.

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FIGURE 31-6: CLKO AND I/O TIMING
Q4 Q1 Q2 Q3

OSC1

10 11

CLKO

13 12
14 19 18
16

I/O pin
(Input)

17 15

I/O pin Old Value New Value

(Output)

20, 21

Note: Refer to Figure 31-4 for load conditions.

TABLE 31-13: CLKO AND I/O TIMING REQUIREMENTS

Param
Symbol Characteristic Min Typ Max Units Conditions
No.
10 TOSH2CKL OSC1  to CLKO  — 75 200 ns (Note 1)
11 TOSH2CKH OSC1  to CLKO  — 75 200 ns (Note 1)
12 TCKR CLKO Rise Time — 15 30 ns (Note 1)
13 TCKF CLKO Fall Time — 15 30 ns (Note 1)
14 TCKL2IOV CLKO  to Port Out Valid — — 0.5 TCY + 20 ns
15 TIOV2CKH Port In Valid before CLKO  0.25 TCY + 25 — — ns
16 TCKH2IOI Port In Hold after CLKO  0 — — ns
17 TOSH2IOV OSC1  (Q1 cycle) to Port Out Valid — 50 150 ns
18 TOSH2IOI OSC1  (Q2 cycle) to Port Input Invalid 100 — — ns
(I/O in hold time)
19 TIOV2OSH Port Input Valid to OSC1  0 — — ns
(I/O in setup time)
20 TIOR Port Output Rise Time — — 6 ns
21 TIOF Port Output Fall Time — — 5 ns
22† TINP INTx pin High or Low Time TCY — — ns
23† TRBP RB7:RB4 Change INTx High or Low TCY — — ns
Time
† These parameters are asynchronous events not related to any internal clock edges.
Note 1: Measurements are taken in EC mode, where CLKO output is 4 x TOSC.

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FIGURE 31-7: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND
POWER-UP TIMER TIMING

VDD

MCLR

30
Internal
POR

33
PWRT
Time-out 32

Oscillator
Time-out

Internal
Reset

Watchdog
Timer
Reset
31
34 34

I/O pins

Note: Refer to Figure 31-4 for load conditions.

TABLE 31-14: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER
AND BROWN-OUT RESET REQUIREMENTS
Param.
Symbol Characteristic Min Typ Max Units Conditions
No.

30 TMCL MCLR Pulse Width (low) 2 — — s

31 TWDT Watchdog Timer Time-out Period 2.67 4.0 5.53 ms
(no postscaler)
32 TOST Oscillator Start-up Timer Period 1024 TOSC — 1024 TOSC — TOSC = OSC1 period
33 TPWRT Power-up Timer Period — 1.0 — ms
34 TIOZ I/O High-Impedance from MCLR — — 3 TCY + 2 s (Note 1)
Low or Watchdog Timer Reset
36 TIRVST Time for Internal Reference — 20 — s
Voltage to become Stable
37 TLVD High/Low-Voltage Detect — 200 — s
Pulse Width
38 TCSD CPU Start-up Time — 200 — s (Note 2)
Note 1: The maximum TIOZ is the lesser of (3 TCY + 2 s) or 700 s.
2: MCLR rising edge to code execution, assuming TPWRT (and TOST if applicable) has already expired.

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TABLE 31-15: LOW-POWER WAKE-UP TIME
Param.
Symbol Characteristic Min Typ Max Units Conditions
No.
W1 WDS Deep Sleep — 500 — s REGSLP = 1
W2 WSLEEP Sleep — 35 — s REGSLP = 1, PLLEN = 0
FOSC = 8 MHz INTOSC
W3 WDOZE1 Sleep — 12 — s REGSLP = 0, PLLEN = 0,
FOSC = 8 MHz INTOSC
W4 WDOZE2 Sleep — 1.1 — s REGSLP = 0, PLLEN = 0,
FOSC = 8 MHz EC
W5 WDOZE3 Sleep — 230 — ns REGSLP = 0, PLLEN = 0,
FOSC = 48 MHz EC
W6 WIDLE Idle — 230 — ns FOSC = 48 MHz EC

FIGURE 31-8: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS

T0CKI

40 41

42

T1OSO/T1CKI

45 46

47 48

TMR0 or
TMR1

Note: Refer to Figure 31-4 for load conditions.

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TABLE 31-16: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS
Param
Symbol Characteristic Min Max Units Conditions
No.
40 TT0H T0CKI High Pulse Width No prescaler 0.5 TCY + 20 — ns
With prescaler 10 — ns
41 TT0L T0CKI Low Pulse Width No prescaler 0.5 TCY + 20 — ns
With prescaler 10 — ns
42 TT0P T0CKI Period No prescaler TCY + 10 — ns
With prescaler Greater of: — ns N = prescale
20 ns or value
(TCY + 40)/N (1, 2, 4,..., 256)
45 TT1H T1CKI/T3CKI Synchronous, no prescaler 0.5 TCY + 20 — ns
High Time Synchronous, with prescaler 10 — ns
Asynchronous 30 — ns
46 TT1L T1CKI/T3CKI Synchronous, no prescaler 0.5 TCY + 5 — ns
Low Time Synchronous, with prescaler 10 — ns
Asynchronous 30 — ns
47 TT1P T1CKI/T3CKI Synchronous Greater of: — ns N = prescale
Input Period 20 ns or value
(TCY + 40)/N (1, 2, 4, 8)
Asynchronous 83 — ns
FT 1 T1CKI Input Frequency Range(1) DC 12 MHz
48 TCKE2TMRI Delay from External T1CKI Clock Edge to 2 TOSC 7 TOSC —
Timer Increment
Note 1: The Timer1 oscillator is designed to drive 32.768 kHz crystals. When T1CKI is used as a digital input,
frequencies up to 12 MHz are supported.

FIGURE 31-9: ENHANCED CAPTURE/COMPARE/PWM TIMINGS

ECCPx
(Capture Mode)

50 51

52

ECCPx
(Compare or PWM Mode)
53 54

Note: Refer to Figure 31-4 for load conditions.

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TABLE 31-17: ENHANCED CAPTURE/COMPARE/PWM REQUIREMENTS
Param
Symbol Characteristic Min Max Units Conditions
No.
50 TCCL ECCPx Input Low Time No prescaler 0.5 TCY + 20 — ns
With prescaler 10 — ns
51 TCCH ECCPx Input High Time No prescaler 0.5 TCY + 20 — ns
With prescaler 10 — ns
52 TCCP ECCPx Input Period 3 TCY + 40 — ns N = prescale
3 TCY + 40 ---------------------------- value (1, 4 or 16)
N
N
53 TCCR ECCPx Output Fall Time — 25 ns
54 TCCF ECCPx Output Fall Time — 25 ns

FIGURE 31-10: PARALLEL MASTER PORT READ TIMING DIAGRAM

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2

System
Clock

PMA<13:18> Address

PMD<7:0> Address<7:0> Data

PM6
PM2
PM7
PM3
PMRD
PM5
PMWR

PMALL/PMALH
PM1

PMCS<2:1>

Operating Conditions: 2.0V < VDD < 3.6V, -40°C < TA < +85°C unless otherwise stated.

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TABLE 31-18: PARALLEL MASTER PORT READ TIMING REQUIREMENTS
Param.
Symbol Characteristics Min Typ Max Units
No
PM1 PMALL/PMALH Pulse Width — 0.5 TCY — ns
PM2 Address Out Valid to PMALL/PMALH — 0.75 TCY — ns
Invalid (address setup time)
PM3 PMALL/PMALH Invalid to Address Out — 0.25 TCY — ns
Invalid (address hold time)
PM5 PMRD Pulse Width — 0.5 TCY — ns
PM6 PMRD or PMENB Active to Data In Valid — — — ns
(data setup time)
PM7 PMRD or PMENB Inactive to Data In Invalid — — — ns
(data hold time)

FIGURE 31-11: PARALLEL MASTER PORT WRITE TIMING DIAGRAM

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2

System
Clock

PMA<13:18> Address

PMD<7:0> Address<7:0> Data

PM12 PM13

PMRD

PMWR
PM11

PMALL/
PMALH

PMCS<2:1>
PM16

Note: Operating Conditions: 2.0V < VDD < 3.6V, -40°C < TA < +85°C unless otherwise stated.

TABLE 31-19: PARALLEL MASTER PORT WRITE TIMING REQUIREMENTS

Param.
Symbol Characteristics Min Typ Max Units
No
PM11 PMWR Pulse Width — 0.5 TCY — ns
PM12 Data Out Valid before PMWR or PMENB — — — ns
goes Inactive (data setup time)
PM13 PMWR or PMEMB Invalid to Data Out — — — ns
Invalid (data hold time)
PM16 PMCS Pulse Width TCY – 5 — — ns

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FIGURE 31-12: EXAMPLE SPI MASTER MODE TIMING (CKE = 0)

SCKx
(CKP = 0)

78 79

SCKx
(CKP = 1)

79 78

SDOx MSb bit 6 - - - - - - 1 LSb

75, 76

SDIx MSb In bit 6 - - - - 1 LSb In

74
73

Note: Refer to Figure 31-4 for load conditions.

TABLE 31-20: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 0)

Param
Symbol Characteristic Min Max Units Conditions
No.
73 TDIV2SCH, Setup Time of SDIx Data Input to SCKx Edge 35 — ns VDD = 3.3V,
TDIV2SCL VDDCORE = 2.5V
100 — ns VDD = 2.15V,
VDDCORE = 2.15V
73A TB2B Last Clock Edge of Byte 1 to the 1st Clock 1.5 TCY + 40 — ns
Edge of Byte 2
74 TSCH2DIL, Hold Time of SDIx Data Input to SCKx Edge 30 — ns VDD = 3.3V,
TSCL2DIL VDDCORE = 2.5V
83 — ns VDD = 2.15V
75 TDOR SDOx Data Output Rise Time — 25 ns PORTB or PORTC
76 TDOF SDOx Data Output Fall Time — 25 ns PORTB or PORTC
78 TSCR SCKx Output Rise Time (Master mode) — 25 ns PORTB or PORTC
79 TSCF SCKx Output Fall Time (Master mode) — 25 ns PORTB or PORTC

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FIGURE 31-13: EXAMPLE SPI MASTER MODE TIMING (CKE = 1)

81
SCKx
(CKP = 0)

79
73
SCKx
(CKP = 1)

78

SDOx MSb bit 6 - - - - - - 1 LSb

75, 76

SDIx MSb In bit 6 - - - - 1 LSb In

74

Note: Refer to Figure 31-4 for load conditions.

TABLE 31-21: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 1)

Param.
Symbol Characteristic Min Max Units Conditions
No.
73 TDIV2SCH, Setup Time of SDIx Data Input to SCKx Edge 35 — ns VDD = 3.3V,
TDIV2SCL VDDCORE = 2.5V
100 — ns VDD = 2.15V,
VDDCORE = 2.15V
74 TSCH2DIL, Hold Time of SDIx Data Input to SCKx Edge 30 — ns VDD = 3.3V,
TSCL2DIL VDDCORE = 2.5V
83 — ns VDD = 2.15V
75 TDOR SDOx Data Output Rise Time — 25 ns PORTB or PORTC
76 TDOF SDOx Data Output Fall Time — 25 ns PORTB or PORTC
78 TSCR SCKx Output Rise Time (Master mode) — 25 ns PORTB or PORTC
79 TSCF SCKx Output Fall Time (Master mode) — 25 ns PORTB or PORTC
81 TDOV2SCH, SDOx Data Output Setup to SCKx Edge TCY — ns
TDOV2SCL

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FIGURE 31-14: EXAMPLE SPI SLAVE MODE TIMING (CKE = 0)

SSx

70
SCKx
(CKP = 0) 83

71 72

SCKx
(CKP = 1)

80

SDOx MSb bit 6 - - - - - - 1 LSb

75, 76 77

SDIx
SDI MSb In bit 6 - - - - 1 LSb In
74
73

Note: Refer to Figure 31-4 for load conditions.

TABLE 31-22: EXAMPLE SPI MODE REQUIREMENTS (SLAVE MODE TIMING, CKE = 0)
Param
Symbol Characteristic Min Max Units Conditions
No.

70 TSSL2SCH, SSx  to SCKx  or SCKx  Input 3 TCY — ns

TSSL2SCL
70A TSSL2WB SSx to Write to SSPxBUF 3 TCY — ns
71 TSCH SCKx Input High Time Continuous 1.25 TCY + 30 — ns
71A (Slave mode) Single byte 40 — ns (Note 1)
72 TSCL SCKx Input Low Time Continuous 1.25 TCY + 30 — ns
72A (Slave mode) Single byte 40 — ns (Note 1)
73 TDIV2SCH, Setup Time of SDIx Data Input to SCKx Edge 25 — ns
TDIV2SCL
73A TB2B Last Clock Edge of Byte 1 to the First Clock Edge of 1.5 TCY + 40 — ns (Note 2)
Byte 2
74 TSCH2DIL, Hold Time of SDIx Data Input to SCKx Edge 35 — ns VDD = 3.3V,
TSCL2DIL VDDCORE = 2.5V
100 — ns VDD = 2.15V
75 TDOR SDOx Data Output Rise Time — 25 ns PORTB or PORTC
76 TDOF SDOx Data Output Fall Time — 25 ns PORTB or PORTC
77 TSSH2DOZ SSx  to SDOx Output High-Impedance 10 70 ns
80 TSCH2DOV, SDOx Data Output Valid after SCKx Edge — 50 ns VDD = 3.3V,
TSCL2DOV VDDCORE = 2.5V
— 100 ns VDD = 2.15V
83 TSCH2SSH, SSx  after SCKx Edge 1.5 TCY + 40 — ns
TSCL2SSH
Note 1: Requires the use of Parameter #73A.
2: Only if Parameter #71A and #72A are used.

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FIGURE 31-15: EXAMPLE SPI SLAVE MODE TIMING (CKE = 1)
82
SSx

70
SCKx 83
(CKP = 0)

71 72
73
SCKx
(CKP = 1)
80

SDOx MSb bit 6 - - - - - - 1 LSb

75, 76 77
SDI
SDIx
MSb In bit 6 - - - - 1 LSb In

74
Note: Refer to Figure 31-4 for load conditions.

TABLE 31-23: EXAMPLE SPI SLAVE MODE REQUIREMENTS (CKE = 1)

Param
Symbol Characteristic Min Max Units Conditions
No.
70 TSSL2SCH, SSx  to SCKx  or SCKx  Input 3 TCY — ns
TSSL2SCL
70A TSSL2WB SSx to Write to SSPxBUF 3 TCY — ns
71 TSCH SCKx Input High Time Continuous 1.25 TCY + 30 — ns
71A (Slave mode) Single byte 40 — ns (Note 1)
72 TSCL SCKx Input Low Time Continuous 1.25 TCY + 30 — ns
72A (Slave mode) Single byte 40 — ns (Note 1)
73 TDIV2SCH, Setup Time of SDIx Data Input to SCKx Edge 25 — ns
TDIV2SCL
73A T B 2B Last Clock Edge of Byte 1 to the First Clock Edge of Byte 2 1.5 TCY + 40 — ns (Note 2)
74 TSCH2DIL, Hold Time of SDIx Data Input to SCKx Edge 35 — ns VDD = 3.3V,
TSCL2DIL VDDCORE = 2.5V
100 — ns VDD = 2.15V
75 TDOR SDOx Data Output Rise Time — 25 ns
76 TDOF SDOx Data Output Fall Time — 25 ns
77 TSSH2DOZ SSx  to SDOx Output High-Impedance 10 70 ns
80 TSCH2DOV, SDOx Data Output Valid after SCKx Edge — 50 ns VDD = 3.3V,
TSCL2DOV VDDCORE = 2.5V
— 100 ns VDD = 2.15V
81 TDOV2SCH, SDOx Data Output Setup to SCKx Edge TCY — ns
TDOV2SCL
82 TSSL2DOV SDOx Data Output Valid after SSx  Edge — 50 ns
83 TSCH2SSH, SSx  after SCKx Edge 1.5 TCY + 40 — ns
TSCL2SSH
Note 1: Requires the use of Parameter #73A.
2: Only if Parameter #71A and #72A are used.

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FIGURE 31-16: I2C™ BUS START/STOP BITS TIMING

SCLx
91 93
90 92

SDAx

Start Stop
Condition Condition

Note: Refer to Figure 31-4 for load conditions.

TABLE 31-24: I2C™ BUS START/STOP BITS REQUIREMENTS (SLAVE MODE)

Param.
Symbol Characteristic Min Max Units Conditions
No.
90 TSU:STA Start Condition 100 kHz mode 4700 — ns Only relevant for Repeated
Setup Time 400 kHz mode 600 — Start condition
91 THD:STA Start Condition 100 kHz mode 4000 — ns After this period, the first
Hold Time 400 kHz mode 600 — clock pulse is generated
92 TSU:STO Stop Condition 100 kHz mode 4700 — ns
Setup Time 400 kHz mode 600 —
93 THD:STO Stop Condition 100 kHz mode 4000 — ns
Hold Time 400 kHz mode 600 —

FIGURE 31-17: I2C™ BUS DATA TIMING

103 100 102

101
SCLx
90
106 107

91 92
SDAx
In
110
109 109

SDAx
Out

Note: Refer to Figure 31-4 for load conditions.

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TABLE 31-25: I2C™ BUS DATA REQUIREMENTS (SLAVE MODE)
Param.
Symbol Characteristic Min Max Units Conditions
No.

100 THIGH Clock High Time 100 kHz mode 4.0 — s

400 kHz mode 0.6 — s
MSSP modules 1.5 TCY —
101 TLOW Clock Low Time 100 kHz mode 4.7 — s
400 kHz mode 1.3 — s
MSSP modules 1.5 TCY —
102 TR SDAx and SCLx Rise Time 100 kHz mode — 1000 ns
400 kHz mode 20 + 0.1 CB 300 ns CB is specified to be from
10 to 400 pF
103 TF SDAx and SCLx Fall Time 100 kHz mode — 300 ns
400 kHz mode 20 + 0.1 CB 300 ns CB is specified to be from
10 to 400 pF
90 TSU:STA Start Condition Setup Time 100 kHz mode 4.7 — s Only relevant for Repeated
400 kHz mode 0.6 — s Start condition

91 THD:STA Start Condition Hold Time 100 kHz mode 4.0 — s After this period, the first clock
400 kHz mode 0.6 — s pulse is generated

106 THD:DAT Data Input Hold Time 100 kHz mode 0 — ns

400 kHz mode 0 0.9 s
107 TSU:DAT Data Input Setup Time 100 kHz mode 250 — ns (Note 2)
400 kHz mode 100 — ns
92 TSU:STO Stop Condition Setup Time 100 kHz mode 4.7 — s
400 kHz mode 0.6 — s
109 TAA Output Valid from Clock 100 kHz mode — 3500 ns (Note 1)
400 kHz mode — — ns
110 TBUF Bus Free Time 100 kHz mode 4.7 — s Time the bus must be free
400 kHz mode 1.3 — s before a new transmission can
start
D102 CB Bus Capacitive Loading — 400 pF
Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns)
of the falling edge of SCLx to avoid unintended generation of Start or Stop conditions.
2: A Fast mode I2C™ bus device can be used in a Standard mode I2C bus system, but the requirement, TSU:DAT  250 ns,
must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCLx signal.
If such a device does stretch the LOW period of the SCLx signal, it must output the next data bit to the SDAx line, TR
max. + TSU:DAT = 1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification), before the SCLx line is
released.

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FIGURE 31-18: MSSPx I2C™ BUS START/STOP BITS TIMING WAVEFORMS

SCLx
91 93
90 92

SDAx

Start Stop
Condition Condition

Note: Refer to Figure 31-4 for load conditions.

TABLE 31-26: MSSPx I2C™ BUS START/STOP BITS REQUIREMENTS

Param.
Symbol Characteristic Min Max Units Conditions
No.
90 TSU:STA Start Condition 100 kHz mode 2(TOSC)(BRG + 1) — ns Only relevant for
Setup Time 400 kHz mode 2(TOSC)(BRG + 1) — Repeated Start
condition
1 MHz mode(1) 2(TOSC)(BRG + 1) —
91 THD:STA Start Condition 100 kHz mode 2(TOSC)(BRG + 1) — ns After this period, the
Hold Time 400 kHz mode 2(TOSC)(BRG + 1) — first clock pulse is
generated
1 MHz mode(1) 2(TOSC)(BRG + 1) —
92 TSU:STO Stop Condition 100 kHz mode 2(TOSC)(BRG + 1) — ns
Setup Time 400 kHz mode 2(TOSC)(BRG + 1) —
1 MHz mode(1) 2(TOSC)(BRG + 1) —
93 THD:STO Stop Condition 100 kHz mode 2(TOSC)(BRG + 1) — ns
Hold Time 400 kHz mode 2(TOSC)(BRG + 1) —
1 MHz mode(1) 2(TOSC)(BRG + 1) —
Note 1: Maximum pin capacitance = 10 pF for all I2C™ pins.

FIGURE 31-19: MSSPx I2C™ BUS DATA TIMING

103 100 102
101
SCLx
90 106
91 107 92
SDAx
In
109 109 110

SDAx
Out

Note: Refer to Figure 31-4 for load conditions.

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TABLE 31-27: MSSPx I2C™ BUS DATA REQUIREMENTS
Param.
Symbol Characteristic Min Max Units Conditions
No.
100 THIGH Clock High Time 100 kHz mode 2(TOSC)(BRG + 1) — s
400 kHz mode 2(TOSC)(BRG + 1) — s
1 MHz mode(1) 2(TOSC)(BRG + 1) — s
101 TLOW Clock Low Time 100 kHz mode 2(TOSC)(BRG + 1) — s
400 kHz mode 2(TOSC)(BRG + 1) — s
(1)
1 MHz mode 2(TOSC)(BRG + 1) — s
102 TR SDAx and SCLx 100 kHz mode — 1000 ns CB is specified to be
Rise Time 400 kHz mode 20 + 0.1 CB 300 ns from 10 to 400 pF
1 MHz mode(1) — 300 ns
103 TF SDAx and SCLx 100 kHz mode — 300 ns CB is specified to be
Fall Time 400 kHz mode 20 + 0.1 CB 300 ns from 10 to 400 pF
1 MHz mode(1) — 100 ns
90 TSU:STA Start Condition 100 kHz mode 2(TOSC)(BRG + 1) — s Only relevant for
Setup Time 400 kHz mode 2(TOSC)(BRG + 1) — s Repeated Start condition
1 MHz mode(1) 2(TOSC)(BRG + 1) — s
91 THD:STA Start Condition 100 kHz mode 2(TOSC)(BRG + 1) — s After this period, the first
Hold Time 400 kHz mode 2(TOSC)(BRG + 1) — s clock pulse is generated
1 MHz mode(1) 2(TOSC)(BRG + 1) — s
106 THD:DAT Data Input 100 kHz mode 0 — ns
Hold Time 400 kHz mode 0 0.9 s
1 MHz mode(1) TBD — ns
107 TSU:DAT Data Input 100 kHz mode 250 — ns (Note 2)
Setup Time 400 kHz mode 100 — ns
1 MHz mode(1) TBD — ns
92 TSU:STO Stop Condition 100 kHz mode 2(TOSC)(BRG + 1) — s
Setup Time 400 kHz mode 2(TOSC)(BRG + 1) — s
1 MHz mode(1) 2(TOSC)(BRG + 1) — s
109 TAA Output Valid 100 kHz mode — 3500 ns
from Clock 400 kHz mode — 1000 ns
(1)
1 MHz mode — — ns
110 TBUF Bus Free Time 100 kHz mode 4.7 — s Time the bus must be
400 kHz mode 1.3 — s free before a new
transmission can start
1 MHz mode(1) TBD — s
D102 CB Bus Capacitive Loading — 400 pF
Legend: TBD = To Be Determined
Note 1: Maximum pin capacitance = 10 pF for all I2C™ pins.
2: A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but parameter
#107  250 ns must then be met. This will automatically be the case if the device does not stretch the LOW
period of the SCLx signal. If such a device does stretch the LOW period of the SCLx signal, it must output
the next data bit to the SDAx line, parameter #102 + parameter #107 = 1000 + 250 = 1250 ns (for 100 kHz
mode), before the SCLx line is released.

 2010 Microchip Technology Inc. Preliminary DS39964B-page 549

PIC18F47J53 FAMILY
FIGURE 31-20: EUSARTx SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING

TXx/CKx
pin
121 121
RXx/DTx
pin

120
122
Note: Refer to Figure 31-4 for load conditions.

TABLE 31-28: EUSARTx SYNCHRONOUS TRANSMISSION REQUIREMENTS

Param
Symbol Characteristic Min Max Units Conditions
No.
120 TCKH2DTV Sync XMIT (Master and Slave)
Clock High to Data Out Valid — 40 ns
121 TCKRF Clock Out Rise Time and Fall Time (Master mode) — 20 ns
122 TDTRF Data Out Rise Time and Fall Time — 20 ns

FIGURE 31-21: EUSARTx SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING

TXx/CKx
pin 125
RXx/DTx
pin
126

Note: Refer to Figure 31-4 for load conditions.

TABLE 31-29: EUSARTx SYNCHRONOUS RECEIVE REQUIREMENTS

Param.
Symbol Characteristic Min Max Units Conditions
No.
125 TDTV2CKL Sync RCV (Master and Slave)
Data Hold before CKx  (DTx hold time) 10 — ns
126 TCKL2DTL Data Hold after CKx  (DTx hold time) 15 — ns

DS39964B-page 550 Preliminary  2010 Microchip Technology Inc.

 PIC18F47J53 FAMILY
TABLE 31-30: A/D CONVERTER CHARACTERISTICS: PIC18F47J53 FAMILY (INDUSTRIAL)
Param
Symbol Characteristic Min Typ Max Units Conditions
No.
A01 NR Resolution — — 12 bit VREF  3.0V
A03 EIL Integral Linearity Error — <±1 ±2 LSb VREF  3.0V
A04 EDL Differential Linearity Error — <±1 1.5 LSb VREF  3.0V
A06 EOFF Offset Error — <±1 5 LSb VREF  3.0V
A07 EGN Gain Error — — <±3.5 LSb VREF  3.0V
A10 Monotonicity Guaranteed(1) — VSS  VAIN  VREF
A20 VREF Reference Voltage Range 2.0 — — V VDD  3.0V
(VREFH – VREFL) 3 — — V VDD  3.0V
A21 VREFH Reference Voltage High
For 10-bit resolution VREFL — VDD + 0.3V V
For 12-bit resolution VSS + 3V — VDD + 0.3V V
A22 VREFL Reference Voltage Low
For 10-bit resolution VSS – 0.3V — VREFH V
For 12-bit resolution VSS – 0.3V — VDD - 3V V
A25 VAIN Analog Input Voltage VREFL — VREFH V
A30 ZAIN Recommended Impedance of
Analog Voltage Source
For 10-bit resolution — — 10 k
For 12-bit resolution — — 2.5 k
A50 IREF VREF Input Current(2) — — 5 A During VAIN acquisition.
— — 150 A During A/D conversion
cycle.
Note 1: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes.
2: VREFH current is from RA3/AN3/VREF+/C1INB pin or VDD, whichever is selected as the VREFH source.
VREFL current is from RA2/AN2/VREF-/CVREF/C2INB pin or VSS, whichever is selected as the VREFL source.

FIGURE 31-22: A/D CONVERSION TIMING

BSF ADCON0, GO
(Note 2)
131
Q4
130
A/D CLK 132

A/D DATA 9 8 7 ... ... 2 1 0

ADRES OLD_DATA NEW_DATA

ADIF TCY (Note 1)

GO DONE

SAMPLING STOPPED
SAMPLE

Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts.
This allows the SLEEP instruction to be executed.
2: This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input.

 2010 Microchip Technology Inc. Preliminary DS39964B-page 551

PIC18F47J53 FAMILY
TABLE 31-31: 10-BIT A/D CONVERSION REQUIREMENTS
Param
Symbol Characteristic Min Max Units Conditions
No.
130 TAD A/D Clock Period 0.7 25.0(1) s TOSC based, VREF  3.0V
131 TCNV Conversion Time 11 12 TAD
(not including acquisition time)(2)
132 TACQ Acquisition Time(3) 1.4 — s -40C to +85C
135 TSWC Switching Time from Convert  Sample — (Note 4)
137 TDIS Discharge Time 0.2 — s
Note 1: The time of the A/D clock period is dependent on the device frequency and the TAD clock divider.
2: ADRES registers may be read on the following TCY cycle.
3: The time for the holding capacitor to acquire the “New” input voltage when the voltage changes full scale after the con-
version (VDD to VSS or VSS to VDD). The source impedance (RS) on the input channels is 50W.
4: On the following cycle of the device clock.

TABLE 31-32: 12-BIT A/D CONVERSION REQUIREMENTS

Param
Symbol Characteristic Min Max Units Conditions
No.
130 TAD A/D Clock Period 0.8 12.5(1) s TOSC based, VREF  3.0V
131 TCNV Conversion Time 13 14 TAD
(not including acquisition time)(2)
132 TACQ Acquisition Time(3) 1.4 — s
135 TSWC Switching Time from Convert  Sample — (Note 4)
137 TDIS Discharge Time 0.2 — s
Note 1: The time of the A/D clock period is dependent on the device frequency and the TAD clock divider.
2: ADRES registers may be read on the following TCY cycle.
3: The time for the holding capacitor to acquire the “New” input voltage when the voltage changes full scale
after the conversion (VDD to VSS or VSS to VDD). The source impedance (RS) on the input channels is 50.
4: On the following cycle of the device clock.

DS39964B-page 552 Preliminary  2010 Microchip Technology Inc.

 PIC18F47J53 FAMILY
FIGURE 31-23: USB SIGNAL TIMING

USB Data Differential Lines

90%

VCRS

10%

TLR, TFR TLF, TFF

TABLE 31-33: USB LOW-SPEED TIMING REQUIREMENTS

Param
Symbol Characteristic Min Typ Max Units Conditions
No.
TLR Transition Rise Time 75 — 300 ns CL = 200 to 600 pF
TLF Transition Fall Time 75 — 300 ns CL = 200 to 600 pF
TLRFM Rise/Fall Time Matching 80 — 125 %

TABLE 31-34: USB FULL-SPEED REQUIREMENTS

Param
Symbol Characteristic Min Typ Max Units Conditions
No.
TFR Transition Rise Time 4 — 20 ns CL = 50 pF
TFF Transition Fall Time 4 — 20 ns CL = 50 pF
TFRFM Rise/Fall Time Matching 90 — 111.1 %

 2010 Microchip Technology Inc. Preliminary DS39964B-page 553

PIC18F47J53 FAMILY
NOTES:

DS39964B-page 554 Preliminary  2010 Microchip Technology Inc.

 PIC18F47J53 FAMILY
32.0 PACKAGING INFORMATION
32.1 Package Marking Information

28-Lead QFN Example

XXXXXXXX 18F27J53
XXXXXXXX /ML e3
YYWWNNN 0910017

28-Lead SOIC (.300”) Example

XXXXXXXXXXXXXXXXXXXX PIC18F27J53/SO e3
PIC18F26J50/SO
XXXXXXXXXXXXXXXXXXXX 0910017
XXXXXXXXXXXXXXXXXXXX
YYWWNNN

28-Lead SPDIP Example

XXXXXXXXXXXXXXXXX PIC18F27J53
XXXXXXXXXXXXXXXXX -I/SP e3
YYWWNNN 0910017

28-Lead SSOP Example

XXXXXXXXXXXX PICXXFXXXX
XXXXXXXXXXXX -I/SS
YYWWNNN 0610017

Legend: XX...X Customer-specific information

Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
* This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.

 2010 Microchip Technology Inc. Preliminary DS39964B-page 555

PIC18F47J53 FAMILY
Package Marking Information (Continued)

44-Lead QFN Example

XXXXXXXXXX 18F47J53
XXXXXXXXXX -I/ML e3
XXXXXXXXXX 0910017
YYWWNNN

44-Lead TQFP Example

XXXXXXXXXX 18F47J53
XXXXXXXXXX -I/PT e3
XXXXXXXXXX 0910017
YYWWNNN

DS39964B-page 556 Preliminary  2010 Microchip Technology Inc.

 PIC18F47J53 FAMILY
32.2 Package Details
The following sections give the technical details of the packages.


      
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 2010 Microchip Technology Inc. Preliminary DS39964B-page 557

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 2010 Microchip Technology Inc. Preliminary DS39964B-page 559

PIC18F47J53 FAMILY

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

DS39964B-page 560 Preliminary  2010 Microchip Technology Inc.

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 2010 Microchip Technology Inc. Preliminary DS39964B-page 561

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DS39964B-page 562 Preliminary  2010 Microchip Technology Inc.

 PIC18F47J53 FAMILY

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

 2010 Microchip Technology Inc. Preliminary DS39964B-page 563

PIC18F47J53 FAMILY

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DS39964B-page 564 Preliminary  2010 Microchip Technology Inc.

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 2010 Microchip Technology Inc. Preliminary DS39964B-page 565

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DS39964B-page 566 Preliminary  2010 Microchip Technology Inc.

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 2010 Microchip Technology Inc. Preliminary DS39964B-page 567

PIC18F47J53 FAMILY
NOTES:

DS39964B-page 568 Preliminary  2010 Microchip Technology Inc.

 PIC18F47J53 FAMILY
APPENDIX A: REVISION HISTORY APPENDIX B: MIGRATION FROM
PIC18F46J50 TO
Revision A (December 2009)
PIC18F47J53
Original data sheet for PIC18F47J53 family devices.
Code for the devices in the PIC18F46J50 family can be
Revision B (June 2010) migrated to the PIC18F47J53 without many changes.
The differences between the two device families are
Updates typical and maximum DC current specifica- listed in Table B-1.
tions in Section 31.2 “DC Characteristics:
Power-Down and Supply Current PIC18F47J53
Family (Industrial)”.
Removes all references to the LPT1OSC Configuration
bit throughout the data sheet; substitutes appropriate
references to the SOSCSEL Configuration bits.

TABLE B-1: NOTABLE DIFFERENCES BETWEEN PIC18F47J53 AND PIC18F46J50 FAMILIES

Characteristic PIC18F47J53 Family PIC18F46J50 Family
Max Program Memory 128 Kbytes 64 Kbytes
Oscillator options PLL can be enabled at start-up with Requires firmware to set the PLLEN bit at
Config bit option run time
SOSC Oscillator Options Low-power oscillator option for SOSC, Low-power oscillator option for SOSC,
with run-time switch only via Configuration bit setting
T1CKI Clock Input T1CKI can be used as a clock input No
without enabling the Timer1 oscillator
INTOSC Up to 8 MHz Up to 8 MHz
Timers 8 5
ECCP 3 2
CCP 7 0
SPI Fosc/8 Master Clock Yes No
Option
ADC 13 Channel, 10/12-bit conversion modes 13 Channel, 10-bit only
with Special Event Trigger option.
Peripheral Module Disable Yes, allowing further power reduction No
Bits
Band Gap Voltage Reference Yes, enabled on pin RA1 by setting the No
Output VBGOE bit (WDTCON<4>)
REPU/RDPU Pull-Up Enable Moved to TRISE register (avoids read, Pull-up bits configured in PORTE register
Bits modify, write issues)
Comparators Three, each with four input-pin selections Two, each with two input-pin selections
Increased Output Drive RA0 through RA5, RDx and REx No
Strength

 2010 Microchip Technology Inc. Preliminary DS39964B-page 569

PIC18F47J53 FAMILY
NOTES:

DS39964B-page 570 Preliminary  2010 Microchip Technology Inc.

 PIC18F47J53 FAMILY
INDEX
Symbols Clock Source Multiplexing ........................................ 250
Comparator Analog Input Model............................... 410
............................................................................................ 71
<$end ................................................................................ 101 Comparator Simplified .............................................. 407
<$start ................................................................................. 94 Comparator Voltage Reference................................ 415
Comparator Voltage Reference Output
A Buffer Example ................................................. 417
A/D .................................................................................... 367 Compare Mode Operation ................................ 264, 274
A/D Converter Interrupt, Configuring ........................ 373 CTMU ....................................................................... 425
Acquisition Requirements ......................................... 374 CTMU Current Source Calibration Circuit ................ 428
ADCAL Bit................................................................. 377 CTMU Typical Connections and Internal
ADRESH Register..................................................... 372 Configuration for Pulse Delay Generation ........ 436
Analog Port Pins, Configuring................................... 375 CTMU Typical Connections and Internal
Associated Registers ................................................ 378 Configuration for Time Measurement ............... 435
Automatic Acquisition Time....................................... 375 Demultiplexed Addressing Mode.............................. 194
Calibration................................................................. 377 Device Clock............................................................... 36
Configuring the Module............................................. 373 Dual Power ............................................................... 400
Conversion Clock (TAD) ............................................ 375 Enhanced PWM Mode.............................................. 275
Conversion Requirements, 10-bit ............................. 552 EUSART Transmit .................................................... 355
Conversion Requirements, 12-bit ............................. 552 EUSARTx Receive ................................................... 357
Conversion Status (GO/DONE Bit) ........................... 372 External Circuitry ...................................................... 384
Conversions .............................................................. 376 Fail-Safe Clock Monitor ............................................ 456
Converter Characteristics ......................................... 551 Fully Multiplexed Addressing Mode.......................... 194
Operation in Power-Managed Modes ....................... 378 Generic I/O Port Operation....................................... 141
Use of the Special Event Triggers ............................ 376 High/Low-Voltage Detect with External Input ........... 420
Absolute Maximum Ratings .............................................. 513 Interrupt Logic........................................................... 122
AC (Timing) Characteristics .............................................. 533 LCD Control.............................................................. 202
Load Conditions for Device Timing Specifications.... 534 Legacy Parallel Slave Port ....................................... 188
Parameter Symbology .............................................. 533 MSSPx (I2C Master Mode) ....................................... 330
Temperature and Voltage Specifications .................. 534 MSSPx (I2C Mode) ................................................... 310
Timing Conditions ..................................................... 534 MSSPx (SPI Mode) .................................................. 292
ACKSTAT ......................................................................... 335 Multiplexed Addressing Application.......................... 201
ACKSTAT Status Flag ...................................................... 335 On-Chip Reset Circuit................................................. 65
ADCAL Bit ......................................................................... 377 Parallel EEPROM (Up to 15-Bit Address,
ADCON0 Register 16-Bit Data) ...................................................... 202
GO/DONE Bit............................................................ 372 Parallel EEPROM (Up to 15-Bit Address,
ADDFSR ........................................................................... 502 8-Bit Data) ........................................................ 202
ADDLW ............................................................................. 465 Parallel Master/Slave Connection
ADDULNK ......................................................................... 502 Addressed Buffer.............................................. 191
ADDWF ............................................................................. 465 Parallel Master/Slave Connection Buffered.............. 190
ADDWFC .......................................................................... 466 Partially Multiplexed Addressing Application ............ 201
ADRESL Register ............................................................. 372 Partially Multiplexed Addressing Mode..................... 194
Analog-to-Digital Converter. See A/D. PIC18F2XJ53 (28-Pin) ............................................... 14
ANDLW ............................................................................. 466 PIC18F4XJ53 (44-Pin) ............................................... 15
ANDWF ............................................................................. 467 PMP Module ............................................................. 179
Assembler PWM Operation (Simplified) ..................................... 266
MPASM Assembler................................................... 510 Reads From Flash Program Memory ....................... 113
Auto-Wake-up on Sync Break Character .......................... 358 RTCC........................................................................ 237
Self-Power Only........................................................ 400
B Simplified Steering.................................................... 288
Baud Rate Generator ........................................................ 331 Single Comparator.................................................... 410
BC ..................................................................................... 467 Table Read Operation .............................................. 109
BCF ................................................................................... 468 Table Write Operation .............................................. 110
BF ..................................................................................... 335 Table Writes to Flash Program Memory ................... 115
BF Status Flag .................................................................. 335 Timer0 in 16-Bit Mode .............................................. 206
Block Diagrams Timer0 in 8-Bit Mode ................................................ 206
+5V System Hardware Interface ............................... 142 Timer1 ...................................................................... 212
8-Bit Multiplexed Address and Data Application ....... 201 Timer2 ...................................................................... 220
A/D ............................................................................ 372 Timer3 ...................................................................... 225
Analog Input Model ................................................... 373 Timer4 ...................................................................... 234
Baud Rate Generator................................................ 332 USB Interrupt Logic .................................................. 394
Buffer Descriptor ....................................................... 388 USB Layers .............................................................. 404
Bus Power Only ........................................................ 400 USB Peripheral and Options .................................... 379
Capture Mode Operation .................................. 262, 273 Using the Open-Drain Output ................................... 142

 2010 Microchip Technology Inc. Preliminary DS39964B-page 571

PIC18F47J53 FAMILY
USTAT FIFO ............................................................. 385 Changing Between Capture Prescalers............ 263, 273
Watchdog Timer........................................................ 451 Communicating with the +5V System....................... 142
BN ..................................................................................... 468 Computed GOTO Using an Offset Value.................... 85
BNC................................................................................... 469 Configuring EUSART2 Input and
BNN................................................................................... 469 Output Functions .............................................. 164
BNOV ................................................................................ 470 Current Calibration Routine ...................................... 430
BNZ ................................................................................... 470 Erasing Flash Program Memory ............................... 114
BOR. See Brown-out Reset. Fast Register Stack .................................................... 85
BOV................................................................................... 473 How to Clear RAM (Bank 1) Using
BRA................................................................................... 471 Indirect Addressing........................................... 103
Break Character (12-Bit) Transmit and Receive ............... 360 Initializing PORTA..................................................... 145
BRG. See Baud Rate Generator. Initializing PORTB..................................................... 148
Brown-out Reset (BOR) ...................................................... 67 Initializing PORTC .................................................... 152
and On-Chip Voltage Regulator ................................ 454 Initializing PORTD .................................................... 155
Detecting ..................................................................... 67 Initializing PORTE..................................................... 158
Disabling in Sleep Mode ............................................. 67 Loading the SSP1BUF (SSP1SR) Register.............. 295
BSF ................................................................................... 471 Reading a Flash Program Memory Word ................. 113
BTFSC .............................................................................. 472 Saving STATUS, WREG and BSR
BTFSS............................................................................... 472 Registers in RAM.............................................. 140
BTG................................................................................... 473 Setting the RTCWREN Bit ........................................ 251
BZ...................................................................................... 474 Setup for CTMU Calibration Routines ...................... 429
Two-Word Instructions................................................ 87
C Ultra Low-Power Wake-up Initialization ...................... 62
C Compilers Writing to Flash Program Memory ............................ 116
MPLAB C18 .............................................................. 510 Code Protection ................................................................ 441
Calibration (A/D Converter)............................................... 377 COMF ............................................................................... 476
CALL ................................................................................. 474 Comparator....................................................................... 407
CALLW.............................................................................. 503 Analog Input Connection Considerations ................. 410
Capture (CCP Module)...................................................... 262 Associated Registers ................................................ 413
Associated Registers ................................................ 265 Configuration ............................................................ 411
CCP Pin Configuration .............................................. 262 Control ...................................................................... 411
CCPR4H:CCPR4L Registers .................................... 262 Effects of a Reset ..................................................... 413
Software Interrupt ..................................................... 263 Enable and Input Selection....................................... 411
Timer1/Timer3 Mode Selection ................................. 262 Enable and Output Selection .................................... 411
Capture (ECCP Module) ................................................... 272 Interrupts .................................................................. 412
CCPRxH:CCPRxL Registers .................................... 272 Operation .................................................................. 410
ECCP Pin Configuration ........................................... 272 Operation During Sleep ............................................ 413
Prescaler ................................................................... 273 Registers .................................................................. 407
Software Interrupt ..................................................... 273 Response Time......................................................... 410
Timer1/Timer3 Mode Selection ................................. 273 Comparator Specifications................................................ 529
Capture/Compare/PWM (CCP)......................................... 257 Comparator Voltage Reference ........................................ 415
Capture Mode. See Capture. Accuracy and Error ................................................... 417
CCP Mode and Timer Resources ............................. 261 Associated Registers ................................................ 417
CCP6/7/8/9 Pin Assignment ..................................... 262 Configuring ............................................................... 416
CCPRxH Register ..................................................... 261 Connection Considerations....................................... 417
CCPRxL Register...................................................... 261 Effects of a Reset ..................................................... 417
Compare Mode. See Compare. Operation During Sleep ............................................ 417
Configuration............................................................. 261 Compare (CCP Module) ................................................... 263
Open-Drain Output Option ........................................ 262 Associated Registers ................................................ 265
CCP................................................................................... 261 CCP Pin Configuration.............................................. 263
Clock Sources ..................................................................... 42 CCPR4 Register ....................................................... 263
Effects of Power-Managed Modes .............................. 46 Software Interrupt ..................................................... 263
Selecting the 31 kHz Source....................................... 42 Special Event Trigger ............................................... 263
Selection Using OSCCON Register ............................ 42 Timer1/Timer3 Mode Selection................................. 263
CLRF................................................................................. 475 Compare (ECCP Module)................................................. 274
CLRWDT........................................................................... 475 CCPRx Register ....................................................... 274
Code Examples Pin Configuration ...................................................... 274
16 x 16 Signed Multiply Routine ............................... 120 Software Interrupt ..................................................... 274
16 x 16 Unsigned Multiply Routine ........................... 120 Special Event Trigger ....................................... 230, 274
512-Byte SPI Master Mode Init and Transfer............ 308 Timer1/Timer3 Mode Selection................................. 274
8 x 8 Signed Multiply Routine ................................... 119 Computed GOTO................................................................ 85
8 x 8 Unsigned Multiply Routine ............................... 119 Configuration Bits ............................................................. 441
A/D Calibration Routine ............................................ 378 Configuration Mismatch (CM) Reset................................... 68
Calculating Baud Rate Error ..................................... 350 Configuration Register Protection..................................... 457
Capacitance Calibration Routine .............................. 432 Configuration Registers
Capacitive Touch Switch Routine ............................. 434

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Bits and Device IDs................................................... 442 Other Special Features............................................... 12
Mapping Flash Configuration Words......................... 442 Direct Addressing ............................................................. 104
Core Features
Easy Migration ............................................................ 12 E
Expanded Memory...................................................... 11 Effect on Standard PIC18 Instructions.............................. 506
Extended Instruction Set............................................. 12 Electrical Characteristics .................................................. 513
nanoWatt Technology ................................................. 11 Absolute Maximum Ratings ...................................... 513
Oscillator Options and Features ................................. 11 DC Characteristics............................................ 515–527
Universal Serial Bus (USB)......................................... 11 Enhanced Capture/Compare/PWM (ECCP)..................... 269
CPFSEQ ........................................................................... 476 Associated Registers................................................ 289
CPFSGT ........................................................................... 477 Capture Mode. See Capture.
CPFSLT ............................................................................ 477 Compare Mode. See Compare.
Crystal Oscillator/Ceramic Resonators ............................... 37 ECCP Mode and Timer Resources .......................... 272
CTMU Enhanced PWM Mode.............................................. 275
Associated Registers ................................................ 439 Auto-Restart ..................................................... 284
Calibrating................................................................. 427 Auto-Shutdown ................................................. 282
Creating a Delay with................................................ 436 Direction Change in Full-Bridge
Effects of a Reset...................................................... 436 Output Mode............................................. 281
Initialization ............................................................... 427 Full-Bridge Application...................................... 279
Measuring Capacitance with..................................... 433 Full-Bridge Mode .............................................. 279
Measuring Time with................................................. 435 Half-Bridge Application ..................................... 278
Operation .................................................................. 426 Half-Bridge Application Examples .................... 285
Operation During Idle Mode...................................... 436 Half-Bridge Mode.............................................. 278
Operation During Sleep Mode .................................. 436 Output Relationships (Active-High
CTMU Current Source Specifications ............................... 530 and Active-Low)........................................ 276
Customer Change Notification Service ............................. 583 Output Relationships Diagram.......................... 277
Customer Notification Service........................................... 583 Programmable Dead-Band Delay..................... 285
Customer Support ............................................................. 583 Shoot-Through Current..................................... 285
Start-up Considerations.................................... 282
D Outputs and Configuration........................................ 272
Data Addressing Modes.................................................... 103 Enhanced Universal Synchronous Asynchronous
Comparing Addressing Modes with the Receiver Transmitter (EUSART). See EUSART.
Extended Instruction Set Enabled .................... 107 Equations
Direct......................................................................... 103 A/D Acquisition Time ................................................ 374
Indexed Literal Offset................................................ 106 A/D Minimum Charging Time ................................... 374
BSR .................................................................. 108 Bytes Transmitted for a Given DMABC .................... 306
Instructions Affected ......................................... 106 Calculating the Minimum Required
Mapping Access Bank ...................................... 108 Acquisition Time ............................................... 374
Indirect ...................................................................... 103 Calculating USB Transceiver Current....................... 402
Inherent and Literal ................................................... 103 Estimating USB Transceiver Current
Data Memory ...................................................................... 88 Consumption ............................................................ 401
Access Bank ............................................................... 91 Errata .................................................................................... 9
Bank Select Register (BSR)........................................ 89 EUSART ........................................................................... 345
Extended Instruction Set........................................... 106 Asynchronous Mode................................................. 355
General Purpose Registers......................................... 91 12-Bit Break Transmit and Receive.................. 360
Memory Maps Associated Registers, Reception...................... 358
Access Bank Special Function Registers ........... 92 Associated Registers, Transmission ................ 356
Non-Access Bank Special Auto-Wake-up on Sync Break .......................... 358
Function Registers...................................... 93 Receiver ........................................................... 357
PIC18F47J53 Family Devices ............................ 90 Setting Up 9-Bit Mode with Address Detect ..... 357
Special Function Registers ......................................... 92 Transmitter ....................................................... 355
Context Defined SFRs ........................................ 94 Baud Rate Generator
USB RAM.................................................................... 88 Operation in Power-Managed Mode................. 349
DAW.................................................................................. 478 Baud Rate Generator (BRG) .................................... 349
DC Characteristics ............................................................ 527 Associated Registers........................................ 350
Power-Down and Supply Current ............................. 516 Auto-Baud Rate Detect..................................... 353
Supply Voltage.......................................................... 515 Baud Rates, Asynchronous Modes .................. 351
DCFSNZ ........................................................................... 479 Formulas........................................................... 349
DECF ................................................................................ 478 High Baud Rate Select (BRGH Bit) .................. 349
DECFSZ............................................................................ 479 Sampling .......................................................... 349
Development Support ....................................................... 509 Synchronous Master Mode....................................... 361
Device Migration to PIC18F47J53 .................................... 569 Associated Registers, Reception...................... 364
Device Overview ................................................................. 11 Associated Registers, Transmission ................ 362
Details on Individual Family Members ........................ 12 Reception ......................................................... 363
Features (28-Pin Devices) .......................................... 13 Transmission .................................................... 361
Features (44-Pin Devices) .......................................... 13 Synchronous Slave Mode......................................... 365

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Associated Registers, Reception ...................... 366 TTL Input Buffer Option ............................................ 142
Associated Registers, Transmission................. 365 I2C Mode........................................................................... 310
Reception.......................................................... 366 I2C Mode (MSSP)
Transmission..................................................... 365 Acknowledge Sequence Timing ............................... 338
Extended Instruction Set Associated Registers ................................................ 344
ADDFSR ................................................................... 502 Baud Rate Generator ............................................... 331
ADDULNK ................................................................. 502 Bus Collision
CALLW...................................................................... 503 During a Repeated Start Condition................... 342
MOVSF ..................................................................... 503 During a Stop Condition ................................... 343
MOVSS ..................................................................... 504 Clock Arbitration ....................................................... 333
PUSHL ...................................................................... 504 Clock Stretching........................................................ 325
SUBFSR ................................................................... 505 10-Bit Slave Receive Mode (SEN = 1) ............. 325
SUBULNK ................................................................. 505 10-Bit Slave Transmit Mode ............................. 325
External Clock Input ............................................................ 38 7-Bit Slave Receive Mode (SEN = 1) ............... 325
7-Bit Slave Transmit Mode ............................... 325
F Clock Synchronization and CKP bit .......................... 326
Fail-Safe Clock Monitor............................................. 441, 455 Effects of a Reset ..................................................... 339
Interrupts in Power-Managed Modes ........................ 457 General Call Address Support .................................. 329
POR or Wake-up From Sleep ................................... 457 I2C Clock Rate w/BRG.............................................. 332
WDT During Oscillator Failure .................................. 456 Master Mode............................................................. 329
Fast Register Stack............................................................. 85 Operation.......................................................... 331
Firmware Instructions........................................................ 459 Reception ......................................................... 335
Flash Program Memory..................................................... 109 Repeated Start Condition Timing ..................... 334
Associated Registers ................................................ 118 Start Condition Timing ...................................... 333
Control Registers ...................................................... 110 Transmission .................................................... 335
EECON1 and EECON2 .................................... 110 Multi-Master Communication, Bus Collision
TABLAT (Table Latch) Register........................ 112 and Arbitration .................................................. 339
TBLPTR (Table Pointer) Register ..................... 112 Multi-Master Mode .................................................... 339
Erase Sequence ....................................................... 114 Operation .................................................................. 315
Erasing ...................................................................... 114 Read/Write Bit Information (R/W Bit) ................ 315, 318
Operation During Code-Protect ................................ 118 Registers .................................................................. 310
Reading..................................................................... 113 Serial Clock (SCLx Pin) ............................................ 318
Table Pointer Slave Mode............................................................... 315
Boundaries Based on Operation....................... 112 Addressing........................................................ 315
Table Pointer Boundaries ......................................... 112 Addressing Masking Modes
Table Reads and Table Writes ................................. 109 5-Bit .......................................................... 316
Write Sequence ........................................................ 115 7-Bit .......................................................... 317
Writing ....................................................................... 115 Reception ......................................................... 318
Unexpected Termination................................... 118 Transmission .................................................... 318
Write Verify ....................................................... 118 Sleep Operation........................................................ 339
FSCM. See Fail-Safe Clock Monitor. Stop Condition Timing .............................................. 338
INCF ................................................................................. 480
G INCFSZ............................................................................. 481
GOTO................................................................................ 480 In-Circuit Debugger........................................................... 458
In-Circuit Serial Programming (ICSP)....................... 441, 458
H
Indexed Literal Offset Addressing
Hardware Multiplier ........................................................... 119 and Standard PIC18 Instructions.............................. 506
8 x 8 Multiplication Algorithms .................................. 119 Indexed Literal Offset Mode.............................................. 506
Operation .................................................................. 119 Indirect Addressing ........................................................... 104
Performance Comparison (table) .............................. 119 INFSNZ............................................................................. 481
High/Low-Voltage Detect .................................................. 419 Initialization Conditions for All Registers....................... ??–80
Applications............................................................... 423 Instruction Cycle ................................................................. 86
Associated Registers ................................................ 424 Clocking Scheme........................................................ 86
Characteristics .......................................................... 532 Flow/Pipelining............................................................ 86
Current Consumption ................................................ 421 Instruction Set................................................................... 459
Effects of a Reset...................................................... 424 ADDLW..................................................................... 465
Operation .................................................................. 420 ADDWF..................................................................... 465
During Sleep ..................................................... 424 ADDWF (Indexed Literal Offset Mode) ..................... 507
Setup......................................................................... 421 ADDWFC .................................................................. 466
Start-up Time ............................................................ 421 ANDLW..................................................................... 466
Typical Application .................................................... 423 ANDWF..................................................................... 467
I BC............................................................................. 467
BCF .......................................................................... 468
I/O Ports ............................................................................ 141
BN............................................................................. 468
Open-Drain Outputs .................................................. 142
BNC .......................................................................... 469
Pin Capabilities ......................................................... 141

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BNN .......................................................................... 469 TBLWT ..................................................................... 498
BNOV........................................................................ 470 TSTFSZ .................................................................... 499
BNZ........................................................................... 470 XORLW .................................................................... 499
BOV .......................................................................... 473 XORWF .................................................................... 500
BRA........................................................................... 471 INTCON Registers............................................ 123, 123–125
BSF ........................................................................... 471 Inter-Integrated Circuit. See I2C.
BSF (Indexed Literal Offset Mode) ........................... 507 Internal Oscillator
BTFSC ...................................................................... 472 Frequency Drift. See INTOSC Frequency Drift.
BTFSS ...................................................................... 472 Internal Oscillator Block ...................................................... 38
BTG........................................................................... 473 Adjustment.................................................................. 39
BZ ............................................................................. 474 OSCTUNE Register.................................................... 39
CALL ......................................................................... 474 Internal RC Oscillator
CLRF......................................................................... 475 Use with WDT........................................................... 451
CLRWDT................................................................... 475 Internal Voltage Reference Specifications........................ 530
COMF ....................................................................... 476 Internet Address ............................................................... 583
CPFSEQ ................................................................... 476 Interrupt Sources .............................................................. 441
CPFSGT ................................................................... 477 A/D Conversion Complete ........................................ 373
CPFSLT .................................................................... 477 Capture Complete (CCP) ......................................... 263
DAW.......................................................................... 478 Capture Complete (ECCP) ....................................... 273
DCFSNZ ................................................................... 479 Compare Complete (CCP) ....................................... 263
DECF ........................................................................ 478 Compare Complete (ECCP) ..................................... 274
DECFSZ.................................................................... 479 Interrupt-on-Change (RB7:RB4)............................... 148
Extended Instructions ............................................... 501 TMR0 Overflow......................................................... 207
Considerations when Enabling ......................... 506 TMR1 Overflow......................................................... 214
Syntax ............................................................... 501 TMR2 to PR2 Match (PWM)..................................... 266
Use with MPLAB IDE Tools .............................. 508 TMR3 Overflow................................................. 221, 230
General Format......................................................... 461 TMRx to PRx Match ................................................. 234
GOTO ....................................................................... 480 TMRx to PRx Match (PWM) ..................................... 233
INCF.......................................................................... 480 Interrupts .......................................................................... 121
INCFSZ ..................................................................... 481 Control Bits ............................................................... 121
INFSNZ ..................................................................... 481 Control Registers. See INTCON Registers.
IORLW ...................................................................... 482 During, Context Saving............................................. 140
IORWF ...................................................................... 482 INTx Pin.................................................................... 140
LFSR......................................................................... 483 PORTB, Interrupt-on-Change................................... 140
MOVF........................................................................ 483 RCON Register......................................................... 139
MOVFF ..................................................................... 484 TMR0........................................................................ 140
MOVLB ..................................................................... 484 Interrupts, Flag Bits
MOVLW .................................................................... 485 Interrupt-on-Change (RB7:RB4) Flag (RBIF Bit) ...... 148
MOVWF .................................................................... 485 INTOSC Frequency Drift..................................................... 39
MULLW ..................................................................... 486 INTOSC, INTRC. See Internal Oscillator Block.
MULWF..................................................................... 486 IORLW .............................................................................. 482
NEGF ........................................................................ 487 IORWF.............................................................................. 482
NOP .......................................................................... 487 IPR Registers............................................................ 135–138
Opcode Field Descriptions........................................ 460
POP .......................................................................... 488 L
PUSH ........................................................................ 488 LFSR ................................................................................ 483
RCALL ...................................................................... 489 Low-Power Modes .............................................................. 47
RESET ...................................................................... 489 Clock Transitions and Status Indicators ..................... 48
RETFIE ..................................................................... 490 Deep Sleep Mode....................................................... 55
RETLW ..................................................................... 490 and RTCC Peripheral ......................................... 57
RETURN ................................................................... 491 Brown-out Reset (DSBOR)................................. 57
RLCF......................................................................... 491 Fault Detection ................................................... 57
RLNCF ...................................................................... 492 Preparing for....................................................... 55
RRCF ........................................................................ 492 Registers ............................................................ 58
RRNCF ..................................................................... 493 Typical Sequence ............................................... 57
SETF......................................................................... 493 Wake-up Sources ............................................... 56
SETF (Indexed Literal Offset Mode) ......................... 507 Watchdog Timer (DSWDT)................................. 56
SLEEP ...................................................................... 494 Exiting Idle and Sleep Modes ..................................... 54
Standard Instructions ................................................ 459 By Interrupt ......................................................... 54
SUBFWB................................................................... 494 By Reset ............................................................. 54
SUBLW ..................................................................... 495 By WDT Time-out ............................................... 54
SUBWF ..................................................................... 495 Without an Oscillator Start-up Delay .................. 55
SUBWFB................................................................... 496 Idle Modes .................................................................. 52
SWAPF ..................................................................... 496 PRI_IDLE ........................................................... 52
TBLRD ...................................................................... 497 RC_IDLE ............................................................ 54
SEC_IDLE .......................................................... 52

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Multiple Sleep Commands .......................................... 48 Packaging
Run Modes.................................................................. 49 Details....................................................................... 557
PRI_RUN ............................................................ 49 Marking ............................................................. 555, 556
RC_RUN ............................................................. 50 Parallel Master Port (PMP) ............................................... 179
SEC_RUN........................................................... 49 Application Examples ............................................... 201
Sleep Mode ................................................................. 51 Associated Registers ................................................ 203
Summary (table) ......................................................... 48 Data Registers .......................................................... 186
Ultra Low-Power Wake-up .......................................... 61 Master Port Modes ................................................... 193
Module Registers...................................................... 180
M Slave Port Modes ..................................................... 188
Master Clear (MCLR) .......................................................... 67 Peripheral Pin Select (PPS).............................................. 160
Master Synchronous Serial Port (MSSP). See MSSP. Peripheral Pin Select Registers ................................ 165–177
Memory Organization.......................................................... 81 PIE Registers............................................................ 131–134
Data Memory .............................................................. 88 Pin Functions
Program Memory ........................................................ 81 AVDD1......................................................................... 29
Return Address Stack ................................................. 83 AVDD2......................................................................... 29
Memory Programming Requirements ....................... 529, 530 AVSS1 ......................................................................... 29
Microchip Internet Web Site .............................................. 583 MCLR ................................................................... 22, 16
MOVF................................................................................ 483 OSC1/CLKI/RA7 ................................................... 16, 22
MOVFF.............................................................................. 484 OSC2/CLKO/RA6 ................................................. 16, 22
MOVLB.............................................................................. 484 RA0/AN0/C1INA/ULPWU/PMA6/RP0 ........................ 23
MOVLW............................................................................. 485 RA0/AN0/C1INA/ULPWU/RP0 ................................... 17
MOVSF ............................................................................. 503 RA1/AN1/C2INA/VBG.................................................. 23
MOVSS ............................................................................. 504 RA1/AN1/C2INA/VBG/RP1.......................................... 17
MOVWF ............................................................................ 485 RA2/AN2/C2INB/C1IND/C3INB/VREF-/CVREF...... 17, 23
MPLAB ASM30 Assembler, Linker, Librarian ................... 510 RA3/AN3/C1INB/VREF+........................................ 17, 23
MPLAB Integrated Development RA5/AN4/C1INC/SS1/HLVDIN/RCV/RP2 ............ 17, 23
Environment Software............................................... 509 RA6....................................................................... 17, 23
MPLAB PM3 Device Programmer..................................... 512 RA7....................................................................... 17, 23
MPLAB REAL ICE In-Circuit Emulator System................. 511 RB0/AN12/C3IND/INT0/RP3 ................................ 18, 24
MPLINK Object Linker/MPLIB Object Librarian ................ 510 RB1/AN10/C3INC/PMBE/RTCCS/RP4 ...................... 24
MSSP RB1/AN10/C3INC/RTCC/RP4 .................................... 18
ACK Pulse......................................................... 315, 318 RB2/AN8/C2INC/CTED1/PMA3/VMO/REFO/RP5 ..... 24
I2C Mode. See I2C Mode. RB2/AN8/C2INC/CTED1/VMO/REFO/RP5 ................ 18
Module Overview ...................................................... 291 RB3/AN9/C3INA/CTED2/PMA2/VPO/RP6 ................. 24
SPI Master/Slave Connection ................................... 296 RB3/AN9/C3INA/CTED2/VPO/RP6............................ 18
TMR4/6/8 Output for Clock Shift ............................... 234 RB4/CCP4/KBI0/SCK1/SCL1/RP7 ............................. 19
MULLW ............................................................................. 486 RB4/CCP4/PMA1/KBI0/SCK1/SCL1/RP7 .................. 25
MULWF ............................................................................. 486 RB5/CCP5/KBI1/SDI1/SDA1/RP8 .............................. 19
RB5/CCP5/PMA0/KBI1/SDI1/SDA1/RP8 ................... 25
N RB6/CCP6/KBI2/PGC/RP9................................... 19, 25
NEGF ................................................................................ 487 RB7/CCP7/KBI3/PGD/RP10................................. 19, 25
NOP .................................................................................. 487 RC0/T1OSO/T1CKI/RP11 .................................... 20, 26
Notable Differences Between PIC18F47J53 and RC1/CCP8/T1OSI/UOE/RP12.............................. 20, 26
PIC18F46J50 Families.............................................. 569 RC2/AN11/C2IND/CTPLS/RP13 .......................... 20, 26
RC4/D-/VM ........................................................... 20, 26
O
RC5/D+/VP ........................................................... 20, 26
Oscillator Configuration RC6/CCP9/PMA5/TX1/CK1/RP17.............................. 27
Internal Oscillator Block .............................................. 38 RC6/CCP9/TX1/CK1/RP17 ........................................ 20
Oscillator Control ........................................................ 35 RC7/CCP10/PMA4/RX1/DT1/SDO1/RP18................. 27
Oscillator Modes ......................................................... 35 RC7/CCP10/RX1/DT1/SDO1/RP18 ........................... 20
Oscillator Modes and USB Operation ......................... 35 RD0/PMD0/SCL2........................................................ 28
Oscillator Types .......................................................... 35 RD1/PMD1/SDA2 ....................................................... 28
Oscillator Configurations ..................................................... 35 RD2/PMD2/RP19........................................................ 28
Oscillator Selection ........................................................... 441 RD3/PMD3/RP20........................................................ 28
Oscillator Settings for USB.................................................. 40 RD4/PMD4/RP21........................................................ 28
Configuration Options ................................................. 41 RD5/PMD5/RP22........................................................ 28
Oscillator Start-up Timer (OST) .......................................... 46 RD6/PMD6/RP23........................................................ 28
Oscillator Switching............................................................. 42 RD7/PMD7/RP24........................................................ 28
Oscillator Transitions........................................................... 43 RE0/AN5/PMRD ......................................................... 29
Oscillator, Timer1 .............................................. 209, 213, 226 RE1/AN6/PMWR ........................................................ 29
Oscillator, Timer3 .............................................................. 221 RE2/AN7/PMCS ......................................................... 29
P VDD ............................................................................. 21
VDD1 ........................................................................... 29
P1A/P1B/P1C/P1D.See Enhanced
VDD2 ........................................................................... 29
Capture/Compare/PWM (ECCP). ............................. 275

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VDDCORE/VCAP ...................................................... 29, 21 Instructions ................................................................. 87
VSS1...................................................................... 21, 29 Two-Word ........................................................... 87
VSS2...................................................................... 21, 29 Interrupt Vector........................................................... 82
VUSB ...................................................................... 21, 29 Look-up Tables........................................................... 85
Pinout I/O Descriptions Memory Maps............................................................. 81
PIC18F2XJ53 (28-Pin)................................................ 16 Hard Vectors and Configuration Words.............. 82
PIC18F4XJ53 (44-Pin)................................................ 22 Reset Vector............................................................... 82
PIR Registers .............................................................. 126–?? Program Verification and Code Protection ....................... 457
PLL Frequency Multiplier .................................................... 38 Programming, Device Instructions.................................... 459
POP .................................................................................. 488 Pulse Steering .................................................................. 286
POR. See Power-on Reset. Pulse-Width Modulation. See PWM (CCP Module).
PORTA PUSH................................................................................ 488
Additional Pin Functions PUSH and POP Instructions............................................... 84
Ultra Low-Power Wake-up .................................. 61 PUSHL.............................................................................. 504
Associated Registers ................................................ 147 PWM (CCP Module)
LATA Register........................................................... 145 Associated Registers................................................ 268
PORTA Register ....................................................... 145 Duty Cycle ................................................................ 267
TRISA Register ......................................................... 145 Example Frequencies/Resolutions ........................... 267
PORTB Period ....................................................................... 266
Associated Registers ................................................ 151 Setup for PWM Operation ........................................ 267
LATB Register........................................................... 148 TMR2 to PR2 Match ................................................. 266
PORTB Register ....................................................... 148 TMRx to PRx Match ................................................. 233
RB7:RB4 Interrupt-on-Change Flag (RBIF Bit)......... 148 PWM (ECCP Module)
TRISB Register ......................................................... 148 Effects of a Reset ..................................................... 289
PORTC Operation in Power-Managed Modes ....................... 289
Associated Registers ................................................ 154 Operation with Fail-Safe Clock Monitor .................... 289
LATC Register .......................................................... 152 Pulse Steering .......................................................... 286
PORTC Register ....................................................... 152 Steering Synchronization.......................................... 288
TRISC Register......................................................... 152 PWM Mode. See Enhanced Capture/Compare/PWM ...... 275
PORTD
Associated Registers ................................................ 157 Q
LATD Register .......................................................... 155 Q Clock ............................................................................. 267
PORTD Register ....................................................... 155
TRISD Register......................................................... 155
R
PORTE RAM. See Data Memory.
Associated Registers ................................................ 159 RBIF Bit ............................................................................ 148
LATE Register........................................................... 158 RC_IDLE Mode................................................................... 54
PORTE Register ....................................................... 158 RC_RUN Mode................................................................... 50
TRISE Register ......................................................... 158 RCALL .............................................................................. 489
Power-Managed Modes RCON Register
and EUSART Operation............................................ 349 Bit Status During Initialization..................................... 70
and PWM Operation ................................................. 289 Reader Response............................................................. 584
and SPI Operation .................................................... 300 Real-Time Clock and Calendar (RTCC) ........................... 237
Clock Sources............................................................. 47 Operation.................................................................. 249
Entering....................................................................... 47 Registers .................................................................. 238
Selecting ..................................................................... 47 Reference Clock Output ..................................................... 45
Power-on Reset (POR) ....................................................... 67 Register File........................................................................ 91
Power-up Delays................................................................. 46 Registers
Power-up Timer (PWRT) .............................................. 46, 68 ADCON0 (A/D Control 0).......................................... 368
Time-out Sequence..................................................... 68 ADCON1 (A/D Control 1).......................................... 369
Prescaler, Capture ............................................................ 263 ADCTRIG (A/D Trigger)............................................ 376
Prescaler, Timer0.............................................................. 207 ALRMCFG (Alarm Configuration)............................. 241
Prescaler, Timer2.............................................................. 267 ALRMDAY (Alarm Day Value).................................. 246
PRI_IDLE Mode .................................................................. 52 ALRMHR (Alarm Hours Value)................................. 247
PRI_RUN Mode .................................................................. 49 ALRMMIN (Alarm Minutes Value) ............................ 248
Product Identification System ........................................... 585 ALRMMNTH (Alarm Month Value) ........................... 246
Program Counter ................................................................ 83 ALRMRPT (Alarm Repeat Counter) ......................... 242
PCL, PCH and PCU Registers.................................... 83 ALRMSEC (Alarm Seconds Value) .......................... 248
PCLATH and PCLATU Registers ............................... 83 ALRMWD (Alarm Weekday Value)........................... 247
Program Memory ANCON0 (A/D Port Configuration 0) ........................ 371
ALU ANCON1 (A/D Port Configuration 1) ........................ 371
STATUS............................................................ 102 Associated with Comparator..................................... 407
Extended Instruction Set........................................... 105 Associated with Program Flash Memory .................. 118
Flash Configuration Words ......................................... 82 BAUDCONx (Baud Rate Control)............................. 348
Hard Memory Vectors ................................................. 82 BDnSTAT ................................................................. 389

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BDnSTAT (Buffer Descriptor n Status, PIE3 (Peripheral Interrupt Enable 3)......................... 133
CPU Mode) ....................................................... 390 PIE4 (Peripheral Interrupt Enable 4)......................... 134
BDnSTAT (Buffer Descriptor n Status, PIE5 (Peripheral Interrupt Enable 5)......................... 134
SIE Mode) ......................................................... 391 PIR1 (Peripheral Interrupt Request (Flag) 1)............ 126
BDnSTAT (SIE Mode)............................................... 391 PIR2 (Peripheral Interrupt Request (Flag) 2)............ 127
Buffer Descriptors, Summary .................................... 393 PIR3 (Peripheral Interrupt Request (Flag) 3)............ 128
CCPTMRS0 (ECCP1/2/3 Select 0) ........................... 271 PMADDRH (Parallel Port Address High Byte).......... 187
CCPxCON (CCPx CCP4-10 Control)........................ 257 PMADDRL (Parallel Port Address Low Byte) ........... 187
CCPxCON (ECCP1/2/3 Control)............................... 270 PMCONH (Parallel Port Control High Byte).............. 180
CMSTAT (Comparator Status).................................. 409 PMCONL (Parallel Port Control Low Byte) ............... 181
CMxCON (Comparator Control 1/2/3)....................... 408 PMEH (Parallel Port Enable High Byte).................... 184
CONFIG1H (Configuration 1 High) ........................... 444 PMEL (Parallel Port Enable Low Byte) ..................... 184
CONFIG1L (Configuration 1 Low)............................. 443 PMMODEH (Parallel Port Mode High Byte) ............. 182
CONFIG2H (Configuration 2 High) ........................... 446 PMMODEL (Parallel Port Mode Low Byte)............... 183
CONFIG2L (Configuration 2 Low)............................. 445 PMSTATH (Parallel Port Status High Byte).............. 185
CONFIG3H (Configuration 3 High) ................... 370, 448 PMSTATL (Parallel Port Status Low Byte) ............... 185
CONFIG3L (Configuration 3 Low)............................. 447 PPSCON (Peripheral Pin Select Input 0).................. 165
CONFIG4H (Configuration 4 High) ........................... 449 PSTRxCON (Pulse Steering Control) ....................... 287
CONFIG4L (Configuration 4 Low)............................. 448 RCON (Reset Control)........................................ 66, 139
CTMUCONH (CTMU Control High) .......................... 437 RCSTAx (Receive Status and Control)..................... 347
CTMUCONL (CTMU Control Low)............................ 438 REF0CON (Reference Oscillator Control) .................. 45
CTMUICON (CTMU Current Control) ....................... 439 Reserved .................................................................. 243
CVRCON (Comparator Voltage RPINR1 (Peripheral Pin Select Input 1).................... 165
Reference Control).................................................... 416 RPINR12 (Peripheral Pin Select Input 12)................ 168
DAY (Day Value)....................................................... 244 RPINR13 (Peripheral Pin Select Input 13)................ 168
DEVID1 (Device ID 1) ............................................... 449 RPINR14 (Peripheral Pin Select Input 14)................ 168
DEVID2 (Device ID 2) ............................................... 450 RPINR16 (Peripheral Pin Select Input 16)................ 169
DMACON1 (DMA Control 1) ..................................... 304 RPINR17 (Peripheral Pin Select Input 17)................ 169
DMACON2 (DMA Control 2) ..................................... 305 RPINR2 (Peripheral Pin Select Input 2).................... 165
DSCONH (Deep Sleep Control High Byte) ................. 58 RPINR21 (Peripheral Pin Select Input 21)................ 169
DSCONL (Deep Sleep Control Low Byte) .................. 58 RPINR22 (Peripheral Pin Select Input 22)................ 170
DSGPR0 (Deep Sleep Persistent RPINR23 (Peripheral Pin Select Input 23)................ 170
General Purpose 0)............................................. 59 RPINR24 (Peripheral Pin Select Input 24)................ 170
DSGPR1 (Deep Sleep Persistent RPINR3 (Peripheral Pin Select Input 3).................... 166
General Purpose 1)............................................. 59 RPINR4 (Peripheral Pin Select Input 4).................... 166
DSWAKEH (Deep Sleep Wake High Byte) ................. 59 RPINR6 (Peripheral Pin Select Input 6)............ 166, 169
DSWAKEL (Deep Sleep Wake Low Byte) .................. 60 RPINR7 (Peripheral Pin Select Input 7).................... 167
ECCPxAS (ECCP1/2/3 Auto-Shutdown Control) ...... 283 RPINR8 (Peripheral Pin Select Input 8).................... 167
ECCPxDEL (ECCP1/2/3 Enhanced RPINR9 (Peripheral Pin Select Input 9).................... 167
PWM Control) ................................................... 286 RPOR0 (Peripheral Pin Select Output 0).................. 171
EECON1 (EEPROM Control 1)................................. 111 RPOR1 (Peripheral Pin Select Output 1).................. 171
HLVDCON (High/Low-Voltage Detect Control)......... 419 RPOR10 (Peripheral Pin Select Output 10).............. 174
HOURS (Hours Value) .............................................. 245 RPOR11 (Peripheral Pin Select Output 11).............. 174
I2C Mode (MSSP) ..................................................... 310 RPOR12 (Peripheral Pin Select Output 12).............. 175
INTCON (Interrupt Control) ....................................... 123 RPOR13 (Peripheral Pin Select Output 13).............. 175
INTCON2 (Interrupt Control 2) .................................. 124 RPOR17 (Peripheral Pin Select Output 17).............. 175
INTCON3 (Interrupt Control 3) .................................. 125 RPOR18 (Peripheral Pin Select Output 18).............. 176
IPR1 (Peripheral Interrupt Priority 1)......................... 135 RPOR19 (Peripheral Pin Select Output 19).............. 176
IPR2 (Peripheral Interrupt Priority 2)......................... 136 RPOR2 (Peripheral Pin Select Output 2).................. 171
IPR3 (Peripheral Interrupt Priority 3)......................... 137 RPOR20 (Peripheral Pin Select Output 20).............. 176
IPR4 (Peripheral Interrupt Priority 4)......................... 138 RPOR21 (Peripheral Pin Select Output 21).............. 177
IPR5 (Peripheral Interrupt Priority 5)......................... 138 RPOR22 (Peripheral Pin Select Output 22).............. 177
MINUTES (Minutes Value)........................................ 245 RPOR23 (Peripheral Pin Select Output 23).............. 177
MONTH (Month Value) ............................................. 243 RPOR24 (Peripheral Pin Select Output 24).............. 178
ODCON1 (Peripheral Open-Drain Control 1)............ 143 RPOR3 (Peripheral Pin Select Output 3).................. 172
ODCON2 (Peripheral Open-Drain Control 2)............ 144 RPOR4 (Peripheral Pin Select Output 4).................. 172
ODCON3 (Peripheral Open-Drain Control 3)............ 144 RPOR5 (Peripheral Pin Select Output 5).................. 172
OSCCON (Oscillator Control) ..................................... 43 RPOR6 (Peripheral Pin Select Output 6).................. 173
OSCCON2 (Oscillator Control 2) ........................ 44, 224 RPOR7 (Peripheral Pin Select Output 7).................. 173
OSCTUNE (Oscillator Tuning) .................................... 40 RPOR8 (Peripheral Pin Select Output 8).................. 173
PADCFG1 (Pad Configuration Control 1) ................. 145 RPOR9 (Peripheral Pin Select Output 9).................. 174
PADCFG1 (Pad Configuration) ................................. 240 RTCCAL (RTCC Calibration).................................... 240
Parallel Master Port .................................................. 180 RTCCFG (RTCC Configuration) ............................... 239
PIE1 (Peripheral Interrupt Enable 1) ......................... 131 SECONDS (Seconds Value) .................................... 245
PIE2 (Peripheral Interrupt Enable 2) ......................... 132 SPI Mode (MSSP) .................................................... 293

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SSPxCON1 (MSSPx Control 1, I2C Mode)............... 312 RRNCF ............................................................................. 493
SSPxCON1 (MSSPx Control 1, SPI Mode) .............. 294 RTCC
SSPxCON2 (MSSPx Control 2, I2C Alarm ........................................................................ 253
Master Mode).................................................... 313 Configuring ....................................................... 253
SSPxCON2 (MSSPx Control 2, I2C Interrupt ............................................................ 254
Slave Mode)...................................................... 314 Mask Settings ................................................... 253
SSPxMSK (I2C Slave Address Mask)....................... 314 Alarm Value Register Mappings (ALRMVAL) ........... 246
SSPxSTAT (MSSPx Status, I2C Mode) .................... 311 Control Registers...................................................... 239
SSPxSTAT (MSSPx Status, SPI Mode) ................... 293 Control/Value Register Maps.................................... 255
STATUS.................................................................... 102 Low-Power Modes.................................................... 254
STKPTR (Stack Pointer) ............................................. 84 Operation
T0CON (Timer0 Control)........................................... 205 Calibration ........................................................ 252
T1CON (Timer1 Control)........................................... 209 Clock Source .................................................... 250
T1GCON (Timer1 Gate Control) ............................... 210 Digit Carry Rules .............................................. 250
T2CON (Timer2 Control)........................................... 219 General Functionality........................................ 251
TxCON (Timer3/5 Control)........................................ 222 Leap Year ......................................................... 251
TxCON (Timer4/6/8 Control)..................................... 234 Register Mapping ............................................. 251
TxGCON (Timer3/5 Gate Control) ............................ 223 ALRMVAL................................................. 252
TXSTAx (Transmit Status and Control) .................... 346 RTCVAL ................................................... 252
UADDR ..................................................................... 387 Safety Window for Register Reads
UCFG (USB Configuration)....................................... 383 and Writes ................................................ 251
UCON (USB Control) ................................................ 381 Write Lock......................................................... 251
UEIE (USB Error Interrupt Enable) ........................... 399 Peripheral Module Disable (PMD) Register.............. 255
UEIR (USB Error Interrupt Status) ............................ 398 Register Interface ..................................................... 249
UEPn (USB Endpoint n Control) ............................... 386 Reset ........................................................................ 254
UFRMH:UFRML........................................................ 387 Device .............................................................. 254
UIE (USB Interrupt Enable)....................................... 397 Power-on Reset (POR)..................................... 254
UIR (USB Interrupt Status) ....................................... 395 Value Register Mappings (RTCVAL)........................ 243
USTAT (USB Status) ................................................ 385 RTCEN Bit Write............................................................... 249
WDTCON (Watchdog Timer Control) ....................... 452
WKDY (Weekday Value)........................................... 244 S
YEAR (Year Value) ................................................... 243 SCKx ................................................................................ 292
RESET .............................................................................. 489 SDIx .................................................................................. 292
Reset................................................................................... 65 SDOx ................................................................................ 292
Brown-out Reset ......................................................... 67 SEC_IDLE Mode ................................................................ 52
Brown-out Reset (BOR) .............................................. 65 SEC_RUN Mode................................................................. 49
Configuration Mismatch (CM) ..................................... 65 Serial Clock, SCKx ........................................................... 292
Configuration Mismatch Reset.................................... 68 Serial Data In (SDIx)......................................................... 292
Deep Sleep ................................................................. 65 Serial Data Out (SDOx) .................................................... 292
Fast Register Stack..................................................... 85 Serial Peripheral Interface. See SPI Mode.
MCLR.......................................................................... 67 SETF ................................................................................ 493
MCLR Reset, During Power-Managed Modes............ 65 Shoot-Through Current..................................................... 285
MCLR Reset, Normal Operation ................................. 65 Slave Select (SSx)............................................................ 292
Power-on Reset .......................................................... 67 SLEEP .............................................................................. 494
Power-on Reset (POR) ............................................... 65 Software Simulator (MPLAB SIM) .................................... 511
Power-up Timer .......................................................... 68 Special Event Trigger. See Compare (CCP Module).
RESET Instruction ...................................................... 65 Special Event Trigger. See Compare (ECCP Mode).
Stack Full Reset.......................................................... 65 Special Features of the CPU ............................................ 441
Stack Underflow Reset ............................................... 65 SPI Mode (MSSP) ............................................................ 292
State of Registers ....................................................... 70 Associated Registers................................................ 301
Watchdog Timer (WDT) Reset.................................... 65 Bus Mode Compatibility ............................................ 300
Resets ............................................................................... 441 Clock Speed, Interactions......................................... 300
Brown-out Reset (BOR) ............................................ 441 DMA Module............................................................. 302
Oscillator Start-up Timer (OST) ................................ 441 I/O Pin Considerations...................................... 302
Power-on Reset (POR) ............................................. 441 Idle, Sleep Considerations................................ 302
Power-up Timer (PWRT) .......................................... 441 RAM to RAM Copy ........................................... 302
RETFIE ............................................................................. 490 Registers .......................................................... 302
RETLW ............................................................................. 490 Effects of a Reset ..................................................... 300
RETURN ........................................................................... 491 Enabling SPI I/O ....................................................... 296
Return Address Stack ......................................................... 83 Master Mode............................................................. 297
Associated Registers .................................................. 83 Master/Slave Connection ......................................... 296
Revision History ................................................................ 569 Operation.................................................................. 295
RLCF................................................................................. 491 Open-Drain Output Option................................ 295
RLNCF .............................................................................. 492 Operation in Power-Managed Modes ....................... 300
RRCF ................................................................................ 492 Registers .................................................................. 293
Serial Clock .............................................................. 292

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PIC18F47J53 FAMILY
Serial Data In ............................................................ 292 Overflow Interrupt ............................................. 221, 230
Serial Data Out ......................................................... 292 Special Event Trigger (ECCP) .................................. 230
Slave Mode ............................................................... 298 TMR3H Register ....................................................... 221
Slave Select .............................................................. 292 TMR3L Register........................................................ 221
Slave Select Synchronization ................................... 298 Timer4
SPI Clock .................................................................. 297 PR4/6/8 Register ...................................................... 233
SSPxBUF Register ................................................... 297 TMR4/6/8 Register.................................................... 233
SSPxSR Register...................................................... 297 TMRx to PRx Match Interrupt ................................... 234
Typical Connection ................................................... 296 Timer4/6/8......................................................................... 233
SSPOV.............................................................................. 335 Associated Registers ................................................ 235
SSPOV Status Flag........................................................... 335 Interrupt .................................................................... 234
SSPxSTAT Register MSSP Clock Shift ..................................................... 234
R/W Bit .............................................................. 315, 318 Operation .................................................................. 233
.......................................................................................... 292 Output ....................................................................... 234
Stack Full/Underflow Resets ............................................... 85 Postscaler. See Postscaler, Timer4/6/8.
SUBFSR............................................................................ 505 Prescaler. See Prescaler, Timer4/6/8.
SUBFWB........................................................................... 494 TMR4 to PR4 Match Interrupt................................... 233
SUBLW ............................................................................. 495 Timing Diagrams
SUBULNK ......................................................................... 505 A/D Conversion......................................................... 551
SUBWF ............................................................................. 495 Asynchronous Reception.......................................... 358
SUBWFB........................................................................... 496 Asynchronous Transmission..................................... 356
SWAPF ............................................................................. 496 Asynchronous Transmission (Back-to-Back)............ 356
Automatic Baud Rate Calculation ............................. 354
T Auto-Wake-up Bit (WUE) During
Table Pointer Operations (table) ....................................... 112 Normal Operation ............................................. 359
Table Reads/Table Writes........................................... 85, 375 Auto-Wake-up Bit (WUE) During Sleep .................... 359
TBLRD .............................................................................. 497 Baud Rate Generator with Clock Arbitration............. 333
TBLWT .............................................................................. 498 BRG Overflow Sequence.......................................... 354
Timer0 ............................................................................... 205 BRG Reset Due to SDAx Arbitration
Associated Registers ................................................ 207 During Start Condition ...................................... 341
Operation .................................................................. 206 Bus Collision During a Repeated
Overflow Interrupt ..................................................... 207 Start Condition (Case 1) ................................... 342
Prescaler ................................................................... 207 Bus Collision During a Repeated Start
Switching Assignment....................................... 207 Condition (Case 2).................................................... 342
Prescaler Assignment (PSA Bit) ............................... 207 Bus Collision During a Start Condition
Prescaler Select (T0PS2:T0PS0 Bits) ...................... 207 (SCLx = 0) ........................................................ 341
Reads and Writes in 16-Bit Mode ............................. 206 Bus Collision During a Stop Condition (Case 1) ....... 343
Source Edge Select (T0SE Bit)................................. 206 Bus Collision During a Stop Condition (Case 2) ....... 343
Source Select (T0CS Bit) .......................................... 206 Bus Collision During Start Condition
Timer1 ............................................................................... 209 (SDAx Only)...................................................... 340
16-Bit Read/Write Mode............................................ 213 Bus Collision for Transmit and Acknowledge ........... 339
Associated Registers ................................................ 218 CLKO and I/O ........................................................... 536
Clock Source Selection ............................................. 211 Clock Synchronization .............................................. 326
Gate .......................................................................... 215 Clock/Instruction Cycle ............................................... 86
Interrupt..................................................................... 214 Enhanced Capture/Compare/PWM .......................... 539
Operation .................................................................. 211 EUSARTx Synchronous Receive
Oscillator ........................................................... 209, 213 (Master/Slave) .................................................. 550
Layout Considerations ...................................... 214 EUSARTx Synchronous Transmission
Resetting, Using the ECCP Special (Master/Slave) .................................................. 550
Event Trigger .................................................... 215 Example SPI Master Mode (CKE = 0) ...................... 542
TMR1H Register ....................................................... 209 Example SPI Master Mode (CKE = 1) ...................... 543
TMR1L Register ........................................................ 209 Example SPI Slave Mode (CKE = 0) ........................ 544
Use as a Clock Source ............................................. 214 Example SPI Slave Mode (CKE = 1) ........................ 545
Timer2 ............................................................................... 219 External Clock........................................................... 534
Associated Registers ................................................ 220 Fail-Safe Clock Monitor ............................................ 456
Interrupt..................................................................... 220 First Start Bit ............................................................. 333
Operation .................................................................. 219 Full-Bridge PWM Output........................................... 280
Output ....................................................................... 220 Half-Bridge PWM Output .................................. 278, 285
PR2 Register............................................................. 266 High/Low-Voltage Detect Characteristics ................. 532
TMR2 to PR2 Match Interrupt ................................... 266 High-Voltage Detect (VDIRMAG = 1) ....................... 423
Timer3 ............................................................................... 221 I22C Bus Data........................................................... 546
16-Bit Read/Write Mode............................................ 226 I2C Acknowledge Sequence ..................................... 338
Associated Registers ................................................ 231 I2C Bus Start/Stop Bits ............................................. 546
Gate .......................................................................... 226 I2C Master Mode (7 or 10-Bit Transmission) ............ 336
Operation .................................................................. 225 I2C Master Mode (7-Bit Reception)........................... 337
Oscillator ........................................................... 221, 226

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I2C Slave Mode (10-Bit Reception, SEN = 0, Time-out Sequence on Power-up (MCLR
ADMSK = 01001) ...................................................... 322 Tied to VDD, VDD Rise < TPWRT) ........................ 68
I2C Slave Mode (10-Bit Reception, SEN = 0) ........... 323 Timer Pulse Generation............................................ 254
I2C Slave Mode (10-Bit Reception, SEN = 1) ........... 328 Timer0 and Timer1 External Clock ........................... 538
I2C Slave Mode (10-Bit Transmission)...................... 324 Timer1 Gate Count Enable Mode............................. 215
I2C Slave Mode (7-Bit Reception, SEN = 0, Timer1 Gate Single Pulse Mode............................... 217
ADMSK = 01011).............................................. 320 Timer1 Gate Single Pulse/Toggle
I2C Slave Mode (7-Bit Reception, SEN = 0) ............. 319 Combined Mode ............................................... 218
I2C Slave Mode (7-Bit Reception, SEN = 1) ............. 327 Timer1 Gate Toggle Mode........................................ 216
I2C Slave Mode (7-Bit Transmission)........................ 321 Timer3 Gate Count Enable Mode............................. 226
I2C Slave Mode General Call Address Timer3 Gate Single Pulse Mode............................... 228
Sequence (7 or 10-Bit Addressing Mode)......... 329 Timer3 Gate Single Pulse/Toggle
I2C Stop Condition Receive or Transmit Mode ......... 338 Combined Mode ....................................................... 229
Low-Voltage Detect (VDIRMAG = 0) ........................ 422 Timer3 Gate Toggle Mode........................................ 227
MSSPx I2C Bus Data ................................................ 548 Transition for Entry to Idle Mode ................................ 53
MSSPx I2C Bus Start/Stop Bits................................. 548 Transition for Entry to SEC_RUN Mode ..................... 49
Parallel Master Port Read......................................... 540 Transition for Entry to Sleep Mode ............................. 51
Parallel Master Port Write ......................................... 541 Transition for Two-Speed Start-up
Parallel Slave Port Read................................... 189, 191 (INTRC to HSPLL)............................................ 455
Parallel Slave Port Write ................................... 189, 192 Transition for Wake From Idle to Run Mode............... 53
PWM Auto-Shutdown with Auto-Restart Enabled..... 284 Transition for Wake From Sleep (HSPLL) .................. 51
PWM Auto-Shutdown with Firmware Restart............ 284 Transition From RC_RUN Mode to
PWM Direction Change ............................................ 281 PRI_RUN Mode.................................................. 50
PWM Direction Change at Near 100% Transition From SEC_RUN Mode to
Duty Cycle................................................................. 282 PRI_RUN Mode (HSPLL) ........................................... 49
PWM Output ............................................................. 266 Transition to RC_RUN Mode...................................... 50
PWM Output (Active-High)........................................ 276 USB Signal ............................................................... 553
PWM Output (Active-Low) ........................................ 277 Write, 16-Bit Data, Demultiplexed Address .............. 199
Read and Write, 8-Bit Data, Demultiplexed Write, 16-Bit Multiplexed Data, Fully
Address............................................................. 196 Multiplexed 16-Bit Address............................... 200
Read, 16-Bit Data, Demultiplexed Address .............. 199 Write, 16-Bit Multiplexed Data, Partially
Read, 16-Bit Multiplexed Data, Fully Multiplexed Multiplexed Address ......................................... 200
16-Bit Address .................................................. 200 Write, 8-Bit Data, Fully Multiplexed
Read, 16-Bit Multiplexed Data, Partially 16-Bit Address .................................................. 198
Multiplexed Address ......................................... 199 Write, 8-Bit Data, Partially Multiplexed Address ....... 197
Read, 8-Bit Data, Fully Multiplexed Write, 8-Bit Data, Partially Multiplexed Address,
16-Bit Address .................................................. 198 Enable Strobe................................................... 198
Read, 8-Bit Data, Partially Multiplexed Address ....... 196 Write, 8-Bit Data, Wait States Enabled,
Read, 8-Bit Data, Partially Multiplexed Address, Partially Multiplexed Address ........................... 197
Enable Strobe ................................................... 197 Timing Diagrams and Specifications
Read, 8-Bit Data, Wait States Enabled, Partially AC Characteristics
Multiplexed Address.................................................. 196 Internal RC Accuracy........................................ 535
Repeated Start Condition.......................................... 334 CLKO and I/O Requirements.................................... 536
Reset, Watchdog Timer (WDT), Oscillator Enhanced Capture/Compare/PWM
Start-up Timer (OST) and Power-up Requirements ................................................... 540
Timer (PWRT)................................................... 537 EUSARTx Synchronous Receive Requirements...... 550
Send Break Character Sequence ............................. 360 EUSARTx Synchronous Transmission
Slave Synchronization .............................................. 298 Requirements ........................................................... 550
Slow Rise Time (MCLR Tied to VDD, VDD Example SPI Mode Requirements (Master Mode,
Rise > TPWRT)............................................................. 69 CKE = 0)........................................................... 542
SPI Mode (Master Mode).......................................... 297 Example SPI Mode Requirements (Master Mode,
SPI Mode (Slave Mode, CKE = 0) ............................ 299 CKE = 1)........................................................... 543
SPI Mode (Slave Mode, CKE = 1) ............................ 299 Example SPI Mode Requirements (Slave Mode,
Steering Event at Beginning of Instruction CKE = 0)........................................................... 544
(STRSYNC = 1) ................................................ 288 Example SPI Slave Mode Requirements
Steering Event at End of Instruction (CKE = 1).................................................................. 545
(STRSYNC = 0) ........................................................ 288 External Clock Requirements ................................... 535
Synchronous Reception (Master Mode, SREN) ....... 363 I2C Bus Data Requirements (Slave Mode) ............... 547
Synchronous Transmission....................................... 361 I2C Bus Start/Stop Bits Requirements
Synchronous Transmission (Through TXEN) ........... 362 (Slave Mode) .................................................... 546
Time-out Sequence on Power-up (MCLR MSSPx I2C Bus Data Requirements ........................ 549
Not Tied to VDD), Case 1 .................................... 69 MSSPx I2C Bus Start/Stop Bits Requirements......... 548
Time-out Sequence on Power-up (MCLR Parallel Master Port Read Requirements ................. 541
Not Tied to VDD), Case 2 ............................................ 69 Parallel Master Port Write Requirements ................. 541
PLL Clock ................................................................. 535

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Reset, Watchdog Timer, Oscillator Start-up Timer, V
Power-up Timer and Brown-out Reset
Voltage Reference Specifications..................................... 529
Requirements............................................ 537, 538
Voltage Regulator (On-Chip) ............................................ 453
Timer0 and Timer1 External Clock
Operation in Sleep Mode .......................................... 454
Requirements............................................................ 539
USB Full-Speed Requirements ................................. 553 W
USB Low-Speed Requirements ................................ 553 Watchdog Timer (WDT)............................................ 441, 451
TSTFSZ............................................................................. 499 Associated Registers ................................................ 452
Two-Speed Start-up .................................................. 441, 455 Control Register........................................................ 451
Two-Word Instructions During Oscillator Failure ........................................... 456
Example Cases ........................................................... 87 Programming Considerations ................................... 451
TXSTAx Register WCOL ....................................................... 333, 334, 335, 338
BRGH Bit .................................................................. 349 WCOL Status Flag.................................... 333, 334, 335, 338
U WWW Address ................................................................. 583
WWW, On-Line Support ....................................................... 9
Ultra Low-Power Wake-up .................................................. 61
Universal Serial Bus.......................................................... 379 X
Address Register (UADDR) ...................................... 387 XORLW............................................................................. 499
Associated Registers ................................................ 403 XORWF ............................................................................ 500
Buffer Descriptor Table ............................................. 388
Buffer Descriptors ..................................................... 388
Address Validation ............................................ 391
Assignment in Different Buffering Modes.......... 393
BDnSTAT Register (CPU Mode) ...................... 389
BDnSTAT Register (SIE Mode) ........................ 391
Byte Count ........................................................ 391
Memory Map ..................................................... 392
Ownership......................................................... 388
Ping-Pong Buffering.......................................... 392
Register Summary ............................................ 393
Status and Configuration .................................. 388
Endpoint Control ....................................................... 386
External Pull-up Resistors......................................... 384
Eye Pattern Test Enable ........................................... 384
Firmware and Drivers................................................ 403
Frame Number Registers.......................................... 387
Internal Pull-up Resistors .......................................... 384
Internal Transceiver .................................................. 382
Interrupts ................................................................... 394
and USB Transactions ...................................... 394
Oscillator Requirements............................................ 403
Overview ........................................................... 379, 404
Class Specifications and Drivers ...................... 405
Descriptors........................................................ 405
Enumeration...................................................... 405
Frames.............................................................. 404
Layered Framework .......................................... 404
Power................................................................ 404
Speed................................................................ 405
Transfer Types.................................................. 404
Ping-Pong Buffer Configuration ................................ 384
Power Modes ............................................................ 400
Bus Power Only ................................................ 400
Dual Power with Self-Power Dominance .......... 400
Self-Power Only ................................................ 400
Transceiver Current Consumption .................... 401
RAM .......................................................................... 387
Memory Map ..................................................... 387
Status and Control .................................................... 380
UFRMH:UFRML Registers ....................................... 387
USB Specifications............................................................ 531
USB. See Universal Serial Bus.

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 PIC18F47J53 FAMILY
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 2010 Microchip Technology Inc. Preliminary DS39964B-page 583

PIC18F47J53 FAMILY
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Device: PIC18F47J53 family Literature Number: DS39964B

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DS39964B-page 584 Preliminary  2010 Microchip Technology Inc.

 PIC18F47J53 FAMILY
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO. X /XX XXX
Examples:
Device Temperature Package Pattern a) PIC18F47J53-I/PT 301 = Industrial temp.,
Range TQFP package, QTP pattern #301.
b) PIC18F47J53T-I/PT = Tape and reel, Industrial
temp., TQFP package.

Device PIC18F26J53, PIC18F27J53, PIC18F46J53 and

PIC18F47J53
VDD range 2.15V to 3.6V
PIC18LF26J53, PIC18LF27J53, PIC18LF46J53 and
PIC18LF47J53 Note 1: F = Standard Voltage Range, with
VDD range 2.0V to 3.6V internal 2.5V core voltage regulator
LF = Wide Voltage Range, with no
internal core voltage regulator
Temperature Range I = -40C to +85C (Industrial) 2: T = in tape and reel TQFP
E = -40C to +125C (Extended) packages only.

Package ML = QFN
PT = TQFP (Thin Quad Flatpack)
SO = SOIC
SP = Skinny Plastic DIP
SS = SSOP

Pattern QTP, SQTP, Code or Special Requirements

(blank otherwise)

 2010 Microchip Technology Inc. Preliminary DS39964B-page 585

 WORLDWIDE SALES AND SERVICE
AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE
Corporate Office Asia Pacific Office India - Bangalore Austria - Wels
2355 West Chandler Blvd. Suites 3707-14, 37th Floor Tel: 91-80-3090-4444 Tel: 43-7242-2244-39
Chandler, AZ 85224-6199 Tower 6, The Gateway Fax: 91-80-3090-4123 Fax: 43-7242-2244-393
Tel: 480-792-7200 Harbour City, Kowloon Denmark - Copenhagen
India - New Delhi
Fax: 480-792-7277 Hong Kong Tel: 45-4450-2828
Tel: 91-11-4160-8631
Technical Support: Tel: 852-2401-1200 Fax: 45-4485-2829
Fax: 91-11-4160-8632
http://support.microchip.com Fax: 852-2401-3431
India - Pune France - Paris
Web Address:
Australia - Sydney Tel: 91-20-2566-1512 Tel: 33-1-69-53-63-20
www.microchip.com
Tel: 61-2-9868-6733 Fax: 91-20-2566-1513 Fax: 33-1-69-30-90-79
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Tel: 678-957-9614 Tel: 81-45-471- 6166
Tel: 86-10-8528-2100 Fax: 49-89-627-144-44
Fax: 678-957-1455 Fax: 81-45-471-6122
Fax: 86-10-8528-2104 Italy - Milan
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China - Chengdu Tel: 39-0331-742611
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Tel: 86-28-8665-5511 Fax: 39-0331-466781
Tel: 774-760-0087 Fax: 82-53-744-4302
Fax: 86-28-8665-7889 Netherlands - Drunen
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Cleveland
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Tel: 216-447-0464 China - Nanjing Tel: 44-118-921-5869
Malaysia - Penang
Fax: 216-447-0643 Tel: 86-25-8473-2460 Fax: 44-118-921-5820
Tel: 60-4-227-8870
Dallas Fax: 86-25-8473-2470 Fax: 60-4-227-4068
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Tel: 972-818-7423 Tel: 86-532-8502-7355 Tel: 63-2-634-9065
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Tel: 248-538-2250 Fax: 86-21-5407-5066 Fax: 65-6334-8850
Fax: 248-538-2260
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Kokomo Tel: 86-24-2334-2829 Tel: 886-3-6578-300
Kokomo, IN Fax: 86-24-2334-2393 Fax: 886-3-6578-370
Tel: 765-864-8360
Fax: 765-864-8387 China - Shenzhen Taiwan - Kaohsiung
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Los Angeles Fax: 86-755-8203-1760 Fax: 886-7-536-4803
Mission Viejo, CA
Tel: 949-462-9523 China - Wuhan Taiwan - Taipei
Fax: 949-462-9608 Tel: 86-27-5980-5300 Tel: 886-2-2500-6610
Fax: 86-27-5980-5118 Fax: 886-2-2508-0102
Santa Clara
Santa Clara, CA China - Xian Thailand - Bangkok
Tel: 408-961-6444 Tel: 86-29-8833-7252 Tel: 66-2-694-1351
Fax: 408-961-6445 Fax: 86-29-8833-7256 Fax: 66-2-694-1350

Toronto China - Xiamen

Mississauga, Ontario, Tel: 86-592-2388138
Canada Fax: 86-592-2388130
Tel: 905-673-0699 China - Zhuhai
Fax: 905-673-6509 Tel: 86-756-3210040
Fax: 86-756-3210049

01/05/10

DS39964B-page 586 Preliminary  2010 Microchip Technology Inc.