Solution Manual

for
Modern Digital Electronics
Third Edition

R P Jain
 CHAPTER 1

1.1 (a) Analog. The output of a pressure gauge is proportional to the pressure
being measured and can assume any value in the given range.
(b) Digital. An electric pulse is produced for every person entering the exhibi-
tion using a photoelectric device. These pulses are counted using a digital
circuit.
(c) Analog. The reading of the thermometer is proportional to the temperature
being measured and can assume any value in the given range.
(d) Digital. Inputs are given with the help of switches, which are converted
into digital signals 1 and 0 corresponding to the switch in the ON or OFF
position. These signals are processed using digital circuits and the results
are displayed using digital display devices.
(e) Analog. It receives modulated signals which are analog in nature. These
signals are processed by analog circuits and the output is again in the
analog form.
(f) Digital. It has only two possible positions (states), ON and OFF.
(g) Digital. An electric pulse is produced for every vote cast by pressing of
switch of a candidate. The pulses thus produced for each candidate are
counted separately and also the total number of votes polled are counted.
1.2 (a)

(i) S1 S2 Bulb (ii) S1 S2 Bulb

OFF OFF OFF OFF OFF OFF
OFF ON OFF OFF ON ON
ON OFF OFF ON OFF ON
ON ON ON ON ON ON

(iii) S Bulb (iv) S1 S2 Bulb

OFF ON OFF OFF OFF
ON OFF OFF ON ON
ON OFF ON
ON ON OFF
(b)

(i) S1 S2 Bulb (ii) S1 S2 Bulb

0 0 0 0 0 0
0 1 0 0 1 1
1 0 0 1 0 1
1 1 1 1 1 1

(iii) S Bulb (iv) S1 S2 Bulb

0 1 0 0 0
1 0 0 1 1
1 0 1
1 1 0

(c) (i) AND (ii) OR (iii) NOT (iv) EX-OR

1.3
1
Input A
0
0 1 2 3 4 5 t(ms)

1
Input B
0
0 1 2 3 4 5 t(ms)

1
AND
0

1
OR
0

1
NAND
0

1
NOR
0

1
EX-OR
0

1.4
Inputs Outputs of
A B (a) (b) (c) (d)
0 0 1 1 0 0
0 1 0 1 0 1
1 0 0 1 0 1
1 1 0 0 1 1

The operations performed are

(a) NOR (b) NAND (c) AND (d) OR

2
1.5 For Fig. 1.6
(a) A Y (b) A B AB Y
0 1 0 0 1 0
1 0 0 1 1 0
1 0 1 0
1 1 0 1

(c) A B A B Y
0 0 1 1 0
0 1 1 0 1
1 0 0 1 1
1 1 0 0 1

For Fig. 1.8

(a) A Y (b) A B A+B Y

0 1 0 0 1 0
1 0 0 1 0 1
1 0 0 1
1 1 0 1

(c) A B A B Y
0 0 1 1 0
0 1 1 0 0
1 0 0 1 0
1 1 0 0 1
1.6 (a) NAND, NOR (b) AND
(c) NAND (d) OR
1.7 (a)
Inputs AB AB Output
A B Y
0 0 0 0 0
0 1 0 1 1
1 0 1 0 1
1 1 0 0 0

(b) EX–OR
(c) A

3
 (d) Y = AB + A B
\ Y = AB + A B
= AB ⋅ A B

Y = Y = AB ⋅ AB
= Y1 ⋅ Y2
where, Y1 = AB and Y2 = AB

A
Y1

B Y2

1.8 For simplicity, we shall consider 2-input gates, but the results are equally
valid for any number of inputs. In the positive logic system, the higher of the
two voltages is designated as 1 and the lower voltage as 0. On the other hand
in the negative logic system, the lower of the two voltage is designated as 1
and the higher voltage as 0. Therefore, if 1s and 0s are interchanged, the logic
system will change from positive to negative and vice-versa.
(a) In the truth table of positive logic AND gate replace all zeros by ones
and all ones by zeros. The resulting truth table is same as that of the OR
gate. Similarly, if all ones and zeros are interchanged in the truth table
of the OR gate, the resulting truth table will be same as that of the AND
gate.
(b) Repeat part (a) for NAND and NOR gates.
1.9 (a) A + A B + A B = (A + A B ) + A B
= A (1 + B ) + A B
= A × 1 + AB
= A + AB
= (A + A ) (A + B) = A + B
(b) AB + A B + A B = (A + A ) B + A B
= B + A B = (B + A ) (B + B )
= A +B
(c) A BC + A B C + AB C + ABC
= A BC + A B C + AB (C + C )
= A BC + A B C + AB
= A BC + A (B + B C)
= A BC + A (B + B ) (B + C)

4
 = A BC + AB + AC
= C (A + A B) + AB
= C (A + A ) (A + B) + AB
= C (A + B) + AB
= AB + BC + CA
1.10 (a)
A B AB AB A + A B + AB A+B
0 0 0 0 0 0
0 1 1 0 1 1
1 0 0 1 1 1
1 1 0 0 1 1

(b)
A B AB AB AB AB + A B + A B A +B
0 0 0 0 1 1 1
0 1 0 1 0 1 1
1 0 0 0 0 0 0
1 1 1 0 0 1 1

(c)
A B C A BC AB C AB C ABC LHS AB BC CA RHS
0 0 0 0 0 0 0 0 0 0 0 0
0 0 1 0 0 0 0 0 0 0 0 0
0 1 0 0 0 0 0 0 0 0 0 0
0 1 1 1 0 0 0 1 0 1 0 1
1 0 0 0 0 0 0 0 0 0 0 0
1 0 1 0 1 0 0 1 0 0 1 1
1 1 0 0 0 1 0 1 1 0 0 1
1 1 1 0 0 0 1 1 1 1 1 1

1.11 (a) The realization of LHS requires, two inverters, two 2-input AND gates,
and one 3-input OR gate, whereas the realization of RHS requires only
one two input OR gate.
A

A
B
B

(i) (ii)

5
 (b) The realization of LHS requires two inverters, three 2-input AND gates
and one 3-input OR gate, whereas the realization of RHS requires only
one inverter and one 2-input OR gate.

B B

(i) (ii)
(c) The realization of LHS requires three inverters, four 3-input AND gates
and one 4-input OR gate, whereas the realization of RHS requires only
three 2-input AND gates and one 3-input OR gate.

(i)

(ii)

1.12 (a) AB + CD = AB + CD = AB ⋅ CD

6
 (b) (A + B) (C + D) = ( A + B) ⋅ ( C + D )

= ( A + B) + ( C + D )
(i) The left hand side of (a) can be realized by using two 2-input AND
gates followed by one 2-input OR gate, while the right hand side is
realizable by two 2-input NAND gates followed by another 2-input
NAND gate. Hence an AND-OR configuration is equivalent to a NAND-
NAND configuration.
(ii) The left hand side of (b) is realizable by two 2-input OR gates followed
by a 2-input AND gate, while the right hand side is realizable by two
2-input NOR gates followed by another 2-input NOR gate. Hence an
OR-AND configuration is equivalent to a NOR-NOR configuration.
1.13
(a)
A A
B B

Y Y

C C
D D
(i) (ii)
(b)
A A
B B

Y Y

C C
D D
(i) (ii)

1.14 (a) Since A × B = B × A

Therefore, the AND operation is commutative. If A × (B × C) = (A × B) × C, then the
AND operation is associative. This can be proved by making truth table as given
below:
A B C (A × B) × C A × (B × C)
0 0 0 0 0
0 0 1 0 0
0 1 0 0 0
0 1 1 0 0
1 0 0 0 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1

7
 Since the last two columns of the truth table are identical, which proves
that the AND operation is associative.
(b) Since, A + B = B + A, therefore, OR operation is commutative.
The associative property requires
A + (B + C) = (A + B) + C
which can be proved by making the truth table in a way similar to the
truthtable of (a) above
(c) Since, A Å B = B Å A, which means the EX-OR operation is commutative.
The associative property requires
(A Å B) Å C = A Å (B Å C)
This can be proved by making truth table
1.15 (a) Since = A ⋅ B = B ⋅ A , therefore, the NAND operation is commutative.
To verify whether the NAND operation is associative or not, we prepare
the truth table as given below. From the Table we observe that the last
two columns are not identical, which means
A ⋅ ( B ⋅ C ) ≠ ( A ⋅ B) ⋅ C
This shows that the NAND operation is not associative.
A B C A ⋅ ( B ⋅ C) ( A ⋅ B) C
0 0 0 1 1
0 0 1 1 0
0 1 0 1 1
0 1 1 1 0
1 0 0 0 1
1 0 1 0 0
1 1 0 0 1
1 1 1 1 1

(b) Since, A + B = B + A , which means the NOR operation is commutative.

By making a truth table similar to the truth table of (a) above we can
verify that

( A + B) + C ≠ A + ( B + C )
Therefore, the NOR operation is not associative.
1.16 Two possible realizations are given on page 9:
1.17 (i) If only one of the variables is 1 and all others are zero, then
(1 Å 0) Å 0 Å 0 Å . . . = 1 Å 0 Å 0 Å . . .
=1 Å0=1
(ii) If only two of the variables are 1 and all others are zero, then (since EX-
OR operation is commutative and associative)
(1 Å 1) Å 0 Å 0 Å 0 Å . . . = 0 Å 0 Å 0 Å 0 Å . . . = 0
(iii) Similarly, if only three of the variables are 1, then
(1 Å 1) Å 1 Å 0 Å 0 Å . . .
=0 Å1Å0Å0Å0Å...
=1

8
 A AÅB
B
AÅBÅC
C

Y
D AÅBÅCÅD
or

A AÅB

Y
AÅBÅCÅD
C
D CÅD
Fig. 1.17

In the same way we can try higher number of ones. It is obvious from
the above discussion that Z = 1, if an odd number of variables are 1 and
Z = 0 if an even number of variables are 1.
1.18 Since a logical variable can assume one of the two values (0 or 1) the
number of possible combinations is 2N.
Take an N-bit binary number bN–1 bN–2 . . . b2b1b0 and write all combina-
tions from 00 . . . 000 to 11 . . . 111 in normal binary ascending order.
1.19 (a) 7402 is a quad 2-input NOR gate. This means there are four identical
2-input NOR gates. Each gate requires three pins, two for inputs and one
for output. Therefore, the four gates requires 3 ´ 4 = 12 pins. Two pins
are required for the power supply (VCC and GND). Hence it is a 14-pin
IC.
(b) 7404 is a hex inverter.
The number of pins = 2 ´ 6 + 2 = 14.
(c) 7408 is a quad 2-input AND gate.
The number of pins = 3 ´ 4 + 2 = 14.
(d) 7410 is a triple 3-input NAND gate.
The number of pins = 4 ´ 3 + 2 = 14.
(e) 7411 is a triple 3-input AND gate.
The number of pins = 4 ´ 3 + 2 = 14.
(f) 7420 is a dual 4-input NAND gate.
The number of pins = 5 ´ 2 + 2 = 12.
Since 12-pin IC package is not used, therefore, it is packaged as 14-pin IC.
Two pins are left free (NC).
(g) 7427 is a triple 3-input NOR gate.
The number of pins = 4 ´ 3 + 2 = 14.
(h) 7432 is a quad 2-input OR gate.
The number of pins = 3 ´ 4 + 2 = 14.

9
 (i) 7486 is a quad EX-OR gate.
The number of pins = 3 ´ 4 + 2 = 14.
1.20 (a) (i) 7408 and 7432
(ii) 7400
(b) (i) 7432 and 7408
(ii) 7402
1.21 Logic Circuit A
0.4V = 0
2V = 1
Logic Circuit B
–0.75V = 1
–1.55V = 0
1.22
Inputs Output
AND OR NAND NOR
A B C Y1 Y2 Y3 Y4
0 0 0 0 0 1 1
0 0 1 0 1 1 0
0 1 0 0 1 1 0
0 1 1 0 1 1 0
1 0 0 0 1 1 0
1 0 1 0 1 1 0
1 1 0 0 1 1 0
1 1 1 1 1 0 0

1.23 Yes.
A A
(a) B Y or B Y
C C

Logic 1
A A
(b) B Y or B Y
C C

Logic 0
A A
(c) B Y or B Y
C C

Logic 1
A A
(d) B Y or B Y
C C

Logic 0

10
1.24 Yes.
AND — by connecting one of the inputs to logic 0
OR — by connecting one of the inputs to logic 1
NAND — by connecting one of the inputs to logic 0
NOR — by connecting one of the inputs to logic 1.
1.25 (a) Active-high (b) Active-low
(c) Active-high (d) Active-low
1.26 (a) Active-low (b) Active-high
(c) Active-low (d) Active-high
1.27 (a)
A
B

C
Y = A × B × C = (A × B) × (C)
(b)
A
B

C
Y = A + B + C = (A + B) + (C)

(c)
A AB
B AB

C
C

Y = A ⋅ B ⋅ C = ( A ⋅ B) + C

= ( A ⋅ B) ⋅ C
= A⋅ B⋅C
(d)
A
B Y

11
1.28 (a) A Å B = A B + A B
A Å B = AB + A B
= AB + AB = A Å B
(b) A ⊕ B = AB + AB
A Å B = AB + A B
= AB + AB
A Å B = AB + A B = AB + AB
(c) B Å (B Å AC) = B Å B Å AC = 0 Å AC
= AC

12
 CHAPTER 2
2.1
(a) 111001 = 1 ´ 25 + 1 ´ 24 + 1 ´ 23 + 0 ´ 22 + 0 ´ 21 + 1 ´ 20
= 32 + 16 + 8 + 0 + 0 + 1
= (57)10
(b) 101001 = 1 ´ 25 + 0 ´ 24 + 1 ´ 23 + 0 ´ 22 + 0 ´ 21 + 1 ´ 20
= 32 + 0 + 8 + 0 + 0 + 1
= (41)10
(c) 11111110 = 1 ´ 27 + 1 ´ 26 + 1 ´ 25 + 1 ´ 24 + 1 ´ 23 + 1 ´ 22
+ 1 ´ 21 + 0 ´ 20
= 128 + 64 + 32 + 16 + 8 + 4 + 2 + 0 = (254)10
(d) 1100100 = 64 + 32 + 0 + 0 + 4 + 0 + 0 = (100)10
(e) 1101.0011 = 1 ´ 23 + 1 ´ 22 + 0 ´ 21 + 1 ´ 20 + 0 ´ 2–1 + 0 ´ 2–2
+ 1 ´ 2–3 + 1 ´ 2–4
= 8 + 4 + 0 + 1 + 0 + 0 + 0.125 + 0.0625
= (13.1875)10
(f) 1010.1010 = 8 + 2 + 0.5 + 0.125
= (10.625)10
(g) 0.11100 = 0.5 + 0.25 + 0.125
= (0.875)10
2.2 (a) Quotient Remainder
37
18 1
2
18
9 0
2
9
4 1
2
4
2 0
2
2
1 0
2
1 0 1
2

1 0 0 1 0 1
Thus (37)10 = (100101)2
Similarly,
(b) (255)10 = (11111111)2
(c) (15)10 = (1111)2

13
 (d) Integer part: (26)10 = (11010)2
Fractional part:
0.25 0.5
´2 ´2
0.5 1.0
¯ ¯
0 1
Therefore, (26.25)10 = (11010.01)2
(e) Integer part: (11)10 = (1011)2
Fractional part: 0.75 0.5
´2 ´2
1.5 1.0
¯ ¯
1 1
Thus (11.75)10 = (1011.11)2
(f) 0.1 0.2 0.4 0.8 0.6 0.2 0.4 0.8
´2 ´2 ´2 ´2 ´2 ´2 ´2 ´2
0.2 0.4 0.8 1.6 1.2 0.4 0.8 1.6
¯ ¯ ¯ ¯ ¯ ¯ ¯ ¯
0 0 0 1 1 0 0 1...
Thus, (0.1)2 = (0.00011001)2
The process may be terminated at the required number of significant bits.
2.3 (a) 1 1 1 ¬ Carry
1 0 1 1
+1 1 0 1
1 1 0 0 0
­
Final carry
(b) 1 1 1 1 1 ¬ Carry
1 0 1 0. 1 1 0 1
+ 1 0 1. 0 1
1 0 0 0 0. 0 0 0 1
­
Final carry
2.4
(a) 01000 01000
–01001 + 10111 (2’s complement)
11111
Since the MSB of the sum is 1, which means the result is negative and it is
in 2’s complement form. 2’s complement of 11111 = 00001 = (1)10
Therefore, the result is –1.

14
 (b) 01100 Þ 01100
–00011 + 11101 (2’s complement)
101001 = + 9
­
Ignore
(c) 0011.1001 Þ 0011.1001
–0001.1110 +1110.0010 (2’s complement)
10001.1011 = + 1.6875
­
Ignore

2.5 (a) Quotient Remainder

375
46 7
8
46
5 6
8
5
0 5
8
5 6 7
Therefore, (375)10 = (567)8 = (101110111)2
(b) Quotient Remainder
249
31 1
8
31
3 7
8
3
0 3
8
3 7 1

Therefore, (249)10 = (371)8 = (011111001)2

(c) Integer part: (27)10 = (33)8 = (011011)2
Fractional part: 0.125
´8
1.000
¯
1
Thus (0.125)10 = (0.1)8 = (0.001)2
Therefore, (27.125)10 = (33.1)8 = (011011.001)2
2.6 (a) 11 011 100.101 010 = (334.52)8
(334.52)8 = 3 ´ 82 + 3 ´ 81 + 4 ´ 80 + 5 ´ 8–1 + 2 ´ 8–2
= (220.65625)10
(b) 01 010 011.010 101 = (123.25)8 = (83.328125)10
(c) 10 110 011 = (263)8 = (179)10
15
2.7 (a) Quotient Remainder
375
23 7
16
23
1 7
16
1
0 1
16
1 7 7
Therefore, (375)10 = (177)16 (or 177H) = (0001 0111 0111)2
(b) Quotient Remainder
249
15 9
16
15
0 15
16
F 9
Therefore, (249)10 = (F9)16 (or F9H) = (1111 1001)2
(c) Integer part:
Quotient Remainder
27
1 11
16
1
0 1
16
1 B
Thus (27)10 = 1BH
Fractional part:
0.125
´ 16
2.000
¯
2
\ (0.125)10 = 0.2H
\ (27.125)10 = (1B.2)16 = 1B.2H = (00011011.0010)2
2.8 (a) 1101 1100.1010 10 = (DC.A8)16
(DC.A8)16 = 13 ´ 161 + 11 ´ 160 + 10 ´ 16–1 + 8 ´ 16–2
= (220.65625)10
(b) 0101 0011.0101 01 = (53.54)16 = (83.328125)10
(c) 1011 0011 = (B3)16 = (179)10
2.9 For each decimal digit write its natural BCD code
(a) 46 = 0100 0110 (BCD)
(b) 327.89 = 0011 0010 0111.1000 1001 (BCD)
(c) 20.305 = 00100000.0011 0000 0101 (BCD)
2.10 For each decimal digit write its 4-bit Excess-3 code.
(a) 46 = 0111 1001 (Excess-3)
(b) 327.89 = 0110 0101 1010.1011 1100 (Excess-3)
(c) 20.305 = 0101 0011.0110 0011 1000 (Excess-3)

16
2.11 Starting from 4-bit Gray code given in Table 2.8 formulate 5-bit Gray code as
given below in Table 1.
Table 1 Table 2

Decimal G4 G3 G2 G1 G0 Decimal G5 G4 G3 G2 G1 G0
No. No.
0 0 0 0 0 0 0 0 0 0 0 0 0
1 0 0 0 0 1 1 0 0 0 0 0 1
2 0 0 0 1 1 2 0 0 0 0 1 1
: : : 3 0 0
: : : : 0
13 0 1 0 1 1 17 0 1 1 0 0 1
14 0 1 0 0 1 : 0
15 0 1 0 0 0 30 0 1 0 0 0 1
16 1 1 0 0 0 31 0 1 0 0 0 0
17 1 1 0 0 1 32 1 1 0 0 0 0
18 1 1 0 1 1 33 1 1 0 0 0 1
: : : 1
: : 46 1 1 1 0 0 1
29 1 0 0 1 1 : 1
30 1 0 0 0 1 62 1 0 0 0 0 1
31 1 0 0 0 0 63 1 0 0 0 0 0

Similarly, form 6-bit Gray Code as given in Table 2.

From Table 2, we obtain
(46)10 = 111001 (Gray Code)
2.12 Writing the 6-bit code for each character (See Table 2.9), we obtain
100111 001011 000011 101100 101000
2.13 (a) Write the 7-bit ASCII code for each character (See Table 2.10)
R.P. JAIN = 1010010 0101110 1010000 0101110 1001010
1000001 1001001 1001110
(b) Write the 8-bit EBCDIC code for each character (See Table 2.9)
R.P. JAIN = 11011001 01001011 11010111 01001011 11010001
11000001 11001001 11010101
(c) Write the 6-bit internal code for each character (See Table 2.9)
R.P. JAIN = 101001 011011 100111 011011 100001 010001
011001 100101
2.14 (a) Count the number of ones for every character from ASCII table and
attach a 1 or 0 as the MSB for odd or even number of ones respectively.
For example, the ASCII code for R is 1010010, which has three ones.
Therefore, a 1 is to be attached as MSB and the resulting 8-bit code
with even parity will be
11010010
Similarly, the code for l is 0101110 which has four ones. Therefore, a
0 is to be attached as MSB and the resulting 8-bit code with even parity
will be 00101110.

17
 In a similar way parity bit can be attached to every character.
(b) Repeat part (a) for EBCDIC code.
2.15 (a) Attach 0 or 1 as MSB to make the number of ones odd. For example,
8-bit ASCII code for R with odd parity is 01010010
(b) Repeat part (a) for EBCDIC code.
2.16 (a) Since, 25 = 32 and 26 = 64, therefore, the minimum number of bits
required to encode 56 elements of information is 6.
(b) 27 < 130 < 28
Therefore, 8 bits are required to encode 130 elements of information.
2.17 In the 8 bit ASCII code with the parity bit, if binary to hexadecimal conversion
is used, the resulting format will be hexadecimal. For example,
R = 11010010 = D2 H
and l = 00101110 = 2EH
for even parity and
R = 01010010 = 52H
and l = 10101110 = AEH
for odd parity.
2.18 Consider the following examples:
(i) 7 0111 Þ 0111
–3 –0011 + 1100 (1’s complement)
4 10011
1 End-Around Carry (EAC)
0100 = 4
(ii) 3 0011 Þ 0011
–7 – 0111 + 1000 (1’s complement)
–4 1011 = –4 in 1’s complement form
From the above examples the rules of subtraction can be summarized as:
(a) Add ones complement of the subtrahend to the minuend.
(b) If a carry is produced, add end-around carry (EAC)
(c) If the MSB of the sum is 0, the result is positive
(d) If the MSB of the sum is 1, the result is negative and it is in one’s
complement format.
2.19 100 ´ 20 ´ 8 bits.
2.20 132 ´ 7 bits.
2.21 Let us consider the BCD code for 9 and find out its Hamming code for
error correction.
Hamming Code
Decimal Position ® 1 2 3 4 5 6 7
digit p1 p2 n1 p3 n2 n3 n4
9 BCD : : 1 : 0 0 1
: : : : : : :
odd parity for : : : : : : :
1,3,5,7 requires p1 = 1 1 : 1 : 0 0 1
odd parity for 2,3,6,7 : : : : : : :
requires p2 = 1 1 1 1 : 0 0 1
odd parity for 4,5,6,7 : : : : : : :
requires p3 = 1 1 1 1 0 0 0 1

18
Therefore, Hamming code for decimal digit 9 is 1 1 1 0 0 0 1.
Similarly, Hamming code is determined for each BCD digit and the complete se-
quence is given below.
Hamming code
Decimal Position ® 1 2 3 4 5 6 7
digit p1 p2 n1 p3 n2 n3 n4
0 1 1 0 1 0 0 0
1 0 0 0 0 0 0 1
2 1 0 0 0 0 1 0
3 0 1 0 1 0 1 1
4 0 1 0 0 1 0 0
5 1 0 0 1 1 0 1
6 0 0 0 1 1 1 0
7 1 1 0 0 1 1 1
8 0 0 1 1 0 0 0
9 1 1 1 0 0 0 1

19
 CHAPTER 3

3.1 (a) The number of covalent bonds breaking away increases with temperature,
which decreases the resistivity of the semiconductor material, whereas in a
metal an increase in the temperature results in a greater thermal motion of
the ions, and hence decreases the mean free path of the free electrons. This
results in a decrease in the mobility and hence resistivity increases with
temperature.
(b) All the covalent bonds are intact at 0 K and hence there are no free charge
carriers, whereas at room temperature some of the covalent bonds break
away resulting in small conductivity.
3.2 (a) Using the V-I relation of the diode, we obtain
I1 » I0 exp (V1/hVT) (3.1)
and I2 = 2I1 » I0 exp (V2/hVT) (3.2)
From Eqs. (3.1) and (3.2),
2 = exp (V2 – V1/hVT)
or V2 – V1 = hVT 1n 2 = 2 ´ 26 ´ 0.693 mV » 36 mV
(b) Since, V1 = 700 mV
Therefore, V2 = 700 + 36 = 736 mV
736 − 700
Percentage change = × 100%
700
= 5.14%
3.3 From the V–I relation of the diode, we obtain
I1 » I0 exp (700/hVT)
and I2 » I0 exp (750/hVT)
\ I2/I1 = exp (50/2 ´ 26) = 2.616
or I2 = 2.616 ´ 2 = 5.232 mA

5. 232 − 2
(b) Percent change = × 100%
2
= 161.6%
I2
3.4 = 10 = e {(V2 – V1)/2 ´ 26}
I1
or V2 – V1 = 52 1n 10 = 119.73 mV
3.5 (a) The circuit will be under steady-state at t = 20ms,

dQ
i.e., =0
dt
20
 V1 10
∴ I1 ≈ = = 1mA
R 10

Q
Since, =I
t
\ Q = 1 ´ 10–6 ´ 10–3 = 10–9 C
(b) The diode will turn off when excess minority charge has been removed.

VR
IR ≈ = 5 = 0. 5 mA
R 10
The differential equation is
dQ Q
+ = − 0. 5 × 10 −3
dt τ
Solving this with initial condition
Q(0) = 10–9 C (part (a)), we obtain
Q = – 0.5 ´ 10–9 + 1.5 ´ 10–9 e–t
Set Q = 0 for cut-off
\ t = 1.099 ms
(c) The various waveforms are given below. The recovery time constant
tR = RCO = 10 ´ 103 ´ 10 ´ 10–12 = 0.1 ms
Vi
V1 = 0V

0 t
-V2 = -5V

Vd

0.7V
0 t
tR
-5V
Id
1 mA

0 t
-0.5 mA tR

Excess Q t
Minority
Charge 0
t
0 1.099 ms

21
3.6 (a) Since the E-B junction is forward-biased, therefore, the transistor is con-
ducting (i.e., IC is flowing). It may either be operating in the active region
or in the saturation region.
Let us assume that the transistor is operating in the saturation region.
Then the base and collector voltages will be VBE, sat (= 0.8 V) and VCE, sat
(= 0.1 V) respectively.
Therefore, the collector current IC and the base current IB are given by

VCC − VCE , sat 10 − 0. 1

IC = = = 3. 33 mA
RC 3

V BB − V BE , sat 5 − 0. 8
and IB = = = 21 µA
RB 200

⋅
hFE IB = 21 ´ 100 = 2.1 mA
Since IC>hFE IB, therefore the transistor cannot be in saturation. Hence it is
conducting in the active region.
with VCC = 6V, let us again assume that the transistor is operating in the
saturation region. Therefore,
6 − 0.1
IC = ≈ 2 mA
3
The current IB remains same as in part (a).
Therefore, now
IC < hFEIB
which means the transistor is certainly operating in the saturation region.
(b) The value of RC required for the transistor to be in saturation is given by
VCC − VCE , sat
≤ h FE I B
RC

or RC ≥ 10 − 0. 1 kW
2. 1
³ 4.7 kW
\ The value of Rc just sufficient for saturation will be 4.7 kW.
If the value of RC used is more than 4.7kW, the transistor will continue to
be operating in the saturation region.
(c) The value of RB required to drive the transistor into saturation is given by
V BB − V BE , sat
IC ≤ h FE ×
RB

5 − 0. 8
or RB ≤ 100 ⋅ kW
3. 3
£ 127.27 kW

22
 The value of RB just sufficient to drive the transistor into saturation will be
127.27 kW. If a smaller value of RB than the value calculated above is
used, the transistor will be driven deeper into saturation.
3.7 (a) For the transistor to be in the cut-off region, the voltage
VBB £VBE, cut–in
£ 0.5 V
(b) For active region operation
VCE − VCE , sat V BB − V BE , sat
≥ ⋅ h FE
RC RB

R B VCC − VCE , sat

or, VBB < ⋅ + V BE , sat
RC h FE

5 − 0.1
< 100 ⋅ + 0. 8
2 100
< 3.25 V
Therefore, the range of VBB for active region is
0.5 V < VBB < 3.25 V
(c) The range of VBB for saturation region is
VBB ³ 3.25 V
3.8 For the transistor to be in saturation
VCC − VCE , sat V BB − V BE , sat
≤ ⋅ h FE
RC RB

R B VCC − V CE, sat

or, hFE (min) = R ⋅ V
C BB − V BE , sat

5 − 0. 1
= 200 ⋅
1 5 − 0. 8
= 233.3
3.9 Assume the transistor to be in saturation. Writing KVL equations for the
collector and base circuits,
RCIC + VCE, sat + RE (IC + IB) = VCC
and RBIB + VBE, sat + RE (IC + IB) = VBB
Substituting the values, we obtain,
53 IC + 50 IB = 4.8

23
 and 50 IC + 100 IB = 4.2
Solving these equations,
IC = 0.096 mA
and IB = –6.214 mA
Since IB comes out to be negative, hence the transistor is not in saturation.
Assuming VBE = 0.7 V in the active region, KVL for the base circuit
will be
[RB + (1 + hFE) RE] IB = 5 – 0.7
or, IB = 8.43 ´ 10–4 mA
\ IC = hFE IB = 8.43 ´ 10–2 mA

and IE » –8.43 ´ 10–2 mA

3.10 The equivalent circuit at the input of a transistor consists of input resistance Ri
in parallel with the input capacitance Ci as shown in Fig. given below:
C

B
+
RB
Vi Ri Ci

Equivalent circuit at the

transistor input
When fast changes occur in Vi, the voltages at B change with the time con-
stant
Ci (RB||Ri)
If a capacitor C is connected across RB, the voltage at B will change as soon as
Vi changes because of the capacitive voltage divider. This helps in improving
the switching speed of transistor circuit.
3.11 (a) For the load transistors
5V
IC,sat = = 2.5 mA
2 kW
2. 5 mA
IB,sat = = 2. 5 µA
100
\ The minimum value of Vi required for the load transistors to be in satura-
tion is
Vi(min) = 25 ´ 10–3 ´ 10 + 0.8
= 1.05 V

24
 (b) Assuming the load transistors to be in saturation the equivalent circuit at
their input will be as shown in Fig. (a), which reduces to the circuit shown
in Fig. (b).
Now, the voltage Vi = VO can be determined using the principle of super-
position and is given by
5 2
Vi = VO = ´5+ ´ 0.8
5+2 5+2
= 3.8 V
10 kW
Vi
Vi
0.8 V
5 kW
10 kW
0.8 V
0.8 V

(a) (b)

3. 8 − 0. 8
(c) The base current IB1 = I B2 = mA
10
= 0.3 mA
3.12 (a) When both the transistors are cut-off, there is no current drawn from the
supplies, and the voltage at Y is 5 V.
(b) When both the transistors are in saturation, the voltage at Y is 0V.
(c) Assume T1 to be cut-off and T2 to be in saturation. Since T2 is in saturation,
æ VCC ö
the voltage at Y will be 0 V. The currents I1 and I2 will be same ç =
è RC ÷ø
and IC2 = I1 + I2.
Similarly, if T1 is in saturation and T2 is cut-off then IC1 = I1 + I2

(d) V1 V2 Y
0V 0V 5V
0V 5V 0V
5V 0V 0V
5V 5V 0V

It performs NOR operation.

3.13 (a) Assume the transistor to be in saturation.
5 − 0. 8
Therefore, IC = 5 = 5 mA, I B = = 0. 042 mA
1 100
hFE IB = 150 ´ 0.042 = 6.3 mA
Since IC < hFE IB, therefore, the transistor is definitely in saturation.
25
 (b) When S1 is closed, I1 = (5 – 0.7/4) = 1.075 mA assuming the transistor to
be in saturation.
Therefore, IC = I + I1
= 5 + 1.075
= 6.075 mA
Since IC < hFE ⋅ IB
Therefore, the transistor continues to remain in saturation.
(c) When both S1 and S2 are closed, if we again assume the transistor to be in
saturation,
I C = I + I1 + I2
= 5 + 2 ´ 1.075
= 7.15
Now IC <hFE⋅IB
Which means the transistor no longer remains in saturation. Therefore, it
is conducting in the active region.
3.14 The base current required for each transistor to be in saturation is 25mA.
Therefore, total base current will be 25 ´ 100 mA. If this current flows
through RC of driver, the voltage at its collector will be
VO = 5 – 2 ´ 103 ´ 25 ´ 100 ´ 10–6
=0
Which shows that it is not possible to have a base current of 25 mA for each
of the load transistor. Hence, the load transistors will not remain in saturation.
3.15 Let T1 be cut-off. Therefore, the circuit will be as shown below:

VCC VCC

RC RC

T1
T2

Now, the total resistance in the collector circuit of T2 is RC || RC = RC/2 which

means its collector current increases. This requires the base current to be
doubled for the transistor to remain in saturation. Therefore, the transistor will
be operating in the active region.
RC
3.16 The effective resistance = RC || RC =
2

26
 RC
Therefore, the time constant = ⋅ CO
2
3.17 (a) Since VGS = 0, therefore, the VDS VS ID characteristic will be same as the
characteristic for VGS = 0 in Fig. 3.41(b).
(b) Transistor T2 acts as load for T1, the v-i characteristic of the load is that of
part (a). Since the current ID is same in both T1 and T2, therefore, for a
given value of ID, the voltage.
VDS1 = VDD – VDS2
Take various values of ID and for each ID determine VDS2 from the
curve of (a).
Calculate VDS1 and locate a point corresponding to VDS1, ID on the char-
acteristic of Fig. 3.28. Thus, we get a load curve AB as shown below.
From this we see that when
Vi = 0, VO = 5V
and Vi = 5V, VO » 0V
Therefore, the circuit functions as an inverter.

ID, mA

Load curve
4 B VGS = 5 V

3 4 V

2 3 V

1 2 V
A 1 V
0
0 5 10 VDS, V

27
 CHAPTER 4

4.1 When the output of the driver gate is high, the load gates are in saturation and
T1 and T2 are cut-off. Therefore, VO = 1.14V. The current drawn from the
supply,
VCC − VO 3. 6 − 1. 14
I1 = = = 3. 844 mA
RC 640
when the output of the driver is low, T1 and/or T2 are in saturation and
VO = 0.2V.
The current drawn from the supply

3. 6 − 0. 2
I2 = = 5. 312 mA
640

I1 + I 2 3. 844 + 5. 312
Average current = I av = =
2 2
= 4.578 mA
Average Power drawn from the supply = VCC ´ Iav
= 3.6 ´ 4.578 mW
= 16.48 mW
4.2 (a) & (b)
hFE = 10 hFE = 20
N VO Noise Margin VO Noise Margin
D1 D1
5 1.14 0.1 1.14 0.22
6 1.09 0.05 1.09 0.17
7 1.055 0.015 1.055 0.135
8 <1.04 Load gate transistors
not in saturation 1.026 0.106
9 <1.04 ’’ 0.997 0.077
10 <1.04 ’’ 0.984 0.064

The voltage VO and noise margin D1 are given in Table.

(c) Fan out and noise margin increases with increase in hFE.
(d) For hFE = 10, if N > 7, the load gate transistors come out of saturation.
The value of noise margin decreases with increased N.
4.3 (a) Let us consider all the possible cases:
Case I A = B = C = D = 0.
Therefore, all the transistors TA, TB, TC, and TD are cut-off, hence
Y = Y1 = Y2 = 1
Corresponding to this, each gate will be able to drive 5 gates. Therefore,
the fan-out of this combination will be 10. Alternatively, we can consider

28
 equivalent collector resistance R¢C = RC || RC = RC/2, which means the base
current of 5 + 5 load transistors can flow through R¢C and give same output
voltage corresponding to logic 1 as the output voltage of each gate individ-
ually while driving 5 load gates.
Case II At least one of the inputs of each gate P and Q are HIGH. This
will drive the corresponding transistors into saturation and consequently
Y = Y1 = Y2 will be LOW and hence the load transistors will be cut-off.
Therefore, there is no problem of fan-out.
Case III At least one of the inputs to gate P is HIGH and C = D = 0. The
transistor whose input is HIGH will be driven to saturation forcing the
output voltage to LOW. Consequently, Y = Y1 = Y2 will be LOW and this
situation is similar to that of Case II.
Case IV A = B = 0 and at least one of the inputs to gate Q is LOW. This
will lead to a situation similar to that of Case III.
Therefore, the fan-out is 10.
(b) Without load gates, the propagation delay time-constant

RC
= ⋅ 2C O
2
= RC ⋅ CO
which is same as the propagation delay time-constant of a single gate.
With load gates, the propagation delay time-constant for a single driver
(without wired-logic) is

æ RB ö
RC + × ( CO + NCi )
èç N ø÷
where, N is the number of load gates.
RB is the resistance in the base circuit of a load gate.
Ci is the input capacitance of a load gate. With wire-ANDing, the time-
constant will be
æ RC RB ö
çè 2 + N ÷ø × (2 CO + NCi )

When the output is high, the current drawn from the supply is
IH = 3.844 ´ 2 mA (see Prob. 4.1)
Similarly, for low output
IL = 5.312 ´ 2 mA
\ Iav = 9.156 mA
Power drawn from the supply = 3.6 ´ 9.156 mW
= 32.96 mW
4.4 (a) This circuit has active pull-up (consisting of T2 and 100 W resistor) instead
of passive pull-up RC used in normal RTL gates. The state of transistor T2

29
 will always be opposite to that of T3, i.e., if T3 is cut-off, T2 is in saturation
(since T1 is cut-off) and vice-versa. Therefore, when the input Vi is HIGH,
T3 will be in saturation, while T2 is cut-off and VO = VCE,sat » 0 V.
When Vi is LOW, T2 is in saturation and T3 is cut-off. The output
voltage VO will be HIGH.
(b) If it is driving N load gates, the output circuit corresponding to HIGH state
will be as shown in Fig. Prob. 4.4(a).
VCC(3.6 V)

640 W 100 W

450 W T2
IB IO

450 W/N
Equivalent
P input circuit
VBE, sat
of load gates
» 0.8 V

Fig. Prob. 4.4(a)

VCC − VCE , sat − V BE, sat

IO =
100 + 450 / N

3. 6 − 0. 2 − 0. 8
=
100 + 450 / N

= 2. 6
100 + 450 / N
Writing KVL for the closed path P, we obtain

450
VCC – 1090 IB – VBE, sat − I – VBE, sat = 0
N O

1 é 450 æ 2.6 öù
or IB = ê 3.6 - 0.8 - 0.8 - ú
1090 êë N è 100 + 450/ N ÷ø úû
ç

For T2 to be in saturation
hFE.IB ³ IO

30 é 450 æ 2.6 öù 2.6

\ ê2 - ´ç ÷ ú³
1090 ëê N è 100 + 450/ N ø ûú 100 + 450/ N

From the above equation, we obtain N ³ 2.5. Therefore, N ³ 3 since N is an

integer.

30
 Since, I1 = I2 = . . . = IN.

Therefore, IO = 2. 6
= N ⋅ I1
100 + 450 / N

The values of I1 for various values of N are given in Table

Table
N1 I1 (mA)
30 750
40 585
50 480
60 403
70 349

The base current required for saturation for a normal RTL is about 300 mA,
which means N can be taken as 70, which is very large.
(c) The relevant portion of the circuit is shown in Fig. Prob. 4.4(b). Here T3A
and T2B are in saturation, whereas T2A and T3B are cut-off. Neglecting the
base currents

3. 6 − 0. 2 − 0 . 2
IE2B = I C 3 A =
100
= 32 mA
VCC = 3.6 V

100 W 100 W

T2A T2B
IE2B
IC3A
A = 1 T3A T3B B = 0

Fig. Prob. 4.4(b)

4.5 (a) When all the inputs are HIGH the voltage at the point P will be Vp = 0.8 +
0.7 = 1.5 volts.
5 − 1. 5
∴ I1 = = 0. 7 mA
5
and IB = 0.7 – 0.16 = 0.54 mA
This will increase the fan-out to 17, but the noise margin D0 will be
reduced from 0.8 V to 0.2 V.

31
 (b) In this case VP = 0.8 + 0.7 ´ 3 = 2.9 V
\ I1 = 0.42 mA, and IB = 0.26 mA
This will reduce the fan-out to 6, but the noise margin D0 will be increased
to 1.4 V.
4.6 For a fan-out of 10,
0.82 ´ 10 + 2.182 = hFE ´ 0.4
or hFE » 26
4.7 The Fig. Prob. 4.7 shows the relevant portion of the circuit. The worst condi-
tion corresponds to the situation when the output transistor of one of the
driving gates is in saturation and all others are cut-off. Corresponding to this
the output voltage at Y is VCE,sat » 0.2 V, which means the input diodes of all
the load gates driven from this combination are conducting. Assuming all the
other inputs of load gates to be HIGH.
IL = 0.82 mA
Assuming T1 to be in saturation, the collector current of T1 is given by,
N¢ IL + MI¢1
where, N¢ is the fan-out with the wire-ANDed connection. This collector cur-
rent must be same as the collector current of the single gate driving N gates
which is given by
NIL + I¢1
\ NIL + I¢1 = N¢IL + MI¢1

VCC(5 V) VCC(5 V)
IL
I¢1 RC Y1 R
Y

T1 P1

VCC VCC
IL
RC I¢1 R
Y2
T2 P2

VCC VCC
IL
RC I¢1 R
YM
TM PN¢

M Gates wire-ANDed N¢ Load gates

Fig. Prob. 4.7

32
 or N¢ = N – (M – 1) I¢1/IL = N – (M – 1) 2. 182
0. 82
= N – 2.66 (M – 1)
4.8 When all the inputs are HIGH, the input diodes are non-conducting. If we
assume that the transistor T1 is in saturation, then
VP = VBE, sat + VD + VBE, sat = 0.8 + 0.7 + 0.8 = 2.3 V
The voltage at the collector of T1
= VCE, sat + VD + VBE, sat
= 0.2 + 0.7 + 0.8 = 1.7 V
Since the voltage at P is higher than the voltage at the collector of T1, IB1 can-
not exist, therefore, the assumption that T1 is in saturation is inconsistent.
Hence T1 is in active region. In fact when T1 is conducting, the voltage drop
across R2 will reverse-bias the C-B junction of T1 and therefore T1 will defi-
nitely be operating in active region.
4.9 If any input is LOW, the corresponding input diode conducts and therefore,
VP = 0.9 V, which keeps T1, D2, and T2 cut-off. Hence Y = 1.
If all the inputs are HIGH, the input diodes will be nonconducting. T1 will be
in active region and T2 in saturation region. Hence Y = 0. This shows that the
circuit operates as a NAND gate.
(a) When all the inputs are HIGH,
VP = VBE1 + VD + VBE3, sat
= 0.7 + 0.7 + 0.8 = 2.2 V
Here, VBE has been assumed to be 0.7 V in active region. Therefore,
VCC – VP = R1I1 + R2IB1
Also I1 = (1 + hFE) IB1

5 − 2. 2
IB1 = × 10 3 = 49. 78 µA
1. 75 × 31 + 2

V BE 2 , sat
and I1 = 1.543 mA, I2 = = 0.16 mA,
5
IB2 = I1 – I2 = 1.543 – 0.16 = 1.383 mA
VCC − V D − VCE,sat
Standard load =
R1 + R 2

5 − 0. 7 − 0. 2
= = 1. 093 mA
1. 75 + 2

VCC − VCE , sat

\ IC2 = N ⋅ I L + = 1. 093 N + 2.182
RC

33
 For T2 to be in saturation, IC2 £ hFE IB2
or, 1.093 N + 2.182 £ 30 ´ 1.383
or, N < 36
Therefore, the fan-out of this gate is 35 which is much higher than the fan-
out of the DTL gate of Fig. 4.12.
(b) Noise margins
D1 = 0.5 + 0.6 + 0.5 – 0.9 = 0.7 V
D0 = –V(1) + (VP – VDg)
= – 5 + (2.2 – 0.6) = – 3.4 V
(c) When the output is LOW, the power
P (0) = (I1 + I¢1) VCC
= (1.543 + 2.182) ´ 5
= 18.625 mW
When the output is HIGH, the power
P (1) = I1 ´ Vcc = 1.093 ´ 5 = 5.465 mW

P ( 0 ) + P (1)
The average power Pav =
2

18. 625 + 5. 465

= = 12 . 045 mW
2
4.10 (a) When at least one of the inputs is LOW,
VP = V (0) + VD = 0.2 + 0.7 = 0.9 V
Corresponding to this T1 and T2 will be nonconducting. When all the inputs
are HIGH, T1 will be conducting in active region, Zener will be in the
breakdown region and T2 in saturation. Therefore,
VP = VBE, active + VZ + VBE, sat
= 0.7 + 6.9 + 0.8 = 8.4 V
The 1 level noise margin = D1 = Vg + VZ + Vg – VP
= 0.5 + 6.9 + 0.5 – 0.9
=7V
The 0 level noise margin = D0 = – [V (1) – (VP – VDg)]
= – [15 – (8.4 – 0.6)]
= – 7.2 V
(b) When all the inputs are HIGH, VP = 8.4 V. Writing KVL from VCC to VP,
VCC – VP = R1 (1 + hFE) IB1 + R2 IB1

34
 VCC − V P 15 − 8. 4
or, IB1 = =
R1 (1 + h FE ) + R 2 3 ( 41) + 12
= 0.0489 mA
The current through Zener diode, I1 = 41 ´ 0.0489 = 2.004 mA
\ IB2 = I1 – I2 = 2.004 – 0.16 = 1.844 mA

The current through RC = 14. 8 = 0. 9867 mA

15
The load current IL = 0.95 mA
\ IC2 = 0.9867 + 0.95 N £ 40 ´ 1.844
or, N £ 76
(c) P(0) = (I1 + I¢1) ´ VCC
= (2.004 + 0.9867) ´ 15 = 44.86 mW
P(1) = I1 ´ VCC = 0.94 ´ 15 = 14.1 mW
\ Pav = 29.48 mW
4.11 IL = 0.94 mA, I¢1 = 0.9867 mA
N¢ = N – (M – 1) I¢1/IL
= N – 1.03 (M – 1)
4.12 The noise margins depend upon temperature because the voltage across a
conducting diode and VBE are temperature dependent. The input diode and the
base-emitter junction of T1 are in polarity opposition, therefore, the tempera-
ture sensitivities of these two junctions cancel. Therefore, the temperature
sensitivity of the circuit depends on the temperature sensitivities of D2 and the
base-emitter junction of T2. In HTL, D2 is replaced by the Zener diode. Since
the temperature sensitivity of a Zener diode is positive whereas for a forward-
biased diode it is negative, therefore, the temperature sensitivities of Z and the
base-emitter junction of T2 cancel (their magnitudes are of the same order).
Hence the temperature sensitivity of the HTL gate is significantly better than
that of the DTL gate.
4.13 (a) When the output is LOW.
Base-collector junction of T1 is forward-biased T2 and T3 are in saturation.
Therefore, VB1 = 0.7 + 0.8 + 0.8 = 2.3 V

5 − 2. 3
Current through RB1 = = 0 . 675 mA
4
VC2 = 0.8 + 0.2 = 1V

5 −1
Current through RC2 = = 2. 857 mA
1. 4
35
 Since, T4 and D are cut-off, therefore, IC4 = 0
Therefore,
ICC(0) = 0.675 + 2.857
= 3.532 mA
(b) At least one of the inputs is LOW.
\ VB1 = 0.2 + 0.7 = 0.9
T2, T3 and T4 are cut-off
5 − 0. 9
\ ICC1 = Current through RB1 =
4
= 1.025 mA
(c) The total current will be sum of current through RB1 (as given in (b) part
above) and given in Eqs. 4.10 and 4.11
= 1.025 + 41.36
= 42.385 mA
4.14 The current I remains same and it does not affect the fan-out of the gate G1.
4.15 (a) If RC4 = 0, the change in output from logic 0 to logic 1 will be faster. Since
T3 does not turn off (because of storage time) as quickly as T4 turns on,
therefore, both T3 and T4 will be conducting simultaneously for some time
which will cause almost short circuiting of the VCC supply.
(b) When the output is in LOW state, VB4 = 1 V which makes VBE4 = 0.8 V if
the diode D is not present. This means T4 will be in saturation and its
collector current would be

VCC − VCE 4 , sat − VCE 3, sat

IC4 =
100

5 − 0. 2 − 0. 2
= = 46 mA
100
which is very large and will increase significantly the power dissipation.
Moreover, it is simply a wastage of power.
(c) (i) When output is in LOW state, the shorting of output to ground will not
have any effect.
(ii) When output is in HIGH state, the relevant portion of the circuit with
output shorted to ground is shown in Fig. Prob. 4.15. The base current
and the collector current of T4 will become

VCC − V BE 4 ,sat − V D
IB4 =
RC 2

5 − 0 . 8 − 0. 7
= = 2. 5 mA
1. 4

36
 VCC − VCE 4 ,sat − V D
and IC4 =
RC 4

5 − 0. 2 − 0. 7
= = 41 mA
100
\ Is = IC4 + IB4
= 41 + 2.5 = 43.5 mA
This large current will continuously be drawn from the supply as long as at
least one of the inputs is LOW. This will damage the transistor T4 and the
diode D.
VCC = 5V

RC4 = 100 kW
RC2 = 1.4 kW
IC4
T4
IB4
C2 D
E2
C3 Is
E3

Fig. Prob. 4.15

4.16 Let the output transistor T3 of one gate is in saturation, while that of the other
gate is cut-off. The voltage at Y will be LOW, which will make the transistor
T4 of the gate whose T3 is cut-off to conduct through T3 of the other gate which
is in saturation. The corresponding current drawn from the power supply will
be IC4 + IB4 = 41.4 mA. This continuous current will damage these transistors.
When both the outputs are HIGH or LOW, the currents drawn from the
supply will be same as the currents without this connection.
4.17 The circuit is shown in Fig. Prob. 4.17.
VCC − VOH (5 − 2. 4) × 10 3
RC(max) = = kW
I OH + 8 I IH 250 + 8 × 40
= 4.56 kW
VCC − VOL 5 − 0. 4
RC(min) = = = 1. 44 kW
I OL + 8 I IL 16 − 8 × 1. 6
Therefore, 1.44kW < RC < 4.56 kW
4.18 The relevant portion of the circuit is given in Fig. Prob. 4.18.
(i) When the output Y = 1,
VCC – (5 IOH + 6 IIH) RC ³ VOH

37
which gives
VCC − VOH ( 5 − 2 . 4 ) × 10 3
RC(max) = = kW = 1. 74 kW
5 I OH + 6 I IH 5 × 250 + 6 × 40

VCC = +5 V

RC

IIH

IOH

Output circuit
of open-collector
gate

Fig. Prob. 4.17 Load gates

VCC = 5 V

RC IIH
IOL
IIL
IIH
IOH Y
IIL
IIH
IOH
IIL
IIH
IOH
IIL
IIH
IOH
IIL
IIH
IOH
IIL
Fig. Prob. 4.18

38
 (ii) When the output Y = 0, it is assumed that only one of the driving gates has
its output transistor in saturation while the output transistors of all the other
gates are cut-off.

VCC − VOL
£ IOL + NIIL
RC

which gives

VCC − VOL
RC(min) =
I OL + NI IL

5 − 0. 4
= ≈ 0. 72 kW
16 − 6 × 1. 6
Therefore, RC should be between 0.72 kW and 1.74 kW. A value of RC = 1 kW
is reasonable.
4.19 Let us assume a supply voltage VCC = + 5V and corresponding VOH = 2.4 V

( 5 − 2. 4 ) × 10 3
\ RC(max) = ≈ 1. 28 kW
7 × 250 + 7 × 40

5 − 0. 4
and RC(min) = ≈ 0.159 kW
40 − 7 × 1. 6
Therefore, 0.159kW < RC < 1.28 kW
4.20 (a) No (b) No (c) No (d) Yes

VCC = +5 V VCC = +10 V

10 V, 30 A
Lamp
A 7407

Fig. Prob. 4.20

7407 is an open-collector non-inverting buffer with VOH = 30V (maximum),

which means a lamp load along with the necessary supply voltage may be
connected as shown in Fig. Prob. 4.20.
4.21 Let us take ALS devices driving other devices.
(i) ALS driving standard devices
IOH (ALS) = – 400 mA
IOL (ALS) = 8 mA (74 series)
IIH (Standard) = 40 mA
IIL (Standard) = – 1.6 mA

39
 Here, – IOH (ALS) = 10 ´ IIH (Standard)
and – IOL (ALS) = 5 ´ IIL (Standard)
This means, when the output is LOW, the fan-out is 5, whereas it is 10
when the output is HIGH. Therefore, the fan-out is 5
(ii) ALS driving ALS
IIH (ALS) = 20 mA
IIL (ALS) = – 0.1 mA
Which gives a fan-out of 20 when the output is HIGH and 80 when it is
LOW. Therefore, the fan-out is 20.
Similarly, the complete table can be verified.
4.22 Case I
Let T2 be cut-off. Then the output circuit will appear as shown in Fig.
Prob. 4.22(a), whose equivalent circuit is shown in Fig. Prob. 4.22(b).

P P
C4
RC2 RC2
hFE I
T4 B4

Vn Vn I E4
Y Y
RE4 RE4

Q Q
(a) (b)
Fig. Prob. 4.22
From the equivalent circuit, we obtain
R E 4 (1 + h FE )
(a) VYQ = V
R C 2 + (1 + h FE ) R E 4 n
1. 5 (101)
= V
0. 3 + (101) (1. 5) n
= 0.998 Vn
(b) VYP = – (Vn – VYQ) = – 0.002 Vn
Therefore, if the terminal P is grounded, the noise voltage present in the
output is negligibly small.
Case II
Let T2 be conducting and T1 be cut-off.
(a) The noise voltage at the collector of T2 = the noise voltage at the base of
T4.
= 1.18 Vn = 0. 797 Vn .
1.18 + 0. 3
Since T4 is operating as an emitter-follower, therefore,
VYQ = 0.797 Vn
(b) VYP = – (Vn – 0.797 Vn) = – 0.203 Vn

40
 This again shows that the noise voltage is very small between Y and P
and hence the terminal P is grounded.
4.23 (a) The 5.2 V supply will appear across RE4 or RE3 and no damage is caused to
the supply and the circuit.
(b) The 5.2 V supply voltage will appear across the output transistor T4 or T3.
Also 5.2 V supply gets applied to their bases through RC2 and RC1 respec-
tively. Therefore, the output transistor will burn out.
4.24 In a TTL gate, when the output changes from V(0) to V(1), a current spike of
41.4 mA is produced, whereas in the case of ECL the change in current is
negligibly small when the output changes from LOW to HIGH and vice-versa.
4.25 Let A = B = C = 0, D = 1, and E = 0
Therefore, Y1 = 0 and Y2 = 1.
Corresponding to this T4 of G1 is acting as an emitter follower while that of
G2 is acting as a diode. The relevant portions of the circuits are shown in Fig.
Prob. 4.25. In this when Y1 and Y2 are connected together, the voltage at the
output terminal will be equal to – 0.75 V (i.e., the voltage across T4 acting as
a diode). Consequently T4 goes to cut-off. Similarly, when Y1 = 1 and Y2 = 0
identical situation will prevail making the output 1. When Y1 and Y2 both are
same, the output will be equal to Y1 = Y2. This confirms that OR operation is
performed when the outputs are connected in wired logic. Similarly, it can be
proved for all the other cases.
VCC = 0 VCC = 0

RC2 RC2

T4 T4
(-0.85 V)
Y1 Y2
RE4 (-1.55 V) (-0.75 V)
RE4

-5.2 V -5.2 V
Fig. Prob. 4.25
4.26 The output logic levels of ECL, input/output logic levels of MC10H125 IC,
and the input logic levels of TTL are shown in Fig. Prob. 4.26
2.5V VOH 2V VIH
0.5V VOL 0.8 VIL
–0.9V VOH
–1.13V VIH
–1.48V VIL
–1.7V VOL
ECL MC10H125 TTL
Translator
(a) Output logic level (b) Input/output logic (c) Input logic level
voltages of ECL level voltages of voltages of TTL
Translator
Fig. Prob. 4.26

41
 From the logic levels, we observe,
VIH (Translator) < VOH (ECL)
VIL (Translator) > VOL (ECL)
which shows that the input of MC10H125 IC is ECL compatible.
Similarly,
VIH (TTL) < VOH (Translator)
VIL (TTL) > VOL (Translator)
which shows that the output of the translator is compatible with TTL.
4.27 The output Y of ECL NOR gate is Y = A + B
The output of the Translator circuit is Y and the output of TTL Inverter will
be Y = Y.

A Y
B Y
Y
ECL MC10H125 TTL
Translator
Fig. Prob. 4.27

The complete circuit is shown in the above figure.

4.28 (a) Consider the NMOS inverters shown in Fig. 4.25. If the output accidently
gets shorted, large current from VDD will continuously flow through the
load transistor T2 which may damage the load transistor.
(b) Consider the CMOS inverter of Fig. 3.33. When T1 is ON, the output
voltage is LOW (» 0V). Now if the output gets shorted to ground, it does
not cause any problem. On the other hand when Vi is LOW, T1 is cut-off,
and if the output gets shorted to ground, whole of VCC will appear across
T2 which is conducting. This will cause a relatively very high current to
flow through T2 which may damage it, since T2 is not meant to carry such
large currents. The normal current through T1 and T2 is extremely small
being the OFF current of either T1 or T2.
4.29 Its operation is given below
Inputs State of Output
A B T1 T2 T3 T4 Y
0 0 OFF OFF ON ON VCC
0 VCC ON OFF OFF ON 0
VCC 0 OFF ON ON OFF 0
VCC VCC ON ON OFF OFF 0

42
4.30 The fan-out is given below.
TTL/CMOS 74HC 74HCT 74AC 74ACT
54/74 400 400 400 400
54H/74H 500 500 500 500
54L/74L 200 200 200 200
54S/74S 1000 1000 1000 1000
54LS/74LS 4000 4000 4000 4000
54AS/74AS 2000 2000 2000 2000
54ALS/74ALS 400 400 400 400

4.31
54/74 54H/74H 54L/ 54S/ 54LS/ 54AS/ 54ALS/
74L 74S 74LS 74AS 74ALS
(a) 74HC/74HCT 2 2 21 2 11 8 40
(b) 74 AC/74 ACT 15 12 133 12 66 48 240

4.32 When output is HIGH, it can drive a total of up to 1200 gates.

When output is LOW, it can drive 20 74AS gates requiring 10 mA of current.
The remaining 14 mA of current can drive 140 74ALS gates. Therefore, max-
imum possible number of ALS gates which can be driven is 140.
4.33 The output logic levels of CMOS and the input logic levels of MC10H124
TTL-to-ECL translator are given in Fig. Prob. 4.33.

VOH 3.76V
VIH 2V
VIL 0.8V
VOL 0.37V
CMOS MC10H124
translator
(a) (b)
Fig. Prob. 4.33

From these logic levels, we observe,

VIH (Translator) < VOH (CMOS)
VIL (Translator) > VOL (CMOS)
which shows that the input of the translator is compatible with CMOS. Since
the output of the translator is compatible with ECL, therefore, CMOS-to-ECL
interfacing is possible using TTL-to-ECL translator.
4.34 The output logic levels of MC10H125 translator and the input logic levels of
CMOS (74HCT & 74 ACT) are shown in Fig. Prob. 4.34.

43
 VOH 2.5V
VIH 2V
VIL 0.8V
VOL 0.5V
MC10H125 CMOS
Translator (74HCT & 74ACT)
(a) (b)
Fig. Prob. 4.34

From these logic levels, we observe,

VIH (CMOS) < VOH (Translator)
VIL (CMOS) > VOL (Translator)
Therefore, the output of the translator is compatible with these CMOS devices.
Since the input of the translator is compatible with ECL, therefore, ECL-to-
CMOS interfacing is possible.
For CMOS 74 HC, and 74 AC series
VIL = 1.35V
VIH = 3.85V
and for CMOS 74 C series
VIL = 1.5V
VIH = 3.5V
For these CMOS ICs, VIL (CMOS) > VOL Translator
but VIH (CMOS) < VOH (Translator)
Therefore, a resistance R and VCC are required to be connected to pull up the
voltage at P corresponding to VOH (Translator)

VCC
R
P

MC10H125 CMOS
Translator
(c)
Fig. Prob. 4.34

44
 CHAPTER 5
5.1 Let S1 and S2 be the two switches. The circuit diagram of the system is shown
in Fig. Prob. 5.1(a):

0 1 0 1
L
S1 S2

ON = 1
OFF = 0
Bulb
Supply
Fig. Prob. 5.1(a)
(a) The truth table is given below:
S1 S2 L
0 0 0
0 1 1
1 0 1
1 1 0

(b) The logic equation is

L = S 1 S2 + S1 S 2
(c) The AND-OR realization is given in Fig. Prob. 5.1(b):
S1
S2

Fig. Prob. 5.1(b)

(d) Replace each of the AND gates and the OR gate in the above figure by
NAND gates. The resulting circuit will be NAND-NAND realization.

5.2 (a) Inputs Output

A B C D f
0 0 0 0 0
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 0
0 1 0 1 1
0 1 1 0 1
(Contd.)
45
 (Contd.)
Inputs Output
A B C D f
0 1 1 1 1
1 0 0 0 0
1 0 0 1 0
1 0 1 0 0
1 0 1 1 0
1 1 0 0 0
1 1 0 1 1
1 1 1 0 1
1 1 1 1 1

(b) The K-map is given in Fig. Prob. 5.2.

The simplified expression is f = BC + BD
AB
CD 00 01 11 10
B
00
C
01 1 1 BD
f
11 1 1
B
10 1 1 BC (b)
D
(a)
Fig. Prob. 5.2

5.3 (a) f1 = (A + B + C + D ) ( A + B + C + D) ( A + B + C + D)
(A + B + C + D ) (A + B + C + D ) (A + B + C + D)
(A + B + C + D) ( A + B + C + D) ( A + B + C + D )
f2 = (A + B + C + D) (A + B + C + D ) (A + B + C + D )
(A + B + C + D ) (A + B + C + D) (A + B + C + D)
(A + B + C + D) (A + B + C + D) (A + B + C + D)
(b) The K-maps for f1 and f2 are given in Fig. Prob. 5.3(a) and (b) respectively.
The minimized expressions are:
AB AB
CD 00 01 11 10 CD 00 01 11 10
00 0 0 0 00 0

01 0 0 01 0 0 0

11 0 0 11 0 0 0

10 0 0 10 0 0
(a) (b)
Fig. Prob. 5.3

46
 f1 = ( B + C + D) ( A + B + C) ( A + B + D) (A + B + D ) (A + B + C )
f2 = (A + C ) (A + B) ( A + C + D ) (B + D )
(c) The OR-AND realizations are shown in Fig. Prob. 5.3(c) and (d) for f1 and
f2 respectively.

B A
C
D C

A
B A
C
B
A f2
B f1
D
B
A
B D
D
A A
B C
C D
(c) (d)
Fig. Prob. 5.3
(d) Replace all the AND and OR gates in figures (A) and (B) by NOR gates to
obtain realizations using only NOR gates.
5.4
(a)

A
B
C
D

B
C

B f
D

A
D

A
B
Fig. Prob. 5.4(a)

47
 (b) A
B
C
D

A
B
C

A
B
D

A
B
D
Fig. Prob. 5.4(b)
(c) Realization for (a) requires
7400 – 1
7420 – 1/2
7430 – 1
a total of three chips.
Realization for (b) requires
7427 – 1
74260 – 1
a total of only two chips.
5.5 (a)
7410
A
C

A
C Y
D

B
(b)
A
B
C

A
B Y
C 1/
3 7427
B
C
D
7427
Fig. Prob. 5.5
48
 (c) Realization of (a) requires only one chip whereas (b) requires two chips.
5.6
3/4 7402
A
D

C
f
D
B
Fig. Prob. 5.6
5.7 (a)
AB
CD
00 01 11 10
00 1 1 A

01 1 1

11 1 1 1 1

10 1 1 1 1

C
Fig. Prob. 5.7(a)
(b) f = å m (2, 3, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
(c) f = A + C

Fig. Prob. 5.7(b)

5.8 (a) Figure Prob. 5.8 (i) below gives the K-map. Using offset adjacencies shown
in the K-map, the expression for f1 can be written as
f1 = (C ¤ D) (A ¤ B) + (C ⊕ D) (A ⊕ B)
= (A ⊕ B) ¤ (C ⊕ D)

AB C D (A ¤ B)
CD
00 01 11 10
00 1 1 C D (A Å B)

01 1 1
CD (A ¤ B)
11 1 1
C D (A Å B)
10 1 1

Fig. Prob. 5.8(i)

49
 A
B

C f1

D
Logic 1
Fig. Prob. 5.8(ii)

Its realization using EX-OR gates is given in Fig. Prob. 5.8(ii). This real-
ization requires only one 7486 IC chip.
(b) Its K-map is given in Fig. Prob. 5.8(iii)
The minimized expression is
f2 = A B + AB D + ACD
The realization using NAND gates is given in Fig. Pro. 5.8(iv). This re-
quires one 7410 chip and one gate of 7400 chip.

AB A
CD 00 01 11 10
B
00 1 1

01 1 A
B f2
D
11 1 1 1

10 1 1 A
C
D
(iii) (iv)
Fig. Prob. 5.8
5.9 Truth table of BCD-to-Excess-3 code converter is given below.
BCD Excess-3
D C B A E3 E2 E1 E0
0 0 0 0 0 0 1 1
0 0 0 1 0 1 0 0
0 0 1 0 0 1 0 1
0 0 1 1 0 1 1 0
0 1 0 0 0 1 1 1
0 1 0 1 1 0 0 0
0 1 1 0 1 0 0 1
0 1 1 1 1 0 1 0
1 0 0 0 1 0 1 1
1 0 0 1 1 1 0 0

Here only ten out of sixteen combinations are used and the other six are
taken as don’t-care conditions. The K-maps for the outputs E0, E1, E2 and
E3 are given in Fig. Prob. 5.9. The minimized expressions are:
E0 = A
50
 DC DC
BA 00 01 11 10 BA 00 01 11 10
00 1 1 ´ 1 00 1 1 ´ 1

01 0 0 ´ 0 01 0 0 ´ 0

11 0 0 ´ ´ 11 1 1 ´ ´

10 1 1 ´ ´ 10 0 0 ´ ´
E0 E1
(a) (b)

DC DC
BA 00 01 11 10 BA 00 01 11 10
00 0 1 ´ 0 00 0 0 ´ 1

01 1 0 ´ 1 01 0 1 ´ 1

11 1 0 ´ ´ 11 0 1 ´ ´

10 1 0 ´ ´ 10 0 1 ´ ´
E2 E3
(c) (d)
Fig. Prob. 5.9
E1 = BA + B A
E2 = CB A + C A + C B
E3 = D + CA + CB
The circuit can be drawn using NAND gates.
5.10 Truth table of Excess-3-to-BCD converter can be prepared using the truthtable
of Prob. 5.9. The K-maps can then be prepared and minimized. The minimized
expressions are given below.
A = E0
B = E1 E 0 + E1 E 0
C = E 2 E 1 + E2 E1 E0 + E3 E1 E 0
D = E3 E2 + E3 E1 E0
The circuit can now be drawn using NAND gates.
5.11 (a) The K-map is shown in Fig. Prob. 5.11(a). The minimized expression is
f1 = C D = C + D
(b) The K-map is shown in Fig. Prob. 5.11(b). The minimized expression is
f 2 = ( A + B + D) ( B + C + D ) ( A + C )
(c) The K-map is shown in Fig. Prob. 5.11(c). The minimized expression is
f 3 = ( A + B + C + D ) ( B + C + D) ( A + B + C ) ( A + C + D )
The circuits for f1, f2, and f3 can be drawn using NOR gates.
51
 AB AB
CD 00 01 11 10 CD 00 01 11 10
00 00 0

01 0 0 0 0 01 0 0

11 0 0 0 0 11 0 0

10 0 0 0 0 10 0 0 0

(a) (b)
AB
CD 00 01 11 10
00 0 0

01 0

11 0

10 0 0

(c)
Fig. Prob. 5.11
5.12 The K-map for f1 is shown in Fig. Prob. 5.12 and the minimized expression is

f 1 = A BE + AC E + ABD + BC + AB CD E
This can be realized using NAND gates.
Similarly, the minimized expression for f2 is

f 2 = C E + ABD + ADE + AD E + B CE + CDE + AB E

which can be realized using NAND gates.

A = 0 A = 1 AB CDE AC E
BC BC
DE 00 01 11 10 DE 00 01 11 10
00 1 00 1 1

01 1 1 01 1

11 1 1 11 1 1 ABD
10 1 10 1 1 1

A BE BC

Fig. Prob. 5.12

5.13 (a) Its K-map is given in Fig. Prob. 513(a).

52
 (a) AB
CD 00 01 11 10
00 0

01 1 1 0 1

11 0 0

10 1 1 0 0
Fig. Prob. 5.13(a)
The minimized expression is
Y = AC D + B C D + ACD
A
C
D

B
C Y
D

A
C
D
Fig. Prob. 5.13(b)
(b) The K-map is given in Fig. 5.18 of the book and Y = C D + CD
(c) Realization of part (a) requires 2 IC chips (7410) whereas for part (b) one
IC chip (7400) only is required.
C
D

C
D
Fig. Prob. 5.13(c)

5.14 (a) Figure Prob. 5.14(a) and (b) show the K-maps of f1 for NAND and NOR
realizations respectively. The minimized expressions are
f1 = ABC + CD + BD + AD (SOP)
and f1 = ( A + B + C ) (C + D) ( B + D) ( A + D) (POS)
Circuits using NAND and NOR gates can be designed using the above
expressions.
(b) Similar to part (a), the minimized expressions are obtained which are given
below.
f2 = A C D + BC + AB (SOP)

53
and f2 = ( A + B ) ( B + D ) ( B + C ) ( A + C ) (POS)
These equations can be used to design circuits with NAND and NOR gates.

AB AB
CD
CD 00 01 11 10 00 01 11 10

00 1 00 0 0 0

01 1 1 ´ 1 01 ´

11 1 1 1 11 0

10 ´ 10 ´ 0 0 0

(a) (b)
Fig. Prob. 5.14

5.15 Its K-map and circuit realization are given in Fig. Prob. 5.15.
(a)
A C (B Å D)
AB
CD 00 01 11 10
A
00 1 1
B
01 1 1

11 D
f1
10
C
A C (B ¤ D)

(b)

B
AB
CD 00 01 11 10 C
00 1
A
01 1 1 1

11 1 f2
A
10 1 1 1
C
A(C Å D)
D
A (B Å C)

54
 (c)
AB
CD 00 01 11 10
A
00 1
C
01 1
A C (BÅD) f3
11 1
B
10 1
D

A C(B Å D)
Fig. Prob. 5.15
5.16 Its truth table is given in Table Prob. 5.16.
Table Prob. 5.16
4-bit word Odd parity bit Even parity bit
A B C D PO PE
0 0 0 0 1 0
0 0 0 1 0 1
0 0 1 0 0 1
0 0 1 1 1 0
0 1 0 0 0 1
0 1 0 1 1 0
0 1 1 0 1 0
0 1 1 1 0 1
1 0 0 0 0 1
1 0 0 1 1 0
1 0 1 0 1 0
1 0 1 1 0 1
1 1 0 0 1 0
1 1 0 1 0 1
1 1 1 0 0 1
1 1 1 1 1 0
The K-map for Po is given in Fig. Prob. 5.16(a), from which Po is obtained as
Po = AC (B ¤ D) + A C (B Å D) + A C (B Å D) + AC (B ¤ D)
= (A Å C) ¤ (B + D)
Its realization using EX-OR and EX-NOR gates is given in Fig. Prob. 5.16(b).
AB
CD 00 01 11 10
00 1 0 1 0 A
C
01 0 1 0 1
Po
11 1 0 1 0
B
10 0 1 0 1
D
(a) (b)
Fig. Prob. 5.16
55
5.17 From the truthtable given in Prob. 5.16, K-map is prepared and the circuit is
designed. These are given in Fig. Prob. 5.17.
PE = A ⊕ B ⊕ C ⊕ D

AB
CD 00 01 11 10
A
00 1 1
B
01 1 1

11 1 1 C

10 1 1 PE
D
(a) (b)
Fig. Prob. 5.17
5.18 (a) The K-map using 1’s is given in Fig. Prob. 5.18(a). The minimized expres-
sion for f1 is
f 1 = ABC D E + ABCD F + CEF + A B C DEF
The circuit for f1 can be realized using NAND gates.
Similarly, we can minimize using 0’s which will lead to a circuit realizable
by NOR gates.
(b) The K-map using 0’s is given in Fig. Prob. 5.18(b). The minimized expres-
sion for f2 is
f2 = (A + B + C + D + E + F ) ( A + B + D + E + F)
( A + B + C + E + F ) (A + C + D + E + F)
(A + B + C + E + F) (A + B + C + E + F)
(A + B + C + E + F) (A + B + C + D )
(A + B + D + E) (B + C + D + E)
(B + C + D + F ) (A + B + C + D)
The circuit for f2 can be realized using NOR gates. Similarly, we can minimize
the function using 1s which will lead to a circuit realizable by NAND gates.
5.19 Let the augend, addend, and the carry inputs to the full-adder be An, Bn, and
Cn – 1 respectively and Sn, and Cn be the sum and carry outputs respectively.
(a) An and Bn are applied at the two inputs of first half-adder HA – 1.
Its outputs are S1 (Sum) and C1 (Carry). Its truth table is given in Table
Prob. 5.19.
Table Prob. 5.19(a)
An Bn S1 C1
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

56
 A 0 1
B

CD CD
EF 00 01 11 10 EF 00 01 11 10
00 00

01 1 1 01 1 1
0
11 11

10 1 10

AB CDEF

CD
CEF
CD
EF 00 01 11 10 EF 00 01 11 10
00 00

01 1 1 01 1 1
1
11 1 1 11

10 1 10

ABC D E ABCDF
Fig. Prob. 5.18(a)
A
B 0 1
CD CD
EF 00 01 11 10 EF 00 01 11 10
00 0 0 0 00 0 0

01 0 0 01 0
0
11 0 11 0 0

10 0 10 0

CD CD
EF 00 01 11 10 EF 00 01 11 10

00 0 0 00

01 0 0 0 01
1
11 0 11

10 0 0 10

Fig. Prob. 5.18(b)

57
 An Bn Cn – 1

HA – 1

C1 S1

HA – 2

C2
S2 = Sn

Cn
Fig. Prob 5.19(a)

Truth table of the full-adder using input variables S1, C1, and Cn – 1 is given
below:
Table Prob. 5.19(b)
C1 S1 Cn – 1 Cn Sn
0 0 0 0 0
0 1 0 0 1
1 0 0 1 0
0 0 1 0 1
0 1 1 1 0
1 0 1 1 1
K-maps for Cn and Sn are shown below:
C 1 S1
Cn – 1 C1 S1
00 01 11 10 Cn – 1 00 01 11 10
0 0 0 ´ 1
0 0 1 ´ 0
1 0 1 ´ 1
1 1 0 ´ 1
K-map for Cn K-map for Sn

Cn = C1 + S1 × Cn – 1 Sn = S1 C n - 1 + S 1 Cn – 1
= C1 + C2 = S1 Å Cn – 1
Sn and Cn are generated using HA –2 and an OR gate as shown in the block
diagram.

58
 (b) EX–OR(1)
An S1 EX–OR(2)
Bn S2 = Sn

C2
C1
AND-2
Cn
AND–1 OR
Cn–1
Fig. Prob. 5.19(b)

5.20 Propagation delay time for Sn

= tpd [EX-OR(1)] + tpd [EX –OR(2)]
= 20 + 20 = 40 ns.
Propagation dealy time for Cn
= tpd [EX-OR(1) + tpd (AND-2) + tpd(OR)
= 20 + 10 + 10 = 40 ns.
Since the propagation delay time (tpd) of AND–1 is less than the tpd of
EX-OR(1), therefore, it is not counted.
5.21 f (A, B, C, D) = p M(2, 7, 8, 9, 10, 12)
= S m (0, 1, 3, 4, 5, 6, 11, 13, 14, 15)

Table (a) Grouping of minterms according to number of 1’s.

Group Minterm Variables Check for inclusion
A B C D in groups of 2
0 0 0 0 0 0 ü
1 1 0 0 0 1 ü
4 0 1 0 0 ü
3 0 0 1 1 ü
2 5 0 1 0 1 ü
6 0 1 1 0 ü
11 1 0 1 1 ü
3 13 1 1 0 1 ü
14 1 1 1 0 ü
4 15 1 1 1 1 ü

Table (b) Grouping of two minterms

Group Minterms Variables Check for inclusion
A B C D in groups of 4
0 0, 1 0 0 0 — ü
0, 4 0 — 0 0 ü
1, 3 0 0 — 1
1, 5 0 — 0 1 ü
(Contd.)

59
 (Contd.)
Group Minterms Variables Check for inclusion
A B C D in group of 4
1 4,5 0 1 0 — ü
4, 6 0 1 — 0
3, 11 — 0 1 1
2 5,13 — 1 0 1
6, 14 — 1 1 0
11, 15 1 — 1 1
3 13, 15 1 1 — 1
14, 15 1 1 1 —

Table (c) Grouping of 4 minterms

Group Minterms Variables

A B C D
0 0, 1, 4, 5 0 — 0 —
0, 4, 1, 5 0 — 0 —

Table (d) PI table

PI Decimal Minterms
terms numbers 0 1 3 4 5 6 11 13 14 15
AC ü 0, 1, 4, 5 Ä ´ ´ ´
AB Dü 1, 3 ´ ´
A B Dü 4, 6 ´ ´
B CDü 3, 11 ´ ´
BC Dü 5,13 ´ ´
BC D ü 6, 14 ´ ´
ACD ü 11, 15 ´ ´
ABD 13, 15 ´ ´
ABC 14, 15 ´ ´
ü ü ü ü ü ü ü

From the PI table, we see that the column for minterms 0 contains only one
´, therefore, A C is an essential prime-implicant. All the other columns con-
tain 2 or more Xs. Therefore, starting from the prime-implicant A B D, we see
the minterms that are covered by each prime-implicant and find the minimum
number of prime-implicants that will cover all the minterms. Depending upon
the prime-implicants selected above, the minimized function is
f (A, B, C, D) = AC + ABD + ABD + B CD + BC D + BCD + ACD
There can be other options also.

60
5.22 f (A, B, C, D) = Sm (1, 3, 5, 8, 9, 11, 15) + d(2, 13)

Table (a) Grouping of minterms/don’t care terms according to number of 1’s.

Group Minterm/ Variables Check for inclusion

don’t care term A B C D in group of 2
1 0 0 0 1 ü
1 2* 0 0 1 0 ü
8 1 0 0 0 ü
3 0 0 1 1 ü
2 5 0 1 0 1 ü
9 1 0 0 1 ü
11 1 0 1 1 ü
3 13* 1 1 0 1 ü
4 15 1 1 1 1 ü

Table (b) Grouping of 2 minterms/don’t care terms

Group Minterms/ Variables Check for inclusion

don’t care terms A B C D in group of 4
1, 3 0 0 — 1 ü
1, 5 0 — 0 1 ü
1 1, 9 — 0 0 1 ü
2*, 3 0 0 1 —
8, 9 1 0 0 —
3, 11 — 0 1 1 ü
5, 13* — 1 0 1 ü
2 9, 11 1 0 — 1 ü
9, 13* 1 — 0 1 ü
3 11, 15 1 — 1 1 ü
13, 15 1 1 — 1 ü

Table (c) Grouping of 4 minterms/don’t care terms

Group Minterms/ Variables

don’t care terms A B C D
1, 3, 9, 11 — 0 — 1
1 1, 5, 9, 13* — — 0 1
1, 9, 3, 11 — 0 — 1
1, 9, 5, 13* — — 0 1
9, 11, 13*, 15 1 — — 1
2 9, 13*, 11, 15 1 — — 1

There are a total of 5 prime-implicants BD , CD, and AD from Table (c) and
AB C and AB C from Table (b).

61
 Table (d) PI Table

PI Decimal Minterms/don’t care terms

terms numbers 1 2* 3 5 8 9 11 13* 15
BD 1, 3, 9, 11 ´ ´ ´ ´
CD 1, 5, 9, 13* ü ´ Ä ´ ´
AD 9, 11, 13*, 15 ü ´ ´ ´ Ä
ABC 2*, 3 ´ ´
AB C 8, 9 ü Ä ´
ü ü ü

The essential prime- implicants are: CD, AD, and ABC . Except the minterm
3 all the other minterms have heen covered by the essential prime-implicatns.
Therefore, B D is to be included in the minimized expression. The minimized
function is
f (A, B, C, D) = B D + C D + AD + AB C .
5.23 f (A, B, C, D, E) = Sm (8, 9, 10, 11, 13, 15, 16, 18 , 21, 24, 25, 26, 27, 30, 31)

Table (a) Grouping of minterms according to number of 1’s

Group Minterm Variables Check for inclusion

A B C D E in group of 2
1 8 0 1 0 0 0 ü
16 1 0 0 0 0 ü
9 0 1 0 0 1 ü
2 10 0 1 0 1 0 ü
18 1 0 0 1 0 ü
24 1 1 0 0 0 ü
11 0 1 0 1 1 ü
13 0 1 1 0 1 ü
3 21 1 0 1 0 1
25 1 1 0 0 1 ü
26 1 1 0 1 0 ü
15 0 1 1 1 1 ü
4 27 1 1 0 1 1 ü
30 1 1 1 1 0 ü
5 31 1 1 1 1 1 ü

Table (b) Grouping of 2 minterms

Group Minterms Variables Check for inclusion

A B C D E in group of 4
8, 9 0 1 0 0 — ü
1 8, 10 0 1 0 — 0 ü

(Contd.)

62
(Contd.)

Group Minterm Variables Check for circlusion

A B C D E in group of 4
8, 24 — 1 0 0 0 ü
16, 18 1 0 0 — 0 ü
16, 24 1 — 0 0 0 ü
9, 11 0 1 0 — 1 ü
2 9, 13 0 1 — 0 1 ü
9, 25 — 1 0 0 1 ü
10, 11 0 1 0 1 — ü
10, 26 — 1 0 1 0 ü
18, 26 1 — 0 1 0 ü
24, 25 1 1 0 0 — ü
24, 26 1 1 0 — 0 ü
11, 15 0 1 — 1 1 ü
11, 27 — 1 0 1 1 ü
3 13, 15 0 1 1 — 1 ü
25, 27 1 1 0 — 1 ü
26, 27 1 1 0 1 — ü
26, 30 1 1 — 1 0 ü
15, 31 — 1 1 1 1 ü
4 27,31 1 1 — 1 1 ü
30, 31 1 1 1 1 — ü

Table (c) Grouping of 4 minterms

Group Minterms Variables Check for inclusion
A B C D E in group of 8
8, 9, 10, 11 0 1 0 — — ü
8, 9, 24, 25 — 1 0 0 — ü
8, 10, 9, 11 0 1 0 — — ü
1 8, 10, 24, 26 — 1 0 — 0 ü
8, 24, 9, 25 — 1 0 0 — ü
8, 24, 10, 26 — 1 0 — 0
16, 18, 24, 26 1 — 0 — 0
16, 24, 18, 26 1 — 0 — 0
9, 11, 13, 15 0 1 — — 1
9, 11, 25, 27 — 1 0 — 1 ü
9, 13, 11, 15 0 1 — — 1
9, 25, 11, 27 — 1 0 — 1 ü
2 10, 11, 26, 27 — 1 0 1 — ü
10, 26, 11, 27 — 1 0 1 — ü
24, 25, 26, 27 1 1 0 — — ü
24, 26, 25, 27 1 1 0 — — ü
11, 15, 27, 31 — 1 — 1 1
11, 27, 15, 31 — 1 — 1 1
3 26, 27, 30, 31 1 1 — 1 —
26, 30, 27, 31 1 1 — 1 —

63
 Tabe (d) Grouping of 8 minterms

Group Minterms Variables

A B C D E
1 8, 9, 10, 11, 24, 25, 26, 27 — 1 0 — —

Tabe (e) PI Table

PI Decimal Minterms
terms numbers 8 9 10 11 13 15 16 18 21 24 25 26 27 30 31
AB CDE ü 21 Ä
ACE ü 16, 18, 24, 26 Ä ´ ´ ´
ABE ü 9, 11, 13, 15 ´ ´ Ä ´
BDE 11, 15, 27, 31 ´ ´ ´ ´
ABD ü 26, 27, 30, 31 ´ ´ Ä ´
BC ü 8, 9, 10, 11, 24, ´ ´ ´ ´ ´ Ä ´ ´
25, 26, 27
ü ü ü ü ü

The minimized function is

f (A, B, C, D, E) = A B C D E + A C E + A BE + ABD + B C

64
 CHAPTER 6
6.1 (a) In the 16:1 multiplexer IC 74150, the data output is inverted input, i.e.,
complement of the data input line selected. Since the data output is 1 when
the input variables correspond to decimal numbers 2, 4, 6, 7, 9, 10, 11, 12
and 15, therefore, the data input lines corresponding to these decimal
numbers are to be connected to logic 0 and the data input lines 0, 1, 3, 5, 8,
13, and 14 are to be connected to logic 1. The circuit is shown in Fig.
Prob. 6.1.
Logic 1
Logic 0
0
1
2
3
4
5
6
7
8 16:1 Y
9 Multiplexer
10
11 74150
12
13
14
15
G
S3 S2 S1 S0

Logic 0
(MSB) A B C D (LSB)
Fig. Prob. 6.1
(b) To realize a four variable truthtable or logic expression using an 8:1 multi-
plexer the truth table is partitioned as shown by dotted lines (Table 6.3). In
this, the inputs A, B, and C are to be connected to S2, S1 , and S0

Table Prob. 6.1(b)

Inputs Output
A B C Y
0 0 0 0
0 0 1 D
0 1 0 D
0 1 1 1
1 0 0 D
1 0 1 1
1 1 0 D
1 1 1 D

65
 select inputs respectively. Now, we observe the relationship between input
D and output Y for each group of two rows. There are four possible values
of Y and these are 0, 1, D, and D . These are given in Table Prob. 6.1(b).
From this table, we note the output Y for each of the combinations of A, B,
and C and then make the connections accordingly. The implementation of
this function using a 74152 IC is shown in Fig. Prob. 6.1(b). This IC also
has the data output which is complement of the data input line selected.

Logic 1

0
D 1
2
3
D
4 74152 Y
5
Logic 0
6
7
S2 S1 S0

A B C
Fig. Prob. 6.1(b)

6.2 A 32:1 multiplexer can be designed using two 16:1 multiplexers following any
one of the following approaches.
(i) A 32:1 multiplexer will have five selection lines, say, A, B, C, D, and E,
where A is the MSB. If A is connected to the Enable input of one of the
16:1 multiplexers, while the enable input of the other multiplexer is
connected to A , then for A = 0, the first multiplexer is enabled and for
A = 1 the second multiplexer is enabled. Thus for the first 16 of the
32 data inputs one multiplexer gives output depending upon the select
inputs while for the remaining 16 data inputs the other multiplexer
gives the output. Now if the two outputs are ORed together, the system will
function as a 32:1 multiplexer. The complete circuit is shown in
Fig. Prob. 6.2(i).
(ii) Another method can use two 16:1 multiplexers with their select lines con-
nected together. This is followed by a 2:1 multiplexer to select one of the
two outputs. The select line of the 2 : 1 multiplexer is driven from input A.
The complete circuit is shown in Fig. Prob. 6.2(ii).
6.3 The truth table of a full-adder in given in Table Prob. 6.3. To realize this,
using 8:1 multiplexers requires one multiplexer for Sn and one for Cn output.
Assuming 74152 IC, the circuit is shown in Fig. Prob. 6.3.

66
 ì 0
ïï 1
Data í 2
inputs ï M 1 Y1
ïî 15 16 : 1

S3 S2 S1 S0
G1
E
(LSB)
D Output
F (A, B, C, D, E)
C
B S3 S2 S1 S0
ì 16
ï 17
Data ï 18
M2
inputs
í Y2
ï 16 : 1
ïî 31

A
·
(MSB) G2
Fig. Prob. 6.2(i)

ì 0
ïï 1
Data í 2
inputs ï M1 Y1
ïî 15
16 : 1
G1 A(MSB)
Logic 0 S3 S2 S1 S0
B S
C 0
M3 Y Output
D 1 2 : 1 F (A, B, C, D, E)
E G3
(LSB) S3 S2 S1 S0
16
ì
ï 17
Data ï 18
M2 Logic 0
inputsí Y2
ï 16 : 1
ïî 31
G2
Logic 0

Fig. Prob. 6.2(ii)

67
 Table Prob. 6.3

Inputs Outputs
An Bn Cn–1 Sn Cn
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

The gates required for NAND-NAND realization are:

4-input NAND gate 1
3-input NAND gates 5
2-input NAND gates 3
Inverters 3
Logic 1

0
1
2
3
4 74152 Sn
5 IC1
6
7
S2 S1 S0
Logic 0
An
Bn
Cn–1

Logic 1
S2 S1 S0
0
1
2
3
4 74152 Cn
5 IC2
6
7
Logic 0
Fig. Prob. 6.3

68
 Therefore, the following IC packages will be required:
7420 – 1
7410 – 2
7400 – 1
In contrast to four packages required in NAND-NAND realization, the real-
ization using 8:1 multiplexers require only 2 IC packages.
6.4 The A inputs are applied directly to the adder, whereas the B inputs are applied
through EX-OR gates. When the switch S is in ADD position the outputs of the
EX-OR gates will be same as the B inputs. Also Cin = 0. Therefore, the circuit
functions as a 4-bit adder. On the other hand, when S is in SUB position, the
EX-OR gates function as inverters. Also Cin = 1, therefore, the circuit adds A
to the 2’s complement of B and hence functions as a 4-bit subtractor. The
complete circuit is shown below.
B Input
64444
4744444
8
B3 B2 B1 B0

A input
64748
A3 A2 A1 A0

7 4 8 3 ADD
4-bit Adder Cin
S
SUB

VCC

C0 S3 S2 S1 S0

6.5 Table Prob 6.5 (i) gives the truth table of Gray-to-BCD code converter.
Table Prob. 6.5(i)
Gray code BCD code
G3 G2 G1 G0 D C B A
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 1 0 0 1 0
0 0 1 0 0 0 1 1
0 1 1 0 0 1 0 0
0 1 1 1 0 1 0 1
0 1 0 1 0 1 1 0
0 1 0 0 0 1 1 1
1 1 0 0 1 0 0 0
1 1 0 1 1 0 0 1

69
 (a) For A output
(i) When G3 G2 = 00 (ii) When G3G2 = 01
G1 G0 A G1 G0 A
0 0 0 1 0 0
0 1 1 1 1 1
1 1 0 0 1 0
1 0 1 0 0 1

\ A = G1 ⊕ G0 \ A = G1 ¤ G0
(iii) When G3 G2 = 10 (iv) When G3 G2 = 11
G1 G0 A G1 G0 A
1 0 X 0 0 0
1 1 X 0 1 1
0 1 X 1 1 X
0 0 X 1 0 X

\A= X \ A = G1 ⊕ G0
Similarly, we can obtain the expressions for the D, C, and B outputs. These
are given in Table Prob. 6.5 (ii).

Table Prob. 6.5(ii)

G3 G2 D C B A
0 0 0 0 G1 G1 ⊕ G0
0 1 0 1 G1 G 1 ¤ G0
1 0 X X X X
1 1 1 0 0 G1 ⊕ G0

The G3 and G2 are used as the select inputs. The complete circuit can be
drawn which requires two 74153 packages and one 7486 package.
(b) The complete circuit is shown in Fig. Prob. 6.5(b).
It requires one 74154, one 7430, one 7420, and one 7400 IC packages.
6.6 The truth table of BCD-to-7-segment decoder is given in Table Prob. 6.6(i)
and Fig. Prob 6.6(i) shows a common-anode 7-segment display device.

Table Prob. 6.6(i)

BCD Inputs Seven-Segment Outputs

D C B A a b c d e f g
0 0 0 0 0 0 0 0 0 0 1
0 0 0 1 1 0 0 1 1 1 1
0 0 1 0 0 0 1 0 0 1 0
0 0 1 1 0 0 0 0 1 1 0
0 1 0 0 1 0 0 1 1 0 0
0 1 0 1 0 1 0 0 1 0 0
(Contd.)

70
 Table Prob. 6.6(i) (Contd.)

BCD Inputs Seven-Segment Outputs

D C B A a b c d e f g
0 1 1 0 1 1 0 0 0 0 0
0 1 1 1 0 0 0 1 1 1 1
1 0 0 0 0 0 0 0 0 0 0
1 0 0 1 0 0 0 1 1 0 0
1 0 1 0 X X X X X X X
1 0 1 1 X X X X X X X
1 1 0 0 X X X X X X X
1 1 0 1 X X X X X X X
1 1 1 0 X X X X X X X
1 1 1 1 X X X X X X X

Y0
Y1 Aü
Y2 (LSB)ï
ï
Y3 ï
Y4 ï
ï
Y5 ï
G1 Y6 Bï
ï
74154 ï
Y7
G0 ï
Y8 ïï BCD
Y9 ýoutputs
ï
Y10 ï
Cï
Y11 ï
Y12 ï
ï
Y13 ï
Y14 ï
ï
Y15 ï
Dï
S3 S2 S1 S0 (MSB) ïþ

G G G G
13444
2 2444
1 3
0

Gray code inputs

Fig. Prob. 6.5(b)
(a) From Table Prob. 6.6(i), we can prepare Table Prob. 6.6(ii) which gives
outputs in terms of A and B inputs for each combination of D and C inputs.
The circuit for generating data inputs for the multiplexers corresponding to
Table Prob. 6.6 (ii) is shown in Fig. Prob. 6.6 (ii). The ICs required are:
74153 3 1 packages
2
71
 7408 3/4 package
7432 3/4 package
7404 1/2 package

Anode

a
a
b
c f b
g
d
e e c
f
d ·
g DP DP

Fig. Prob. 6.6(i)

Table Prob. 6.6(ii)

Inputs Outputs
D C a b c d e f g

0 0 BA 0 BA BA A A+B B
0 1 A B⊕ A 0 B¤A A+ B AB AB
1 0 0 0 0 A A 0 0
1 1 X X X X X X X

B A+ B

B
BA

A+B BÅA B¤A

AB BA
A
A
Fig. Prob. 6.6(ii)

(b) The circuit is designed in a way similar to Prob. 6.5. The ICs required are:
74154 one package
7420 one package
7410 one package
72
 7430 one package
7404 1/6 package
(c) The IC 7442 is a BCD-to-decimal decoder circuit with active-low outputs.
These outputs are to be connected exactly in the same way as in the case of
part (b) realization. The IC packages required are same as in part (b) with
74154 replaced by 7442.
(d) From the IC packages requirements for parts (a), (b), and (c), we observe
the savings in hardware when demultiplexers/decoders are used for the
realization of multiple output systems.
6.7 Table Prob. 6.5(i) can be rearranged suitably to give the truth table of BCD-to-
Gray code converter.
(a) From the truth table, Table Prob. 6.7 (a) is obtained following the
procedure used in Prob. 6.1(b).

Table Prob. 6.7(a)

D C B G3 G2 G1 G0
0 0 0 0 0 0 A
0 0 1 0 0 1 A
0 1 0 0 1 1 A
0 1 1 0 1 0 A
1 0 0 1 1 0 A

The circuit can now be designed using four 74151A ICs (one for each of
the outputs). The D, C, and B inputs are to be applied to the S2, S1, and S0
select inputs respectively.
(b) Table Prob. 6.7(b) can be obtained from the truth table following the
procedure of Prob. 6.5 (a). The circuit can now be designed using two
74153 ICs and two EX-OR (7486) gates.

Table Prob. 6.7(b)

D C G3 G2 G1 G0
0 0 0 0 B A⊕ B
0 1 0 1 B A⊕ B
1 0 1 1 0 A
1 1 X X X X

(c) Following the approach similar to (b), we obtain Table Prob. 6.7 (c). Here
eight rows of the truth table are grouped together.

Table Prob. 6.7(c)

D G3 G2 G1 G0
0 0 C B⊕ C A ⊕ B
1 1 1 0 A

73
 The circuit can now be designed using one 74157 (Quad 2:1 multiplexer)
IC and two EX-OR gates of 7486.
(d) Following the procedure used in Example 6.3, the circuit can be designed
using one BCD-to-decimal decoder IC 7442 and NAND gates (2-, 4-, 5-,
and 6-input).
(e) The minimized expressions are
G3 = D G2 = C + D G1 = C B + C B G0 = B A + B A
The realization will require eleven 2-input NAND gates.
(f) The package count for each part are given in Table Prob 6.7(d)

Table Prob. 6.7(d)

Part No. of IC packages
a 74151A – 4, 7404 – 1
b 74153 – 2, 7486 – 1
c 75157 – 1, 7486 – 1
d 7442 – 1, 7430 – 2, 7420 – 1
e 7400 – 3

6.8 The truth table for f1, f2, and f3 outputs is given in Table Prob. 6.8(i)
(a) The truth table is reduced to Table Prob. 6.8(ii) for realization using 8 : 1
multiplexers. The circuits can now be designed for f1, f2, and f3 outputs
using multiplexers and inverters.
(b) Using the truth table the circuits for f1, f2, and f3 can be designed following
the procedure outlined in Example 6.1. The realizations will require one 16
: 1 multiplexer for each output.
(c) The circuit can be designed using one demultiplexer and two 8-input and
one 6-input NAND gates.
Table Prob. 6.8(i)
Inputs Outputs
D C B A f1 f2 f3
0 0 0 0 1 1 0
0 0 0 1 0 1 0
0 0 1 0 0 1 1
0 0 1 1 1 1 0
0 1 0 0 0 0 1
0 1 0 1 1 0 1
0 1 1 0 1 0 1
0 1 1 1 0 0 0
1 0 0 0 0 0 1
1 0 0 1 1 0 0
1 0 1 0 1 0 0
1 0 1 1 0 1 0
1 1 0 0 1 1 1
1 1 0 1 0 0 0
1 1 1 0 0 1 0
1 1 1 1 1 1 0

74
 Table Prob. 6.8(ii)

D C B f1 f2 f3

0 0 0 A 1 0
0 0 1 A 1 A
0 1 0 A 0 1
0 1 1 A 0 A
1 0 0 A 0 A
1 0 1 A A 0
1 1 0 A A A
1 1 1 A 1 0

6.9 In a 40:1 multiplexer, there are 40 data input lines (I0 through I39), 6 select
lines FEDCBA. The lower order three select bits C, B, and A are used as S2, S1,
S0 select inputs respectively for 8:1 multiplexers M1 through M5. The higher
order three select bits F, E, and D are used as select inputs S2, S1, and S0 for
the multiplexer M6, which selects output of one of the multiplexers M1 through
M5.

I0 – I7 M1
G
S2 S1 S0

C B A

I8 – I15 S2 S1 S0

M2 0
G 1
2
3
4 M6 Y
5
6
I16 – I23 M3 7
G S2 S1 S0
S2 S1 S0
G
C B A F E D
I24 – I31 S2 S1 S0 (MSB)
M4
G
C B A (LSB)

I32 – I39 S2 S1 S0
M5
Enable
G
Fig. Prob. 6.9
75
 For example if the select inputs are 011111, data input 7 of M2 (I15) will
appear at the output Y.
6.10 The BCD-to-decimal decoder is to be used as an 1 : 8 demultiplexer. The
address inputs for demultiplexers D1 through D6 are C, B, and A. D is active-

0 0
1 1
2 2
D 3 3
X2 C D1 4 4
5 5
7442 6 6
X1 B
7 7
X0 A 8
(LSB) 9
0 8
1 9
2 10
D 3 11
C D2 4 12
X2 5 13
7442 6 14
B
X1 7 15
A 8
X0 9
0 0 16
1 1 17
2 D 2 18
3 3 19
D6 4 D3 20
4
Enable D C
7442 5 X2 7442 5 21
6 B 6 22
7 X1 7 23
8 A 8
C B A9 X0 9
(
0 24
1 25
X5 X4 X3 2 26
(MSB) D 3 27
C D4 4 28
X2 5 29
7442 6 30
B
X1 7 31
A 8
X0 9
0 32
1 33
2 34
D 3 35
X2 C D5 4 36
5 37
7442 38
X1 B 6
7 39
X0 A 8
9
Fig. Prob. 6.10
76
 low input for demultiplexer function. The outputs 8 and 9 of D1 through D5 are
not used in this configuration. The lower order three bits of the address X2, X1,
and X0 are applied at the C, B, A select inputs respectively of each decoder
chip D1 through D5. The higher order three bits of the address X5, X4, and X3
are applied at the C, B, and A select inputs respectively of D6. For example, if
the 6-bit select inputs are 001111, then output 1 of D6 is activated, which
activates decoder D2 and the output 7 of this decoder goes low. This corre-
sponds to output on line 15 (which is same as the decimal equivalent of
001111). The complete circuit is shown in Fig. Prob. 6.10.
6.11 For the full-adder circuit designed using half-adder circuits shown in Fig.
Prob. 6.11.
EX–OR(1)
An S1 EX–OR(2)
Bn S2 = Sn

C1
C2 Cn
AND-2
OR
AND–1
Cn–1
Fig. Prob. 6.11

The propagation delay time for Cn is

tpd = tpd [EX-OR(1)] + tpd (AND-2) + tpd (OR) = 20 + 10 + 10 = 40 ns
This is the propagation delay time for carry to travel one full-adder. For an n-
bit adder, this carry has to ripple through all the n adders. Therefore, the
propagation delay time for the carry to propagate from C–1 to Cn–1 in the
circuit of Fig. 6.12 (a) will be n ´ 40 = 40 ns.
6.12 Let the four digits BCD numbers be P4P3P2P1 and Q4Q3Q2Q1. P4 and Q4 are
applied at the A and B inputs respectively of adder # 4 and similarly the other
inputs are applied as shown below.
Q4 P4 Q3 P3 Q2 P2 Q1 P1

BCD adder BCD adder BCD adder BCD adder

#4 #3 #2 #1
C¢¢¢¢
0 C2 C¢¢¢
0 C1 C¢¢0 C0 C¢0 C–1

C0 S15–S12 S11–S8 S7–S4 S3–S0

144444444444444
42444444444444444
3
5-digit output
Fig. Prob. 6.12

77
6.13 Its truth table is given in Table Prob. 6.13. Using K-maps the minimized
expressions given below are obtained.
Table Prob. 6.13
Inputs Outputs
A1 A0 B1 B0 A>B A=B A<B
0 0 0 0 0 1 0
0 0 0 1 0 0 1
0 0 1 0 0 0 1
0 0 1 1 0 0 1
0 1 0 0 1 0 0
0 1 0 1 0 1 0
0 1 1 0 0 0 1
0 1 1 1 0 0 1
1 0 0 0 1 0 0
1 0 0 1 1 0 0
1 0 1 0 0 1 0
1 0 1 1 0 0 1
1 1 0 0 1 0 0
1 1 0 1 1 0 0
1 1 1 0 1 0 0
1 1 1 1 0 1 0

A > B = A0 B 1 B0 + A1 A0 B 0 + A1 B 1

A = B = A1 B 1 (A0 ¤ B0) + A1B1 (A0 ¤ B0)

= (A0 ¤ B0) (A1 ¤ B1)

A < B = A 1 A 0 B0 + A 0 B1B0 + A 1B1

The complete circuit can be drawn using gates.
6.14 The comparator C1 compares the least significant four bits. Its A > B, A = B,
and A < B outputs are connected to the corresponding cascading inputs of C2
respectively. The complete circuit is shown below.
A4 – A7
A0 – A3 A>B
A>B
A=B B4 – B7
B0 – B3 C1 C2 A=B
A<B
7485 A<B
7485

A>B A>B
A=B A=B
A<B A<B

Logic 1 Logic 0
Fig. Prob. 6.14

78
6.15 The operation is given below.

Inputs Outputs
CIC 1 A = 1001
B = 1011
A>B =1 A>B=0
A=B =0 A<B=1
A<B =1

CIC 2 A = 0000
B = 0000 A>B=0
A>B =1 A<B=0
A=B =0
A<B =1

CIC 3 A = 1011
B = 1101 A>B=0
A>B =1 A<B=0
A=B =0
A<B =1

CIC 4 A = 0010
B = 0001 A>B=1
A>B =1 A<B=0
A=B =0
A<B =0

CIC 5 A = 0010
B = 0011 A>B=0
A>B =0 A<B=1
A=B =1 A=B=0
A<B =0

CIC 6 A = 0001
B = 1000 A>B=0
A>B =0 A=B=0
A=B =0 A<B=1
A<B =1

6.16 The least-significant bit (A1) of BCD input is same as the least-significant bit
of the output. The other three bits (D1, C1, and B1) are applied to C, B, and A
inputs respectively. D and E inputs are connected to logic 0. The binary output
is obtained at B3B2B1B0 outputs as shown in Fig. Prob. 6.16.

79
 ì A1 B0
ü
BCD ï ï B1 A Y1 B1 ï
ï Binary
inputs í C ý outputs
ï 1 B Y2 B2 ï
ïî D C 74184 Y3 B3 ï
þ
1
(MSB) D Y4
E Y5
G

Fig. Prob. 6.16

6.17 The IC 74148 is a priority octal-to-binary encoder. If more than one inputs are
given in the same chip, the highest numbered input will appear in the binary
form at the output.
If two inputs are given simultaneously, one of which is in IC1 and the other
one in IC2, then E0 of IC2 will be HIGH, which will disable the IC1 chip. This
shows that the circuit is a priority encoder.
6.18 Apply the 6-bit input to A through F inputs and connect the other two inputs
G and H to logic 0. Connect EVEN and ODD inputs to logic 1 and 0 respec-
tively.
If the parity of the 6-bit word is even, å EVEN output will be 1, whereas, if
the parity of the 6-bit word is ODD, then å ODD output will be 1.
6.19 The 7-bit input is applied at A through G inputs and H = 0. If EVEN and ODD
inputs are at logic 1 and 0 respectively, then å EVEN output is 1 if the 7-bit
input is even and 0 if the 7-bit input is odd. Therefore, these seven bits along
with the å EVEN output bit will give an 8-bit word with odd parity. The
circuit is shown below.

A - G ü
ï 8-bit odd
ý parity word
A - G SEVEN ïþ

74180
H
EVEN SODD
ODD

Logic 1 Logic 0
Fig. Prob. 6.19

80
6.20 The circuit is shown in Fig. Prob. 6.20 and its operation is given in Table
Prob. 6.20.

B0 – B7 SEVEN B8 – B13 SEVEN

P1 P2
Logic 0 G
74180 74180
Logic 1 B14
SODD H

parity word
15-bit even
EVEN SODD ü
B0 – B13 ï
ý
EVEN ïþ
ODD ODD

Fig. Prob. 6.20

Table Prob. 6.20

Parity of B0 – B7 P1 Parity of P2
åEVEN åODD B8 – B13 åEVEN åODD
EVEN 1 0 EVEN 1 0
ODD 0 1
ODD 0 1 EVEN 0 1
ODD 1 0

From the table we see that the parity of B0 – B13 and åODD of P2 is
even.
6.21 The circuit is shown in Fig. Prob. 6.21 and its operation is explained in the
Table Prob. 6.21.
B0 A
B1 B
B2 C
B3 D S EVEN 1 on
B4 E even parity
B5 F
B6 G 74180
B7 H
EVEN
7486 SODD

B8
ODD
B9

Logic 1
Fig. Prob. 6.21
81
 Table Prob. 6.21

Parity of Parity of Cascading Outputs

B0 – B7 B8 – B9 inputs
EVEN ODD åEVEN åODD
EVEN EVEN 1 0 1 0
EVEN ODD 0 1 0 1
ODD ODD 0 1 1 0
ODD EVEN 1 0 0 1

6.22
b0 – b 7 SEVEN
P1
EVEN

b8 ODD

b9 – b16 SEVEN
P2
EVEN

High on
b17 ODD SEVEN
EVEN
P10
EVEN
High on
ODD ODD
b72 – b79 SEVEN
P9
EVEN

b80 ODD
Fig. Prob. 6.22

6.23 The circuit is given in Fig. Prob. 6.23. Here P1, P2, and P3 are 9-bit
parity checkers.
6.24 See Fig. Prob. 6.24 (a and b)
6.25 See Fig. Prob. 6.25
6.26 Let the four BCD digits be ABCD, with A as MSD. The circuit is given in
Fig. Prob. 6.26.
The least-significant bits of the BCD digits are applied at the data inputs of
M1 and similarly higher order bits are applied to M2, M3, and M4. The select
input are fed from the mod-4 counter, which drives a BCD-to-decimal
decoder.

82
 b0
SEVEN

P1

b8

b9 SEVEN High on
EVEN
P2

b15 SODD High on

ODD

b16

SEVEN
P3

b24

Fig. Prob. 6.23

(a) VCC VCC

Current Limiting
resistor

VCC
0
(MSB) 1
2
ìD
BCD input

3
ïC
í 7442 4
ïB 5
îA 6
7
8
GND 9

Fig. Prob. 6.24(a)

83
 (b) +170 V

R = 10 kW Anode

0 1 2 3 4 5 6 7 8 9

NIXIE Tube
0 1 2 3 4 5 6 7 8 9

+5V VCC 74141

(LSB)
D444
1 C424444
B A
3
BCD Input
(b)
Fig. Prob. 6.24

0 0
A E
1 1
B 2 F
C D1 3 G D2

D H
14
15 15
Enable Detects Detects
(logic 0) 0001 0001111
Fig. Prob. 6.25

The multiplexer outputs are decoded by the BCD-to-7-segment decoder with

active-low outputs. When the counter output is 00, digit A is selected and at
the same time anode A1 goes HIGH, thereby displaying the digit A on the
left-most 7-segment display. Similarly, when the counter outputs are 01, 10,
and 11 B, C, and D digits are displayed respectively on second, third, and
fourth displays in sequence. In this way each display will be ON for one-
fourth of the total time. If the clock frequency is sufficiently high, the display
would appear to be continuous.
6.27 For R to glow, the inputs required at the rows for each column are as given in
Table Prob. 6.27.
The circuit is to be designed in a way similar to that of Prob. 6.26. One
column must glow at a time in sequence. Seven 5:1 multiplexers and a mod-5
counter will be required for this.

84
A0 0
B0 1 M1
C0 2
D0 3 S S
1 0

BCD-to-7-segment
A1 0 decoder
B1 1
M2 a
C1 2
D1 3 S S A b
1 0
c
B
d
C e
A2 0
(MSB) D f
B2 1
g A1 A2 A3 A4
C2 2 M3
D2 3 S S
1 0 Buffer
inverters
···
A3 0 0 1 2 3 4
B3 1 BCD-to-decimal
C3 2 M4 decoder
D3 3 S S
1 0

Q0 Q1 Q2 Q3
Mod-4 counter

Clock
Fig. Prob. 6.26

Table Prob. 6.27

Row/Column ® 1 2 3 4 5
¯
1 1 1 1 1 0
2 1 0 0 0 1
3 1 0 0 0 1
4 1 1 1 1 0
5 1 0 1 0 0
6 1 0 0 1 0
7 1 0 0 0 1

85
 CHAPTER 7

7.1 When S = R = 0, the outputs of the gates G3 and G4 will be 1. Therefore,

G1 and G2 will act as inverters. Hence, the circuit of fig. 7.4 is same as that of
Fig. 7.3.
7.2 (a) With S = 1 and R = 0, the outputs of G3 and G4 are 0 and 1 respectively.
Since one of the inputs of G1 is 0, therefore, its output Q = 1. This makes
both the inputs of G2 as 1 giving an output Q = 0. Now if S = R = 0, the
inputs and output of G2 remain unaffected, which makes the lower input of
G1 as 0 while the upper one becomes one giving again Q = 1. This means
the outputs do not change.
(b) With S = 0 and R = 1, Q1 = 1 and Q = 0 in a manner similar to part (a) and
also Q and Q will remain unchanged when S and R both are made 0.
7.3
R
Q

Q
S

Fig. Prob 7.3

7.4 (a) With Pr = 0, Q will be 0 which makes one of the inputs of G3 0. There-
fore, whatever may be the other input of G3, its output will be 1. This
results in both the inputs of AND gate G5 to be 1 giving Q = 1. That is, the
FLIP-FLOP is set irrespective of the S, R, and CK inputs.
(b) If Cr = 0, then the FLIP-FLOP is reset following the same logic as
discussed in part (a).
(c) If Pr = Cr = 1, the AND gates G5 and G6 are enabled, making this circuit
identical to a normal clocked S – R FLIP-FLOP as shown in Fig. 7.5.
7.5 (i) When Jn = Kn = 0, the AND gates are disabled resulting in Sn = Rn = 0.
Therefore, when a clock pulse is applied, the outputs Q and Q will not
change, i.e., Qn+1 = Qn.
(ii) When Jn = 1 and Kn = 0, then Sn = Q n and Rn = 0. Now, if Qn = 1 then
Sn = 0, i.e., Sn = Rn = 0 and the output Qn+1 = Qn = 1. On the other hand if
Qn = 0 then Sn = 1 which will make Qn+1 = 1. Therefore, whatever may be
the state of the FLIP-FLOP, it will go to set state in this condition when a
clock pulse is applied.
(iii) If Jn = 0 and Kn = 1 then Sn = 0 and Rn = Qn. Following the above
discussion, we find that the FLIP-FLOP will go to the reset state when a
clock pulse is applied.
(iv) If Jn = Kn = 1, then Sn = Q n and Rn = Qn. Now, if Qn = 1, then Sn = 0 and
Rn = 1 which will make Qn+1 = 0. Similarly, if Qn = 0, then Sn = 1 and Rn
= 0 which makes Qn+1 = 1. Therefore, Qn+1 = Q n.
86
7.6
Y1 = ( J ⋅ Q ) ⋅ CK

= J ⋅ Q ⋅ CK

and Y2 = J ⋅ Q ⋅ CK
Hence, Y1 = Y2
7.7
Q1 = Q

and Q2 = Q
7.8
Clock

Input

ìQ
Output í
îQ

7.9
Clock

Input

ìQ
Output í
îQ

7.10
Clock

Input

Output
Q

7.11 Let Q = 1 and Q = 0.

This makes R = Q = 1 and S = Q = 0. When a clock pulse is applied, Q and
Q will become 0 and 1 respectively. Now, R = Q = 0 and S = Q = 1 and on

87
 application of a clock pulse, Q and Q become 1 and 0 respectively. This
show that Q and Q change with every clock pulse, and hence the circuit
behaves as a toggle switch.
7.12 The truth table is given in Table Prob. 7.12. From this table we observe that
when Tn = 0, Qn+1 = Qn, whereas, when Tn = 1, Qn+1 = Q n.

Table Prob. 7.12

Tn Qn Sn Rn Qn+1
0 0 0 1 0
0 1 1 0 1
1 0 1 0 1
1 1 0 1 0

7.13 When Q = D = 0, a clock pulse will make Q and Q 0 and 1 respectively. Now
Q = D = 1 and the next clock pulse will change the Q output to 1. Thus, the
outputs change with every clock pulse.
7.14 The characteristic table and the truth table for decoder are given in Table
Prob. 7.14 (a). The K-maps for Y1 and Y2 are shown below, which give
Y1 = Q + CK + J = Q ⋅ J ⋅ CK
and Y2 = CK + K + Q = Q ⋅ K ⋅ CK

Table Prob. 7.14 (a)

Characteristic table Truth table for decoder

CK J K Qn Qn + 1 Y1 Y2
0 0 0 0 0 1 X
0 0 0 1 1 X 1
0 0 1 0 0 1 X
0 0 1 1 1 X 1
0 1 0 0 0 1 X
0 1 0 1 1 X 1
0 1 1 0 0 1 X
0 1 1 1 1 X 1
1 0 0 0 0 1 X
1 0 0 1 1 X 1
1 0 1 0 0 1 X
1 0 1 1 0 1 0
1 1 0 0 1 0 1
1 1 0 1 1 X 1
1 1 1 0 1 0 1
1 1 1 1 0 1 0

(b) The excitation table and the truth table for decoder are given in Table
Prob. 7.14(b). The K-maps can be prepared and minimized. The mini-
mized expressions are:

88
 CKJ CKJ
KQ 00 01 11 10 KQ 00 01 11 10
00 1 1 0 1 00 ´ ´ 1 ´

01 ´ ´ ´ ´ 01 1 1 1 1

11 ´ ´ 1 1 11 1 1 0 0

10 1 1 0 1 10 ´ ´ 1 ´

Y 1 = Q + CK + J Y 2 = CK + K + Q
= Q ⋅ J ⋅ CK = Q ⋅ K ⋅ CK
(a) (b)

Y1 = CK + D = CK ⋅ D

and Y = CK + D = CK ⋅ D

Table Prob. 7.14(b)

Excitation table Truth table for decoder

CK D Qn Qn+1 Y1 Y2
0 0 0 0 1 X
0 0 1 1 X 1
0 1 0 0 1 X
0 1 1 1 X 1
1 0 0 0 1 X
1 0 1 0 1 0
1 1 0 1 0 1
1 1 1 1 X 1

(c) Using the above method, we obtain

Y1 = CK ⋅ T ⋅ Q
and Y2 = CK ⋅ T ⋅ Q
Complete circuits can be drawn for each of the above cases.
7.15 (a) The truth table required for conversion from S-R to D FLIP-FLOP is
given in Table Prob. 7.15(a). The K-maps for S and R outputs are prepared
as shown in Fig. Prob. 7.15(i) from which we obtain the minimized expres-
sions for S and R as
S = D and R = D
Table Prob. 7.15(a)
Data input Output S-R FF inputs
D Q S R
0 0 0 X
1 0 1 0
0 1 0 1
1 1 X 0

89
 D D
Q 0 1 Q 0 1
0 0 1 0 ´ 0

1 0 ´ 1 1 0

(a) (b)
Fig. Prob. 7.15(i)

(b) The required truth table is given in Table Prob. 7.15(b) from which the
minimized expressions are obtained as

J= D and K= D

Table Prob. 7.15(b)

Data input Output J-K FF inputs

D Q J K
0 0 0 X
1 0 1 X
0 1 X 1
1 1 X 0

(c) The required truth table is given in Table Prob. 7.15(c) and the minimized
expression for D is given by

D = JQ + KQ

Table Prob. 7.15(c)

Data inputs Output D-FF input
J K Q D
0 0 0 0
0 1 0 0
1 0 0 1
1 1 0 1
0 1 1 0
1 1 1 0
0 0 1 1
1 0 1 1

(d) Table Prob. 7.15 (d) gives the required truth table from which we obtain
the minimized expressions for S and R as

S = T ⋅Q

and R =T⋅Q

90
 Table Prob. 7.15(d)

Data input Output S – R FF inputs

T Q S R
0 0 0 X
1 0 1 0
1 1 0 1
0 1 X 0

(e) The truth table can be prepared and expressions for J and K inputs
obtained.
J=K=T
Similarly, all the other conversions can be made. The minimized expres-
sions obtained are given below:
(f) T = J Q + KQ
(g) T =D⊕Q
(h) D = S + RQ
(i) D =T⊕Q
(j) T = S Q + RQ
(k) J = S, K = R
7.16 Let the inputs to the latch be Y1 and Y2.
(i) When the clock is LOW:
Y1 = Y2 = 1 independent of D input and the state of the FLIP-FLOP can-
not change.
(ii) When the clock is HIGH:
Y1 and Y2 are complement to each other and for each value of D we find
that the values of Y1 and Y2 do not change. This means the state of the
FLIP-FLOP cannot change.
(iii) When the clock goes from LOW to HIGH:
Case I: Let D = 0
Y1 will remain 1 and Y2 changes from 1 to 0. Therefore, Q becomes 0.
While the clock is HIGH, if there is any change in D, Y1 and Y2 will remain
unaltered. When the clock comes back to 0 from 1, then Y1 = Y2 = 1 which
also does not affect the output Q.
Case II: Let D = 1. Y2 will remain 1 and Y1 changes from 1 to 0. Therefore,
Q goes to 1.
Now, while the clock is HIGH, if there is any change in D, Y1 and Y2
will remain unaltered. When the clock goes back to 0, then Y1 = Y2 = 1
which will not affect the output Q.
7.17 The waveforms obtained are shown in Fig. Prob. 7.17.
7.18 (a) When the switch is in position 1, Pr = 0 and Cr = 1. Therefore, Q = 1.
Now, if the switch is changed over to position 0, as soon as it makes
contact for the first time, Q will become 0. Now, even if the switch

91
 1
Clock
0
0 1 2 3 4 5 6 7 8 9 10 11 12
1
J
0

1
Q
0
(a)
1
Q
0
(b)
Fig. Prob. 7.17

debounces, the output Q will not be affected. Similarly, the switch will
operate in the reverse switching.
(b) When the switch is in position 1, Q = 0 and Q = 1. When the switch is
thrown to position 0, at the first contact Q becomes 1. Now, when the
switch debounces, the outputs Q and Q do not change.
7.19 The clock, CKs and CKD waveforms are shown in Fig. Prob. 7.19. At the rising
edge of the clock CKs, the data present at the data input terminal Ds is loaded
into the source FF. When CKD goes HIGH, the data is loaded into the destina-
tion FF.
Now, if the delay time Dt2 is more than it takes to change the present output
of the source FF, the operation will not be reliable. In fact, the clock skew may
violate the hold time requirements of the destination FF. This difficulty can be
overcome by adding additional delay to assure reliable operation.
Clock

Dt1
CKS

CKD Dt2

Fig. Prob 7.19

7.20 The waveforms are shown in Fig. Prob. 7.20. The states of the counter are 00,
01 and 10.
7.21 The waveform at CK will be as shown in Fig. Prob. 7.21. This means, the level
triggered D-type FF will operate as a positive-edge-triggered FF.

92
 1 2 3 4 5 6 7
1
Clock
pulses 0
1
J 0 = Q1
0
1
Q 0 = J1
0
1
Q1
0
Fig. Prob. 7.20

Fig. Prob. 7.21

93
 CHAPTER 8

8.1 (i) When the mode control input, M = 1, all the A AND gates are enabled and
all the B AND gates are disabled. The circuit effectively reduces to that of
Fig. Prob. 8.1(i). This is a right-shift register.

Serial
D3 Q3 D2 Q2 D1 Q1 D0 Q0
input
FF3 FF2 FF1 FF0

Fig. Prob. 8.1(i)

(ii) When M = 0, all the B AND gates are enabled and all the A AND gates are
disabled. The circuit effectively reduces to that of Fig. Prob. 8.1(ii). In this
case the data will get shifted to the left direction, i.e., it functions as a left-
shift register.

Q3 D3 Q2 D2 Q1 D1 D0 Q0
Serial
FF3 FF2 FF1 FF0 input

Fig. Prob. 8.1(ii)

8.2 A 5-stage twisted-ring counter is shown in Fig. Prob. 8.2(a). Let us assume
that all the FLIP-FLOPs are in the clear state, i.e., Q4 = Q3 = Q2 = Q1 = Q0 =
0. The various outputs when clock pulses are applied are given in Table Prob.
8.2.
Table Prob. 8.2
At the end of Outputs
clock pulse Q4 Q3 Q2 Q1 Q0
0 0 0 0 0 0
1 1 0 0 0 0
2 1 1 0 0 0
3 1 1 1 0 0
4 1 1 1 1 0
5 1 1 1 1 1
6 0 1 1 1 1
7 0 0 1 1 1
8 0 0 0 1 1
9 0 0 0 0 1
10 0 0 0 0 0
At the end of the tenth clock pulse, the circuit comes back to its initial state.
Therefore, it is a mod-10 counter. Its state diagram is shown in Fig. Prob. 8.2(b).
94
 D4 Q4 D3 Q3 D2 Q2 D1 Q1 D0 Q0
FF4 FF3 FF2 FF1 FF0
Q0

Clock
Clear
Fig. Prob. 8.2(a)

00000 10000 11000 11100 11110

00001 00011 00111 01111 11111

Fig. Prob. 8.2(b)

8.3 Let Y0, Y1. . . be the outputs corresponding to pulses 0, 1, 2, . . . respectively.
The truth table for the decoder is given in Table Prob. 8.3. For all the remain-
ing combinations of Q’s, the Y outputs are don’t care. The K-map is to be
prepared for each output. Figure Prob. 8.3 gives the K-map for Y0 . Similarly,
other K-maps can be prepared. The minimized expressions are given by
Y0 = Q 4 Q 0 Y5 = Q4Q0
Y1 = Q4 Q 3 Y6 = Q 4Q3
Y2 = Q3 Q 2 Y7 = Q 3Q2
Y3 = Q2 Q 1 Y8 = Q 2Q1
Y4 = Q1 Q 0 Y9 = Q 1Q0

Table Prob. 8.3

Inputs Outputs
Q4 Q3 Q2 Q1 Q0 Y0 Y1 Y2 Y3 Y 4 Y5 Y6 Y7 Y8 Y9
0 0 0 0 0 1 0 0 0 0 0 0 0 0 0
1 0 0 0 0 0 1 0 0 0 0 0 0 0 0
1 1 0 0 0 0 0 1 0 0 0 0 0 0 0
1 1 1 0 0 0 0 0 1 0 0 0 0 0 0
1 1 1 1 0 0 0 0 0 1 0 0 0 0 0
1 1 1 1 1 0 0 0 0 0 1 0 0 0 0
0 1 1 1 1 0 0 0 0 0 0 1 0 0 0
0 0 1 1 1 0 0 0 0 0 0 0 1 0 0
0 0 0 1 1 0 0 0 0 0 0 0 0 1 0
0 0 0 0 1 0 0 0 0 0 0 0 0 0 1

95
 The circuit can be drawn using ten 2-input AND gates.

Q4 = 0 Q4 = 1
Q3Q2 Q3Q2
Q1Q0 Q1Q0
00 01 11 10 00 01 11 10
00 1 ´ ´ ´ 00 0 ´ 0 0

01 0 ´ ´ ´ 01 ´ ´ ´ ´

11 0 0 0 ´ 11 ´ ´ 0 ´

10 ´ ´ ´ ´ 10 ´ ´ 0 ´

Fig. Prob. 8.3

8.4 To generate these waveforms, a 4-stage twisted-ring counter is required. The

waveforms at the Q outputs are shown in Fig. Prob. 8.4(i). The required,
waveforms can be obtained by using decoders shown in Fig. Prob. 8.4(ii),
which are designed in the same way as Prob. 8.3.

1 2 3 4 5 6 7 8 9 10 11 12 13

Clock
Pulses

Q3

Q2

Q1

Q0
Fig. Prob. 8.4(i)

Q3 Q1
f1 f2
Q2 Q0

Q2 Q0
f3 f4
Q3 Q1
Fig. Prob. 8.4(ii)

8.5 The count sequence is given in Table Prob. 8.5. From the count sequence we
observe that Q0 changes with every clock pulse. This can be obtained by using
a T-type FLIP-FLOP (FF0) with T0 = 1.
96
 Q1 changes whenever Q0 changes from 0 to 1, therefore, if Q 0 is used as the
clock input for FF1 with T1 = 1, the desired changes in Q1 will be obtained.
Similarly, Q2 changes whenever Q1 goes from 0 to 1. The desired changes in
Q2 can be obtained by using Q1 as the clock input for FF2 with T2 = 1. The
complete circuit is shown in Fig. Prob. 8.5.
T0 = T1 = T2 = 1

T0 T1 T2
Q1 Q2
Q0
Clock
FF0 FF1 FF2
Q0 Q1 Q2

Fig. Prob. 8.5

Table Prob. 8.5

Q2 Q1 Q0
0 0 0
1 1 1
1 1 0
1 0 1
1 0 0
0 1 1
0 1 0
0 0 1

8.6 For a ripple UP counter Q outputs of the preceding stages are to be connected
to the clock inputs of the succeeding stages, whereas for a DOWN counter Q
outputs are to be connected to the clock inputs. Therefore, AND-OR gates are
used between stages as shown below. The AND gates A are enabled when UP/
DOWN input is at logic 1, connecting Q outputs to clock inputs, whereas the
AND gates B are enabled when UP/DOWN input is at logic 0 connecting Q
outputs to the clock inputs.
T0 = T1 = T2 = T3 = 1
T0 Q0 T1 Q1 T2 Q2 T3 Q3
A0 A1 A2
Clock pulses

FF0 FF1 FF2 FF3

Q0 B0 Q1 B1 Q2 B2 Q3

UP/
DOWN
Fig. Prob. 8.6

97
 D0 D1 D2 D3

Load

Pr Pr Pr Pr
Q0 Q1 Q2 Q3
FF0 FF1 FF2 FF3
Q0 Q1 Q2 Q3

Fig. Prob. 8.7

The preset inputs are used for asynchronous loading. The relevant portion of
the circuit is shown on next page. When load input is HIGH, the data at the D
inputs will be entered in the FLIP-FLOPs. The other details will be same as
in Prob. 8.6.
8.8 At the end of the tenth pulse Q3 = Q1 = 1, the output of G becomes 0. Also
CK = 0, therefore, the output of the latch is 0. Now if Q1 or Q3 goes to 0, the
output of the latch continues to be 0.
When the eleventh clock pulse appears at CK, the output of the latch will go
to 1 and normal counting will proceed.
8.9 (a) For the divide-by-5 circuit, the count sequence will be 000, 001, 010, 011,
100, 000. Therefore, as soon as the count reaches 101, all the three FLIP-
FLOPs must be cleared. The circuit is shown in Fig. Prob. 8.9.

T0 = T1 = T2 = 1

T0 T1 T2
Q0 Q1 Q2
Clock FF0 FF1 FF2
pulses
Cr Q 0 Cr Q 1 Cr Q 2

Fig. Prob. 8.9

(b) For the divide-by-7, the resetting of FLIP-FLOPs is required as soon as

the count reaches 111. Therefore, a 3-input NAND gate with inputs Q0, Q1,
and Q2 will be required to clear the FLIP-FLOPs.
8.10 The waveforms are shown in Fig. Prob. 8.10. It is clear from the waveforms
that the frequency divisions by 3, 6, and 12 are obtained at the QC, QD, and QA
outputs respectively.

98
 1 2 3 4 5 6 7 8 9 10 11 12 13
Clock 1
pulses 0
1
QD
0
1
QC
0
1
QB
0
1
QA
0
Fig. Prob. 8.10
8.11 The states of the circuit of Prob. 8.10 are given below.
QD QC QB QA
0 0 0 0
0 0 1 0
0 1 0 0
1 0 0 0
1 0 1 0
1 1 0 0
0 0 0 1
0 0 1 1
0 1 0 1
1 0 0 1
1 0 1 1
1 1 0 1
0 0 0 0

(a) The ÷ 7 counter is obtained by terminating the count sequence when

QB = QA = 1. The circuit is shown in Fig. Prob. 8.11(a).
Output
QA
QB QC
QD

A input
7 4 9 2
Clock B input
pulses R1 R2

Fig. Prob. 8.11(a)

99
 (b) The ÷ 9 counter is obtained by terminating the count sequence as soon as
QD = QA = 1. The circuit is shown in Fig. Prob. 8.11(b).
Output
QA
QB QC QD

A input
7 4 9 2
Clock
pulses B input R1 R2

Fig. Prob. 8.11(b)

(c) The ÷ 11 counter is obtained by terminating the count sequence as soon as
QD = QC = QA = 1. The circuit is shown in Fig. Prob. 8.11(c).

Output
QA
QB QC QD

A input 7 4 9 2
Clock
pulses B input R1 R2

Fig. Prob. 8.11(c)

8.12 If we use the complements of QD, QC, QB, and QA as outputs, we obtain the
DOWN counter. The sequence is given in Table Prob. 8.12.
QD QC QB QA
0 0 0 0
1 1 1 1
1 1 1 0
1 1 0 1
1 1 0 0
1 0 1 1
1 0 1 0
1 0 0 1
1 0 0 0
0 1 1 1
0 1 1 0
0 1 0 1
0 1 0 0
(Contd.)
100
(Contd.)
QD QC QB QA
0 0 1 1
0 0 1 0
0 0 0 1

8.13 Since 128 = 16 ´ 8, therefore, a divide-by-16 counter followed by a divide-by-

8 counter will become a divide-by-128 counter. IC 7493 is a 4-bit binary
counter. Therefore, two IC packages will be required. The resulting circuit is
shown in Fig. Prob. 8.13.
Q0 Q1 Q2 Q3 Q4 Q5 Q6
QA QB QC QD QA QB QC QD

A input A input
Clock IC1 IC2
pulses 7493 7493
B input R1 R2 B input R1 R2

Logic 0 Logic 0
Fig. Prob. 8.13
8.14 IC7490 is a decade counter. If two such ICs are cascaded, it becomes a divide-
by-100 circuit. To get a divide-by-96 counter, the counter is reset as soon as it
becomes 1001 0110. The complete circuit is shown below.

100 101

QA QB QC QD QA QB QC
QD
A
A input input
Clock IC1 IC2
pulses 7490 7490
B S1 S2 R1 R2 B input S1 S2 R1 R2
input

Fig. Prob. 8.14

101
8.15 Since 78 = 13 ´ 6, therefore, we have to use 7493 as a mod-13 and 7492 as
mod-6 counters. For the mod-13 counter QD, QC, and QA outputs of 7493 are
ANDed and used to clear the counter when the count reaches 1101. For the
mod-6 counter, QA output of 7492 is connected to B input and the QD output of
7493 is connected to A input of 7492. The complete circuit is shown in Fig.
Prob. 8.15.

QA QB QC QD
QA QB QC QD

A input
Clock pulses 7493 A
input 7492
B input R1 R2 B input R1 R2

Fig. Prob. 8.15

8.16 1 2 3 4 5 6 7 8 9 10 11 12 13

Clock
pulses

QA

QB

QC

QD
Fig. Prob. 8.16

102
8.17 1 2 3 4 5 6 7 8 9 10 11 12 13

Clock
pulses
QA

QB

QC

QD

RC

Fig. Prob. 8.17

8.18 The counter have states from 0000 to 1100. The clearing operation will occur
at the rising edge of the next clock. The waveforms are

1 2 3 4 5 6 7 8 9 10 11 12 13 14
Clock
pulses

QA

QB

QC

QD

Cr

Fig. Prob. 8.18

8.19 The counter ICI operates as a counter for counting in the UP direction when Cr
= L = 1. When the count reaches the maximum value (111 in 4-bit binary and
1001 in decade counter) its RC output goes HIGH which makes ENP = ENT
of IC2 HIGH for one clock cycle advancing its output by 1 and making Q

103
 outputs of ICI 0 at the next clock cycle. After this clock cycle ENP = ENT
= 0 for IC2 and IC1 will go on counting the pulses. When the outputs of IC1
and IC2 both reach the maximum count, RC outputs of both of these ICs will
go HIGH. This will make ENP = ENT of IC3 HIGH and therefore, the next
clock pulse will be registered in this counter and simultaneously IC1 and IC2
will be cleared. This way the counting will continue.
8.20 Alternative I: Connect the circuit shown in Fig. Prob. 8.20(a) between the QC,
QD outputs and the clear input (with L = 1). As soon as the count becomes
1100, the counter is cleared.
Alternative II: Connect the circuit shown in Fig. Prob. 8.20(b) between QC, QD
outputs and load (L) input (with Cr = 1). As soon as the count reaches 1100,
the counter is loaded with P inputs which must be PA = PB = PC = PD = 0.
There are two possible operations in this circuit, whereas only one type of
operation is possible in the circuit of Fig. 8.27.

QC QC
Cr L
QD QD
(a) (b)
Fig. Prob. 8.20

8.21 For the DOWN counter, the clock pulses are applied at CK-DOWN input.
When the output becomes 0, the counter is loaded with preset inputs 0101 and
the states will be: 0101, 0100, 0011, 0010, and 0001. The circuit is given in
Fig. Prob. 8.21(a) and waveforms are shown in Fig. Prob. 8.21(b).

QA QB QC QD Carry
+VCC

Borrow
CK-UP
Clock CK-DOWN
74192
pulses
Cr
PA PB PC PD L

+VCC

Fig. Prob. 8.21(a)

104
 Clock 1
pulses
0
1
QA
0
1
QB
0
1
QC
0
1
QD 0

Borrow

Fig. Prob. 8.21(b)

8.22 The modified state diagram is given in Fig. Prob. 8.22(a). Its state table is
given in Table Prob. 8.22(i) from which Table Prob. 8.22(ii) is obtained to
determine the FF inputs.

1 00 1

0 0
11 0 0 01

1 10 1

Fig. Prob. 8.22(a)

Table 8.22(i)

Next State
Present State X=0 X=1
A B A B A B
0 0 1 1 0 1
0 1 0 0 1 0
1 0 0 1 1 1
1 1 1 0 0 0

Table Prob. 8.22(ii)

Counter State FLIP-FLOP Inputs

X QA QB JA KA JB KB
0 0 0 1 X 1 X
0 1 1 X 0 X 1
(Contd.)
105
 (Contd.) Table Prob. 8.22(ii)

Counter State FLIP-FLOP Inputs

X QA QB JA KA JB KB
0 1 0 X 1 1 X
0 0 1 0 X X 1
1 0 0 0 X 1 X
1 0 1 1 X X 1
1 1 0 X 0 1 X
1 1 1 X 1 X 1

This gives JB = KB = 1
and JA = KA = (QB ¤ X)
The circuit is shown in Fig. Prob. 8.22(b).

QB
Logic 1 JB QB JA QA

FFB FFA

KB QB KA QA

Clock
pulses

x = 1 UP
= 0 DOWN
Fig. Prob. 8.22(b)

8.23 A divide-by-5 circuit will give the required input-output relationship. The
states of this circuit are: 000, 001, 010, 011, and 100. The Q2 output will be
the required output when the input waveform is used as the clock input.
8.24 Since there are ten states, therefore, it requires four FFs. The FFs with their
inputs are given as follows.
FF0 : J0, K0
FF1 : J1, K1
FF2 : J2, K2
FF3 : J3, K3
The count sequence and the corresponding values of the FF inputs re-
quired to get the count sequence are given below. The unused states are
taken as don’t care (X) conditions.
Count Sequence FF Inputs
Q3 Q2 Q1 Q0 J0 K0 J1 K1 J2 K2 J3 K3
0 0 1 1 X 1 X 1 1 X 0 X
0 1 0 0 1 X 0 X X 0 0 X
(Contd.)

106
(Contd.)
Count Sequence FF Inputs
Q3 Q2 Q1 Q0 J0 K0 J1 K1 J2 K2 J3 K3
0 1 0 1 X 1 1 X X 0 0 X
0 1 1 0 1 X X 0 X 0 0 X
0 1 1 1 X 1 X 1 X 1 1 X
1 0 0 0 1 X 0 X 0 X X 0
1 0 0 1 X 1 1 X 0 X X 0
1 0 1 0 1 X X 0 0 X X 0
1 0 1 1 X 1 X 1 1 X X 0
1 1 0 0 1 X 1 X X 1 X 1
0 0 1 1

Using K-maps, the expressions for FF inputs can be minimized and the
minimized expressions are:
J0 = K0 = 1
J1 = Q1 ⋅ Q0 + Q3 ⋅ Q2
K1 = Q0
J2 = Q1 ⋅ Q0
K2 = Q1 ⋅ Q0 + Q3 ⋅ Q2
J3 = Q2 ⋅ Q1 ⋅ Q0
K3 = Q2
Using the FLIP-FLOPs and the above expressions, the circuit can be
drawn.
8.25 The circuit is given in Fig. Prob. 8.25.

Pulses QA QB QC QD
ENT
Logic 1 74163
ENP
Load Cr

Logic 1

Fig. Prob. 8.25

107
8.26 (a)
Q1

Q1
Q0

Q1
Q0 Q1
D1
FF1
Q1

Q0 X

Q0
Q0
D0
FF0
Q0

Clock
Fig. Prob. 8.26(a)
(b)
0/0

00
1/1 1/0
0/0
11 01
0/0

1/0 1/0
10

0/0

Fig. Prob. 8.26(b)

(c)
Present State Input Next state Output FF Inputs
FF1 FF0
Q1 Q0 X Q1* Q0* Y J1 K1 J0 K0
0 0 0 0 0 0 0 X 0 X
0 0 1 0 1 0 0 X 1 X
(Contd.)
108
(Contd.)
Present State Input Next state Output FF Inputs
FF1 FF0
Q1 Q0 X Q1* Q0* Y J1 K1 J0 K0
0 1 0 0 1 0 0 X X 0
0 1 1 1 0 0 1 X X 1
1 0 0 1 0 0 X 0 0 X
1 0 1 1 1 0 X 0 1 X
1 1 0 1 1 0 X 0 X 0
1 1 1 0 0 1 X 1 X 1

Q1Q0 Q1Q0
X 00 01 11 10 X 00 01 11 10
0 0 0 ´ ´ 0 ´ ´ 0 0
1 0 1 ´ ´ 1 ´ ´ 1 0
J1 = Q0× X K1 = Q0× X
Q1Q0 Q1Q0
X 00 01 11 10 X 00 01 11 10
0 0 ´ ´ 0 0 ´ 0 0 ´
1 1 ´ ´ 1 1 ´ 1 1 ´
J0 = X K0 = X
Y = Q1 × Q0 × X

X
J1 Q1
FF1
K1 Q1

J0 Q0
FF0
K0 Q0

Clock
Fig. Prob. 8.26(c)

8.27 (a) D1 = Q1 ⊕ X
D0 = Q0 ⊕ Q1

Z = Q1 ⋅ X + Q0
109
 (b) The state table will be
Present State Input Next State Output
Q1 Q0 X Q1* Q0* Z
0 0 0 0 0 1
0 0 1 1 0 0
1 0 0 1 1 0
1 0 1 0 1 0
1 1 0 1 0 1
1 1 1 0 0 1
0 1 0 0 1 1
0 1 1 1 1 1

Here, the initial state has been assumed as Q1 Q0 = 00 and correspondingly

the other states have been assigned.
From the table, we obtain the output sequence as 001110.
8.28
Present State Input Next State FF inputs
FF1 FF0
Q1 Q0 X Q1* Q0* J1 K1 J0 K0
0 0 0 0 0 0 X 0 X
0 0 1 0 1 0 X 1 X
0 1 0 1 0 1 X X 1
0 1 1 0 1 0 X X 0
1 0 0 1 0 X 0 0 X
1 0 1 1 1 X 0 1 X
1 1 0 1 1 X 0 X 0
1 1 1 0 0 X 1 X 1

From the state diagram, state table as shown above is prepared and inputs to
FF0 and FF1 are obtained using the excitation table of J-K FF.
K-maps are prepared for J1, K1, J0, and K0 with Q1, Q0, and X as the input
variables as given below.

Q1Q0 Q1Q0
X 00 01 11 10 X 00 01 11 10
0 0 1 ´ ´ 0 ´ ´ 0 0
1 0 0 ´ ´ 1 ´ ´ 1 0
J1 = Q0× X K1 = Q0× X
Q1Q0 Q1Q0
X 00 01 11 10 X 00 01 11 10
0 0 ´ ´ 0 0 ´ 1 0 ´
1 1 ´ ´ 1 1 ´ 0 1 ´
J0 = X K0 = Q1 ¤ X
Fig. Prob. 8.28(a)
The circuit can be drawn using the above expressions.
110
 J0 Q0 J1 Q1

FF0 FF1

K0 Q0 K1 Q1

Clock
X
Fig. Prob. 8.28 (b)

8.29 The State table along with the inputs required for T, S-R, and J-K FLIP-
FLOPs are given in the Table. From this the simplified expressions for
these inputs are obtained using K-maps. These are

(a) T2 = Q 2 ⋅ Q1 ⋅ Q 0 ⋅ X + Q 2 ⋅ X + Q 0 ⋅ X

T1 = Q 0 + Q 2 ⋅ Q1 ⋅ X + Q 2 ⋅ Q1 ⋅ X + Q 2 ⋅ Q1 ⋅ X

T0 = Q 0 + Q1 X

and Y = Q0 ⋅ X

(b) S2 = Q 0 ⋅ X + Q1 ⋅ Q 0 ⋅ X

R2 = Q 0 ⋅ X

S1 = Q 0 + Q 2 ⋅ X

R1 = Q 2 ⋅ X + Q 2 ⋅ Q 0 ⋅ X

S0 = Q 1 ⋅ Q 0 ⋅ X
R0 = Q0

and Y = Q0 ⋅ X

(c) J2 = Q1 ⋅ Q 0 ⋅ X + Q 0 ⋅ X
K2 = X

J1 = Q 0 + Q 2 ⋅ X

K1 = Q 2 ⋅ X + Q 2 ⋅ X

J0 = Q1 ⋅ X
K0 = 1

and Y = Q0 ⋅ X
The complete circuits can be drawn using the above expressions.
111
112
8.30 Table 8.17 along with the inputs J2, K2, J1, K1, J0, and K0 required for the FFS
is given below.
Present State Input Next State Output FF inputs
Q2 Q1 Q0 X Q2* Q1* Q0* Y J2 K2 J1 K1 J0 K0
0 0 0 0 0 1 0 0 0 X 1 X 0 X
0 0 0 1 0 0 1 0 0 X 0 X 1 X
0 0 1 0 1 0 0 0 1 X 0 X X 1
0 0 1 1 0 1 0 0 0 X 1 X X 1
0 1 0 0 0 1 1 1 0 X X 0 1 X
0 1 0 1 1 0 0 1 1 X X 1 0 X
0 1 1 0 1 0 0 0 1 X X 1 X 1
0 1 1 1 0 0 0 1 0 X X 1 X 1
1 0 0 0 0 1 1 1 X 1 1 X 1 X
1 0 0 1 1 0 0 0 X 0 0 X 0 X

The simplified expressions are:

J2 = Q 0 ⋅ X + Q1 ⋅ Q 0 ⋅ X
K2 = X
J1 = Q 0 ⋅ X + Q 0 ⋅ X
K1 = Q0 + X
J0 = Q 2 ⋅ Q1 ⋅ X + Q1 ⋅ X + Q 2 ⋅ X
K0 = 1
Y = Q 2 ⋅ X + Q1 ⋅ X + Q1 ⋅ Q 0
The Complete circuit can be drawn using the above expressions.
8.31 The state diagram is given below.

1/0 1/0
000 001 010

1/0 1/0 1/1 1/0

0/0

111 011

1/1 0/0 0/0

0/1

110 0/1 101 100

0/0 1/0

0/0 0/1

Fig. Prob. 8.31

113
 From Table 8.18 we observe that from the present states 001 and 100, the
next states and the outputs are same. This means these two states are identical
and one of them can be eliminated. Similarly, the states 011 and 111 are
identical. Therefore, eliminating the states 100 and 111 we obtain Table
Prob. 8.31 (a). From this we observe that the states 000 and 010 are identical.
Therefore, the state 010 can be eliminated and the reduced state table is
given in Table Prob. 8.31 (b).

Table Prob. 8.31(a)

Present State Next State Output
Q2 Q1 Q0 X=0 X=1 Y
Q2* Q1* Q0* Q2* Q1* Q0* X=0X=1
0 0 0 1 0 1 0 0 1 0 0
0 0 1 0 1 1 0 1 0 0 0
0 1 0 1 0 1 0 0 1 0 0
0 1 1 1 1 0 0 0 0 1 0
1 0 1 1 0 1 0 0 1 1 1
1 1 0 1 1 0 0 1 1 0 1

Table Prob. 8.31 (b)

Present State Next State Output
Q2 Q1 Q0 X=0 X=1 Y
Q2* Q1* Q0* Q2* Q1* Q0* X=0X=1
0 0 0 1 0 1 0 0 1 0 0
0 0 1 0 1 1 0 0 0 0 0
0 1 1 1 1 0 0 0 0 1 0
1 0 1 1 0 1 0 0 1 1 1
1 1 0 1 1 0 0 1 1 0 1

8.32 (a) The circuit can be designed using the method similar to that of Example
8.15.
(b) The circuit can be designed using the method similar to the design of
Probs. 8.26(c), 8.28, 8.29(c), and 8.30.
8.33 The output sequence can be obtained similar to Prob. 8.27(b) and is given
below.
01000111010
8.34 (a) (i) The circuit is initially in stable total state 0001 (first row, second
column). When X1, X2 because 11, the state transitions will be
00 ® 11 ® 11
Shown in the Fig. Prob. 8.34(a) (i) by solid arrows.

114
 X1 X2
Q1 Q2 00 01 11 10
00 00 11

01 10

11 11

10 10

Fig. Prob. 8.34(a) (i)

Since, both the states are required to change here, therefore, race con-
dition exists and the circuit will either attain 01 or 10 state first. If it is
01, state transitions will be
00 ® 01 ® 10 ® 10
Shown in the Fig. Prob. 8.34(a) (i) by dotted arrows. If it is 10, the
circuit goes to 10 stable state from 10 unstable state.
00 ® 10 ® 10
(ii) The circuit is initially in stable total state 1111 (third row, third col-
umn).
When X1 X2 becomes 01, the state transitions will be
11 ® 00 ® 00
It is shown by solid arrows in Fig. Prob. 8.34(a) (ii)
Here again both the states are required to change, therefore, race condi-
tion exists. The circuit will be making transitions.
11 ® 10 ® 00 ® 00
or
11 ® 01 ® 00 ® 00
depending upon whether Q1 changes first or Q2 changes first. Both are
shown in Fig. Prob. 8.34(a) (ii)
X1 X2
Q1 Q2 00 01 11 10
00 00

01 00

11 00 11

10 00

Fig. Prob. 8.34 (a) (ii)

(b) In (a)-(i)
The circuit is required to change from stable state 00 to stable state 11 , but
due to unequal time delays, the circuit goes to stable state 10 which shows
that the race is critical. In (a)-(ii).
115
 The state change is from 11 to 00 through both the paths and therefore,
the race is non-critical.

8.35 (a) X1 X2
Q 2 Q2 00 01 11 10

00 00 – 01 00

01 00 11 01 01

11 – 11 11 01

10 – – – –

Fig. Prob. 8.35 (a) Transition Table

For X1 X2 = 00, the next state specified is 00, therefore, the entry in the
first row, first column will be 00 . When X1 changes to 1 while X2 = 0,
again the next state specified is 00, therefore, the entry in the first row,
fourth column will be 00 . Similarly, squares corresponding to input
sequence are filled. These are shown in Fig. Prob. 8.35(a). All the remain-
ing squares are unspecified.
(b) K-maps are prepared for Q1+ and Q 2+ from the state transition table. These
are shown in Fig. Prob. 8.35(b).

X1 X 2 X1 X2
Q1 Q2 00 01 11 10 Q1 Q2 00 01 11 10

00 0 ´ 0 0 00 0 ´ 1 0

01 0 1 0 0 01 0 1 1 1

11 ´ 1 1 0 11 ´ 1 1 1

10 ´ ´ ´ ´ 10 ´ ´ ´ ´

(i) K-map for Q 1+ (ii) K-map for Q 2+

Fig. Prob. 8.35 (b)

The next state logic equations are

Q1+ = X 1 X2 + X2 Q1

Q 2+ = X2 + X1 Q2

116
 (c) The logic circuit is shown in Fig. Prob 8.35 (c).

X1
X2
Q1+
X2
Q1

X1
Q2
Q2+

Fig. Prob. 8.35(c) Logic diagram

8.36 When the circuit is in stable state e inputs can change to 01 or 10.
When X1 X2 = 01, the output Y may be 0 or 1 and the next-state will be b.
Since for the stable state b , the output is 0 and for the stable state e the
output is 1, while transition from e ® b ® b , the output may change dur-
ing unstable b or stable b .
Similarly, when X1 X2 = 10, X2 has changed while X1 = 1, therefore, Y = 1
and the next state will be f and then f .
X1 X2 = 00, is not possible when the circuit is in stable state e , therefore,
the next state and the output are unspecified for X1 = X2 = 0 and the entry in
the first column, fifth row will be –, –.
When the circuit is in stable state f , the input can change to 00 or 11.
If it changes to 00, the next-state will be a and the output may be 0 or 1,
since the outputs for stable states f and a are 1 and 0 respectively.
When X1 X2 becomes 11, the next-state will be e and since X1 = 1 and X2 is
changing state, therefore, Y = 1. From f , it can not go to X1 X2 = 01, there-
fore, the entries in the second column, sixth row will be –, –.

117
 CHAPTER 9

9.1 Let us assume that the voltage vc = V(0), i.e., the voltage corresponding to
LOW level, at t = 0. Therefore, vo = V(1), the output of the AND gate will be
V(1) which will charge the capacitor C with the time constant t = RC. When vc
reaches V(1), the output of the inverter goes to V(0), thereby discharging the
capacitor with the same time constant through the output transistor of the AND
gate, and so on. Thus, square waveform will be generated at the output. The
waveforms of vc and vo are illustrated below.

vc

V(1)
t
t
V(0)
t
vo

V(1)

V(0)
t
0 T1 T2
Fig. Prob. 9.1

9.2 Let vo be in logic 0 state under steady-state condition. The output of the NAND
gate will be logic 1; the capacitor will get charged to voltage V(1) making the
input to the inverter as logic 0 which produces logic 1 at the output. This
shows that it is not possible for vo to be in logic 0 state under steady state.
9.3 When the voltage vi at the input is very low, the output voltage will be maxi-
mum positive. It will saturate at vo = VD + VZ1. This makes the voltage at the
non-inverting input terminal as
R2 R1
(V Z 1 + V D ) + V
R1 + R 2 R1 + R 2 R
When the voltage at the input increases and passes through the above voltage,
the output voltage vo will change from (VD + VZ1) to – (VZ2 + VD). Hence
R2 R1
VUT = (V Z 1 + VD ) + V
R1 + R 2 R1 + R 2 R
Now, when vi > VUT ,
vo = – (VZ2 + VD)
This gives voltage at the non-inverting input terminal as
R2 R1
− (V Z 2 + V D ) + V
R1 + R 2 R1 + R 2 R
118
 When the voltage at the input decreases and passes through this value, the
output vo changes from – (VZ2 + VD) to + (VZ1 + VD). Hence

R2 R1
VLT = − (V + VD ) + V
R1 + R 2 Z 2 R1 + R 2 R
9.4 Using the expressions for VUT and VLT derived in Prob. 9.3, we obtain

0.1 ( 4. 6 + 0. 6 ) + 100 (1)

VUT =
100 + 0.1 100 + 0.1
» 1.0042 V

0. 1 ( 4. 6 + 0. 6) + 100 (1)
VLT = −
100 + 0. 1 100 + 0. 1
» 0.9938 V
The input waveform is shown in Fig. Prob. 9.4(a) with VUT and VLT marked.
When the input voltage is zero, the output is + 5.2 V. Now, when the
increasing input voltage passes through the voltage VUT, the output changes
from +5.2 V to –5.2 V and remains at that level as long as the input
voltage is higher than VLT. As soon as the decreasing input voltage passes
through VLT, the output comes back to +5.2 V. The output waveform is
illustrated in Fig. Prob. 9.4(b).
vi

5V

VUT
VLT
0 t

-5V
(a)
vo

5.2 V

0 t

-5.2 V

(b)
Fig. Prob. 9.4
119
9.5 The maximum negative output voltage Vo′ and the maximum positive output
voltage Vo′′ are given by

Vo′ = VZ2 + VD1

and Vo′′ = VZ1 + VD2

Let us assume the output voltage to be maximum positive (V 0′′ ). The capacitor
C will be charging from –b Vo′ to Vo′′ with the time constant t = RfC, where b
= (R2/R1 + R2). The capacitor voltage is given by
vc = V o′′ – (Vo′′ + b Vo′ )e – t/t

at t = T1, vc = b Vo′′

\ b Vo′′ = Vo′′ – ( Vo′′ + b Vo′ ) e- T1 /t

Vo′′ + bVo′
or T1 = t 1n
Vo′′ (1 − b )

At T1, the output voltage changes from positive maximum to negative maxi-
mum ( Vo′ ). Consequently, the capacitor will discharge with the same time
constant from b Vo′′ to – Vo′ . However, the discharge will be terminated as soon
as vc reaches –b Vo′ , at which time the output will swing back from – Vo′ to
+ Vo′′ . During the discharging of the capacitor.

vc = – Vo′ + ( Vo′ + b V o′′ ) e – t/t

at t = T2, vc = b Vo′

\ b Vo′ = – Vo′ + ( Vo′ + b V o′′ ) e–T2/t

Vo′ + bVo′′
or T2 = t 1n
Vo′ (1 − b )

The charging and discharging will go on in the same way and the time period
of the resulting output square waveform will be
T = T1 + T2
1 1
and the frequency = f = =
T T1 + T2
9.6 During the interval T1 when vo is positive, the feedback resistance R¢f in series
with the conducting diode D will be in the circuit. Similarly, during the inter-
val T2 when the output is negative, R¢¢f in series with the conducting diode will
be effective. Therefore, the output voltage levels will be
Vo′ = VZ2 + VD1 – VD » VZ2
and Vo′′ = VZ1 + VD2 – VD » VZ1

120
 If we assume identical Zeners for convenience, and R¢f = R¢¢f, the square wave
will be symmetrical. In case R¢f ¹ R¢¢f , the periods T1 and T2 can be obtained
using the relationships derived in Prob. 9.5 and are given by

Vo′′ + bVo′
T1 = t 1 1n , t 1 = R ′f C
Vo′′(1 − b )

Vo′ + bVo′′
and T2 = t 2 1n , t 2 = R ′′f C
Vo′ (1 − b )

The output voltage waveform is shown in Fig. Prob. 9.6.

v
vo
V ¢¢o
bVO¢¢

vc
t1
0 t
t2

-bV¢¢O
- VO¢

T1 T2 T3 T4

Fig. Prob. 9.6

9.7 If vo = –Vo under steady-state, the capacitor C will get charged with the
polarity opposite to that indicated in the figure. When the capacitor voltage
passes through the voltage bVo, the output voltage will go to +Vo. This shows
that the output voltage cannot remain as –Vo under steady-state.
9.8 When the output voltage is in logic 1 state, i.e., V(1), the capacitor C charges
with the time constant t = RC. The charging gets terminated when vc reaches
VUT and the output changes to V(0) = 0 V.
Now, the capacitor discharges with the same time constant until its voltage
becomes VLT. At this voltage, the output goes back to V(1). The timings T1 and
T2 corresponding to the charging and discharging of C respectively are given
by
V (1) − V LT
T1 = RC 1n
V (1) − VUT

VUT
and T2 = RC 1n
V LT
121
 Hence,
é V (1) - VLT VUT ù
T = T1 + T2 = RC ê1n + 1n ú
ë V (1) - VUT VLT û

9.9 An astable multivibrator with T1 = 30 s and T2 = 60 s can be used for this

purpose. A circuit using OP AMP Schmit trigger circuit is shown below. In
this circuit when the output is positive, diode D3 conducts and the RED bulb
is ON. On the other hand, the diode D4 will conduct when the output is
negative and consequently the GREEN bulb will be ON. Assuming identical
Zener diodes, we obtain (using the results of Prob. 9.6),
1+ β
T1 = τ 1 1n
1− β

R¢f D1

R¢¢f D2

– R vo
+ –
R1 VZ D3 D4
+
+
C VZ
R2 – GREEN
RED

Fig. Prob. 9.9

1+β
and T2 = τ 2 1n
1−β

Let R1 = R2 = 100 kW, and C = 1000 mF

1
\ b =
2

R¢f = 27.3 kW
and R¢¢f = 54.6 kW
9.10 (a) The pulse duration is given by
TON » 0.7 RC
Assuming R = 1.5 kW

0. 2 × 10 −6
C = ≈ 200 pF
0. 7 × 1. 5 × 10 3

122
 (b) The pulse duration for C < 1000 pF is given by the graph shown in Fig.
Prob. 9.8. Assuming R = 10 kW, we obtain from the graph C » 35 pF.

10000
7000
4000

TON Output pulse width, ns

2000 122
123
1000
700
400
200
100 R = 50 kW
70 R = 30 kW
40 R = 20 kW
R = 10 kW
20
R = 5 kW
10
1 2 4 10 20 40 100 200 400 1000
CEXT External timing capacitance, pF
Fig. Prob. 9.8
9.11 (a) Here R = 2 kW

5 × 10 −3
\C= = 3. 57 µF
0. 7 × 2 × 10 −3
The duty cycle is 67% with the internal resistor. Therefore, the time
period,

5
T = = 7. 5 m s
0. 67
and the maximum frequency,

fmax = 1 ≈ 134 Hz
7. 5 × 10 −3

5 × 10 −3
(b) C= ≈ 178. 6 nF
0. 7 × 40 × 10 3
The duty cycle is 90% with an external resistance of 40 kW.
Therefore, the maximum frequency,
fmax = 180 Hz
9.12 The frequency and duty cycle are given by
1. 4
f= (9.1)
C (RA + 2RB )

RA + RB
and D = × 100 (9.2)
RA + 2RB
123
 From Eq. (9.2)
RA + RB
60 = × 100
RA + 2RB
or RB = 2RA, Assuming RA = 1 kW
Now, from Eq. (9.1), we obtain

1. 4
C= ≈ 4. 67 nF
×
3 10 3 × 100 × 10 3
The circuit is shown in Fig. Prob. 9.12.
VCC

RA
4 8
7

2 RB
555
6
+
C vC
–
1 3 vO
5

0.01 mF
Fig. Prob. 9.12
9.13 (a) When the voltage across the capacitor (vc) is increasing and is less than
2/3 VCC, the output voltage is HIGH and the capacitor charges with the
time constant t1 = RAC. When vc reaches 2/3 VCC, the capacitor gets
discharged through RA and RB with the time constant t2 = (RA||RB) C and
the output voltage drops to 0 V. As soon as this decreasing voltage crosses
1/3 VCC, the charging starts again. The waveforms of vc and output voltage,
vo are illustrated in Fig. Prob. 9.13(a).
(b) The circuit corresponding to the charging of the capacitor C is shown in
Fig. Prob. 9.13(b) and corresponding to the discharging is shown in Fig.
Prob. 9.13(c).
During charging the voltage across the capacitor, vc, is given by

vc = 1 VCC + 2 VCC (1 − e − t / τ 1 )
3 3
at t = T1, vc = 2 VCC
3
124
 vC
To VCC

2/3VCC
t2
t1

1/3VCC

To 0V

0 t
T1 T2

vo

V(1) t

0
T

(a)

VCC
RA
RA
+
vC C RB VCC
+ –
vC C
–

(b) (c)

Fig. Prob. 9.13

\ e - T1 /t 1 = 1
2
or T1 » 0.7 t1 = 0.7 RAC
During discharging, vc is given by

é2 RB ù RB
vc = ê VCC - VCC ú e - t /t 2 + VCC
ë3 R A + RB û R A + RB
1
at t = T2, vc = 3
VCC
which gives
R A RB é 2 R A - RB ù
T2 = C 1n ê ú
+
RA RB ë RA - 2 RB û
125
 RA RB é 2 RA - RB ù
\ T = T1 + T2 = 0.7 RAC + C 1n ê ú
RA + RB ë RA - 2 RB û
Duty cycle = T1/T ´ 100%
(c) From the expressions for T1 and T2 obtained in part (b), we observe that it
is possible to make T1 = T2 (i.e., 50% duty cycle). The condition which
must be satisfied to achieve this is
R A RB é 2 R A - RB ù
0.7RA = 1n ê ú
RA + RB ë RA - 2 RB û
(d) If RB = 20 kW
From part (a), we obtain

RA 20 é 2 RA - 20 ù
1n ê ú = 0.7 R A
RA + 20 ë RA - 40 û

or RA » 48 kW
RB R
(e) From Fig. Prob. 9.13 c, we obtain VCC < 1 VCC , or R B < A
RA + RB 3 2
9.14 (a) The input pulses and the corresponding output for this monostable circuit
of Fig. 9.35 are given in Fig. Prob. 9.14.

T1

Input
pulses A B
Output

1
T

Fig. Prob. 9.14

The output is in LOW state until the first falling edge (A) appears, at which
time it goes HIGH. It remains HIGH for a period T = 1.1 RAC and then
goes LOW. It will remain LOW till the next negative edge (B) appears.
If (n – 1) T < T < nT1
where n is an integer, then the frequency of the output waveform will be

fi æ 1ö
fo = ç fi = ÷
n è T1 ø

Thus the circuit functions as a frequency divider.

126
 (b) Here T1 = 1 m s
10
Choose RA and C values in Fig. 9.35 such that
0.2 ms < T < 0.3 m s
Since T = 1.1 RAC
Therefore, if we choose RA = 2.2 kW and C = 0.1 mF
then T = 0.242 m s
9.15 If the output is in HIGH state under steady-state, the transistor T1 of the timer
is cut-off and the capacitor is therefore getting charged. When the voltage
across the capacitor reaches 2/3 VCC, the transistor goes to saturation, thereby
discharging C and the output goes LOW. Hence, it is not possible for the
circuit to be in HIGH output state under steady-state.
9.16 In the circuit of Fig. 9.35, if we connect pin-4 (Reset) to pin-2 (Trigger) it
becomes a retriggerable monostable multivibrator. In this circuit, whenever the
trigger pulse goes LOW, the circuit is reset, i.e., the output and the discharge
terminals go LOW. When the input pulse goes from LOW to HIGH, the output
goes to HIGH for a time period T = 1.1 RC. Thus, the circuit becomes a
retriggerable monostable multivibrator.

127
 CHAPTER 10

10 10 S
10.1 The step size or resolution = = V. As long as DV < , i.e.,
2 8 − 1 255 2
5/255 V the least-significant bit will be significant.
10.2 The analog output voltages for each of the digital inputs are given below.
From this we observe that this circuit converts digital inputs in one’s com-
plement format to analog output.

Digital Input Output voltage Output due Net Output

S2 S1 S0 without offset to offset Vo
0 0 0 – 3.5 + 3.5 0
0 0 1 – 2.5 + 3.5 1
0 1 0 – 1.5 + 3.5 2
0 1 1 – 0.5 + 3.5 3
1 0 0 + 0.5 – 3.5 –3
1 0 1 + 1.5 – 3.5 –2
1 1 0 + 2.5 – 3.5 –1
1 1 1 + 3.5 – 3.5 0

10.3 (i) Let b3 = 0, b2 = 1 and b1 = b0 = 0.

The equivalent circuit corresponding to the lower order four bits is shown
in Fig. Prob. 10.3(a). From this we obtain
VR (8 /11R)
Iin = ×
r (8 /11R) ( r + 8 /11R)
2R +
( r + 8 /11R )

VR
The current due to b6 is
2R

V R (8/ 11R ) VR
\ =
2 R( r + 8 /11R) + r (8/ 11r ) 16 × 2 R
or r=8R
RF

b2 2R r
-
Iin VO
+
VR R||4R||8R

Fig. Prob. 10.3(a)

(ii) Let b3 = b2 = b0 = 0, and b1 = 1. The corresponding equivalent circuit is

shown in Fig. Prob. 10.3(b).
128
 VR (8 /13 R)
Iin = ´
r (8 /13 R ) ( r + 8 /13 R)
4R +
r + 8 /13 R
VR
The current due to b5 is .
4R
To satisfy the same condition, we obtain
r = 8 R.

RF

b1 4R r Iin
-
VO
+
VR R||2R||8R

Fig. Prob. 10.3(b)

(iii) Let b3 = b2 = b1 = 0, and b0 = 1

The equivalent circuit is shown in Fig. Prob. 10.3(c) from which we obtain

VR ( 4 / 7 R)
Iin = ×
r ( 4 / 7 R) ( r + 4 / 7 R)
8R +
( r + 4 / 7 R)

The current due to b4 is VR/8R. Therefore, to satisfy the same condition, we

obtain
r = 8R

RF

b0 8R r
-
Iin VO
+
VR R||2R||4R

Fig. Prob. 10.3 (c)

10.4 The modified circuit will be equivalent to the circuit given in Fig. 10.4.
The analog output voltages for various digital inputs are given in table
The output voltage is given by

æ RF RF RF ö
Vo = - ç Vo + V1 + V2 ÷
è R R /2 R /3 ø

129
 R
S0 RF = R

R/2
S1 -
VO
+
R/3
S2
Fig. Prob. 10.4
1
where Vn = – 2
if Sn = 1
1
=+ 2
if Sn = 0.

Table Prob. 10.4

Digital Inputs Analog Output

S2 S1 S0 V
0 0 0 0
0 0 1 +1
0 1 0 +2
0 1 1 +3
1 0 0 –3
1 0 1 –2
1 1 0 –1
1 1 1 0

We observe from the table that this circuit also converts digital input in one’s
complement format to analog output.
10.5 The circuit for 4-bit D/A converter is shown in Fig. Prob. 10.5. This circuit
without offset gives an analog output of –7.5 V for the digital input 0000 and
0 1
+
-
1/2 V- S2 1/2 V
+
ROFF
1 R

0
1 R/2 RF = R
0
-
R/4 VO
1 +
0

1 R/8
0
V (1) = -1/2 V V (0) = 1/2 V

Fig. Prob. 10.5

130
 +7.5 V for the digital input 1111. Therefore, the offset required is +7.5 V for
0000 input and –7.5 V for 1111 input.
R
Therefore, ROFF =
15
10.6 When the 4-bit digital input is 0000, the output voltage will be
1 æ RF RF RF RF ö
- çè - R + R /4 + R /2 + R ÷ø
2 X

where, RX is the resistance in the path of switch S 3 . This voltage must be 0.

Therefore,
R
RX = 4 + 2 + 1
or RX = R/7
The resulting circuit is shown in Fig. Prob. 10.6.
R
S0 RF = R

R/2
S1
-
R/4 VO
S2 +
R/7
S3
Fig. Prob. 10.6

10.7 Let the analog voltage range be from –V0 to +V0. The step size will be 2/7 V0.
The reference voltages are given below. There is one more negative number
than the positive numbers in 2’s complement representation. The circuit is
shown in Fig. Prob. 10.7.
Reference voltages 2’s complement digital output
V0
S 011
VR7 = 5/7 V0
010
VR6 = 3/7 V0
001
VR5 = 1/7 V0
0 000
VR4 = –1/7 V0
111
VR3 = –3/7 V0
110
VR2 = –5/7 V0
VR1 = –V0 101
100
–9/7 V0

If we choose to ignore 100 output, the resistor chain will be connected between
+V0 and –Vo and only six comparators will be required. The decoder circuit
can be designed in the usual manner.
131
 V

Va
Analog voltage
VR7 = +5/7 V0 –

R + C7

VR6 = +3/7 V0 –

R + C6

VR5 = +1/7 V0 –
L D
+

Two’s complement
R C5 A E
T C B2 ü
–
VR4 = –1/7 V0 C O ï

format
+ H D B1 ý
C4
R E E ï
B0 þ
– S R
VR3 = –3/7 V0
+ C3
R
VR2 = –5/7 V0 –
+ C2
R

VR1 = –V0 –

R + C1

–9/7 Vo
Fig. Prob. 10.7
10.8 The conversion time t is given by
Va
t = 2 N ⋅ TC +
⋅ 2 N ⋅ TC
VR
where, N is the number of bits in the digital output,
TC is the time period of the clock,
Va is the analog voltage, and
VR is the reference voltage.
The largest Va can be equal to VR.
Therefore, when Va = VR
t = 2 N + 1 ⋅ TC = 2 13 × 10 −5

10 5
or, f<
8192
Therefore, f < 12 per second.

132
10.9 The voltage step =
10
V
26 −1

10
= V
63
10.10 (a) DAC 80 is a 12-bit D/A converter.
(i) Complementary binary input (CBI)
Table Prob. 10.10(a) gives the voltage corresponding to LSB for each of
the ranges.

Table Prob. 10.10(a)

Analog output Voltage corresponding
range to LSB
0 to ± 2.5 V 1.22 mV
0 to ± 5 V 2.44 mV
0 to ± 10 V 4.88 mV
0 to + 5 V 1.22 mV
0 to + 10 V 2.44 mV

(ii) Complementary coded decimal code (CCD) input

The analog output range for this code is 0 to + 10 V. Therefore, the
voltage corresponding to LSD = 10/1000 = 10 mV
(b) ADC 80 is a 12-bit A/D converter. The voltages corresponding to LSB for
various analog input ranges are given in Table Prob. 10.10(b).

Table Prob. 10.10(b)

Analog input Voltage corresponding
voltage range to LSB
± 2.5 V 1.22 mV
±5V 2.44 mV
± 10 V 4.88 mV
0 to 5 V 1.22 mV
0 to 10 V 2.44 mV

10.11 (a) CSB: It is complementary straight binary code. For example, the straight
binary code for decimal 2 is 0010. Decimal 2 will be coded in CSB as
complement of 0010, which is 1101.
(b) COB: It is complementary offset binary code. It is determined by finding
out CSB and then offsetting it by –2n – 1. Where n is the number of bits
used to represent the number. For example, decimal 2 will be coded as
1101 – 1000 = 0101.
(c) CTC: It is complementary two’s complement code. It is obtained by
complementing two’s complement, for example, two’s complement rep-
resentation of – 2 is 1110 and therefore, it will be coded in CTC as 0001.
(d) CCD: It is complementary coded decimal code. It is obtained by
complementing the natural BCD code. For example, natural BCD code
133
for decimal 2 is 0010 and therefore, it will be coded in CCD as 1101.
Table Prob. 10.11 gives the decimal number for each of the 4-bit binary
numbers in each of the above codes.

Table Prob. 10.11

Binary Equivalent decimal values
CSB COB CTC CCD
0000 15 +7 –1 –
0001 14 +6 –2 –
0010 13 +5 –3 –
0011 12 +4 –4 –
0100 11 +3 –5 –
0101 10 +2 –6 –
0110 9 +1 –7 9
0111 8 0 –8 8
1000 7 –1 +7 7
1001 6 –2 +6 6
1010 5 –3 +5 5
1011 4 –4 +4 4
1100 3 –5 +3 3
1101 2 –6 +2 2
1110 1 –7 +1 1
1111 0 –8 0 0

134
 CHAPTER 11

11.1 The number of pins P is given by

2P = M
(a) P = 2
Address range: A1A0 = 00 to 11
(b) P = 4
Address range: A3A2A1A0 = 0000 to 1111
(c) P = 6
Address range: A5A4A3A2A1A0 = 000000 to 111111
(d) P = 8
Address range:
A7A6A5A4A3A2A1A0 = 00000000 to 11111111
(e) P = 10
Address range:
A9A8A7A6A5A4A3A2A1A0 = 0000000000 to 1111111111
(f) P = 11
Address range:
A10A9A8A7A6A5A4A3A2A1A0 = 00000000000 to 11111111111
(g) P = 16
Address range:
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 =
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
to
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
(h) P = 20
Address range:
A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0=
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 to
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
11.2 (a) 0 to 3; 0 to F; 00 to 3F; 00 to FF; 000 to 3FF; 000 to 7FF; 0000 to FFFF;
00000 to FFFFF.
(b) 0 to 3; 00 to 17; 00 to 77; 000 to 377; 0000 to 1777;
0000 to 3777; 000000 to 177777; 0000000 to 3777777.
11.3 The maximum access rate = 1/Cycle time gives the maximum rate for each
memory. It is given below for each memory.
Memory Maximum rate
1
A × 10 9 = 666666/s
1500
1
B × 10 9 = 1724137/s
580
(Contd.)

135
(Contd.)
Memory Maximum rate
1
C × 10 9 = 2222222/s
450
1
× 10 9 = 5 ´ 10 /s
6
D
200
1
E × 10 9 = 16666666/s
60
1
F × 10 9 = 1250000/s
800

11.4 (a) 4 chips of 2142 and one 1-out of-4 (i.e., 2-line-to-4-line) decoder IC will
be required.
(b) 2 chips of 2142.
(c) 16 K bytes = 16 K ´ 8 = (16 ´ 1024) ´ (4 ´ 2)
= 32 ´ (1024 ´ 4)
Therefore, 32 chips of 2142 will be required. One 1-out of-16 decoder will
be required to select a specific chip pair.
11.5 (a) Since the total number of locations is 4 K, therefore, the width of the
address bus required is 12. The lower ten bits of the address (A0 – A9) are
connected to the address bus of each RAM chip, and A10 and A11 are
applied to a 2-line-to-4-line decoder. This decoder will select one out of
the four chips depending upon the values of A10 and A11. The complete
circuit is shown in Fig. Prob. 11.5 (a) which can be understood easily.
(b) For obtaining 1024 ´ 8, two 2142 RAM chips are connected as shown in
Fig. Prob. 11.5 (b). Here, the address A0 – A9 is applied to both the chips.
The upper chip, IC1 has been used for the lower four bits and the lower
chip, IC2 for the upper four bits, of the 8-bit word.
(c) For obtaining 16 K bytes of RAM, 16 sets of 1 K ´ 8 circuits as shown in
Fig. Prob. 11.5 (b) are required. A0 – A9 will be same for all the 16 sets.
The most significant four bits of the addresses are to be used to select one
out of the 16 sets. For this purpose a 4-line-to-16-line decoder circuit is to
be used in a way similar to that used in Fig. Prob. 11.5 (a). Let us, for
convenience, number these sixteen sets as RAM-0 to RAM-15.
11.6 (a) 4 K bytes = 4 K ´ 8 = 2 ´ (2 K ´ 8)
Therefore, two chips of 2716 and one inverter are required.
(b) 2 K ´ 16 = (2 K ´ 8) ´ 2
This also requires two chips of 2716.
(c) 4 K ´ 16 = 2 ´ 2 ´ (2 K ´ 8)
The number of 2716 chips required is four. One inverter will be required
to select one pair of 2716s.
11.7 (a) For 4 K locations, the width of the address bus required is 12. The most
significant bit A11 of the address is used to select the chip and the other 11
bits A10-A0 are applied to both the chips. The address bit A11 is applied at
the chip select ( CS 1 ) input of ROM-0 and its complement is applied at

136
 A0 – A9
2142
WE RAM - 0
I/O1 – I/O4
OD
CS 1 CS2
+VCC

A0 – A9

T)
2142

I
WE RAM - 1

B
0 I/O1 – I/O4

–
2-line- OD
A10 1 CS 1 CS2

(4
to-4-
line- 2 +VCC
A11 decoder 3

S
A0 – A9

U
2142

B
WE RAM - 2
I/O1 – I/O4

A
OD
CS 1 CS2

T
+VCC

A
A0 – A9

D
2142
WE
WE RAM - 3
OD I/O1 – I/O4
OD
CS 1 CS2
+VCC
Fig. Prob. 11.5(a)

CS 2 input. Therefore, when A11 = 0 ROM-0 is selected, whereas A11 = 1

will select ROM-1. Figure Prob. 11.7(a) illustrates the relevant portion of
the circuit.
(b) Figure Prob. 11.7(b) shows 2 K ´ 16 ROM. The lower order eight bits of
each of the 16-bit words are stored in IC1 and the higher order eight bits
are stored in the corresponding location in IC2.
(c) For obtaining 4 K ´ 16 ROM, use two sets of 2 K ´ 16 memory (Fig. Prob.
11.7(b)) and connect them as shown in Fig. Prob. 11.7(a).
11.8 (a) In the linear selection addressing, a one-out-of-N decoder is used to select
one of the N memory locations. For example, Fig. Prob. 11.8(a) shows as
4-line-to-16-line decoder used to select one out of sixteen memory locations.
137
A0 – A9 2142
IC1 (D0 – D3) ü
ï
OD ï
I/O1 – I/O4 ï
ï
ï
WE
CS 1 ï8-bit output
OD CS2 ý (D0 – D7)
ï
ï
ï
2142 ï
(D4 – D7) ï
IC2 ï
A0 – A9 ïþ
I/O1 – I/O4

Fig. Prob. 11.5(b)

2716

(8 – B I T)
A0 – A10 ROM-0
CS 1 O0 – O7

A11 B U S
D A T A

CS 2
2716
A0 – A10
ROM-1
O0 – O7
Fig. Prob. 11.7(a)

2716
A0 – A10 IC1 D0 – D7
O0 – O7
ü
CS ï
ï
ïï 16-bit output
CS ý (D – D )
ï 0 15

CS ï
2716 ï
A0 – A10 D8 – D15 ïþ
IC2 O0 – O7

Fig. Prob. 11.7(b)

138
 0
Memory location 0
1
A Memory location 1
ì 3
ï 4-line-to 2
Memory location 2
ï A2 16-line
Address ï
ï decoder
inputs í
ï A1
ï
ï 14
ïî A0 Memory location 14
15
Memory location 15

Fig. Prob. 11.8(a)

(b) In the coincident selection addressing, a memory location is selected by

applying an X address and a Y address. The decoder circuitry consists of
1-out-of-X and 1-out-of-Y decoders as shown in Fig. Prob 11.8 (b). Here,
the X address is A1A0 which selects a row and the Y address is A3A2 which
enables a column. Each memory element is placed at the intersection of a
row and a column.
0 1 2 3 Column
Row

0
D00 D01 D02 D03

A0
Decoder DL

1
D10 D11 D12 D13
1 of 4

ì
ï A1
ï 2
ï D20 D21 D22 D23
ï
4-bit address

ï
ï D30 D31 D32 D33
3
ïï Row drivers
í Diode
ï matrix
ï Column
ïA Column sense
Decoder DH

enable
ï 2 amplifiers
1 of 4

ï
ï
ï A3
ïî
Chip
select (CS)
Data output
Fig. Prob. 11.8(b)

139
11.9 The operation of this circuit is similar to that of the circuit of Fig. 11.9(a).
Here, the gates of the inverters are not held at VDD but are clocked so that T3
conducts only when f2 = 1 and not when f1 = 1, even if the bit stored on C1
is 1. When T3 conducts, T4 also conducts. The f2 needs to be 1 only long
enough to allow C2 to charge from VDD through T3 and T4. In contrast to this,
in the circuit of Fig. 11.9a, the power is always drawn from the supply
throughout the clock cycle. Therefore, there is considerable reduction in
power dissipation in this circuit.
11.10 When the transistor T4 conducts, C3 charges from C2 forming a capacitive
loop. In order to charge C3 without causing appreciable voltage drop, the
ratio C2/C3 must be very large. Therefore, C2 >> C3.
11.11 During the interval when f1 = 1, C charges to logic 1 through T3, indepen-
dently of data input (since f2 = 0, therefore, T2 is OFF). This logic level
remains on C after f1 returns to logic 0. Now, if the data input is 1, then
during f2 = 1, T1 and T2 will conduct and C will get discharged to logic 0
level. On the other hand, if the input is at logic 0, T1 will be OFF and C will
continue at logic 1 level. In general, the logic level of C will be complement
of input logic level.
Similarly, during f3 and f4 phases, the complement of logic level on C will
be transferred to output capacitor (between drain of T6 and ground).
11.12 (i) Association Operation: When A1A0 = 11, outputs of the OR gates are 1
irrespective of the logic level at W (i.e., W = X). The outputs of the NOR
gates will be 0, which will disable the latches. The output of the EX-OR
gate will be 0, if the data input bit is same as the bit stored (Q0), other-
wise it is 1.
Therefore, the output of the AND gate is 1 for mismatch and 0 for
match. The output Y of the wired-OR gate will be 0 if both the data inputs
match with the bits stored, otherwise it will be 1. The data outputs D1 and
D0 are both 0.
(ii) Associate Operation with Higher Bit Masked: When A1A0 = 01, and
W = 1, the operation of the circuit will be similar to the operation
explained in (i) above except that the output of the AND gate on the I1
side will always be 0, therefore, match condition will be checked only for
I0 bit. The AND gate of D1 output is enabled.
(iii) Associate Operation with Lower Bit Masked: The operation is similar to
the operation of (ii) above.
(iv) Read Operation: When A1A0 = 00, and W = 1, the latches are disabled.
Depending upon which Y is selected by making it 0, the output Q0 of the
latch appears at the corresponding D output.
It is also possible to read more than one location at a time. This
happens when more than one address input is made 0. The output will be
OR operation performed on all the selected outputs.
(v) Write Operation: When A1A0 = 00, and W = 0, the latches are enabled
for the location by making the Y input 0. The same data also appears at
the D outputs following the arguments of (iv) above.

140
 (vi) Associate and Write at the Match Addresses:
(a) When A1A0 = 01 and W = 0, the association operation is performed for
the lower bit (ii) above. The outputs will be 0 for matched conditions
and 1 for mismatch conditions. When there is matching, the correspond-
ing higher bit (I1) is latched into the latch and it also appears at the D1
output.
(b) When A1A0 = 10 and W = 0, the operation will be similar to the
operation of part (a) above. The matching will be performed for higher
bits and the lower bit (I0) will be stored in the locations for which I1
match.
11.13 Since 16 ´ 2 = 2 ´ (8 ´ 2), therefore, it requires two chips. The data inputs,
data outputs, and mode control inputs of two 8 ´ 2 CAMs are connected
as shown in Fig. Prob. 11.13. The resulting system has 16 address inputs
(Y0 – Y15). Thus, it becomes a CAM of sixteen 2-bit words.
I1 I0 A1 A0

Y0
Y1
A0 8´2 Y2
A1 CAM Y3
I0 IC1 Y4
Y5
I1 Y6
W D1 D0 Y7

W D0
D1

W D1 D0 Y8
Y9
A0 Y10
A1 8´2 Y11
I0 CAM Y12
IC2 Y13
I1 Y14
Y15
Fig. Prob. 11.13
11.14 8 ´ 8 = 4 ´ (8 ´ 2)
Therefore, the number of chips required is four. Since the number of words is
8, therefore, Y0 – Y7 of each chip are connected to a common bus. The circuit
of 8 ´ 8 CAM is shown in Fig. Prob. 11.14.
11.15 16 ´ 8 = 2 ´ (8 ´ 8)
Therefore, for designing a 16 ´ 8 CAM, two 8 ´ 8 CAMs as shown in Fig.
11.14 can be connected as shown in Fig. Prob. 11.15.
11.16 It is a 16-word, 8-bit word CAM. The first operation is to interrogate the
MSB of all words for a 1 with all other bits masked, i.e., the key is

141
 A7 A6 I7 I6 A5 A4 I5 I4 A3 A2 I3 I2 A1 A0 I1 I0

A1 A0 I1 I0 A1 A0 I1 I0 A1 A0 I1 I0 A1 A0 I1 I0

8´2 8´2 8´2 8´2

CAM CAM CAM CAM
Y0 – Y7 Y0 – Y7 Y0 – Y7 Y0 – Y7
W D1 D0 W D1 D0 W D1 D0 W D1 D0

D7 D6 D5 D4 D3 D2 D1 D0
W
Fig. Prob. 11.14

I7 I0

Y0-Y7
8 ´ 8 CAM

Y0-Y7
A7 D7 D6 D5 D4 D3 D2 D1 D0
A6 D0
A5 D1
D2
A4
D3
A3 W D4
A2 D5
A1 D6
D7
A0
D7 D6 D5 D4 D3 D2 D1 D0
Y8-Y15

8 ´ 8 CAM

Y0-Y7

I7 I0

Fig. Prob. 11.15

1XXXXXXX. If only one word indicates a match, then the maximum valued
word search is complete. However, if several words indicate a match, then
the CAM is to be interrogated again with key as 11XXXXXX. In case no
match occurs when the MSB is interrogated, then the next key has to be

142
 01XXXXXX. This process is to continue till at the most all the bits of the
words are interrogated. In any case no more than 8 interrogation cycles will
be required to determine the maximum valued word.
In the case of RAM, each word is to be compared sequentially. Therefore,
the time required for the search will be dependent on the number of words
stored which is sixteen in this case.
11.17 The operation is similar to the operation of Prob. 11.16 with 1’s replaced by
0’s in the search process.
11.18 A CAM is ideal for this. Because of the parallel search operation in CAM,
just in one cycle, we can find out whether the word is already stored or not. If
not, it can be stored in the next location available. In contrast to this, the
search process is serial in a RAM which is time consuming and hence a
RAM is not suitable for this purpose.
11.19 The inputs and the outputs of all the CCDs are to be connected in parallel.
The additional address bits are decoded and used to select one of the CCDs
for read/write operation. The clock and write enable are also connected in
parallel.
11.20 For expanding word length, the address, chip select, write enable, and clock
inputs of all the devices are connected in parallel. The number of data inputs
and outputs are used independently. The number of inputs/outputs will be
equal to the number of CCDs.

143
 CHAPTER 12
12.1 The BCD-to-Excess-3 code converter’s truth table is given below.
BCD Excess-3
A B C D E3 E2 E1 E0
0 0 0 0 0 0 1 1
0 0 0 1 0 1 0 0
0 0 1 0 0 1 0 1
0 0 1 1 0 1 1 0
0 1 0 0 0 1 1 1
0 1 0 1 1 0 0 0
0 1 1 0 1 0 0 1
0 1 1 1 1 0 1 0
1 0 0 0 1 0 1 1
1 0 0 1 1 1 0 0

(a) For the design using PROM, a PROM of size 10 ´ 4 is required, but since
PROM of this size does not exist, therefore, a PROM of size 16 ´ 4 is to
be used. Data is to be stored in the PROM at the addresses corresponding
to the BCD code, the data is Excess-3 code. For example at the address
0000, the data stored is 0011 and at the address 1001 the data stored is
1100.
(b) Logical expressions can be written for E3, E2, E1, and E0 outputs in terms
of A,B,C, and D inputs. To reduce the hardware requirements, these ex-
pressions can be minimized using K-maps.

E3
E2
E1
E0

Fig. Prob. 12.1 (b)

The simplified expressions are:
E3 = A + BC + BD
E2 = B C D + B C + B D
E1 = C D + CD
E0 = D

144
 The size of PLA required is
No. of inputs =4
No. of outputs =4
No. of product terms =9
The circuit is given in Fig. Prob. 12.1(b).
(c) The required size of PAL is
No. of inputs =4
No. of outputs =4
Minimum number of =3
AND gates for each output
The circuit is given in Fig. Prob. 12.1(c).

E3

E2

E1

E0

Fig. Prob. 12.1 (c)

12.2 Follow similar procedure as given in Prob. 12.1.

12.3 Prepare truth table and follow similar procedure as given in Prob. 12.1.
12.4 The inputs of two 82S100 devices are to be connected in parallel. This will
result in 8 + 8 = 16 outputs.
12.5 The inputs I0 to IM-1 are common for all the PLAs. Depending on the values of
IM to IM+Q-1, one of the output lines of the decoder will go LOW activating the
corresponding PLA and disabling all the other PLAs. Hence, the number of
inputs increases.
12.6 Architecture of a PLD refers to the attributes of the device significant to the
logic of a design to be implemented. It includes.
· Configuration of pins.
· The size and the arrangement of the programmable array(s).
· Configuration of the input and output interface logic.

145
12.7 Input Column Input/output Column
I1 2 IO2 6
I1 3 IO 2 7
I2 0 IO3 10
I2 1 IO 3 11
I3 4 IO4 14
I3 5 IO 4 15
I4 8 IO5 18
I4 9 IO 5 19
I5 12 IO6 22
I5 13 IO 6 23
I6 16 IO7 26
I6 17 IO 7 27
I7 20
I7 21
I8 24
I8 25
I9 28
I9 29
I10 30
I 10 31

12.8 Input Column Input/output Column

I1 0 IO1 2
I1 1 IO 1 3
I2 4 IO8 30
I2 5 IO 8 31
I3 8 O2 6
I3 9 O2 7
I4 12 O3 10
I4 13 O3 11
I5 16 O4 14
I5 17 O4 15
I6 20 O5 18
I6 21 O5 19
I7 24 O6 22
I7 25 O6 23
I8 28 O7 26
I8 29 O7 27

146
12.9 It has four multiplexers, MUX–1, MUX–2, MUX–3 and MUX–4. Each one
may be programmed to be in 0 or 1, which means its output will be either same
as input 0 or input 1. Table below gives all the possible conditions.
MUX – 1 MUX – 2 MUX – 3 MUX – 4 No. of Output Output Output
product Enable pin/FF
Terms output
0 0 0 0 8 pin-11 Reg. feedback
0 0 0 1 8 pin-11 Comb. input
0 0 1 0 8 Term Reg. feedback
Controlled
Term
0 0 1 1 8 Controlled Comb. input
0 1 0 0 8 pin-11 Reg. feedback
0 1 0 1 8 pin-11 Comb. input
0 1 1 0 8 Term
Controlled Reg. feedback
0 1 1 1 8 Term
Controlled comb. input
1 0 0 0 7 pin-11 Reg. feedback
1 0 0 1 7 pin-11 Comb. input
1 0 1 0 7 Term
Controlled Reg. feedback
1 0 1 1 7 Term
Controlled Comb. input
1 1 0 0 7 pin-11 Reg. feedback
1 1 0 1 7 pin-11 Comb. input
1 1 1 0 7 Term
Controlled Reg. feedback
1 1 1 1 7 Term
Controlled Comb. input

12.10 These are given in Fig. Prob. 12.10.

12.11 Here the output of an AND gate controls the output.
(a) Open all the inputs to the controlling AND gate.
(b) Keep all the inputs intact (connected) to the controlling AND gate.
(c) Keep the connections corresponding to the inputs A, B, C, D, E , F ,
G and H intact to the controlling AND gate and open all other connec-
tions.
12.12 When x1 = 0, f will be obtained from the upper multiplexer. For x2 = 0, top-
most cell will be selected and f will be 1; whereas for x2 = 1, the cell second
from the top will get selected and f = 0.
Similarly, for x1 =1
when x2 = 1, f = 0
and when x2 = 1, f = 1

147
 Registered output B = 1 Combinational output B = 0

A=1

BI-DIRECTIONAL I/O CD = 11
AR
D Q
SP

AR
A=0 D Q
SP

COMBINATIONAL FEEDBACK CD = 10
AR
A=1 D Q
SP

AR
D Q
A=0 SP

REGISTER FEEDBACK CD = 00

AR AR
D Q D Q
A=1 SP SP Q

AR AR
A=0 D Q D Q
SP SP Q

Fig. Prob. 12.10

148
 Therefore, the truth table will be as given below.
x1 x2 f
0 0 1
0 1 0
1 0 0
1 1 1

12.13 The truth table of the given function f is

x1 x2 x3 f
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 0
1 0 0 1
1 0 1 0
1 1 0 0
1 1 1 1

when x1 = 0, f will be obtained from output of top multiplexers’ structure,

when x1 = 1, f will be obtained from output of bottom multiplexers’ structure.
Now, when x2 = 0, the output will be obtained from the top-most multiplexer
and when x2 = 1, it will be obtained from the next multiplexer. When x3 = 0,
the output will be from the top-most cell, and when x3 = 1 it will be from be
next cell. Similarly, the complete circuit can be analyzed. The bits to be
stored will be
0
1
1
0
1
0
0
1

149
 CHAPTER 13
13.1 The memory address space is given by
M = 2P
where, P is the address bus width.
The memory address space for the mPs are given below.

Microprocessor Memory address space

8080A 64 K bytes
6800 64 K bytes
8086 1 M bytes
9900 64 K bytes
Z8000 8 M bytes

13.2 The number of distinct combinations of 8-bit

words = 28 = 256
Therefore, the total number of instruction codes, assuming single byte op
code = 256.
The total number of instruction codes in 8085A mP is 246.
13.3 (a) 2142 is a 1024 ´ 4 bits RAM
Therefore, 4 K bytes = 4 K ´ 8 bits
= 4 ´ 2 ´ (1 K ´ 8) bits
= 8 chips
2716 is a 2 K ´ 8 bits EPRPM. Therefore, only one 2716 chip is required.
(b) Let the first 2 K bytes be in EPROM and next 4 K bytes be in the RAMs.
The relevant connections are shown below.

A8 – A15

WR
8085 A
RD

AD0 – AD7

ALE

A0 – A7
8212

CLR
DS2 MD
DS 1

+VCC

Fig. Prob. 13.3(a)

150
 Other connections are indicated below:
A0 – A10 from mP to A0 – A10 of 2716
A0 – A9 from mP to A0 – A9 of each of 2142
CS2 of each 2142 to Vcc
WR from mP to WE of each 2142
RD from mP to OD of each 2142

A10 A0 0 To CS of 2716
A11 A1 1
A12 A2 2 To CS 1 of RAM set 1
(from mP) 3 To CS 1 of RAM set 2
8205
4 To CS 1 of RAM set 3
A13 E1 5 To CS 1 of RAM set 4
A14 6
E2
A15 E3 7
(from mP)
Fig. Prob. 13.3(b)

(c) The address of various chips are given below.

Memory chips Starting address Last address
in hex. in hex.
EPROM 0000 07FF
RAM pair 1 0800 0BFF
RAM pair 2 0C00 0FFF
RAM pair 3 1000 13FF
RAM pair 4 1400 17FF

13.4 (i) MVI A, 00H ; Load accumulator with zero

(ii) SUB A ; Subtract A from A
(iii) ANI 00H ; AND A with zero
(iv) XRA A ; A EX-OR A
Note that the information beyond semicolon (;) are comments.
13.5 Let D-E and H-L pairs be pointers to source and destination memory locations
respectively. The program is given below:
LXI D, 0F00 H ; Initialize source pointer
LXI H, 1F00 H ; Initialize destination pointer
LXI B, 100H ; Initialize counter
LOOP: LDAX D ; Load A with contents of source memory
CMA ; Complement A
MOV M, A ; Store in destination memory
INX D ; Increment pointers
INX H

151
 DCX B ; Decrement counter
MOV A, C ; Check counter for zero
ORA B
JNZ LOOP
NEXT:
13.6 The program is given below:
LXI H, 0A02H ; Store destination address in H-L pair
LDA 0A00H ; Load A with first number
MOV B, A ; Transfer to B
LDA 0A01H ; Load A with second number
CMP B ; Compare A and B
JZ FINIS ; Go to FINIS if the two numbers are equal
JC GREAT ; If CY = 1, (A) < (B)
MOV M, A ; Otherwise (A) > (B)
JMP FINIS
GREAT: MOV M, B
FINIS :
13.7 The following instructions will clear the memory location.
LXI H, 01A0H
MVI M, 00H
13.8 LXI H, A001H ; Initialize pointer
MOV C, M ; Get the number of bytes in C
INX H ; Increase pointer by 1
START : MOV A, M ; Get a byte of data in A
REP : DCR C
JZ STOP ; Stop at end of data
INX H
CMP M ; Compare
JC REP ; If (A) < (M), try next number
JMP START
STOP: STA FF00H ; Store the smallest element
END
13.9 ANI 0FH
13.10 LOOP: DCR 0
JZ FINIS
IN DATA
MOV M, A
INX H
JMP LOOP
FINIS: MOV B, A

152
 SOLUTION
The operation performed by each instruction is given below:
START: LXI H, BUFR ; Initialize H-L pair with address BUFR
MOV C, 0BH ; Initialize counter with decimal 11
LOOP: DCR C ; Decrease counter by one
JZ FINIS ; Go to FINIS if counter = 0
IN DATA ; Input a byte from DATA port
MOV M, A ; Move the byte to memory
; location pointed to by H-L pair
INX H ; Advance the pointer by one
JMP LOOP ; Go to loop
FINIS: MOV B, A ; Move the contents of A to B
The operation performed by this program is to input ten bytes from input
port DATA and store them in memory locations starting from BUFR.
13.11 N=3+3+1+1+1+1+1+1
= 12 bytes
13.12 (A) 0000 1000
(B) 1001 0011
ADD B 1001 1011
The result is not a valid BCD number. ADD B instruction must be fol-
lowed by DAA instruction. The effect of this is given below:
1001 1011
0000 0110 Add 6 because the least-significant four bits do not
represent a valid BCD digit
1010 0001
0110 0000 Add 60 because the most-significant four bits do not
represent a valid BCD digit
10000 0001 = (101)10
13.13 Assume a set of ten keys for entering BCD number and a 7-segment display
for displaying this number. It is also assumed that BCD-to-7-segment codes
are stored in memory from the starting address 00XXH. The block diagrams
for the input and output devices are shown in Fig. Prob. 13.13(a) and (b)
respectively.
Assume 01H and 02H as the port addresses of the input device and output
device respectively. The addresses are decoded and proper signals are gener-
ated for Enable and Device Select terminals for reading and writing.
The program can be written as
MVI B, XXH
LXI H, 0000H
IN 01H
ADD B
MOV L, A
MOV A, M
OUT 02H
153
 VCC

D
(MSB) D3

Decimal-to- Inverting
BCD Encoder C Tristate D2
Buffer

Data bus
(Inputs &

of mP
outputs B
active-low) D1
A

D0

Enable
(a)

Current limiting
VCC
resistors
Common
anode
a a
b
c f b
g
D-type
d
Latch c
Data bus e e
f
d
g

Device Select
(b)
Fig. Prob. 13.13

13.14 The last six instructions will be

POP PSW
POP H
POP D
POP B
EI
RET

154
 Here it is assumed that the interrupts are kept disabled during the execu-
tion of the sub-routine.
13.15 The ASCII code for decimal 0 is 0110000 and for? is 0111111. The program
is given below:
LXI H, 00F1H
LDA 00F0H
CPI 0AH
JNC QUE
ADI 00110000 B
MOV M, A
JMP STOP
QUE : MVI M, 00111111 B
STOP: END
13.16 Refer to Table 13.3
mP Address bus width
8086 20
80186 20
80286 24
80386SL 25
80386 DX 32
80486 DX 32
Pentium 32

13.17 Eight 8-bit or four 16-bit

AX: AH, AL
BX: BH, BL
CX: CH, CL
DX: DH, DL
13.18 Four zeros at the least-significant four bit positions are appended to the 16-
bit segment register, making it 20-bit address. Actual physical 20-bit address
is this 20-bit data plus the contents of the pointer register.
13.19 CS = 2000H
IP = 1A00H
20-bit address of the next instruction byte will be fetched from
20000
+ 1A00
21A00 H
13.20 20-bit current address of the stack will be
24000
+ A000
2E000 H

155
 CHAPTER 14
14.1 (a)Yes. It contains all the allowed characters.
(b)No. character ‘ ’ is not permitted.
(c)No. starting character can not be a numeral.
(d)Yes. Upper and lower case characters can be mixed.
(e)No. Hyphen (–) is not allowed.
(f)
No. Two consecutive underscores are not allowed.
14.2 (a)ENTITY NAND 2 IS
PORT (X, Y : IN BIT; Z : OUT BIT);
END NAND 2;
(b) ENTITY NAND 3 IS
PORT (A, B, C : IN BIT;
Y : OUT BIT);
END NAND 3;
14.3 A 4:1 multiplexer is shown in Fig. Prob. 14.3. It has four data inputs I0, I1, I2,
and I3 and two select inputs A and B. There is one output Y.

I0
I1

I2 Y
I3
AB

Fig. Prob. 14.3

The entity declaration is
LIBARY IEEE;
USE IEEE STD-LOGIC; 1164 ALL;
ENTITY MULTI-4 IS
PORT (IO, I1, I2, I3, A, B ; IN STD-LOGIC;
Y: OUT STD-LOGIC);
END MULTI_4;
14.4 (a) For 2-input NAND gate
ARCHITECTURE df_nand 2 OF NAND 2 IS
BEGIN
Z Ü NOT (X AND Y) AFTER 10 ns;
END df-nand 2;
(b) For 3-input NAND gate
ARCHITECTURE df_nand 3 OF NAND 3 IS
BEGIN
Y Ü NOT (A AND B AND C) AFTER 10 ns;
END df_nand 3;
14.5 LIBRARY IEEE;
USE IEEE. STD_LOGIC_1164. ALL;
-- Name of entity chosen is F_A
156
 ENTITY F-A IS
PORT (A, B, CIN: IN STD_LOGIC; S COUT: OUT STD_LOGIC);
END F_A;
ARCHITECTURE FA_STR OF F_4 IS
COMPONENT NAND 3
PORT (X1, X2, X3 : IN STD-LOGIC; Y: OUT STD_LOGIC);
END COMPONENT;
COMPONENT NAND 4
PORT (X4, X5, X6, X7 : IN STD-LOGIC; Z: OUT STD_LOGIC);
END COMPONENT;
COMPONENT INV
PORT (P : IN STD_LOGIC; Q : OUT STD_LOGIC);
END COMPONENT;
COMPONENT NAND2
PORT (X8, X9 : IN STD_LOGIC; R : OUT STD_LOGIC);
END COMPONENT;
SIGNAL AB, BB, CINB, S1, S2, S3, S4, S5, S6, S7 : STD_LOGIC;
BEGIN
I1 : INV PORT MAP (A, AB);
I2 : INV PORT MAP (B, BB);
I3 : INV PORT MAP (CIN, CINB);
N1 : NAND3 PORT MAP (AB, B, CINB, S1);
N2 : NAND3 PORT MAP (AB, BB, CIN, S2);
N3 : NAND3 PORT MAP (A, BB, CINB, S3);
N4 : NAND3 PORT MAP (A, B, CIN, S4);
N5 : NAND4 PORT MAP (S1, S2, S3, S4, S);
N6 : NAND2 PORT MAP (A, B, S5);
N7 : NAND2 PORT MAP (B, CIN, S6);
N8 : NAND2 PORT MAP (A, CIN, S7);
N9 : NAND3 PORT MAP (S5, S6, S7 COUT);
END FA_STR;
14.6 LIBARY IEEE;
USE IEEE. STD_LOGIC-1164. ALL;
ENTITY F-A IS
PORT (A, B, CIN: IN STD_LOGIC; S, COUT: OUT STD_LOGIC)
END F-A;
ARCHITECTURE FULL_ADDER OF F_A IS;
BEGIN
S Ü ((NOT A) AND B AND (NOT CIN)) OR
((NOT A) AND (NOT B) AND CIN) OR
(A AND (NOT B) AND (NOT CIN)) OR
(A AND B AND CIN) AFTER 15 ns;
C OUT Ü (A AND B) OR (B AND CIN) OR
(A AND CIN) AFTER 10 ns;
END FULL_ADDER;

157
A B CIN

I1 I2 I3 N S1
1

AB BB CINB

S2
N2

N5 S

S3
N3

S4
N4

A S5
N6
B

B S6
N7 N9 COUT
CIN

A S7
N8
CIN

Fig. Prob. 14.5

158