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Vl9251 Testing of Vlsi Circuits

The document outlines the topics that will be covered in a course on testing of VLSI circuits. The course is divided into 5 units that will cover: 1) basics of testing and fault modelling, 2) test generation for combinational and sequential circuits, 3) design for testability, 4) built-in self-test and test algorithms, and 5) fault diagnosis. The course will discuss faults in digital circuits, logic simulation, design for testability approaches, BIST architectures, and logical level diagnosis. References for further reading on digital circuit testing and testable design are also provided.

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Velmurugan Subbiah Parvathy
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3K views

Vl9251 Testing of Vlsi Circuits

The document outlines the topics that will be covered in a course on testing of VLSI circuits. The course is divided into 5 units that will cover: 1) basics of testing and fault modelling, 2) test generation for combinational and sequential circuits, 3) design for testability, 4) built-in self-test and test algorithms, and 5) fault diagnosis. The course will discuss faults in digital circuits, logic simulation, design for testability approaches, BIST architectures, and logical level diagnosis. References for further reading on digital circuit testing and testable design are also provided.

Uploaded by

Velmurugan Subbiah Parvathy
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as DOC, PDF, TXT or read online on Scribd
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VL9251 TESTING OF VLSI CIRCUITS LTPC 3003 UNIT I BASICS OF TESTING AND FAULT MODELLING 9 Introduction to testing Faults

s in Digital Circuits Modelling of faults Logical Fault Models Fault detection Fault Location Fault dominance Logic simulation Types of simulation Delay models Gate Level Event driven simulation. UNIT II TEST GENERATION FOR COMBINATIONAL AND SEQUENTIAL CIRCUITS 9 Test generation for combinational logic circuits Testable combinational logic circuit design Test generation for sequential circuits design of testable sequential circuits. UNIT III DESIGN FOR TESTABILITY 9 Design for Testability Ad-hoc design generic scan based design classical scan based design system level DFT approaches. UNIT IV SELF TEST AND TEST ALGORITHMS 9 Built-In self Test test pattern generation for BIST Circular BIST BIST Architectures Testable Memory Design Test Algorithms Test generation for Embedded RAMs. UNIT V FAULT DIAGNOSIS 9 Logical Level Diagnosis Diagnosis by UUT reduction Fault Diagnosis for Combinational Circuits Self-checking design System Level Diagnosis. Total: 45 REFERENCES:

1. M.Abramovici, M.A.Breuer and A.D. Friedman, Digital systems and Testable Design, Jaico Publishing House,2002. 2. P.K. Lala, Digital Circuit Testing and Testability, Academic Press, 2002. 3. M.L.Bushnell and V.D.Agrawal, Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits, Kluwer Academic Publishers, 2002. 4. A.L.Crouch, Design Test for Digital ICs and Embedded Core Systems, Prentice Hall International, 2002.

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