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Verilog HDL-A Guide To Digital Design and Synthesis by Samir Palnitkar SunSoft Press

This document is a guide to Verilog HDL (Hardware Description Language) by Samir Palnitkar. It is divided into three parts that cover basic Verilog topics, advanced Verilog topics, and appendices. The first part introduces concepts like hierarchical modeling, modules, ports, gate-level modeling, dataflow modeling, behavioral modeling, tasks and functions. The second part covers timing and delays, switch-level modeling, user-defined primitives, and logic synthesis with Verilog. The appendices include strength modeling, a list of keywords and system tasks, the Verilog syntax definition, and examples.

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Venkatarao Selamneni
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512 views

Verilog HDL-A Guide To Digital Design and Synthesis by Samir Palnitkar SunSoft Press

This document is a guide to Verilog HDL (Hardware Description Language) by Samir Palnitkar. It is divided into three parts that cover basic Verilog topics, advanced Verilog topics, and appendices. The first part introduces concepts like hierarchical modeling, modules, ports, gate-level modeling, dataflow modeling, behavioral modeling, tasks and functions. The second part covers timing and delays, switch-level modeling, user-defined primitives, and logic synthesis with Verilog. The appendices include strength modeling, a list of keywords and system tasks, the Verilog syntax definition, and examples.

Uploaded by

Venkatarao Selamneni
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as PDF, TXT or read online on Scribd
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Verilog HDL

A guide to Digital Design and Synthesis


Samir Palnitkar

SunSoft Press 1996

PART 1 BASIC VERILOG TOPICS 1 Overview of Digital Design with Verilog HDL 2 Hierarchical Modeling Concepts 3 Basic Concepts 4 Modules and Ports 5 Gate-Level Modeling 6 Dataflow Modeling 7 Behavioral Modeling 8 Tasks and Functions 9 Useful Modeling Techniques PART 2 Advance Verilog Topics 10 Timing and Delays 11 Switch- Level Modeling 12 User-Defined Primitives 13 Programming Language Interface 14 Logic Synthesis with Verilog HDL PART3 APPENDICES A Strength Modeling and Advanced Net Definitions B List of PLI Rountines C List of Keywords, System Tasks, and Compiler Directives D Formal Syntax Definition E Verilog Tidbits F Verilog Examples

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