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Mosfet Capacitances

The document discusses the various parasitic capacitances associated with MOS transistors that must be considered when examining the transient response of digital circuits. It describes two major types of parasitic capacitances: 1) oxide related capacitances between the gate, source, drain and bulk terminals and 2) junction related capacitances between the source, drain and bulk. It also explains how some capacitances are voltage dependent while others are not. The document provides details on the parasitic capacitances in different operating modes of the MOSFET and defines the zero bias junction capacitance.

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381 views

Mosfet Capacitances

The document discusses the various parasitic capacitances associated with MOS transistors that must be considered when examining the transient response of digital circuits. It describes two major types of parasitic capacitances: 1) oxide related capacitances between the gate, source, drain and bulk terminals and 2) junction related capacitances between the source, drain and bulk. It also explains how some capacitances are voltage dependent while others are not. The document provides details on the parasitic capacitances in different operating modes of the MOSFET and defines the zero bias junction capacitance.

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bhvkch2n0389
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© Attribution Non-Commercial (BY-NC)
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Prepared by Bhavik chauhan Krunal khilwani

In order to Examine the transient(AC) response in digital circuits consisting of MOSFETs ,we need to determine the nature and the amount of parasitic capacitance associated with the MOS transistor. Most of these capacitances are not lumped but distributed

Based on their physical origins , the parasitic capacitances can be classified into two major groups: 1.Oxide related capacitances  Gate to source capacitance(CGS)  Gate to drain capacitance(CGD)  Gate to bulk capacitance(CGB) 2.Junction related capacitances  Source to bulk capacitance(CSB)  Drain to bulk capacitance(CDB)

Overlap capacitances:-

The two overlap capacitances that arises as a result of structural arrangement are :1. CGDO (gate to drain overlap capacitance) 2. CGSO (gate to source overlap capacitance) CGDO= CGSO = Cox .W. LD where, LD = overlap length on each side of channel ` Overlapping capcitances are voltage independent.

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Now we have to consider the capacitances that results from the interconnection between the gate voltage and the channel charge These capacitances are CGS , CGD and CGB. These capacitances are voltage dependent.

1)Cut-off mode: surface is not inverted  No conducting channel that links surface to source to drain.  CGD =CGS =0  The gate to substrate capacitance is given by, CGB = Cox .W. L

2) Linear mode: Inverted channel extended across the MOSFET, between the source and the drain.  CGB = 0  Gate to source and gate to drain capacitances can be viewed as being shared equally between source and drain  CGS = CGD = [Cox .W. L]

3) Saturation mode: Inversion layer does not extend to the drain.  CGD = 0  CGB = 0  The gate to channel capacitance as seen between gate and the source can given by, CGS = 2/3[Cox .W. L]

Junction capacitances (CSB, CDB)are due to the depletion charge surrounding the respected source or drain diffusion regions. These capacitances are voltage dependent.

The zero bias junction capacitance per unit area is defined as,

Junction with substrate


Bottom area = W * Y (length of drain/source) Side facing channel: area = W * Xj Total cap = Cj

Junction with sidewalls


Channel-stop implant Perimeter = 2Y+ W Area = P * Xj Total cap = Cjsw

Total junction cap C = Cj + Cjsw

CMOS Digital Integrated Circuits by Sung-Mo kang ,Yusuf leblebici


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THANK YOU

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