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CSE-401 E: MDU B.Tech Syllabus (CSE) - IV Year

CSE-401 E is an advanced computer architecture class that is 3 hours per week, with 50% of the final grade based on class work and 50% based on a 3 hour final exam. The class covers 5 units: [1] computer architecture fundamentals, [2] time/area tradeoffs and instruction sets, [3] cache memory organization, [4] memory system design using queuing models, and [5] concurrent and shared memory multiprocessors. The final exam will include at least one question from each unit, and students must answer 5 questions total from the 8 that will be asked.

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158 views

CSE-401 E: MDU B.Tech Syllabus (CSE) - IV Year

CSE-401 E is an advanced computer architecture class that is 3 hours per week, with 50% of the final grade based on class work and 50% based on a 3 hour final exam. The class covers 5 units: [1] computer architecture fundamentals, [2] time/area tradeoffs and instruction sets, [3] cache memory organization, [4] memory system design using queuing models, and [5] concurrent and shared memory multiprocessors. The final exam will include at least one question from each unit, and students must answer 5 questions total from the 8 that will be asked.

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dineshdkj
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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CSE-401 E

L 3 T 1 P -

Advanced Computer Architecture Class Work: 50 Exam: 100 Total: 150 Duration of Exam: 3 Hrs.

Unit1: Architecture And Machines: Some definition and terms, interpretation and microprogramming. The instruction set, Basic data types, Instructions, Addressing and Memory. Virtual to real mapping. Basic Instruction Timing. Unit2: Time, Area And Instruction Sets: Time, cost-area, technology state of the Art, The Economics of a processor project: A study, Instruction sets, Professor Evaluation Matrix Unit-3: Cache Memory Notion: Basic Notion, Cache Organization, Cache Data, adjusting the data for cache organization, write policies, strategies for line replacement at miss time, Cache Environment, other types of Cache. Split I and D-Caches, on chip caches, Two level Caches, write assembly Cache, Cache references per instruction, technology dependent Cache considerations, virtual to real translation, overlapping the Tcycle in V-R Translation, studies. Design summary. Unit4: Memory System Design: The physical memory, models of simple processor memory interaction, processor memory modeling using queuing theory, open, closed and mixed-queue models, waiting time, performance, and buffer size, review and selection of queueing models, processors with cache. Unit5: Concurrent Processors: Vector Processors, Vector Memory, Multiple Issue Machines, Comparing vector and Multiple Issue processors. Shared Memory Multiprocessors: Basic issues, partitioning, synchronization and coherency, Type of shared Memory multiprocessors, Memory Coherence in shared Memory Multiprocessors. Text Book: Advance computer architecture by Hwang & Briggs, 1993, TMH. Reference Books: Pipelined and Parallel processor design by Michael J. Fiynn 1995, Narosa.

Note: Eight questions will be set in all by the examiners taking at least one question from each unit. Students will be required to attempt five questions in all.

MDU B.Tech Syllabus (CSE) IV Year

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