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Lab 6: Traffic Light Controller: 1. Open A New Project by Issuing "File - New Project"

This document provides instructions for a lab assignment to design a traffic light controller using Verilog and FPGA implementation. The steps include: 1) Creating a new project and modules for the traffic light controller, counter, and clock using Verilog; 2) Checking syntax and generating schematic symbols for the modules; 3) Creating a schematic file to interconnect the modules on an FPGA with appropriate I/O pins.

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Subha Murugan
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92 views

Lab 6: Traffic Light Controller: 1. Open A New Project by Issuing "File - New Project"

This document provides instructions for a lab assignment to design a traffic light controller using Verilog and FPGA implementation. The steps include: 1) Creating a new project and modules for the traffic light controller, counter, and clock using Verilog; 2) Checking syntax and generating schematic symbols for the modules; 3) Creating a schematic file to interconnect the modules on an FPGA with appropriate I/O pins.

Uploaded by

Subha Murugan
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as DOC, PDF, TXT or read online on Scribd
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Lab 6: Traffic Light Controller

, [email protected] , [email protected] 1. EC616 EC616

Open a new project by issuing File -> New Project.

i.

Click

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2.

ii. Click iii. Click iv. Click v. Click Create a new module by issuing Project > New Source Create a verilog file traffic_light.v .

(You can copy it from the class handout)

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3.

Save the file and issue Synthesis-> Check syntax by doubling click.

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4.

Create the schematic symbol of the module traffic_light.v by doubling click.

5.

If no syntax error, create a new verilog module by issuing Project > New Source. Create a verilog file bc_4b_ce_aclr.v

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6.

Start HDL Editor and create macro for a 4-bit binary counter with a clock enable and an asynchronous reset inputs.

7.

Save the file and issue Synthesis-> Check syntax by double click.

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8.

Create the schemaric symbol of the module bc_4b_ce_aclr.v by doubling click.

9.

Create another module named clk12Hz to generate 11.9 Hz clock, check syntax and then create the symbol of the module clk12Hz.

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10. In Project Manager window, issue Project -> New Source. Create a schematic file named trf_ltc.
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11. In Schematic Editor window Xilinx ESC, create your design at here.

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12. In addition, assign input and output pads to appropriate pins of the FPGA.

Double click trf_ltc_pin.ucf.

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13. Simulate, implement and download your design.

Requirements:
A. Design a two-way traffic light controller. G g g ? H G

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F B. Refer to the FSM as shown in class-handout. C. Design clock, counter and controller modules using verilog code. D. The top module must implemented in schematic design, cannot use verilog code. (Pin connection:) CAR -> P62 HG -> p5 HY -> p4 HR -> p3 FG- > p9 FY -> p8 FR -> p6

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