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Full Subs

This document describes a program to design a full subtractor using structural modeling. It defines an entity called HPfullsub with inputs a, b, c and outputs d, co. It instantiates logic gates like XOR, AND, OR and NOT and maps their ports to design a full subtractor circuit using structural modeling with signals x, g, z, h, and y.

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Harsh Pandit
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71 views

Full Subs

This document describes a program to design a full subtractor using structural modeling. It defines an entity called HPfullsub with inputs a, b, c and outputs d, co. It instantiates logic gates like XOR, AND, OR and NOT and maps their ports to design a full subtractor circuit using structural modeling with signals x, g, z, h, and y.

Uploaded by

Harsh Pandit
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as DOC, PDF, TXT or read online on Scribd
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6.

Program to Design a Full Substractor Using Structural Modelling


library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity HPfullsub is Port ( a : in STD_LOGIC; b : in STD_LOGIC; c : in STD_LOGIC; d : out STD_LOGIC; co : out STD_LOGIC); end HPfullsub; architecture FullSub of HPfullsub is component XORH is port(k,l: in std_logic; m : out std_logic); end component; component ANDH is port(n,o: in std_logic; p : out std_logic); end component; component ORH is port(q,r: in std_logic; s : out std_logic); end component; component NOTH is port(t : in std_logic; v : out std_logic); end component; signal x,g,z,h,y : std_logic; begin S1: N1: C1: S2: N3: C4: O2: XORH port map(a,b,x); NOTH port map(a,g); ANDH port map(b,g,z); XORH port map(c,x,d); NOTH port map(x,h); ANDH port map(h,c,y); ORH port map(y,z,co);

end FullSub;

Harsh Pandit

Circuit Diagram for Full Substractor using Structural Modelling:

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