Introduction to

CMOS VLSI
Design

Lecture 0: Introduction
David Harris

Harvey Mudd College

Spring 2004
 Administrivia
q Name Tents
q Syllabus
– About the Instructor
– Office Hours & Lab Assistant Hours
– Labs, Problem Sets, and Project
– Grading
– Collaboration
q Textbook
q Cross-cultural Chip Design

0: Introduction CMOS VLSI Design Slide 2

 Introduction
q Integrated circuits: many transistors on one chip.
q Very Large Scale Integration (VLSI): very many
q Complementary Metal Oxide Semiconductor
– Fast, cheap, low power transistors
q Today: How to build your own simple CMOS chip
– CMOS transistors
– Building logic gates from transistors
– Transistor layout and fabrication
q Rest of the course: How to build a good CMOS chip

0: Introduction CMOS VLSI Design Slide 3

 Silicon Lattice
q Transistors are built on a silicon substrate
q Silicon is a Group IV material
q Forms crystal lattice with bonds to four neighbors

Si Si Si

Si Si Si

Si Si Si

0: Introduction CMOS VLSI Design Slide 4

 Dopants
q Silicon is a semiconductor
q Pure silicon has no free carriers and conducts poorly
q Adding dopants increases the conductivity
q Group V: extra electron (n-type)
q Group III: missing electron, called hole (p-type)

Si Si Si Si Si Si
- +

+ -
Si As Si Si B Si

Si Si Si Si Si Si

0: Introduction CMOS VLSI Design Slide 5

 p-n Junctions
q A junction between p-type and n-type semiconductor
forms a diode.
q Current flows only in one direction

p-type n-type

anode cathode

0: Introduction CMOS VLSI Design Slide 6

 nMOS Transistor
q Four terminals: gate, source, drain, body
q Gate – oxide – body stack looks like a capacitor
– Gate and body are conductors
– SiO2 (oxide) is a very good insulator
– Called metal – oxide – semiconductor (MOS)
capacitor Source Gate Drain
Polysilicon
– Even though gate is SiO2
no longer made of metal
n+ n+

p bulk Si

0: Introduction CMOS VLSI Design Slide 7

 nMOS Operation
q Body is commonly tied to ground (0 V)
q When the gate is at a low voltage:
– P-type body is at low voltage
– Source-body and drain-body diodes are OFF
– No current flows, transistor is OFF
Source Gate Drain
Polysilicon
SiO2

0
n+ n+
S D
p bulk Si

0: Introduction CMOS VLSI Design Slide 8

 nMOS Operation Cont.
q When the gate is at a high voltage:
– Positive charge on gate of MOS capacitor
– Negative charge attracted to body
– Inverts a channel under gate to n-type
– Now current can flow through n-type silicon from
source through channel to drain, transistor is ON
Source Gate Drain
Polysilicon
SiO2

1
n+ n+
S D
p bulk Si

0: Introduction CMOS VLSI Design Slide 9

 pMOS Transistor
q Similar, but doping and voltages reversed
– Body tied to high voltage (VDD)
– Gate low: transistor ON
– Gate high: transistor OFF
– Bubble indicates inverted behavior
Source Gate Drain
Polysilicon
SiO2

p+ p+

n bulk Si

0: Introduction CMOS VLSI Design Slide 10

 Power Supply Voltage
q GND = 0 V
q In 1980’s, VDD = 5V
q VDD has decreased in modern processes
– High VDD would damage modern tiny transistors
– Lower VDD saves power
q VDD = 3.3, 2.5, 1.8, 1.5, 1.2, 1.0, …

0: Introduction CMOS VLSI Design Slide 11

 Transistors as Switches
q We can view MOS transistors as electrically
controlled switches
q Voltage at gate controls path from source to drain
g=0 g=1

d d d
nMOS g OFF
ON
s s s

d d d

pMOS g OFF
ON
s s s

0: Introduction CMOS VLSI Design Slide 12

 CMOS Inverter

A Y VDD
0
1

A Y

A Y
GND
0: Introduction CMOS VLSI Design Slide 13
 CMOS Inverter

A Y VDD
0
1 0 OFF
A=1 Y=0

ON
A Y
GND
0: Introduction CMOS VLSI Design Slide 14
 CMOS Inverter

A Y VDD
0 1
1 0 ON
A=0 Y=1

OFF
A Y
GND
0: Introduction CMOS VLSI Design Slide 15
 CMOS NAND Gate
A B Y
0 0
0 1 Y
1 0 A
1 1
B

0: Introduction CMOS VLSI Design Slide 16

 CMOS NAND Gate
A B Y
0 0 1 ON ON
0 1 Y=1
A=0
1 0 OFF
1 1
B=0
OFF

0: Introduction CMOS VLSI Design Slide 17

 CMOS NAND Gate
A B Y
0 0 1 OFF ON
0 1 1 Y=1
A=0
1 0 OFF
1 1
B=1
ON

0: Introduction CMOS VLSI Design Slide 18

 CMOS NAND Gate
A B Y
0 0 1 ON OFF
0 1 1 Y=1
A=1
1 0 1 ON
1 1
B=0
OFF

0: Introduction CMOS VLSI Design Slide 19

 CMOS NAND Gate
A B Y
0 0 1 OFF OFF
0 1 1 Y=0
A=1
1 0 1 ON
1 1 0
B=1
ON

0: Introduction CMOS VLSI Design Slide 20

 CMOS NOR Gate
A B Y
0 0 1 A
0 1 0
1 0 0 B
1 1 0 Y

0: Introduction CMOS VLSI Design Slide 21

 3-input NAND Gate
q Y pulls low if ALL inputs are 1
q Y pulls high if ANY input is 0

0: Introduction CMOS VLSI Design Slide 22

 3-input NAND Gate
q Y pulls low if ALL inputs are 1
q Y pulls high if ANY input is 0

Y
A
B
C

0: Introduction CMOS VLSI Design Slide 23

 CMOS Fabrication
q CMOS transistors are fabricated on silicon wafer
q Lithography process similar to printing press
q On each step, different materials are deposited or
etched
q Easiest to understand by viewing both top and
cross-section of wafer in a simplified manufacturing
process

0: Introduction CMOS VLSI Design Slide 24

 Inverter Cross-section
q Typically use p-type substrate for nMOS transistors
q Requires n-well for body of pMOS transistors
A
GND VDD
Y SiO2

n+ diffusion

p+ diffusion
n+ n+ p+ p+
polysilicon
n well
p substrate
metal1

nMOS transistor pMOS transistor

0: Introduction CMOS VLSI Design Slide 25

Well and Substrate Taps
q Substrate must be tied to GND and n-well to VDD
q Metal to lightly-doped semiconductor forms poor
connection called Shottky Diode
q Use heavily doped well and substrate contacts / taps
A
GND VDD
Y

p+ n+ n+ p+ p+ n+

n well
p substrate

substrate tap well tap

0: Introduction CMOS VLSI Design Slide 26

 Inverter Mask Set
q Transistors and wires are defined by masks
q Cross-section taken along dashed line

GND VDD

nMOS transistor pMOS transistor

substrate tap well tap

0: Introduction CMOS VLSI Design Slide 27

 Detailed Mask Views
q Six masks n well

– n-well
– Polysilicon
Polysilicon

– n+ diffusion
– p+ diffusion n+ Diffusion

– Contact p+ Diffusion

– Metal Contact

Metal

0: Introduction CMOS VLSI Design Slide 28

 Fabrication Steps
q Start with blank wafer
q Build inverter from the bottom up
q First step will be to form the n-well
– Cover wafer with protective layer of SiO2 (oxide)
– Remove layer where n-well should be built
– Implant or diffuse n dopants into exposed wafer
– Strip off SiO2

p substrate

0: Introduction CMOS VLSI Design Slide 29

 Oxidation
q Grow SiO2 on top of Si wafer
– 900 – 1200 C with H2O or O2 in oxidation furnace

SiO2

p substrate

0: Introduction CMOS VLSI Design Slide 30

 Photoresist
q Spin on photoresist
– Photoresist is a light-sensitive organic polymer
– Softens where exposed to light

Photoresist
SiO2

p substrate

0: Introduction CMOS VLSI Design Slide 31

 Lithography
q Expose photoresist through n-well mask
q Strip off exposed photoresist

Photoresist
SiO2

p substrate

0: Introduction CMOS VLSI Design Slide 32

 Etch
q Etch oxide with hydrofluoric acid (HF)
– Seeps through skin and eats bone; nasty stuff!!!
q Only attacks oxide where resist has been exposed

Photoresist
SiO2

p substrate

0: Introduction CMOS VLSI Design Slide 33

 Strip Photoresist
q Strip off remaining photoresist
– Use mixture of acids called piranah etch
q Necessary so resist doesn’t melt in next step

SiO2

p substrate

0: Introduction CMOS VLSI Design Slide 34

 n-well
q n-well is formed with diffusion or ion implantation
q Diffusion
– Place wafer in furnace with arsenic gas
– Heat until As atoms diffuse into exposed Si
q Ion Implanatation
– Blast wafer with beam of As ions
– Ions blocked by SiO2, only enter exposed Si

SiO2

n well

0: Introduction CMOS VLSI Design Slide 35

 Strip Oxide
q Strip off the remaining oxide using HF
q Back to bare wafer with n-well
q Subsequent steps involve similar series of steps

n well
p substrate

0: Introduction CMOS VLSI Design Slide 36

 Polysilicon
q Deposit very thin layer of gate oxide
– < 20 Å (6-7 atomic layers)
q Chemical Vapor Deposition (CVD) of silicon layer
– Place wafer in furnace with Silane gas (SiH4)
– Forms many small crystals called polysilicon
– Heavily doped to be good conductor

Polysilicon
Thin gate oxide

n well
p substrate

0: Introduction CMOS VLSI Design Slide 37

 Polysilicon Patterning
q Use same lithography process to pattern polysilicon

Polysilicon

Polysilicon
Thin gate oxide

n well
p substrate

0: Introduction CMOS VLSI Design Slide 38

 Self-Aligned Process
q Use oxide and masking to expose where n+ dopants
should be diffused or implanted
q N-diffusion forms nMOS source, drain, and n-well
contact

n well
p substrate

0: Introduction CMOS VLSI Design Slide 39

 N-diffusion
q Pattern oxide and form n+ regions
q Self-aligned process where gate blocks diffusion
q Polysilicon is better than metal for self-aligned gates
because it doesn’t melt during later processing

n+ Diffusion

n well
p substrate

0: Introduction CMOS VLSI Design Slide 40

 N-diffusion cont.
q Historically dopants were diffused
q Usually ion implantation today
q But regions are still called diffusion

n+ n+ n+
n well
p substrate

0: Introduction CMOS VLSI Design Slide 41

 N-diffusion cont.
q Strip off oxide to complete patterning step

n+ n+ n+
n well
p substrate

0: Introduction CMOS VLSI Design Slide 42

 P-Diffusion
q Similar set of steps form p+ diffusion regions for
pMOS source and drain and substrate contact

p+ Diffusion

p+ n+ n+ p+ p+ n+
n well
p substrate

0: Introduction CMOS VLSI Design Slide 43

 Contacts
q Now we need to wire together the devices
q Cover chip with thick field oxide
q Etch oxide where contact cuts are needed

Contact

Thick field oxide

p+ n+ n+ p+ p+ n+

n well
p substrate

0: Introduction CMOS VLSI Design Slide 44

 Metalization
q Sputter on aluminum over whole wafer
q Pattern to remove excess metal, leaving wires

Metal

Metal
Thick field oxide
p+ n+ n+ p+ p+ n+

n well
p substrate

0: Introduction CMOS VLSI Design Slide 45

 Layout
q Chips are specified with set of masks
q Minimum dimensions of masks determine transistor
size (and hence speed, cost, and power)
q Feature size f = distance between source and drain
– Set by minimum width of polysilicon
q Feature size improves 30% every 3 years or so
q Normalize for feature size when describing design
rules
q Express rules in terms of λ = f/2
– E.g. λ = 0.3 µm in 0.6 µm process

0: Introduction CMOS VLSI Design Slide 46

 Simplified Design Rules
q Conservative rules to get you started

0: Introduction CMOS VLSI Design Slide 47

 Inverter Layout
q Transistor dimensions specified as Width / Length
– Minimum size is 4λ / 2λ, sometimes called 1 unit
– In f = 0.6 µm process, this is 1.2 µm wide, 0.6 µm
long

0: Introduction CMOS VLSI Design Slide 48

 Summary
q MOS Transistors are stack of gate, oxide, silicon
q Can be viewed as electrically controlled switches
q Build logic gates out of switches
q Draw masks to specify layout of transistors

q Now you know everything necessary to start

designing schematics and layout for a simple chip!

0: Introduction CMOS VLSI Design Slide 49