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AVR Instruction Set Summary

The document summarizes arithmetic, logic, branch, data transfer, bit manipulation, and other instructions for a microcontroller. It lists the mnemonic, operands, description, operation, affected flags, and cycles for each instruction type. The operands column specifies the registers and data used in each instruction.

Uploaded by

Sinan Pravadalioglu
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© Attribution Non-Commercial (BY-NC)
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Download as PDF, TXT or read online on Scribd
79 views

AVR Instruction Set Summary

The document summarizes arithmetic, logic, branch, data transfer, bit manipulation, and other instructions for a microcontroller. It lists the mnemonic, operands, description, operation, affected flags, and cycles for each instruction type. The operands column specifies the registers and data used in each instruction.

Uploaded by

Sinan Pravadalioglu
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as PDF, TXT or read online on Scribd
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Arithmetic and Logic Instructions

Mnemonic
ADD ADC ADIW SUB SUBI SBC SBCI SBIW AND ANDI OR ORI EOR COM NEG SBR CBR INC DEC TST CLR SER MUL MULS MULSU FMUL FMULS FMULSU DES

Operands
Rd, Rr Rd, Rr Rdl, K6 Rd, Rr Rd, K8 Rd, Rr Rd, K8 Rdl, K6 Rd, Rr Rd, K8 Rd, Rr Rd, K8 Rd, Rr Rd Rd Rd, K8 Rd, K8 Rd Rd Rd Rd Rd Rd, Rr Rd, Rr Rd, Rr Rd, Rr Rd, Rr Rd, Rr K8

Description
Add without Carry Add with Carry Add Immediate to Word Subtract without Carry Subtract Immediate Subtract with Carry Subtract with Carry Immedtiate Subtract Immediate from Word Logical AND Logical AND with Immediate Logical OR Logical OR with Immediate Logical Exclusive OR One's Complement Two's Complement Set Bit(s) in Register Clear Bit(s) in Register Increment Register Decrement Register Test for Zero or Negative Clear Register Set Register Multiply Unsigned Multiply Signed Multiply Signed with Unsigned Fractional Multiply Unsigned Fractional Multiply Signed Fractional Multiply Signed with Data Encryption Rd = Rd + Rr Rd = Rd + Rr + C

Operation

Flags
Z,C,N,V,H,S Z,C,N,V,H,S Z,C,N,V,S Z,C,N,V,H,S Z,C,N,V,H,S Z,C,N,V,H,S Z,C,N,V,H,S Z,C,N,V,S Z,N,V,S Z,N,V,S Z,N,V,S Z,N,V,S Z,N,V,S Z,C,N,V,S Z,C,N,V,H,S Z,C,N,V,S Z,C,N,V,S Z,N,V,S Z,N,V,S Z,C,N,V,S Z,C,N,V,S None Z,C Z,C Z,C Z,C Z,C Z,C

Cycles
1 1 2 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2

Rdh:Rdl = Rdh:Rdl + K6 Rd = Rd - Rr Rd = Rd - K8 Rd = Rd - Rr - C Rd = Rd - K8 - C Rdh:Rdl = Rdh:Rdl - K6 Rd = Rd Rr Rd = Rd K8 Rd = Rd | Rr Rd = Rd | K8 Rd = Rd EOR Rr Rd = $FF - Rd Rd = $00 - Rd Rd = Rd | K8 Rd = Rd ($FF - K8) Rd = Rd + 1 Rd = Rd - 1 Rd = Rd Rd Rd = 0 Rd = $FF R1:R0 = Rd * Rr R1:R0 = Rd * Rr R1:R0 = Rd * Rr R1:R0 = (Rd * Rr) << 1 R1:R0 = (Rd * Rr) << 1 R1:R0 = (Rd * Rr) << 1 If (H=0) then R15:R0 = Encrypt(R15:R0, K8)

Branch Instructions
Mnemonic
RJMP IJMP EIJMP JMP RCALL ICALL EICALL CALL RET RETI CPSE CP CPC CPI SBRC SBRS SBIC SBIS BRBC BRBS BREQ BRNE BRCS BRCC BRSH BRLO BRMI BRPL BRGE BRLT BRHS BRHC BRTS BRTC BRVS BRVC BRIE BRID

Operands
K None None K K None None K None None Rd, Rr Rd, Rr Rd, Rr Rd, K8 Rr, b Rr, b P, b P, b s, K s, K K K K K K K K K K K K K K K K K K K

Description
Relative Jump Indirect Jump to (Z) Extended Indirect Jump (Z) Jump Relative Call Subroutine Indirect Call to (Z) Extended Indirect Call to (Z) Call Subroutine Subroutine Return Interrupt Return Compare, Skip if equal Compare Compare with Carry Compare with Immediate Skip if bit in register cleared Skip if bit in register set Skip if bit in I/O register cleared Skip if bit in I/O register set Branch if Status flag cleared Branch if Status flag set Branch if equal Branch if not equal Branch if Carry set Branch if Carry cleared Branch if same or higher Branch if lower Branch if minus Branch if plus Branch if greater than or equal (signed) Branch if less than (signed) Branch if half Carry flag set Branch if half Carry flag cleared Branch if T flag set Branch if T flag cleared Branch if overflow flag set Branch if overflow flag cleared Branch if interrupt enabled Branch if interrupt disabled Rd Rd Rd Rd Rd > >= = <= < Rr Rr Rr Rr Rr BRLT BRGE BREQ BRGE BRLT Rr, Rd, Rd, Rr, Rd, Rd Rr Rr Rd Rr

Operation
PC = PC + K + 1 PC = Z STACK = PC + 1, PC(15:0) = Z, PC(21:16) = EIND PC = K STACK = PC + 1, PC = PC + K + 1 STACK = PC + 1, PC = Z STACK = PC + 1, PC(15:0) = Z, PC(21:16) = EIND STACK = PC + 2, PC = K PC = STACK PC = STACK if (Rd == Rr) PC = PC + 2 or 3 Rd - Rr Rd - Rr - C Rd - K if(Rr(b) == 0) PC = PC + 2 or 3 if(Rr(b) == 1) PC = PC + 2 or 3 if(I/O(P, b) == 0) PC = PC + 2 or 3 if(I/O(P, b) == 1) PC = PC + 2 or 3 if(SREG(s) == 0) PC = PC + K + 1 if(SREG(s) == 1) PC = PC + K + 1 If(Z == 1) PC = PC + K + 1 If(Z == 0) PC = PC + K + 1 if(C == 1) PC = PC + K + 1 if(C == 0) PC = PC + K + 1 if(C == 0) PC = PC + K + 1 if(C == 1) PC = PC + K + 1 if(N == 1) PC = PC + K + 1 if(N == 0) PC = PC + K + 1 if(S == 0) PC = PC + K + 1 if(S == 1) PC = PC + K + 1 if(H == 1) PC = PC + K + 1 if(H == 0) PC = PC + K + 1 if(T == 1) PC = PC + K + 1 if(T == 0) PC = PC + K + 1 if(V == 1) PC = PC + K + 1 if(V == 0) PC = PC + K + 1 if(I == 1) PC = PC + K + 1 if(I == 0) PC = PC + K + 1 Rd Rd Rd Rd Rd > >= = <= < Rr Rr Rr Rr Rr BRLO BRCC BREQ BRSH BRLO Rr, Rd, Rd, Rr, Rd, Rd Rr Rr Rd Rr

Flags
None None None None None None None None None I None Z,C,N,V,H,S Z,C,N,V,H,S Z,C,N,V,H,S None None None None None None None None None None None None None None None None None None None None None None None None

Cycles
2 2 2 3 3/4* 3/4* 4* 4/5* 4/5* 4/5* 1/2/3 1 1 1 1/2/3 1/2/3 1/2/3 1/2/3 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2

(CP, CPI etc.)

Signed:

Unsigned:

Data Transfer Instructions


Mnemonic
MOV MOVW LDI LDS LD LD LD LD LD LD LDD LD LD LD LDD STS ST ST ST ST ST ST ST ST ST ST ST LPM LPM LPM ELPM ELPM ELPM SPM ESPM IN OUT PUSH POP

Operands
Rd, Rr Rd, Rr Rd, K8 Rd, K Rd, X Rd, X+ Rd, -X Rd, Y Rd, Y+ Rd, -Y Rd, Y + Rd, Z Rd, Z+ Rd, -Z Rd, Z + K, Rr X, Rr X+, Rr -X, Rr Y, Rr Y+, Rr -Y, Rr Y + K6, Z, Rr Z+, Rr -Z, Rr Z + K6, None Rd, Z Rd, Z+ None Rd, Z Rd, Z+ None None Rd, P P, Rr Rr Rd

Description
Copy register Copy register pair Load Immediate Load Direct Load Indirect Load Indirect and Post- Increment Load Indirect and Pre- Decrement Load Indirect Load Indirect and Post- Increment Load Indirect and Pre- Decrement Load Indirect with displacement Load Indirect Load Indirect and Post- Increment Load Indirect and Pre- Decrement Load Indirect with displacement Store Direct Store Indirect Store Indirect and Post- Increment Store Indirect and Pre- Decrement Store Indirect Store Indirect and Post- Increment Store Indirect and Pre- Decrement Store Indirect with displacement Store Indirect Store Indirect and Post- Increment Store Indirect and Pre- Decrement Store Indirect with displacement Load Program Memory Load Program Memory Load Program Memory and Post- Increment Extended Load Program Memory Extended Load Program Memory Extended Load Program Memory and Post Increment Store Program Memory Extended Store Program Memory In Port Out Port Push register on Stack Pop register from Stack

Operation
Rd = Rr Rd + 1:Rd = Rr + 1:Rr, rd even Rd = K8 Rd = (K) Rd = (X) Rd = (X), X = X + 1 X = X - 1, Rd = (X) Rd = (Y) Rd = (Y), Y = Y + 1 Y = Y - 1, Rd = (Y) Rd = (Y + K6) Rd = (Z) Rd = (Z), Z = Z + 1 Z = Z - 1, Rd = (Z) Rd = (Z + K6) (K) = Rr (X) = Rr (X) = Rr, X = X + 1 X = X - 1, (X) = Rr (Y) = Rr (Y) = Rr, Y = Y + 1 Y = Y - 1, (Y) = Rr (Y + K6) = Rr (Z) = Rr (Z) = Rr, Z = Z + 1 Z = Z - 1, (Z) = Rr (Z + K6) = Rr R0 = (Z) Rd = (Z) Rd = (Z), Z = Z + 1 R0 = (RAMPZ:Z) Rd = (RAMPZ:Z) Rd = (RAMPZ:Z), Z = Z + 1 (Z) = R1:R0 (RAMPZ:Z) = R1:R0 Rd = P P = Rr STACK = Rr Rd = STACK

Flags
None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None

Cycles
1 1 1 2* 2* 2* 2* 2* 2* 2* 2* 2* 2* 2* 2* 2* 2* 2* 2* 2* 2 2 2 2 2 2 2 3 3 3 3 3 3 1 1 2 2

K6

K6

Rr

Rr

Bit and Bit- Test Instructions


Mnemonic
LSL LSR ROL ROR ASR SWAP BSET BCLR SBI CBI BST BLD SEC CLC SEN CLN SEZ CLZ SEI CLI SES CLN SEV CLV SET CLT SEH CLH NOP SLEEP WDR

Operands
Rd Rd Rd Rd Rd Rd s s P, b P, b Rr, b Rd, b None None None None None None None None None None None None None None None None None None None

Description
Logical shift left Logical shift right Rotate left through Carry Rotate right through Carry Arithmetic shift right Swap nibbles Set flag Clear flag Set bit in I/O register Clear bit in I/O register Bit store from register to T Bit load from register to T Set Carry flag Clear Carry flag Set negative flag Clear negative flag Set Zero flag Clear Zero flag Set interrupt flag Clear interrupt flag Set signed flag Clear signed flag Set overflow flag Clear overflow flag Set T flag Clear T flag Set half Carry flag Clear half Carry flag No operation Sleep Watchdog Reset

Operation
Rd(n + 1) = Rd(n), Rd(0) = 0, C = Rd(7) Rd(n) = Rd(n + 1), Rd(7) = 0, C = Rd(0) Rd(0) = C, Rd(n + 1) = Rd(n), C = Rd(7) Rd(7) = C, Rd(n) = Rd(n + 1), C = Rd(0) Rd(n) = Rd(n + 1), n = 0,...,6 Rd(3..0) = Rd(7..4), Rd(7..4) = Rd(3..0) SREG(s) = 1 SREG(s) = 0 I/O(P, b) = 1 I/O(P, b) = 0 T = Rr(b) Rd(b) = T C = 1 C = 0 N = 1 N = 0 Z = 1 Z = 0 I = 1 I = 0 S = 1 S = 0 V = 1 V = 0 T = 1 T = 0 H = 1 H = 0 None See instruction manual See instruction manual

Flags
Z,C,N,V,H,S Z,C,N,V,S Z,C,N,V,H,S Z,C,N,V,S Z,C,N,V,S None SREG(s) SREG(s) None None T None C C N N Z Z I I S S V V T T H H None None None

Cycles
1 1 1 1 1 1 1 1 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

Rd: Rr: b: s: P:

Destination register in the register file Source register in the register file Constant (0- 7), can be a constant expression Constant (0- 7), can be a constant expression Constant (0- 31/63), can be a constant expression

K: K6: K8: Rdl: X,Y,Z:

Constant, value range depending on instruction. Constant (0 - 63), can be a constant expression Constant (0 - 255), can be a constant expression R24, R26, R28, R30. For ADIW and SBIW instructions Indirect address registers (X = R27:R26, Y = R29:R28, Z = R31:R30)

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