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MUXx 2 X 2

This document discusses using a 74153 multiplexer chip to generate a 16 row truth table by combining the outputs of its two 4-row multiplexers. It explains that each multiplexer's output is controlled by a strobe signal and combined using an OR gate. It also notes that the multiplexer doubling technique is used to implement a 3-input function on the chip's 2-input multiplexers. The accompanying circuit diagram and truth table demonstrate how this expands the chip's capabilities.

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40 views

MUXx 2 X 2

This document discusses using a 74153 multiplexer chip to generate a 16 row truth table by combining the outputs of its two 4-row multiplexers. It explains that each multiplexer's output is controlled by a strobe signal and combined using an OR gate. It also notes that the multiplexer doubling technique is used to implement a 3-input function on the chip's 2-input multiplexers. The accompanying circuit diagram and truth table demonstrate how this expands the chip's capabilities.

Uploaded by

emb2k9
Copyright
© Attribution Non-Commercial (BY-NC)
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Download as PDF, TXT or read online on Scribd
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CSCI 230: Digital Electronics

Dr. McLean

Multiplexer Quadrupling
Using the 74153 MUX to Generate a 16 row Truth Table

The 74153 MUX has two separate 2-input/4-row MUXs on it. To create a single 16-row truth table, we can start by implementing parts of the table on different MUXs, and then combining the two separate outputs into one output. Well turn on only the MUX needed using the STROBEs. The multiple outputs are combined with an OR gate. Remember, each strobe turns its MUX on when it is low. On each MUX, we have to use the MUX doubling technique to fit a 3-input/8-row truth table onto a 2-input/4-row MUX. The circuit shown will generate the accompanying truth table. Besides the 74153 MUX, it requires two inverters ( C and D ), and one two-input OR gate.

D
+5v Vcc 16 2S 15

A 14

2D3 2D2 2D1 2D0 2Q 13 12 11 10 9

74153 Dual 1-of-4 Multiplexer


1 1S 2 B 3 1D3 4 5 1D2 1D1 +5v 6 1D0 7 8 1Q GND

D 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

C 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1

B 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1

A 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

Q 1 0 1 0 0 0 1 1 0 0 0 1 0 1 1 0

Di 1D0 1D1 1D2 1D3 1D0 1D1 1D2 1D3 2D0 2D1 2D2 2D3 2D0 2D1 2D2 2D3

Main Output Q

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