Scribd
Upload
23 views

Xilinx

The document outlines steps to create a new project in Xilinx ISE 9.1i to synthesize a VHDL module with ports a, b as inputs and c as an output. The module entity and architecture are defined, with c assigned as the and of a and b. The project is then synthesized with XST and the synthesis report is viewed.

Uploaded by

arya_mca_05
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
23 views

Xilinx

The document outlines steps to create a new project in Xilinx ISE 9.1i to synthesize a VHDL module with ports a, b as inputs and c as an output. The module entity and architecture are defined, with c assigned as the and of a and b. The project is then synthesized with XST and the synthesis report is viewed.

Uploaded by

arya_mca_05
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
You are on page 1/ 5

Step 1: Xilinx Step 2:OK

ISE 9.1i(Double Click)

Step 3:File New Project Step 4:Project Name: test Next Step 5: Product Category:All Family:Spartan3 Device:XC3S200 Package:FT256 Speed:-5 Top Level Source Type:HDL Synthesis Tool:XST(VHDL/Verilog) Simulator:Modelsim SE VHDL Preferred Language:VHDL Next Step 6:New Source Step 7:File Name:test module Step 8:VHDL Module Next Step 9: Port Name a,b c Next Finish Yes Next Step 10: Next Finish Direction in out

---------------------------------------------------------------------------------- Company: -- Engineer: --- Create Date: -- Design Name: -- Module Name: -- Project Name: -- Target Devices: -- Tool versions: -- Description: --- Dependencies: --- Revision: -- Revision 0.01 - File Created -- Additional Comments: ---------------------------------------------------------------------------------library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; test_file - Behavioral 19:47:30 01/20/2012

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all;

entity test_file is Port ( a,b : in c : out end test_file; STD_LOGIC; STD_LOGIC);

architecture Behavioral of test_file is

begin

end Behavioral;

Step 11: Synthesize XST Step 12: Check Syntax Step 13:View Synthesis Report

oooooooooooooooooooooooooooooooooooooo ---------------------------------------------------------------------------------- Company: -- Engineer: --- Create Date: 19:20:08 01/20/2012

-- Design Name: -- Module Name: -- Project Name: -- Target Devices: -- Tool versions: -- Description: --- Dependencies: --- Revision: -- Revision 0.01 - File Created -- Additional Comments: ---------------------------------------------------------------------------------library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ag - Behavioral

---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all;

entity ag is Port ( a,b : in STD_LOGIC;

c : out end ag;

STD_LOGIC);

architecture Behavioral of ag is

begin c<=a and b;

end Behavioral;

You might also like